Code generation tool for control and status registers

AMBA AXI VIP

Network on Chip Implementation written in SytemVerilog

An AXI4 crossbar implementation in SystemVerilog

Control and status register code generator toolchain

Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedded programs targeted at the microprocessor to control the peripherals

Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.

Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description and software programming languages

Design and program Arm-based embedded systems and implement them in low-level hardware using standard C and assembly language.

AHB3-Lite Interconnect

The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are converted into equivalent transfers on the APB.

Parameterised Asynchronous AHB3-Lite to APB4 Bridge.

A textbook on understanding system on chip design

A reference book on System-on-Chip Design

Verification IP for AMBA APB Protocol

Master and Slave made using AMBA AXI4 Lite protocol.

Multi-Technology RAM with AHB3Lite interface

Assertion-Based Formal Verification of an AHB2APB bridge, featuring SystemVerilog assertions, RTL designs, and detailed documentation including a final report and project progression presentation.

Open-source AMBA CHI infrastructures (supporting Issue B, E.b)

To design test bench of the APB protocol