High throughput JPEG decoder in Verilog for FPGA

An Open Workflow to Build Custom SoCs and run Deep Models at the Edge

This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supported. The project was tested on Xilinx 7-series FPGA with 10G Ethernet MAC IP-core

UART to AXI Stream interface written in VHDL

This project is designed to delay the output of the video stream in AXI-STREAM format.

Tutorials or projects example to use Vivado 2019.2 and Vitis

Various video processing projects will be shared here

Synchronous and Asynchronous FIFO with AXI interface

FPGA implementation for UART interface for rx/tx data with support AXI-Stream protocol

A one-position buffer compatible with AXI Stream interface

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.

An IP used for testing AXI stream protocols. It uses a LFSR to generate ready and valid signals

FPGA implemented component for realize register file in FPGA resources with request and sends data to ADXL345 device

FPGA benchmark of vectorized gradient descent on linear regression

AXI stream protocol checking design

Notes after working with Zynq platform using vivado and petalinux

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.

vivado design to test the skidbuffer IP

Fast bwa-mem dna matching algor implemented in system verilog, fully synthesizable.

Zynq PS connected to a Hermes networkn-on-chip router via AXI streaming interface