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verilog-code

Here are 107 public repositories matching this topic...

snbk001 / Verilog-Design-Examples

Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous F…

verilog testbenches verilog-hdl verilog-programs verilog-project verilog-code verilog-design self-checking

Updated Jan 29, 2024
Verilog

TheSUPERCD / 8bit_MicroComputer_Verilog

This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This project was developed as a Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.

verilog verilog-hdl 8bit iverilog verilog-project ben-eater verilog-code ben-eaters-cpu

Updated Nov 30, 2022
Verilog

benitoss / UnAmiga

Implementation of Amiga 500/1200 in Altera Cyclone IV FPGA

verilog-code

Updated Jun 4, 2019
VHDL

Arjun-Narula / Traffic-Light-Controller-using-Verilog

the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.

traffic verilog vivado verilog-hdl traffic-light traffic-sign-recognition vivado-hls verilog-programs verilog-simulator verilog-project verilog-code vivado-simulator

Updated Jul 18, 2020
JavaScript

mihir8181 / VerilogHDL-Codes

Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.

counter fsm asynchronous verilog fifo testbenches verilog-hdl verilog-programs mealy-machine-code moore-machine-code verilog-project fifo-buffer verilog-code n-bit-alu verilogvalidation design-under-test asynchronous-fifo fifo-verilog

Updated May 10, 2019
Verilog

getting-started-with-verilog

aklsh / getting-started-with-verilog

Verilog modules for beginners

open-source verilog verilog-hdl verilog-snippets verilog-code

Updated May 27, 2022
Verilog

verilog-rle

geraked / verilog-rle

Verilog Implementation of Run Length Encoding for RGB Image Compression

Updated Jun 28, 2021
Verilog

aut-ce / CE202-LC-Lab-Manual

Manual and Template Sources of Logic Circuit Laboratory (Verilog Templates)

homework-assignments verilog-code logic-circuit-laboratory

Updated Jun 2, 2025
C

aditeyabaral / DDCO-Lab-UE18CS207

A repository containing the source codes for the Digital Design and Computer Organization Laboratory course (UE18CS2) at PES University.

verilog logic-programming icarus-verilog digital-design computer-organization verilog-code

Updated Apr 17, 2020
Verilog

jge162 / verilog_compiler

Verilog_Compiler is now available in GitHub Marketplace! This tool can quickly compile Verilog code and check for errors, making it an essential tool for developers.

fast compiler verilog verilog-hdl github-action verilog-code verilog-compiler verilog-scanner

Updated Nov 2, 2024
Verilog

djzenma / RV32IC-CPU

Implementation of the RISC-V 32 bit Integer and Compressed Instructions in Verilog.

cpu verilog risc hdl pipeline-processor verilog-hdl risc-v rv32i verilog-snippets pipeline-cpu risc-processor riscv32 riscv-simulator rv32imc verilog-code riscv32im

Updated May 29, 2020
Verilog

siri-n-shetty / iverilog

This repository contains a series of Verilog codes for the course UE22CS251A (DDCO).

verilog vcd verilog-code pesu ddco

Updated Nov 13, 2024
Verilog

daringpatil3134 / SPI_Serial_Peripheral_Interface_Verilog_Modules

Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device

spi-interface rtl verilog spi hdl testbench verilog-hdl wishbone spi-master spi-protocol spi-slave verilog-project clock-generator verilog-code verilog-rtl-model wishbone-master

Updated Jul 7, 2024
Verilog

vasanthkumar18 / Cache-Compression

Cache compression using BASE-DELTA-IMMEDIATE process in verilog

cache project hacktoberfest verilog-project verilog-code bdi-model hardware-project hacktoberfest2021 cache-compression

Updated Jul 16, 2022
Verilog

Sanskar777 / QRS-peak-detection-in-ECG-signals-using-verilog

ecg-signal ecg-qrs-detection verilog-code curve-length-transform qrs-peak-detection

Updated Dec 1, 2019
Verilog

NellyW8 / VeriReason

This is the Github Repo for the paper: VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation

Updated Jun 9, 2025
Python

mahdizynali / verilog-digital-circuit-codes

simple verilog digital circuits sampels (halfAdder, fullAdder, ALSU , ...)

logic verilog fulladder mux multiplexer shift-register halfadder arithmatic shift-left verilog-code shift-right fullsubtractor halfsubtractor

Updated Jun 9, 2023
Verilog

pratikbhuran / Voting_Machine

Voting machine implemented in verilog

verilog verilog-hdl voting-system voting-machine verilog-project verilog-code

Updated Apr 8, 2023
Verilog

EhsanShahbazii / Digital-VLSI-System-Design-Projects

سورس کد پروژه های درس طراحی سیستم های دیجیتال برنامه پذیر دانشگاه تبریز مقطع کارشناسی رشته مهندسی کامپیوتر

verilog vlsi verilog-components verilog-project verilog-code

Updated Jan 9, 2024
Verilog

mongrelgem / UART-RTL-Physical-Design

Complete ASIC Design of UART Interface with Baud Rate Selection :- RTL to GDS2

layout verilog uart hardware-designs uart-interface verilog-code

Updated Sep 3, 2019
Perl

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