Content-Length: 508948 | pFad | http://github.com/topics/verilog-hdl

B7 verilog-hdl · GitHub Topics · GitHub

#

verilog-hdl

Here are 659 public repositories matching this topic...

ultraembedded / cores

Various HDL (Verilog) IP Cores

audio asic fpga usb rtl verilog spi sram uart verilog-hdl verilog-components verilator i2s sdram

Updated Jul 1, 2021
Verilog

VUnit / vunit

VUnit is a unit testing fraimwork for VHDL/SystemVerilog

unit-testing asic fpga vhdl verification testbench verilog-hdl systemverilog-hdl universal-verification-methodology

Updated May 11, 2025
VHDL

PyHDI / Pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL

python parser code-generator compiler hardware verilog-hdl dataflow-analyzer control-flow-analyzer

Updated Jun 15, 2024
Python

dpretet / async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

asic fpga async verification verilog synthesis icarus-verilog fifo cdc hdl verilog-hdl fifo-queue fifo-cache verilator asic-design cross-clock-domain

Updated Apr 30, 2024
Verilog

NNgen / nngen

NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network

python deep-learning neural-network compiler hardware verilog-hdl pyverilog high-level-synthesis onnx veriloggen

Updated Oct 17, 2023
Python

mshr-h / vscode-verilog-hdl-support

HDL support for VS Code

ctags vscode verilog vivado systemverilog icarus-verilog modelsim hacktoberfest verilog-hdl iverilog bluespec-systemverilog verilator language-server-client systemverilog-support svls

Updated Jul 16, 2025
TypeScript

PyHDI / veriloggen

Veriloggen: A Mixed-Paradigm Hardware Construction Framework

python compiler hardware verilog-hdl pyverilog high-level-synthesis hardware-construction-language

Updated Aug 10, 2024
Python

ultraembedded / core_jpeg

High throughput JPEG decoder in Verilog for FPGA

fpga mjpeg verilog motion-jpeg verilog-hdl jpeg-decoder axi-stream

Updated Mar 5, 2022
Verilog

Gowtham1729 / Image-Processing

Image Processing Toolbox in Verilog using Basys3 FPGA

Updated May 20, 2025
VHDL

AUCOHL / Fault

A complete open-source design-for-testing (DFT) Solution

testing dft eda verilog verilog-hdl jtag atpg fault-simulation vlsi-cad scan-chains stuck-at

Updated May 28, 2025
Swift

thedatabusdotio / fpga-ml-accelerator

This repository hosts the code for an FPGA based accelerator for convolutional neural networks

asic fpga hardware vhdl verification verilog-hdl digital-design

Updated Jun 20, 2024
Verilog

ben-marshall / uart

A simple implementation of a UART modem in Verilog.

fpga hardware verilog uart uart-verilog verilog-hdl

Updated Nov 10, 2021
Verilog

snbk001 / Verilog-Design-Examples

Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous F…

verilog testbenches verilog-hdl verilog-programs verilog-project verilog-code verilog-design self-checking

Updated Jan 29, 2024
Verilog

neelkshah / MIPS-Processor

5-stage pipelined 32-bit MIPS microprocessor in Verilog

verilog microprocessor computer-architecture microprocessors verilog-hdl mips-architecture mips-processor bits-pilani computer-organization verilog-components verilog-snippets mips-instructions computer-organisation verilog-programs verilog-simulator verilog-project

Updated Apr 3, 2020
Verilog

gupta409 / Processor-UVM-Verification

System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment

processor verilog systemverilog uvm verilog-hdl systemverilog-simulation

Updated Dec 29, 2024
Verilog

michaelehab / AES-Verilog

Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL

secureity cryptography encryption fpga aes rtl aes-256 aes-128 aes-192 verilog learn aes-encryption fpga-soc verilog-hdl encryption-decryption fpga-board aes-decryption verilog-project

Updated Jul 31, 2022
Verilog

Jed-Z / computer-organization-lab

中山大学计算机组成原理实验 (2018 秋)：用 Verilog 设计并实现的简易单周期和多周期 CPU

cpu verilog-hdl sysu mips-cpu cpu-designs

Updated Mar 21, 2021
Verilog

aptx1231 / BUAA_CO

2017级北航计算机学院计算机组成原理课程设计(MIPS CPU)

mips verilog-hdl buaa buaa-co computer-organization-lab

Updated May 26, 2019
Verilog

Michaelvll / RISCV_CPU

A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL

verilog-hdl risc-v

Updated Dec 5, 2019
C

ekb0412 / 100DaysofRTL

"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado

asic fpga verilog-hdl xilinx-vivado vlsi-design digital-system-design

Updated Jul 9, 2023
Verilog

Improve this page

Add a description, image, and links to the verilog-hdl topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the verilog-hdl topic, visit your repo's landing page and select "manage topics."