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6E verilog-parser · GitHub Topics · GitHub

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verilog-parser

Here are 3 public repositories matching this topic...

Nic30 / hdlConvertor

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

python parser fpga vhdl verilog systemverilog vhdl-parser antrl4 systemverilog-parser verilog-parser

Updated Jun 30, 2025
C++

codinuum / cca

Code Continuity Analysis Framework

semantic-web ontology software-engineering java-parser python-parser syntax-aware cpp-parser verilog-parser ast-differencing ast-patching fortran-parser ast-diff-tool ast-patch-tool ast-matching

Updated Mar 3, 2025
OCaml

PaletiKrishnasai / VLSI_Practice

work done as part of VLSI Design practice course

register verilog xilinx vlsi wallace-tree-multiplier array-multiplication sklansky-adder dadda-tree recursive-doubling-cla ripple-carry-adder parity-generator verilog-parser

Updated Feb 21, 2021
Verilog

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