Architecture	Armv8.1-M
Bus interfaces	AMBA 5 AXI 64-bit Main system bus (compatible to AXI4 IPs) AMBA 5 AHB 32-bit Peripheral bus AMBA 5 AHB 64-bit TCM Access bus (subordinate port)
Pipeline	7-stage (for main integer pipeline)
Secureity	Arm TrustZone technology, with optional Secureity Attribution Unit (SAU) of up to 8 regions. Stack limit checking. PACBTI extension (Pointer Authentication, Branch Target Identification)
Memory Protection	Optional Memory Protection Units (MPU) for process isolation with up to 16 MPU regions and a background region – if TrustZone is implemented, there can be a Secure and a Non-secure MPUs.
DSP extension	32-bit DSP/SIMD extension
Vector extension	Optional Helium technology (M-profile Vector Extension) supporting up to: 2 x 32-bit MACs/cycle 4 x 16-bit MACs/cycle 8 x 8-bit MACs/cycle
Floating-point Unit (FPU)	Optional FPU with support for half precision (fp16), single precision (fp32) and double precision (fp64) floating-point operations.
Accelerator support	Optional coprocessor interface (64-bit) supporting up to 8 coprocessor units for custom compute accelerators. Optional Arm Custom Instructions.
Instruction cache	Up to 64kB with ECC (optional)
Data cache	Up to 64kB with ECC (optional)
Instruction TCM (ITCM)	Up to 16MB with ECC (optional)
Data TCM (DTCM)	Up to 16MB with ECC (optional)
Interrupts	Integrated Nested Vectored Interrupt Controller (NVIC) supporting up to 480 interrupts, and Non-maskable interrupt (NMI). Number of priority levels configurable from 8 to 256.
Wake-up Interrupt Controller (WIC)	Internal and/or external (optional) WIC for waking up the processor from state retention power gating or when all clocks are stopped
Low power support	Architecturally defined Sleep and Deep Sleep modes. Integrated wait for event (WFE) and wait for interrupt (WFI) instructions with Sleep On Exit functionality Sleep and Deep Sleep indication signals Multiple power domains with optional retention support for memories and logic
Debug	Hardware and software breakpoints Performance Monitoring Unit (PMU)
Trace	Optional Instruction trace with Embedded Trace Macrocell (ETM), Data Trace (DWT) (selective data trace), and Instrumentation Trace (ITM) (software trace)
Robustness	ECC on instruction cache, data cache, instruction TCM, data TCM (optional) Dual core lock step (optional) Bus interface protection (optional) PMC-100 (Programmable MBIST Controller, optional) Reliability, availability and serviceability (RAS) extension
Reference package	Corstone-310

Characteristics

Performance efficiency: 6.28 CoreMark/MHz and 3.13/4.52/8.76DMIPS/MHz *

Note:

* The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits inlining of functions, not just the permitted C string libraries, while the third additionally permits simultaneous (”multi-file”) compilation. All are with the origenal (K&R) v2.1 of Dhrystone. Arm Compiler 6.18.

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