Some salient points:
- 32 SPARC 4th generation cores, each dynamically threaded with 1-8 Threads/core
- New Cache organization with shared L2 data and instruction cache and 64MB L3 cache
- DDR4 DRAM with unto 2TB memory per processor and 2x-3x bandwidth over T5/M6
- PCIe Gen3 Support
- Application Acceleration (more on this later, popularly called "Software in Silicon")
- SMP Scalability from 1-32 Processors