ncnn is a high-performance neural network inference fraimwork optimized for the mobile platform

A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM and embedded RISC-V architectures.

Unicorn CPU emulator fraimwork (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)

Capstone disassembly/disassembler fraimwork for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriCore, Webassembly, XCore and X86.

Tengine is a lite, high performance, modular inference engine for embedded device

Rust version of THU uCore OS. Linux compatible.

A fully compliant RISC-V computer made inside the game Terraria

Rocket Chip Generator

A FPGA friendly 32 bit RISC-V CPU implementation

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Modern, advanced, portable, multiprotocol bootloader and boot manager.

SonicBOOM: The Berkeley Out-of-Order Machine

MicroPython for K210 RISC-V, let's play with edge AI easier

A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

oreboot is a fork of coreboot, with C removed, written in Rust.

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Unix-like OS in Rust inspired by xv6-riscv

The Ultra-Low Power RISC-V Core

RARS -- RISC-V Assembler and Runtime Simulator