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ORCIDIEEE Design & Test of Computers, Volume 26
Volume 26, Number 1, January/February 2009
- Erik Jan Marinissen
, Yervant Zorian:
Guest Editors' Introduction: The Status of IEEE Std 1500. 6-7 - Erik Jan Marinissen, Yervant Zorian:
IEEE Std 1500 Enables Modular SoC Testing. 8-17 - Benoit Nadeau-Dostie, Saman Adham, Russell Abbott:
Improved Core Isolation and Access for Hierarchical Embedded Test. 18-25 - Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Wen-Ben Jone, Jianghao Guo, Kuen-Jong Lee, Wei-Shin Wang, Xiaoqing Wen, Hao-Jan Chao, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li:
Turbo1500: Core-Based Design for Test and Diagnosis. 26-35 - Rohit Kapur, Paul Reuter, Sandeep Bhatia, Brion L. Keller:
CTL and Its Usage in the EDA Industry. 36-43 - Teresa L. McLaurin, Stylianos Diamantidis, Irakis Diamantidis:
The ARM Cortex-A8 Microprocessor IEEE Std 1500 Wrapper. 44-51 - Kedarnath J. Balakrishnan, Grady Giles, James Wingfield:
Test Access Mechanism in the Quad-Core AMD Opteron Microprocessor. 52-59 - Lucia Costas-Perez, Juan J. Rodríguez-Andina:
Algorithmic Concurrent Error Detection in Complex Digital-Processing Systems. 60-67 - Wenjing Rao, Alex Orailoglu, Ramesh Karri:
Logic Mapping in Crossbar-Based Nanoarchitectures. 68-77 - Timothée Levi, Jean Tomas, Noëlle Lewis, Pascal Fouillat:
A CMOS Resizing Methodology for Analog Circuits. 78-87 - Gadi Singer, Rajesh Galivanche, Srinivas Patil, Mike Tripp:
The Challenges of Nanotechnology and Gigacomplexity. 88-93 - Scott Davidson:
A second course on testing [review of System on Chip Test Architectures (Wang, L.-T et al., Eds.; 2007)]. 98-101 - Miron Abramovici, Al Crouch:
We need more standards like IEEE 1500. 104
Volume 26, Number 2, March/April 2009
- Yervant Zorian:
Guest Editor's Introduction: Examples of Management Decision Criteria. 6-7 - Brad Beavers:
The Story behind the Intel Atom Processor Success. 8-13 - Andrew Chang:
Case Study of a 65-nm SoC Design. 14-19 - Jean-Pierre Schoellkopf, Philippe Magarshack:
Low-Power Design Solutions forWireless Multimedia SoCs. 20-29 - Manuel d'Abreu:
From Specification to High-Volume Production. 30-33 - Kai-Hui Chang, David A. Papa, Igor L. Markov, Valeria Bertacco:
Incremental Verification with Error Detection, Diagnosis, and Visualization. 34-43 - Wei Zhang:
Computing and Minimizing Cache Vulnerability to Transient Errors. 44-51 - Andreas Apostolakis, Dimitris Gizopoulos, Mihalis Psarakis, Danilo Ravotto, Matteo Sonza Reorda:
Test Program Generation for Communication Peripherals in Processor-Based SoC Devices. 52-63 - Li-Ming Denq, Yu-Tsao Hsing, Cheng-Wen Wu:
Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories. 64-73 - Grant Martin:
Processor Stew (review of Processor Description Languages by P. Mishra and N. Dutt, Eds.; 2008) [Book reviews]. 76-77 - Peggy Aycinena:
Technical management: Best shaken, not stirred [The Last Byte]. 84
Volume 26, Number 3, May/June 2009
- Metamodeling for model-based system design. 2
- Erik Jan Marinissen, Yervant Zorian:
Guest Editors' Introduction: The Status of IEEE Std 1500 - Part 2. 4 - Krishna Chakravadhanula, Vivek Chickermane:
Automating IEEE 1500 Core Test—An EDA Perspective. 6-15 - Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Paolo Prinetto:
Are IEEE-1500-Compliant Cores Really Compliant to the Standard?. 16-24 - Ozgur Sinanoglu, Erik Jan Marinissen, Anuja Sehgal, Jeff Fitzgerald, Jeff Rearick:
Test Data Volume Comparison: Monolithic vs. Modular SoC Testing. 25-37 - Roberto Passerone, Imene Ben Hafaiedh, Susanne Graf, Albert Benveniste, Daniela Cancila, Arnaud Cuccuru, Sebastien Gerard, François Terrier, Werner Damm, Alberto Ferrari, Leonardo Mangeruca, Bernhard Josko, Thomas Peikenkamp, Alberto L. Sangiovanni-Vincentelli:
Metamodels in Europe: Languages, Tools, and Applications. 38-53 - Alberto L. Sangiovanni-Vincentelli, Sandeep K. Shukla, Janos Sztipanovits, Guang Yang, Deepak Mathaikutty:
Metamodeling: An Emerging Representation Paradigm for System-Level Design. 54-69 - Ishwar Parulkar, Babu Turumella:
Comprehensive Approach to High-Performance Server Chipset Debug. 70-77 - Vladimir A. Zivkovic, Jan Schat, Frank van der Heyden, Geert Seuren:
Core-Based Testing of Embedded Mixed-Signal Modules in a SoC. 78-86 - Peggy Aycinena:
DATE 2009 Workshop on 3D Integration. 87 - CEDA Currents. 88-90
- DATC Newsletter. 91
- Scott Davidson:
Book Review: A book on system test, and testing systems also. 92-93 - Test Technology TC Newsletter. 94-95
- Sandeep K. Shukla:
Metamodeling: What is it good for? 96
Volume 26, Number 4, July/August 2009
- From the EIC: Building and verifying hardware at a higher level of abstraction. 2
- Philippe Coussy, Andrés Takach:
Guest Editors' Introduction: Raising the Abstraction Level of Hardware Design. 4-6 - Philippe Coussy, Daniel D. Gajski, Michael Meredith, Andrés Takach:
An Introduction to High-Level Synthesis. 8-17 - Grant Martin, Gary Smith:
High-Level Synthesis: Past, Present, and Future. 18-25 - Virtual Roundtable: User Perspectives. 26-33
- Soujanna Sarkar, Shashank Dabral, Praveen Tiwari, Raj S. Mitra:
Lessons and Experiences with High-Level Synthesis. 34-45 - Maciej J. Ciesielski, Jérémie Guillot, Daniel Gomez-Prado, Emmanuel Boutillon:
High-Level Dataflow Transformations Using Taylor Expansion Diagrams. 46-57 - Sumit Ahuja, Swathi T. Gurumani, Chad Spackman, Sandeep K. Shukla:
Hardware Coprocessor Synthesis from an ANSI C Specification. 58-67 - María C. Molina, Rafael Ruiz-Sautua, Alberto A. Del Barrio, Jose Manuel Mendias:
Subword Switching Activity Minimization to Optimize Dynamic Power Consumption. 68-77 - Yuan Xie, Yibo Chen:
Statistical High-Level Synthesis under Process Variability. 78-87 - Anmol Mathur, Masahiro Fujita, Edmund M. Clarke, Pascal Urard:
Functional Equivalence Verification Tools in High-Level Synthesis Flows. 88-95 - CEDA Currents. 96-98
- Design Automation Technical Committee Newsletter. 99
- Igor L. Markov:
Book Review: A physical-design picture book. 100-101 - Test Technology TC Newsletter. 102-103
- Jason Cong, Wolfgang Rosenstiel:
The Last Byte: The HLS tipping point. 104
Volume 26, Number 5, September/October 2009
- Stacking chips in 3D. 2
- David S. Kung, Yuan Xie:
Guest Editors' Introduction: Opportunities and Challenges of 3D Integration. 4-5 - Philip G. Emma, Eren Kursun:
Opportunities and Challenges for 3D Systems and Their Design. 6-14 - Pingqiang Zhou, Karthikk Sridharan, Sachin S. Sapatnekar:
Optimizing Decoupling Capacitors in 3D Circuits for Power Grid Integrity. 15-25 - Hsien-Hsin S. Lee, Krishnendu Chakrabarty:
Test Challenges for 3D Integrated Circuits. 26-35 - Hongbin Sun, Jibang Liu, Rakesh S. Anigundi, Nanning Zheng, Jian-Qiang Lu, Kenneth Rose, Tong Zhang:
3D DRAM Design and Application to 3D Multicore Systems. 36-47 - Gordon W. Roberts, Sadok Aouini:
Mixed-Signal Production Test: A Measurement Principle Perspective. 48-62 - W. Robert Daasch, C. Glenn Shirley, Amit Nahar:
Statistics in Semiconductor Test: Going beyond Yield. 64-73 - Kenneth M. Butler, John M. Carulli Jr., Jayashree Saxena, Amit Nahar, W. Robert Daasch:
Multidimensional Test Escape Rate Modeling. 74-82 - Martin Ruckert, Axel Böttcher, Martin Hauser:
A Generic Virtual Bus for Hardware Simulator Composition. 83-91 - Hao Yu, Lei He, Mau-Chung Frank Chang:
Robust On-Chip Signaling by Staggered and Twisted Bundle. 92-104 - Test Technology TC Newsletter. 105
- Grant Martin:
Teaching someone to fish. 106-107 - CEDA Currents. 108-110
- Design Automation Technical Committee Newsletter. 111
- David S. Kung:
The fate of stacking. 112
Volume 26, Number 6, November/December 2009
- Design for reliability and robustness. 2-3
- Yu Cao, Jim Tschanz, Pradip Bose:
Guest Editors' Introduction: Reliability Challenges in Nano-CMOS Design. 6-7 - Sang Phill Park, Kunhyuk Kang, Kaushik Roy:
Reliability Implications of Bias-Temperature Instability in Digital ICs. 8-17 - Muhammad Bashir, Linda Milor:
Modeling Low-k Dielectric Breakdown to Determine Lifetime Requirements. 18-27 - Yanjing Li, Young Moon Kim, Evelyn Mintarno, Donald S. Gardner, Subhasish Mitra:
Overcoming Early-Life Failure and Aging for Robust Systems. 28-39 - Prashant Singh, Cheng Zhuo, Eric Karl, David T. Blaauw, Dennis Sylvester:
Sensor-Driven Reliability and Wearout Management. 40-49 - Dongwoo Lee, Jongwhoa Na:
A Novel Simulation Fault Injection Method for Dependability Analysis. 50-61 - Jude A. Rivers, Prabhakar Kudva:
Reliability Challenges and System Performance at the Architecture Level. 62-73 - Tero Vallius, Juha Röning:
EOC: Electronic Building Blocks for Embedded Systems. 74-83 - Iakovos Mavroidis, Ioannis Mavroidis, Ioannis Papaefstathiou:
Accelerating Emulation and Providing Full Chip Observability and Controllability. 84-94 - Conference Reports. 95
- Test Technology TC Newsletter. 96
- Scott Davidson:
Book Reviews: A guide for the wrapper perplexed. 98-99 - CEDA Currents. 100-101
- Design Automation Technical Committee Newsletter. 102-103
- Scott Davidson:
The Last Byte: Too many reboots. 104
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