default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDDASIP 2011: Tampere, Finland
- Jari Nurmi, Tapani Ahonen:
2011 Conference on Design and Architectures for Signal and Image Processing, DASIP 2011, Tampere, Finland, November 2-4, 2011. IEEE 2011, ISBN 978-1-4577-0620-2
System simulation and processor generation
- Julien Peeters, Nicolas Ventroux, Tanguy Sassolas, Lionel Lacassagne:
A systemc TLM framework for distributed simulation of complex systems with unpredictable communication. 12-19 - Takieddine Majdoub, Sébastien Le Nours, Olivier Pasquier, Fabienne Nouvel:
Performance evaluation of an automotive distributed architecture based on HPAV communication protocol using a transaction level modeling approach. 20-26 - Mathieu Rosiere, Jean Lou Desbarbieux, Nathalie Drach, Franck Wajsbürt:
Morpheo: A high-performance processor generator for a FPGA implementation. 27-34 - Nicolas Siret, Jean-François Nezan, Aimad Rhatay:
Design of a processor optimized for syntax parsing in video decoders. 35-43
Low power design & methodologies
- Santhosh Kumar Rethinagiri, Rabie Ben Atitallah, Smaïl Niar, Eric Senn, Jean-Luc Dekeyser:
Fast and accurate hybrid power estimation methodology for embedded systems. 45-51 - Bassem Ouni, Cécile Belleudy, Sébastien Bilavarn, Eric Senn:
Embedded operating systems energy overhead. 52-57
Reconfigurable systems & tools for signal & image processing - Part 1
- Vincent Brost, Charles Meunier, Debyo Saptono, Fan Yang:
Flexible VLIW processor based on FPGA for real-time image processing. 59-66 - Matthias Birk, Alexander Guth, Michael Zapf, Matthias Norbert Balzer, Nicole V. Ruiter
, Michael Hübner, Jürgen Becker:
Acceleration of image reconstruction in 3D ultrasound computer tomography: An evaluation of CPU, GPU and FPGA computing. 67-74 - Samuel Garcia, Bertrand Granado:
Task model and online operating system API for hardware tasks in OLLAF platform. 75-81
Signal and image processing on GPU
- Sylvain Huet, Vincent Boulos, Vincent Fristot, Luc Salvo:
DFG implementation on multi GPU cluster with computation-communication overlap. 83-90 - Youngsub Ko, Youngmin Yi, Soonhoi Ha:
An efficient parallel motion estimation algorithm and X264 parallelization in CUDA. 91-98
Dynamic architectures & adaptive management for image & signal processing
- Emanuele Cannella, Onur Derin, Todor P. Stefanov:
Middleware approaches for adaptivity of Kahn Process Networks on Networks-on-Chip. 100-107 - Manel Hentati, Yassine Aoudni, Jean-François Nezan, Mohamed Abid, Olivier Déforges:
FPGA dynamic reconfiguration using the RVC technology: Inverse quantization case study. 108-114 - Matthieu Texier, Raphaël David, Karim Ben Chehida, Olivier Sentieys:
Graphic rendering application profiling on a shared memory MPSOC architecture. 115-121
Signal processing and processor designs
- Anand D. Darji, Rajul Bansal, S. N. Merchant, Arun N. Chandorkar:
High speed VLSI architecture for 2-D lifting Discrete Wavelet Transform. 123-128 - Teemu Laukkarinen, Jukka Suhonen, Timo D. Hämäläinen, Marko Hännikäinen:
Pilot studies of wireless sensor networks: Practical experiences. 129-136 - Chenglong Xiao, Emmanuel Casseau:
Efficient maximal convex custom instruction enumeration for extensible processors. 137-143 - Roberto Airoldi, Fabio Garzia, Jari Nurmi:
Efficient FFT pruning algorithm for non-contiguous OFDM systems. 144-149 - Matthieu Texier, Erwan Piriou, Mathieu Thevenin, Raphaël David:
Designing processors using MAsS, a modular and lightweight instruction-level exploration tool. 150-155
Smart image sensors
- Jade Ayoub, Bertrand Granado, Olivier Romain, Yasser Mohanna:
A new approach to 3D form recognition within video capsule endoscopic. 157-163 - Fabio Cenni, Serge Scotti, Emmanuel Simeu:
A SystemC AMS/TLM platform for CMOS video sensors. 164-169
Methods & tools for dataflow programming
- Ghislain Roquier, Endri Bezati, Richard Thavot, Marco Mattavelli:
Hardware/software co-design of dataflow programs for reconfigurable hardware and multi-core platforms. 171-177 - Francesca Palumbo, Nicola Carta, Luigi Raffo:
The Multi-Dataflow Composer tool: A runtime reconfigurable HDL platform composer. 178-185 - Endri Bezati, Hervé Yviquel, Mickaël Raulet, Marco Mattavelli:
A unified hardware/software co-synthesis solution for signal processing systems. 186-191 - Ab Al-Hadi Ab Rahman, Hossam Amer, Anatoly Prihozhy, Christophe Lucarz, Marco Mattavelli:
Optimization methodologies for complex FPGA-based signal processing systems with CAL. 192-199
Reconfigurable systems & tools for signal & image processing - Part 1
- Natalie Frietsch, I. Pashkovskiy, Gert F. Trommer, Lars Braun, Matthias Birk, Michael Hübner, Jürgen Becker:
Development of a method for image-based motion estimation of a VTOL-MAV on FPGA. 201-208 - Tomasz Kryjak, Mateusz Komorkiewicz, Marek Gorgon:
Real-time moving object detection for video surveillance system in FPGA. 209-216 - Walter Stechele, Jan Hartmann, Erik Maehle:
An approach to self-learning multicore reconfiguration management applied on Robotic Vision. 217-222 - Frédéric Amiel, Thomas Ea, Vashishtha Vinay:
Power consumption improvement with residue code for fault tolerance on SRAM FPGA. 223-228
Poster Session: Main Track
- Youssef Souissi, Jean-Luc Danger, Sylvain Guilley, Shivam Bhasin, Maxime Nassar:
Embedded systems security: An evaluation methodology against Side Channel Attacks. 230-237 - Andreas Dahlin, Fareed Jokhio, Johan Lilius, Jérôme Gorin, Mickaël Raulet:
Interfacing and scheduling legacy code within the Canals framework. 238-245 - Ville Kaseva, Timo D. Hämäläinen, Marko Hännikäinen:
Range-free algorithm for energy-efficient indoor localization in Wireless Sensor Networks. 246-253 - Jukka Saastamoinen, Jari Kreku:
Application workload model generation methodologies for system-level design exploration. 254-260 - Carlo Condo, Guido Masera:
A flexible NoC-based LDPC code decoder implementation and bandwidth reduction methods. 261-268 - Majdi Elhaji, Brahim Attia, Abdelkrim Zitouni, Rached Tourki, Samy Meftali, Jean-Luc Dekeyser:
FeRoNoC: Flexible and extensible Router implementation for diagonal mesh topology. 269-276 - Mohsen Amiri Farahani, Eduardo Castillo Guerra, Bruce G. Colpitts:
A new algorithm for realization of FIR filters using multiple constant multiplications. 277-283 - Daniela Genius, Nicolas Pouillon:
Analyzing software inter-task communication channels on a clustered shared memory multi processor system-on-chip. 284-291 - Thomas Schlechter:
Multiplier free filter bank based concept for blocker detection in LTE systems. 292-298 - Markku Hänninen, Jukka Suhonen, Timo D. Hämäläinen, Marko Hännikäinen:
Practical monitoring and analysis tool for WSN testing. 299-306
Poster Session: Reconfigurable Systems & Tools for Signal & Image Processing
- Sana Cherif, Chiraz Trabelsi, Samy Meftali, Jean-Luc Dekeyser:
High level design of adaptive distributed controller for partial dynamic reconfiguration in FPGA. 308-315 - François Duhem, Fabrice Muller, Philippe Lorenzini:
Methodology for designing partially reconfigurable systems using transaction-level modeling. 316-322
Poster Session: Dynamic Architectures & Adaptive Management for Image & Signal Processing
- Hung-Manh Pham, Sébastien Pillement, Olivier Pasquier, Sébastien Le Nours:
A framework for the design of reconfigurable fault tolerant architectures. 324-331 - Gilberto Ochoa, El-Bay Bourennane, Hassan Rabah, Ouassila Labbani:
High-level modelling and automatic generation of dynamicaly reconfigurable systems. 332-339
Poster Session: Smart Image Sensors
- Yves Blanchard, Antoine Dupret, Arnaud Peizerat:
Systemc modelization for fast validation of imager architectures. 341-345
Poster Session: Signal and Image Processing on GPU
- Antoine Pedron, Lionel Lacassagne, Franck Bimbard, Stéphane Le Berre:
Parallelization of an ultrasound reconstruction algorithm for non destructive testing on multicore CPU and GPU. 347-
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-02-24 21:18 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
