default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID24. FPGA 2016: Monterey, CA, USA
- Deming Chen, Jonathan W. Greene:
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, USA, February 21-23, 2016. ACM 2016, ISBN 978-1-4503-3856-1
Workshop on Overlay Architectures for FPGAs
- Hayden Kwok-Hay So
, John Wawrzynek:
OLAF'16: Second International Workshop on Overlay Architectures for FPGAs. 1
Designers' Day Session 1: Hardware Features
- Gregg Baeckler:
HyperPipelining of High-Speed Interface Logic. 2 - Pankaj Shanker:
Spatial Debug & Debug Without Re-programming in FPGAs: On-Chip debugging in FPGAs. 3
Designers' Day Session 2: System Level Methodology
- Vinod Kathail, James Hwang, Welson Sun, Yogesh Chobe, Tom Shui, Jorge Carrillo:
SDSoC: A Higher-level Programming Environment for Zynq SoC and Ultrascale+ MPSoC. 4 - Tan Nguyen, Swathi T. Gurumani, Kyle Rupnow, Deming Chen:
FCUDA-SoC: Platform Integration for Field-Programmable SoC with the CUDA-to-FPGA Compiler. 5-14 - Shlomi Alkalay, Hari Angepat, Adrian M. Caulfield, Eric S. Chung, Oren Firestein, Michael Haselman, Stephen Heil, Kyle Holohan, Matt Humphrey, Tamás Juhász, Puneet Kaur, Sitaram Lanka, Daniel Lo, Todd Massengill, Kalin Ovtcharov, Michael Papamichael, Andrew Putnam, Raja Seera, Rimon Tadros, Jason Thong, Lisa Woods, Derek Chiou, Doug Burger:
Agile Co-Design for a Reconfigurable Datacenter. 15
Technical Session 1: Neural Networks and OpenCL
- Naveen Suda, Vikas Chandra, Ganesh Dasika, Abinash Mohanty, Yufei Ma, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao:
Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks. 16-25 - Jiantao Qiu, Jie Wang, Song Yao, Kaiyuan Guo, Boxun Li, Erjin Zhou, Jincheng Yu, Tianqi Tang, Ningyi Xu, Sen Song, Yu Wang, Huazhong Yang:
Going Deeper with Embedded FPGA Platform for Convolutional Neural Network. 26-35 - Bingzhe Li, M. Hassan Najafi, David J. Lilja:
Using Stochastic Computing to Reduce the Hardware Requirements for a Restricted Boltzmann Machine Classifier. 36-41 - Shih-Hao Hung, Min-Yu Tsai, Bo-Yi Huang, Chia-Heng Tu:
A Platform-Oblivious Approach for Heterogeneous Computing: A Case Study with Monte Carlo-based Simulation for Medical Applications. 42-47 - Nadesh Ramanathan, John Wickerson, Felix Winterstein, George A. Constantinides:
A Case for Work-stealing on FPGAs with OpenCL Atomics. 48-53
Technical Session 2: Cooling and Clocking
- Zhiyuan Yang, Ankur Srivastava:
Physical Design of 3D FPGAs Embedded with Micro-channel-based Fluidic Cooling. 54-63 - Carl Ebeling, Dana How, David M. Lewis, Herman Schmit:
Stratix™ 10 High Performance Routable Clock Networks. 64-73 - Henri Fraisse, Abhishek Joshi, Dinesh Gaitonde, Alireza Kaviani:
Boolean Satisfiability-Based Routing and Its Application to Xilinx UltraScale Clock Network. 74-79
Technical Session 3: Circuit Design, Graph Processing Applications
- Grace Zgheib, Manana Lortkipanidze, Muhsen Owaida, David Novo, Paolo Ienne:
FPRESSO: Enabling Express Transistor-Level Exploration of FPGA Architectures. 80-89 - Safeen Huda, Jason Helge Anderson:
Towards PVT-Tolerant Glitch-Free Operation in FPGAs. 90-99 - Timothy A. Linscott, Benjamin Gojman, Raphael Rubin, André DeHon:
Pitfalls and Tradeoffs in Simultaneous, On-Chip FPGA Delay Measurement. 100-104 - Guohao Dai, Yuze Chi, Yu Wang, Huazhong Yang:
FPGP: Graph Processing Framework on FPGA A Case Study of Breadth-First Search. 105-110 - Tayo Oguntebi, Kunle Olukotun:
GraphOps: A Dataflow Library for Graph Analytics Acceleration. 111-117
Technical Session 4: Applications and System-level Tools
- Nikolaos Alachiotis, Gabriel Weisz:
High Performance Linkage Disequilibrium: FPGAs Hold the Key. 118-127 - Hsin-Jung Yang, Kermin Fleming, Michael Adler, Felix Winterstein, Joel S. Emer:
LMC: Automatic Resource-Aware Program-Optimized Memory Partitioning. 128-137 - Jincheng Su, Fan Yang, Xuan Zeng, Dian Zhou:
Efficient Memory Partitioning for Parallel Data Access via Data Reuse. 138-147
Evening Panel
- Derek Chiou:
Intel Acquires Altera: How Will the World of FPGAs be Affected? 148
Technical Session 5: Architecture and Tools
- Tuan D. A. Nguyen, Akash Kumar:
PRFloor: An Automatic Floorplanner for Partially Reconfigurable FPGA Systems. 149-158 - David M. Lewis, Gordon R. Chiu, Jeffrey Chromczak, David R. Galloway, Ben Gamsa, Valavan Manohararajah, Ian Milton, Tim Vanderhoek, John Van Dyken:
The Stratix™ 10 Highly Pipelined FPGA Architecture. 159-168 - Que Yanghua, Chinnakkannu Adaikkala Raj, Harnhua Ng, Kirvy Teo, Nachiket Kapre:
Case for Design-Specific Machine Learning in Timing Closure of FPGA Designs. 169-172 - Sen Ma, Zeyad Aklah, David Andrews:
Just In Time Assembly of Accelerators. 173-178 - Paul Grigoras, Pavel Burovskiy, Wayne Luk:
CASK: Open-Source Custom Architectures for Sparse Kernels. 179-184
Technical Session 6: System-level Tools
- Nachiket Kapre, Deheng Ye:
GPU-Accelerated High-Level Synthesis for Bitwidth Optimization of FPGA Datapaths. 185-194 - Janarbek Matai, Dustin Richmond, Dajung Lee, Zac Blair, Qiongzhi Wu, Amin Abazari, Ryan Kastner:
Resolve: Generation of High-Performance Sorting Architectures from High-Level Synthesis. 195-204 - Michael J. Wirthlin, Andrew M. Keller, Chase McCloskey, Parker Ridd, David S. Lee, Jeffrey Draper:
SEU Mitigation and Validation of the LEON3 Soft Processor Using Triple Modular Redundancy for Space Processing. 205-214
Technical Session 7: High-level Synthesis and Tools
- François Serre, Thomas Holenstein, Markus Püschel:
Optimal Circuits for Streamed Linear Permutations Using RAM. 215-223 - Xinheng Liu, Yao Chen, Tan Nguyen, Swathi T. Gurumani, Kyle Rupnow, Deming Chen:
High Level Synthesis of Complex Applications: An H.264 Video Decoder. 224-233 - Xitong Gao, John Wickerson, George A. Constantinides:
Automatically Optimizing the Latency, Area, and Accuracy of C Programs for High-Level Synthesis. 234-243
Technical Session 8: Applications
- David Boland:
Reducing Memory Requirements for High-Performance and Numerically Stable Gaussian Elimination. 244-253 - Muhammed Al Kadi, Benedikt Janßen, Michael Hübner:
FGPU: An SIMT-Architecture for FPGAs. 254-263 - Gabriel Weisz, Joseph Melber, Yu Wang, Kermin Fleming, Eriko Nurvitadhi, James C. Hoe:
A Study of Pointer-Chasing Performance on Shared-Memory Processor-FPGA Systems. 264-273
Poster Session 1
- Mohammed Shaaban Ibraheem, Syed Zahid Ahmed, Khalil Hachicha, Sylvain Hochberg, Patrick Garda:
A Low DDR Bandwidth 100FPS 1080p Video 2D Discrete Wavelet Transform Implementation on FPGA (Abstract Only). 274 - Ehsan Ghasemi, Paul Chow:
A Scalable Heterogeneous Dataflow Architecture For Big Data Analytics Using FPGAs (Abstract Only). 274 - Ze-ke Wang, Hui Yan Cheah, Johns Paul, Bingsheng He, Wei Zhang:
Accelerating Database Query Processing on OpenCL-based FPGAs (Abstract Only). 274 - Daolu Zha, Xi Jin, Tian Xiang:
An Improved Global Stereo-Matching on FPGA for Real-Time Applications (Abstract Only). 274 - Wenchao Qian, Christopher Babecki, Robert Karam, Swarup Bhunia:
ENFIRE: An Energy-efficient Fine-grained Spatio-temporal Reconfigurable Computing Fabric (Abstact Only). 275 - Pingakshya Goswami, Dinesh Bhatia:
Floorplanning of Partially Reconfigurable Design on Heterogeneous FPGA (Abstract Only). 275 - Matthias Hinkfoth, Ralf Salomon:
Increasing the Utility of Self-Calibration Methods in High-Precision Time Measurement Systems (Abstract Only). 275 - James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides:
Knowledge is Power: Module-level Sensing for Runtime Optimisation (Abstact Only). 276 - Li Ting, Harri Wijaya, Nachiket Kapre:
Machine-Learning driven Auto-Tuning of High-Level Synthesis for FPGAs (Abstract Only). 276 - Ronak Kogta, Suresh Purini, Ajit Mathew:
Re-targeting Optimization Sequences from Scalar Processors to FPGAs in HLS compilers (Abstract Only). 276
Poster Session 2
- Jie Lei, Yu-Ting Chen, Yunsong Li, Jason Cong:
A High-throughput Architecture for Lossless Decompression on FPGA Designed Using HLS (Abstract Only). 277 - Girish Deshpande, Dinesh K. Bhatia:
An Activity Aware Placement Approach For 3D FPGAs (Abstract Only). 277 - Tianqi Wang, Bo Peng, Xi Jin:
an Extensible Heterogeneous Multi-FPGA Framework for Accelerating N-body Simulation (Abstract Only). 277 - Sabrina Zereen, Sundeep Lal, Mohammed A. S. Khalid, Sazzadur Chowdhury:
An FPGA-Based Controller for a 77 GHz MEMS Tri-Mode Automotive Radar (Abstract Only). 278 - Bo Peng, Tianqi Wang, Xi Jin, Chuanjun Wang:
An FPGA-SOC Based Accelerating Solution for N-body Simulations in MOND (Abstract Only). 278 - Liwei Yang, Swathi T. Gurumani, Suhaib A. Fahmy, Deming Chen, Kyle Rupnow:
Automated Verification Code Generation in HLS Using Software Execution Traces (Abstract Only). 278 - Jing Ye, Yu Hu, Xiaowei Li:
DCPUF: Placement and Routing Constraint based Dynamically Configured Physical Unclonable Function on FPGA (Abstact Only). 279 - Sebastien Bellon, Claudio Favi, Miroslaw Malek, Marco Macchetti, Francesco Regazzoni:
Evaluating the Impact of Environmental Factors on Physically Unclonable Functions (Abstract Only). 279 - Yu Bai, Mingjie Lin:
Stochastic-Based Spin-Programmable Gate Array with Emerging MTJ Device Technology (Abstract Only). 279 - Zhen Yang, Jian Wang, Meng Yang, Jinmei Lai:
Testing FPGA Local Interconnects Based on Repeatable Configuration Modules (Abstract Only). 280
Poster Session 3
- Stefan Visser, Harald Homulle, Edoardo Charbon:
A 1 GSa/s, Reconfigurable Soft-core FPGA ADC (Abstract Only). 281 - Xifan Tang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
A Full-Capacity Local RoutingArchitecture for FPGAs (Abstract Only). 281 - Yu-Ting Chen, Jason Cong, Zhenman Fang, Peipei Zhou:
ARAPrototyper: Enabling Rapid Prototyping and Evaluation for Accelerator-Rich Architecture (Abstact Only). 281 - Aaron Landy, Greg Stitt:
Doubling FPGA Throughput via a Soft SerDes Architecture for Full-Bandwidth Serial Pipelining (Abstract Only). 282 - Cédric Marchand, Lilian Bossuet, Abdelkarim Cherkaoui:
Enhanced TERO-PUF Implementations and Characterization on FPGAs (Abstract Only). 282 - Yunxuan Yu, Lei He:
FPGA Power Estimation Using Automatic Feature Selection (Abstract Only). 282 - Sizhuo Zhang, Hari Angepat, Derek Chiou:
HGum: Messaging Framework for Hardware Accelerators (Abstact Only). 283 - Sayeh Sharifymoghaddam, Ali Sheikholeslami:
Low-Swing Signaling for FPGA Power Reduction (Abstract Only). 283 - Mohammed Alawad, Mingjie Lin:
Stochastic-Based Convolutional Networks with Reconfigurable Logic Fabric (Abstract Only). 283 - Nimish Agashiwala, Satya Prakash Upadhyay, Kia Bazargan:
t-QuadPlace: Timing Driven Quadratic Placement using Quadrisection Partitioning for FPGAs (Abstact Only). 284
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-02-26 20:33 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
