default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDISLPED 2023: Vienna, Austria
- IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2023, Vienna, Austria, August 7-8, 2023. IEEE 2023, ISBN 979-8-3503-1175-4
- Teyuh Chou, Fernando García-Redondo
, Paul N. Whatmough, Zhengya Zhang:
AR-PIM: An Adaptive-Range Processing-in-Memory Architecture. 1-6 - Chukwufumnanya Ogbogu, Soumen Mohapatra, Biresh Kumar Joardar, Janardhan Rao Doppa, Deuk Heo, Krishnendu Chakrabarty, Partha Pratim Pande:
Energy-Efficient ReRAM-Based ML Training via Mixed Pruning and Reconfigurable ADC. 1-6 - Yujin Nam, Minxuan Zhou, Saransh Gupta, Gabrielle De Micheli, Rosario Cammarota, Chris Wilkerson, Daniele Micciancio, Tajana Rosing:
Efficient Machine Learning on Encrypted Data Using Hyperdimensional Computing. 1-6 - Qiankai Cao, Xi Chen, Jie Gu:
Development of Tropical Algebraic Accelerator with Energy Efficient Time-Domain Computing for Combinatorial Optimization and Machine Learning. 1-6 - Gwanjong Park, Osama Khan, Euiseong Seo:
Energy-Harvesting-Aware Adaptive Inference of Deep Neural Networks in Embedded Systems. 1-6 - Sudipta Mondal, Ramprasath S, Ziqing Zeng, Kishor Kunal, Sachin S. Sapatnekar:
A Multicore GNN Training Accelerator. 1-6 - Utkarsh Saxena, Kaushik Roy:
Partial-Sum Quantization for Near ADC-Less Compute-In-Memory Accelerators. 1-6 - Gourav Datta, Haoqin Deng, Robert Aviles, Zeyu Liu, Peter A. Beerel:
Bridging the Gap Between Spiking Neural Networks & LSTMs for Latency & Energy Efficiency. 1-6 - Dina Hussein, Taha Belkhouja, Ganapati Bhat, Janardhan Rao Doppa:
Energy-Efficient Missing Data Recovery in Wearable Devices: A Novel Search-Based Approach. 1-6 - Matteo Risso, Alessio Burrello, Giuseppe Maria Sarda, Luca Benini, Enrico Macii, Massimo Poncino, Marian Verhelst, Daniele Jahier Pagliari:
Precision-aware Latency and Energy Balancing on Multi-Accelerator Platforms for DNN Inference. 1-6 - Omar Ghazal, Simranjeet Singh, Tousif Rahman, Shengqi Yu, Yujin Zheng, Domenico Balsamo, Sachin B. Patkar, Farhad Merchant, Fei Xia, Alex Yakovlev, Rishad A. Shafik:
IMBUE: In-Memory Boolean-to-CUrrent Inference ArchitecturE for Tsetlin Machines. 1-6 - Zijie Chen, Yiming Gao, Junrui Liang:
A Self-Powered Predictive Maintenance System Based on Piezoelectric Energy Harvesting and TinyML. 1-6 - Deepraj Soni, Mohammed Nabeel, Negar Neda, Ramesh Karri, Michail Maniatakos, Brandon Reagen:
Quantifying the Overheads of Modular Multiplication. 1-6 - Shien Zhu, Shuo Huai, Guochu Xiong, Weichen Liu:
iMAT: Energy-Efficient In-Memory Acceleration for Ternary Neural Networks With Sparse Dot Product. 1-6 - Gamze Islamoglu, Moritz Scherer, Gianna Paulin, Tim Fischer, Victor J. B. Jung, Angelo Garofalo, Luca Benini:
ITA: An Energy-Efficient Attention and Softmax Accelerator for Quantized Transformers. 1-6 - Yong-Cheng Liaw, Shuo-Han Chen, Yuan-Hao Chang, Yu-Pei Liang:
Sky-NN: Enabling Efficient Neural Network Data Processing with Skyrmion Racetrack Memory. 1-6 - Chukwufumnanya Ogbogu, Madeleine Abernot, Corentin Delacour, Aida Todri-Sanial, Sudeep Pasricha, Partha Pratim Pande:
Energy-Efficient Machine Learning Acceleration: From Technologies to Circuits and Systems. 1-8 - Johnny Rhe, Kang Eun Jeon, Jong Hwan Ko:
PAIRS: Pruning-AIded Row-Skipping for SDK-Based Convolutional Weight Mapping in Processing-In-Memory Architectures. 1-6 - Erich Malan, Valentino Peluso, Andrea Calimera, Enrico Macii:
Enabling DVFS Side-Channel Attacks for Neural Network Fingerprinting in Edge Inference Services. 1-6 - Doyeon Won, Soomin Kim, Taewhan Kim:
Machine Learning Driven Synthesis of Clock Gating. 1-6 - Guowei Yang, Cansu Demirkiran, Zeynep Ece Kizilates, Carlos A. Ríos Ocampo, Ayse K. Coskun, Ajay Joshi:
Processing-in-Memory Using Optically-Addressed Phase Change Memory. 1-6 - Heewoo Kim, Haojie Ye, Trevor N. Mudge, Ronald G. Dreslinski, Nishil Talati:
RecPIM: A PIM-Enabled DRAM-RRAM Hybrid Memory System For Recommendation Models. 1-6 - Kyeong-Jun Lee, ByungJun Kim, Han-Gyeol Mun, Seunghyun Moon, Jae-Yoon Sim:
Joint Optimization of Cache Management and Graph Reordering for GCN Acceleration. 1-6 - Jina Park, Kyuseung Han, Eunjin Choi, Sukho Lee, Jae-Jin Lee, Woojoo Lee, Massoud Pedram:
Florian: Developing a Low-Power RISC-V Multicore Processor with a Shared Lightweight FPU. 1-6 - Vahidreza Moghaddas, Hammam Kattan, Tim Bücher, Mikail Yayla, Jian-Jia Chen, Hussam Amrouch:
Temperature-Aware Memory Mapping and Active Cooling of Neural Processing Units. 1-6 - Zexi Ji, Hanrui Wang, Miaorong Wang, Win-San Khwa, Meng-Fan Chang, Song Han, Anantha P. Chandrakasan:
A Fully-Integrated Energy-Scalable Transformer Accelerator Supporting Adaptive Model Configuration and Word Elimination for Language Understanding on Edge Devices. 1-6 - Dongho Ha, Won Woo Ro, Hung-Wei Tseng:
TensorCV: Accelerating Inference-Adjacent Computation Using Tensor Processors. 1-6 - Nezam Rohbani, Mohammad Arman Soleimani, Hamid Sarbazi-Azad:
CoolDRAM: An Energy-Efficient and Robust DRAM. 1-6 - Yiqi Jing, Yiyang Sun, Xiao Wang, Wentao Zhao, Meng Wu, Fengyun Yan, Yufei Ma, Le Ye, Tianyu Jia:
DCIM-3DRec: A 3D Reconstruction Accelerator with Digital Computing-in-Memory and Octree-Based Scheduler. 1-6 - Sepehr Tabrizchi, Shaahin Angizi, Arman Roohi:
Ocellus: Highly Parallel Convolution-in-Pixel Scheme Realizing Power-Delay-Efficient Edge Intelligence. 1-6 - Tsung-Yen Hsu, Yi-Shen Chen, Yun-Chih Chen, Yuan-Hao Chang, Tei-Wei Kuo:
REFROM: Responsive, Energy-Efficient Frame Rendering for Mobile Devices. 1-6 - Jakang Lee, Jaeseung Lee, Seonghyeon Park, Seokhyeong Kang:
Multi-Source Transfer Learning for Design Technology Co-Optimization. 1-6 - Gaurav Narang, Raid Ayoub, Michael Kishinevsky, Janardhan Rao Doppa, Partha Pratim Pande:
Uncertainty-Aware Online Learning for Dynamic Power Management in Large Manycore Systems. 1-6 - Wenwen Xu, Zheyu Zhang, Yuankai Xu, Jing Li, Yehan Ma, Yier Jin, Christopher D. Gill, Xuan Zhang, An Zou:
Energy Efficient Real-Time Scheduling on Heterogeneous Architectures with Self-Suspension. 1-6 - Dongrui Li, Tomomasa Yamasaki, Aarthy Mani, Anh Tuan Do, Niangjun Chen, Bo Wang:
LAXOR: A Bit-Accurate BNN Accelerator with Latch-XOR Logic for Local Computing. 1-6 - Edgar Luhulima, Madeleine Abernot, Federico Corradi, Aida Todri-Sanial:
Digital Implementation of On-Chip Hebbian Learning for Oscillatory Neural Network. 1-6 - Sandra Maria Shaji, Lingjun Zhu, Jun-Sik Yoon, Sung Kyu Lim:
A Comparative Study on Front-Side, Buried and Back-Side Power Rail Topologies in 3nm Technology Node. 1-6 - Jung Gyu Min, Dongyun Kam, Younghoon Byun, Gunho Park, Youngjoo Lee:
Energy-Efficient RISC-V-Based Vector Processor for Cache-Aware Structurally-Pruned Transformers. 1-6 - Yifan Zhang, Arnav Vaibhav Malawade, Xiaofang Zhang, Yuhui Li, DongHwan Seong, Mohammad Abdullah Al Faruque, Sitao Huang:
CARMA: Context-Aware Runtime Reconfiguration for Energy-Efficient Sensor Fusion. 1-6 - Hyunmin Kim, Sungju Ryu:
Teleport: A High-Performance ShiftNet Hardware Accelerator with Fused Layer Computation. 1-6 - Chia-Chih Lin, Ming-Syan Chen:
Learning from Output Transitions: A Chosen Challenge Strategy for ML Attacks on PUFs. 1-6 - Mahya Morid Ahmadi, Lilas Alrahis, Ozgur Sinanoglu, Muhammad Shafique:
FPGA-Patch: Mitigating Remote Side-Channel Attacks on FPGAs using Dynamic Patch Generation. 1-6 - Zeqing Li, Yongwei Wu, Youhui Zhang:
Multi-Objective Optimization for Floating Point Mix-Precision Tuning. 1-6 - Daniel Xing, Yuntao Liu, Ankur Srivastava:
Low Power Logic Obfuscation Through System Level Clock Gating. 1-6 - Christian Lanius, Florian Freye, Shutao Zhang, Tobias Gemmeke:
Hardware Trojans in fdSOI. 1-6 - Hyun Woo Oh, Seongmo An, Won Sik Jeong, Seung Eun Lee:
RF2P: A Lightweight RISC Processor Optimized for Rapid Migration from IEEE-754 to Posit. 1-6 - Khaled Sidahmed Sidahmed Alamin, Francesco Daghero, Giovanni Pollo, Daniele Jahier Pagliari, Yukai Chen, Enrico Macii, Massimo Poncino, Sara Vinco:
Model-Driven Dataset Generation for Data-Driven Battery SOH Models. 1-6 - Christian Lanius, Jie Lou, Johnson Loh, Tobias Gemmeke:
Automatic Generation of Structured Macros Using Standard Cells ‒ Application to CIM. 1-6 - Kang Eun Jeon, Johnny Rhe, Hyeonsu Bang, Jong Hwan Ko:
Weight-Aware Activation Mapping for Energy-Efficient Convolution on PIM Arrays. 1-6 - Octavian Pascu, Catalin Visan, Georgian Nicolae, Mihai Boldeanu, Horia Cucu, Cristian Diaconu, Andi Buzo, Georg Pelz:
Efficient Multi-Objective Optimization for PVT Variation-Aware Circuit Sizing Using Surrogate Models and Smart Corner Sampling. 1-6 - Kunal Bharathi, Sunil P. Khatri, Jiang Hu:
Scaled Population Division for Approximate Computing. 1-6 - Jingxiao Ma, Sherief Reda:
WeNet: Configurable Neural Network with Dynamic Weight-Enabling for Efficient Inference. 1-6 - Rakshith Saligram, Suman Datta, Arijit Raychowdhury:
Cryogenic CMOS as an Enabler for Low Power Dynamic Logic. 1-6 - Yu-Shao Lai, Shuo-Han Chen, Yuan-Hao Chang:
Enabling Highly-Efficient DNA Sequence Mapping via ReRAM-based TCAM. 1-6
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-02-28 21:51 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
