default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID38th MICRO 2005: Barcelona, Spain
- 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 12-16 November 2005, Barcelona, Spain. IEEE Computer Society 2005, ISBN 0-7695-2440-0
Introduction
- Message from the General Chairs.
- Message from the Program Co-Chairs.
Keynote I
- James A. Kahle:
The Cell Processor Architecture. 3
Session I: Register File and Memory System
- David W. Oehmke, Nathan L. Binkert, Trevor N. Mudge, Steven K. Reinhardt:
How to Fake 1000 Registers. 7-18 - Stephen Hines, Gary S. Tyson, David B. Whalley:
Reducing Instruction Fetch Cost by Packing Instructions into RegisterWindows. 19-29 - Arvind Krishnaswamy, Rajiv Gupta
:
Efficient Use of Invisible Registers in Thumb Code. 30-42
Session II: Processor Design and Optimization
- Hyesoon Kim, Onur Mutlu, Jared Stark, Yale N. Patt:
Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution. 43-54 - Pierre Salverda, Craig B. Zilles:
A Criticality Analysis of Clustering in Superscalar Processors. 55-66 - Matt T. Yourst, Kanad Ghose:
Incremental Commit Groups for Non-Atomic Trace Processing. 67-80
Session III: Multithreading / CMP
- Taku Ohsawa, Masamichi Takagi, Shoji Kawahara, Satoshi Matsushita:
Pinot: Speculative Multi-threading Processor Architecture Exploiting Parallelism over a Wide Range of Granularities. 81-92 - Jiwei Lu, Abhinav Das, Wei-Chung Hsu, Khoa Nguyen, Santosh G. Abraham:
Dynamic Helper Threaded Prefetching on the Sun UltraSPARC CMP Processor. 93-104 - Guilherme Ottoni, Ram Rangan, Adam Stoler, David I. August:
Automatic Thread Extraction with Decoupled Software Pipelining. 105-118
Session IV: Compilers and Dynamic Optimization
- Samuel Larsen, Rodric M. Rabbah, Saman P. Amarasinghe:
Exploiting Vector Parallelism in Software Pipelined Loops. 119-129 - Michael D. Bond, Kathryn S. McKinley:
Continuous Path and Edge Profiling. 130-140 - David Hiniker, Kim M. Hazelwood, Michael D. Smith:
Improving Region Selection in Dynamic Optimization Systems. 141-154
Keynote II
- Norman P. Jouppi:
The Future Evolution of High-Performance Microprocessors. 155
Session V: Memory Disambiguation and Optimization
- Tingting Sha, Milo M. K. Martin, Amir Roth:
Scalable Store-Load Forwarding via Store Queue Index Prediction. 159-170 - Sam S. Stone, Kevin M. Woley, Matthew I. Frank:
Address-Indexed Memory Disambiguation and Store-to-Load Forwarding. 171-182 - Yuan Chou, Lawrence Spracklen, Santosh G. Abraham:
Store Memory-Level Parallelism Optimizations for Commercial Applications. 183-196
Session VI: Processor Design
- Fred A. Bower, Daniel J. Sorin, Sule Ozev:
A Mechanism for Online Diagnosis of Hard Faults in Microprocessors. 197-208 - Cyrus Bazeghi, Francisco J. Mesa-Martinez, Jose Renau:
uComplexity: Estimating Processor Design Effort. 209-218 - Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott A. Mahlke:
Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System. 219-232
Session VII: Speculation
- Onur Mutlu, Hyesoon Kim, Yale N. Patt:
Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns. 233-244 - Meyrem Kirman, Nevin Kirman, José F. Martínez:
Cherry-MP: Correctly Integrating Checkpointed Early Resource Recycling in Chip Multiprocessors. 245-256 - Smruti R. Sarangi, Wei Liu, Yuanyuan Zhou:
ReSlice: Selective Re-Execution of Long-Retired Misspeculated Instructions Using Forward Slicing. 257-270
Session VIII: Power, Temperature and Fault Management
- Qiang Wu, Margaret Martonosi, Douglas W. Clark, Vijay Janapa Reddi, Dan Connors, Youfeng Wu, Jin Lee, David M. Brooks:
A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance. 271-282 - Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I. Ismail:
Thermal Management of On-Chip Caches Through Power Density Minimization. 283-293 - Michael D. Powell, Ethan Schuchman, T. N. Vijaykumar:
Balancing Resource Utilization to Mitigate Power Density in Processor Pipelines. 294-304 - Tzvetan S. Metodi, Darshan D. Thaker, Andrew W. Cross:
A Quantum Logic Array Microarchitecture: Scalable Quantum Data Movement and Computation. 305-318
Session IX: Processor Architecture and Programming
- Ronald D. Barnes, Shane Ryoo, Wen-mei W. Hwu:
"Flea-flicker" Multipass Pipelining: An Alternative to the High-Power Out-of-Order Offense. 319-330 - Jan-Willem van de Waerdt, Stamatis Vassiliadis, Sanjeev Das, Sebastian Mirolo, Chris Yen, Bill Zhong, Carlos Basto, Jean-Paul van Itegem, Dinesh Amirtharaj, Kulbhushan Kalra, Pedro Rodriguez, Hans Van Antwerpen:
The TM3270 Media-Processor. 331-342 - Jayanth Gummaraju, Mendel Rosenblum:
Stream Programming on General-Purpose Processors. 343-354 - Victor Moya Del Barrio, Carlos González, Jordi Roca, Agustín Fernández, Roger Espasa:
Shader Performance Analysis on a Modern GPU Architecture. 355-364
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-02-24 21:19 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
