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ORCIDIPSJ Transactions on System LSI Design Methodology, Volume 7
Volume 7, February 2014
- Hiroyuki Tomiyama:
Message from the Editor-in-Chief. 1
- Jingcheng Zhuang, Robert Bogdan Staszewski
:
All-Digital RF Phase-Locked Loops Exploiting Phase Prediction. 2-15 - Tsung-Yi Ho:
Design Automation for Digital Microfluidic Biochips. 16-26
- Hao Zhang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Dynamic Power Consumption Optimization for Inductive-Coupling based Wireless 3D NoCs. 27-36 - Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada:
Impact of Resource Sharing and Register Retiming on Area and Performance of FPGA-based Designs. 37-45 - Satoshi Jo, Takeshi Matsumoto, Masahiro Fujita:
SAT-based Automatic Rectification and Debugging of Combinational Circuits with LUT Insertions. 46-55
- Krishnendu Chakrabarty, Mukesh Agrawal, Sergej Deutsch, Brandon Noia, Ran Wang, Fangming Ye:
Test and Design-for-Testability Solutions for 3D Integrated Circuits. 56-73
- Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa:
Energy-efficient High-level Synthesis for HDR Architecture with Multi-stage Clock Gating. 74-80
- Yuta Hagio, Masao Yanagisawa, Nozomu Togawa:
A Delay-variation-aware High-level Synthesis Algorithm for RDR Architectures. 81-90 - Eriko Nagai, Atsushi Hashimoto, Nagisa Ishiura:
Reinforcing Random Testing of Arithmetic Optimization of C Compilers by Scaling up Size and Number of Expressions. 91-100 - Xin Jiang, Lian Zeng, Takahiro Watanabe:
A Sophisticated Routing Algorithm in 3D NoC with Fixed TSVs for Low Energy and Latency. 101-109 - Yoichi Wakaba, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi:
An Area Efficient Regular Expression Matching Engine Using Partial Reconfiguration for Quick Pattern Updating. 110-118 - Shingo Kusakabe, Kenshu Seto:
Forwarding Unit Generation for Loop Pipelining in High-level Synthesis. 119-124
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