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ORCID"Area-Efficient Pipelined VLSI Architecture for Polar Decoder."
Weihang Tan et al. (2020)
- Weihang Tan, Antian Wang, Yunhao Xu, Yingjie Lao:
Area-Efficient Pipelined VLSI Architecture for Polar Decoder. ISVLSI 2020: 352-357
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