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ORCID42nd DAC 2005: San Diego, CA, USA
- William H. Joyner Jr., Grant Martin, Andrew B. Kahng:
Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005. ACM 2005, ISBN 1-59593-058-2
Panel
- Jay Vleeschhouwer, Warren East, Michael J. Fister, Aart J. de Geus, Walden C. Rhines, Jackson Hu, Rick Cassidy:
Differentiate and deliver: leveraging your partners. 1
Error-tolerant design
- Subhasish Mitra, Tanay Karnik, Norbert Seifert, Ming Zhang:
Logic soft errors in sub-65nm technologies design and CAD challenges. 2-4 - William Heidergott:
SEU tolerant device, circuit and processor design. 5-10
Microarchitecture-level power analysis and optimization techniques
- Diana Marculescu
, Emil Talpes:
Variability and energy awareness: a microarchitecture-level perspective. 11-16 - Peter Petrov, Daniel Tracy, Alex Orailoglu:
Energy-effcient physically tagged caches for embedded processors with virtual memory. 17-22 - Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha:
Hybrid simulation for embedded software energy estimation. 23-26 - Patrick Schaumont, Bo-Cheng Charles Lai, Wei Qin, Ingrid Verbauwhede:
Cooperative multithreading on 3mbedded multiprocessor architectures enables energy-scalable design. 27-30
Leakage analysis and optimization
- Feng Gao, John P. Hayes:
Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages. 31-36 - Afshin Abdollahi, Farzan Fallah, Massoud Pedram:
An effective power mode transition technique in MTCMOS circuits. 37-42 - Nikhil Jayakumar, Sandeep Dhar, Sunil P. Khatri:
A self-adjusting scheme to determine the optimum RBB by monitoring leakage currents. 43-46 - Lin Yuan, Gang Qu:
Enhanced leakage reduction Technique by gate replacement. 47-50
Analog macromodeling
- Ning Dong, Jaijeet S. Roychowdhury:
Automated nonlinear Macromodelling of output buffers for high-speed digital applications. 51-56 - Ying Wei, Alex Doboli:
Systematic development of analog circuit structural macromodels through behavioral model decoupling. 57-62 - Mengmeng Ding, Ranga Vemuri:
A combined feasibility and performance macromodel for analog circuits. 63-68
Panel
- Francine Bacchini, David Maliniak, Terry Doherty, Peter McShane, Suhas A. Pai, Sriram Sundararajan, Soo-Kwan Eo, Pascal Urard:
ESL: building the bridge between systems to silicon. 69-70
Statistical timing analysis
- Hongliang Chang, Vladimir Zolotov, Sambasivan Narayan, Chandu Visweswariah:
Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions. 71-76 - Yaping Zhan, Andrzej J. Strojwas, Xin Li, Lawrence T. Pileggi, David Newmark, Mahesh Sharma:
Correlation-aware statistical timing analysis with non-gaussian delay distributions. 77-82 - Lizheng Zhang, Weijen Chen, Yuhen Hu, John A. Gubner, Charlie Chung-Ping Chen:
Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model. 83-88 - Vishal Khandelwal, Ankur Srivastava:
A general framework for accurate statistical timing analysis considering correlations. 89-94
Embedded software
- Feihui Li, Mahmut T. Kandemir:
Locality-conscious workload assignment for array-based computations in MPSOC architectures. 95-100 - Stefan Valentin Gheorghita, Sander Stuijk, Twan Basten, Henk Corporaal:
Automatic scenario detection for improved WCET estimation. 101-104 - Jungeun Kim, Taewhan Kim:
Memory access optimization through combined code scheduling, memory allocation, and array binding in embedded system design. 105-110 - Ravindra Jejurikar, Rajesh K. Gupta:
Dynamic slack reclamation with procrastination scheduling in real-time embedded systems. 111-116
Advances in design-for-testability methods
- Erik H. Volkerink, Subhasish Mitra:
Response compaction with any number of unknowns using a new LFSR architecture. 117-122 - Qiang Xu, Nicola Nicolici, Krishnendu Chakrabarty:
Multi-frequency wrapper design and optimization for embedded cores under average power constraints. 123-128 - Irith Pomeranz:
N-detection under transparent-scan. 129-134 - Bo Yang, Kaijie Wu, Ramesh Karri:
Secure scan: a design-for-test architecture for crypto chips. 135-140
Advances in boundary element methods for parasitic extraction
- Chenggang Xu, Ranjit Gharpurey, Terri S. Fiez, Kartikeya Mayaram:
A green function-based parasitic extraction method for inhomogeneous substrate layers. 141-146 - Xin Hu, Jung Hoon Lee, Jacob White, Luca Daniel:
Analysis of full-wave conductor system impedance over substrate using novel integration techniques. 147-152 - Michael W. Beattie, Hui Zheng, Anirudh Devgan, Byron Krauter:
Spatially distributed 3D circuit models. 153-158 - Dipanjan Gope, Indranil Chowdhury, Vikram Jandhyala:
DiMES: multilevel fast direct solver based on multipole expansions for parasitic extraction of massively coupled 3D microelectronic structures. 159-162 - Rong Jiang, Yi-Hao Chang, Charlie Chung-Ping Chen:
ICCAP: a linear time sparse transformation and reordering algorithm for 3D BEM capacitance extraction. 163-166
Management Day Session
- Dennis Wassung, Yervant Zorian, Magdy S. Abadir, Mark Bapst, Colin Harris:
Choosing flows and methodologies for SoC design. 167
Panel
- Naveed A. Sherwani, Susan Lippincott Mack, Alex Alexanian, Premal Buch, Carlo Guardiani, Harold Lehon, Peter Rabkin, Atul Sharan:
DFM rules! 168-169 - Hang Li, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong:
Partitioning-based approach to fast on-chip decap budgeting and minimization. 170-175 - Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu:
Navigating registers in placement for clock network minimization. 176-181 - Yow-Tyng Nieh, Shih-Hsu Huang, Sheng-Yu Hsu:
Minimizing peak current via opposite-phase clock tree. 182-185 - Haihua Su, David Widiger, Chandramouli V. Kashyap, Frank Liu, Byron Krauter:
A noise-driven effective capacitance method with fast embedded noise rule calculation for functional noise analysis. 186-189 - Chong Zhao, Yi Zhao, Sujit Dey:
Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits. 190-195
Physical considerations in high-level synthesis
- Rajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Memik:
Temperature-aware resource allocation and binding in high-level synthesis. 196-201 - Xiaoyong Tang, Hai Zhou, Prithviraj Banerjee:
Leakage power optimization with dual-Vth library in high-level synthesis. 202-207 - Zhenyu (Peter) Gu, Jia Wang, Robert P. Dick, Hai Zhou:
Incremental exploration of the combined physical and behavioral design space. 208-213 - Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi:
Sign bit reduction encoding for low power applications. 214-217 - Tingyuan Nie, Tomoo Kisaka, Masahiko Toyonaga:
A watermarking system for IP protection by a post layout incremental router. 218-221
Architectures for cryptography and security applications
- Kris Tiri, David D. Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede:
A side-channel leakage free coprocessor IC in 0.18µm CMOS for embedded AES-based cryptographic and biometric processing. 222-227 - Kris Tiri, Ingrid Verbauwhede:
Simulation models for side-channel information leaks. 228-233 - Young H. Cho, William H. Mangione-Smith:
A pattern matching coprocessor for network security. 234-239 - Tomás Balderas-Contreras, René Cumplido:
High performance encryption cores for 3G networks. 240-243 - Pallav Gupta, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Efficient fingerprint-based user authentication for embedded systems. 244-247
Performance, energy, and fault-tolerance considerations for MPSoC designs
- Yanhong Liu, Samarjit Chakraborty, Wei Tsang Ooi:
Approximate VCCs: a new characterization of multimedia workloads for system-level MpSoC design. 248-253 - Christian Sauer, Matthias Gries, Sören Sonntag:
Modular domain-specific implementation and exploration framework for embedded software platforms. 254-259 - Xi Chen, Abhijit Davare, Harry Hsieh, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe:
Simulation based deadlock analysis for system level designs. 260-265 - Sorin Manolache, Petru Eles, Zebo Peng:
Fault and energy-aware communication mapping with guaranteed latency for applications implemented on NoC. 266-269 - Andrey V. Zykov, Elias Mizan, Margarida F. Jacome, Gustavo de Veciana, Ajay Subramanian:
High performance computing on fault-prone nanotechnologies: novel microarchitecture techniques exploiting reliability-delay trade-offs. 270-273
Management Day Session
- Nic Mokhoff, Yervant Zorian, Kamalesh N. Ruparel, Hao Nham, Francesco Pessolano, Kee Sup Kim:
How to determine the necessity for emerging solutions. 274-275
losing the power gap between ASIC and custom
- David G. Chinnery, Kurt Keutzer:
Closing the power gap between ASIC and custom: an ASIC perspective. 275-280 - Andrew Chang, William J. Dally:
Explaining the gap between ASIC and custom power: a custom perspective. 281-284 - Ruchir Puri, Leon Stok, Subhrajit Bhattacharya:
Keeping hot chips cool. 285-288
Panel
- Navraj Nandra, Phil Dworsky, Rick Merritt, John F. D'Ambrosia, Adam Healey, Boris Litinsky, John T. Stonick, Joe Abler:
Interconnects are moving from MHz->GHz should you be afraid?: or... "my giga hertz, does yours?". 289-290
Wireless session: information design methodology
- Jean-Samuel Chenard, Chun Yiu Chu, Zeljko Zilic, Milica Popovic:
Design methodology for wireless nodes with printed antennas. 291-296 - Yan Meng, Andrew P. Brown, Ronald A. Iltis, Timothy Sherwood, Hua Lee, Ryan Kastner:
MP core: algorithm and design techniques for efficient channel estimation in wireless applications. 297-302 - Wolfgang Eberle, Bruno Bougard, Sofie Pollin, Francky Catthoor:
From myth to methodology: cross-layer design for energy-efficient wireless communication. 303-308
Statistical optimization and manufacturability
- Murari Mani, Anirudh Devgan, Michael Orshansky:
An efficient algorithm for statistical minimization of total power under timing yield constraints. 309-314 - Jaskirat Singh, Vidyasagar Nookala, Zhi-Quan Luo, Sachin S. Sapatnekar:
Robust gate sizing by geometric programming. 315-320 - Aseem Agarwal, Kaviraj Chopra, David T. Blaauw, Vladimir Zolotov:
Circuit optimization using statistical static timing analysis. 321-324 - Bor-Yiing Su, Yao-Wen Chang:
An exact jumper insertion algorithm for antenna effect avoidance/fixing. 325-328
Application specific architecture design tools
- Kingshuk Karuri, Mohammad Abdullah Al Faruque, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Fine-grained application source code profiling for ASIP design. 329-334 - Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt:
Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration. 335-340 - Ho Young Kim, Tag Gon Kim:
Performance simulation modeling for fast evaluation of pipelined scalar processor by evaluation reuse. 341-344 - Dohyung Kim, Youngmin Yi, Soonhoi Ha:
Trace-driven HW/SW cosimulation using virtual synchronization technique. 345-348
The Titanic: what went wrong!
- Sani R. Nassif, Paul S. Zuchowski, Claude Moughanni, Mohamed Moosa, Stephen D. Posluszny, Ward Vercruysse:
The Titanic: what went wrong! 349-350
Panel
- Francine Bacchini, Jan M. Rabaey, Allan Cox, Frank Lane, Rudy Lauwereins, Ulrich Ramacher, David Witt:
Wireless platforms: GOPS for cents and MilliWatts. 351-352
Design methods for manufacturability enhancements
- V. Kheterpal, Vyacheslav Rovner, T. G. Hersan, D. Motiani, Y. Takegawa, Andrzej J. Strojwas, Lawrence T. Pileggi:
Design methodology for IC manufacturability based on regular logic-bricks. 353-358 - Jie Yang, Luigi Capodieci, Dennis Sylvester:
Advanced timing analysis based on post-OPC extraction of critical dimensions. 359-364 - Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester:
Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions. 365-368 - Joydeep Mitra, Peng Yu, David Zhigang Pan:
RADAR: RET-aware detailed routing using fast lithography simulations. 369-372
Methods and representations for logic synthesis
- Tsutomu Sasao, Munehiro Matsuura:
BDD representation for incompletely specifiedvmultiple-output logic functions and its applications to functional decomposition. 373-378 - Afshin Abdollahi, Massoud Pedram:
A new canonical form for fast boolean matching in logic synthesis and verification. 379-384 - Xiao Yu Li, Matthias F. M. Stallmann, Franc Brglez:
Effective bounding techniques for solving unate and binate covering problems. 385-390
Generating efficient models for analog circuits
- Yayun Wan, Jaijeet S. Roychowdhury:
Operator-based model-order reduction of linear periodically time-varying systems. 391-396 - Vinita Vasudevan:
Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits. 397-402 - Saurabh K. Tiwary, Rob A. Rutenbar:
Scalable trajectory methods for on-demand analog macromodel extraction. 403-408
Special session: emerging directions in wireless
- William Krenik, Anuj Batra:
Cognitive radio techniques for wide area networks. 409-412 - Jeffrey M. Gilbert, Won-Joon Choi, Qinfang Sun:
MIMO technology for advanced wireless local area networks. 413-415 - Clark T.-C. Nguyen:
RF MEMS in wireless architectures. 416-420
CAD for FPGAs
- Paul Metzgen, Dominic Nancekievill:
Multiplexer restructuring for FPGA implementation cost reduction. 421-426 - Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown:
FPGA technology mapping: a study of optimality. 427-432 - Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown:
Incremental retiming for FPGA physical synthesis. 433-438 - Kenneth Eguro, Scott Hauck, Akshay Sharma:
Architecture-adaptive range limit windowing for simulated annealing FPGA placement. 439-444
Effective formal verification using word-level reasoning, bit-level generality, and parallelism
- Himanshu Jain, Daniel Kroening, Natasha Sharygina, Edmund M. Clarke:
Word level predicate abstraction and refinement for verifying RTL verilog. 445-450 - Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Forrest Brewer:
Structural search for RTL with predicate learning. 451-456 - Markus Wedler, Dominik Stoffel, Wolfgang Kunz:
Normalization at the arithmetic bit level. 457-462 - Hari Mony, Jason Baumgartner, Viresh Paruthi, Robert Kanzelman:
Exploiting suspected redundancy without proving it. 463-466 - Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill, E. Allen Emerson:
Multi-threaded reachability. 467-470
Advances in synthesis
- Grace Nordin, Peter A. Milder, James C. Hoe, Markus Püschel:
Automatic generation of customized discrete fourier transform IPs. 471-474 - Shih-Hsu Huang, Yow-Tyng Nieh, Feng-Pin Lu:
Race-condition-aware clock skew scheduling. 475-478 - Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hamid Mahmoodi-Meimand, Kaushik Roy:
A novel synthesis approach for active leakage power reduction using dynamic supply gating. 479-484 - Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky:
Designing logic circuits for probabilistic computation in the presence of noise. 485-490 - Peggy B. McGee, Steven M. Nowick:
A lattice-based framework for the classification and design of asynchronous pipelines. 491-496
Coping with buffering
- King Ho Tam, Lei He:
Power optimal dual-Vdd buffered tree considering buffer stations and blockages. 497-502 - Brent Goplen, Prashant Saxena, Sachin S. Sapatnekar:
Net weighting to reduce repeater counts during placement. 503-508 - Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi:
Path based buffer insertion. 509-514 - Haoxing Ren, David Zhigang Pan, Charles J. Alpert, Paul Villarrubia:
Diffusion-based placement migration. 515-520
Panel
- Francine Bacchini, Gabe Moretti, Harry Foster, Janick Bergeron, Masayuki Nakamura, Shrenik Mehta, Laurent Ducousso:
Is methodology the highway out of verification hell? 521-522
Impact of process variations on power
- Hongliang Chang, Sachin S. Sapatnekar:
Full-chip analysis of leakage power under process variations, including spatial correlations. 523-528 - Navid Azizi, Muhammad M. Khellah, Vivek De, Farid N. Najm:
Variations-aware low-power design with voltage scaling. 529-534 - Ashish Srivastava, Saumil Shah, Kanak Agarwal, Dennis Sylvester, David T. Blaauw, Stephen W. Director:
Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance. 535-540 - Sarvesh Bhardwaj, Sarma B. K. Vrudhula:
Leakage minimization of nano-scale circuits in the presence of systematic and random variations. 541-546
Special session: The best of wireless at ISSCC
- Pascal Urard, L. Paumier, P. Georgelin, T. Michel, V. Lebars, E. Yeo, B. Gupta:
A 135Mbps DVB-S2 compliant codec based on 64800-bit LDPC and BCH codes (ISSCC paper 24.3). 547-548 - Philippe Royannez, Hugh Mair, Franck Dahan, Mike Wagner, Mark Streeter, Laurent Bouetel, Joel Blasquez, H. Clasen, G. Semino, Julie Dong, D. Scott, B. Pitts, Claudine Raibaut, Uming Ko:
A design platform for 90-nm leakage reduction techniques. 549-550 - Arun Natarajan, Abbas Komijani, Ali Hajimiri:
A 24 GHz phased-array transmitter in 0.18µm CMOS. 551-552
Architectural support for communication
- Taeweon Suh, Daehyun Kim, Hsien-Hsin S. Lee:
Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs. 553-558 - Jongman Kim, Dongkook Park, Theo Theocharides, Narayanan Vijaykrishnan, Chita R. Das:
A low latency router supporting adaptivity for on-chip interconnects. 559-564 - Sudeep Pasricha, Nikil D. Dutt, Elaheh Bozorgzadeh, Mohamed Ben-Romdhane:
Floorplan-aware automated synthesis of bus-based communication architectures. 565-570 - Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology. 571-574 - Sven Heithecker, Rolf Ernst:
Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements. 575-578
New approaches to physical design problems
- Vidyasagar Nookala, Ying Chen, David J. Lilja, Sachin S. Sapatnekar:
Microarchitecture-aware floorplanning using a statistical design of experiments approach. 579-584 - Zhong Xiu, Rob A. Rutenbar:
Timing-driven placement by grid-warping. 585-591 - Ulrich Brenner, Markus Struzyna:
Faster and better global placement by a new transportation algorithm. 591-596 - Tsung-Yi Ho, Chen-Feng Chang, Yao-Wen Chang, Sao-Jie Chen:
Multilevel full-chip routing for the X-based architecture. 597-602
Special session: MATLAB™ - the other emerging system-design language
- David P. Magee:
Matlab extensions for the development, testing and verification of real-time DSP software. 603-606 - Tejas M. Bhatt, Dennis McCain:
Matlab as a development environment for FPGA design. 607-610
Panel
- Tim Fox, Lou Covey, Susan Mack, David Heacock, Ed P. Huijbregts, Vess Johnson, Avner Kornfeld, Andrew Yang, Paul S. Zuchowski:
Should our power approach be current? 611
Emerging ideas in energy management techniques
- Ali Iranli, Massoud Pedram:
DTM: dynamic tone mapping for backlight scaling. 612-617 - Dexin Li, Pai H. Chou:
Application/architecture power co-optimization for embedded systems powered by renewable sources. 618-623 - Le Yan, Lin Zhong, Niraj K. Jha:
User-perceived latency driven voltage scaling for interactive applications. 624-627 - Jianli Zhuo, Chaitali Chakrabarti:
System-level energy-efficient dynamic task scheduling. 628-631
Advances in optimization of mixed-signal circuits
- Yang Xu, Kan-Lin Hsiung, Xin Li, Ivan Nausieda, Stephen P. Boyd, Lawrence T. Pileggi:
OPERA: optimization with ellipsoidal uncertainty for robust analog IC design. 632-637 - Jihong Ren, Mark R. Greenstreet:
A unified optimization framework for equalization filter synthesis. 638-643 - Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Chuanjin Richard Shi:
Template-driven parasitic-aware optimization of analog integrated circuit layouts. 644-647 - Arthur Nieuwoudt, Yehia Massoud:
Multi-level approach for integrated spiral inductor optimization. 648-651
Circuit performance under parameter variation
- Chirayu S. Amin, Noel Menezes, Kip Killpack, Florentin Dartu, Umakanta Choudhury, Nagib Hakim, Yehea I. Ismail:
Statistical static timing analysis: how simple can we get? 652-657 - Yu Cao, Lawrence T. Clark:
Mapping statistical process variations toward circuit performance variability: an analytical modeling approach. 658-663 - Peng Li:
Power grid simulation via efficient sampling-based sensitivity analysis and hierarchical symbolic relaxation. 664-669
Special session: Formally verifying your 10-million gate design
- Yaron Wolfsthal, Rebecca M. Gott:
Formal verification: is it real enough? 670-671 - Umberto Rossi:
Can we really do without the support of formal methods in the verification of large designs? 672-673 - Prosenjit Chatterjee:
Streamline verification process with formal property verification to meet highly compressed design cycle. 674-677
Embedded hardware and system software
- Seraj Ahmad, Rabi N. Mahapatra:
TCAM enabled on-chip logic minimization. 678-683 - Sergiu Nedevschi, Rabin K. Patra, Eric A. Brewer:
Hardware speech recognition for user interfaces in low cost, low power devices. 684-689 - Guangyu Chen, Mahmut T. Kandemir:
Improving java virtual machine reliability for memory-constrained embedded systems. 690-695 - Corey Goldfeder:
Frequency-based code placement for embedded multiprocessors. 696-699
Power estimation and design tradeoffs
- Joel Coburn, Srivaths Ravi, Anand Raghunathan:
Power emulation: a new paradigm for power estimation. 700-705 - John Wei, Chris Rowen:
Implementing low-power configurable processors: practical options and tradeoffs. 706-711 - Yan Luo, Jia Yu, Jun Yang, Laxmi N. Bhuyan:
Low power network processor design using clock gating. 712-715 - Nikhil Jayakumar, Sunil P. Khatri:
A variation tolerant subthreshold design approach. 716-719
Programmable architectures
- Yan Lin, Lei He:
Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction. 720-725 - Marvin Tom, Guy G. Lemieux:
Logic block clustering of large designs for channel-width constrained FPGAs. 726-731 - Antonio Carlos Schneider Beck, Luigi Carro:
Dynamic reconfiguration with binary translation: breaking the ILP barrier with software compatibility. 732-737
SAT: cool algorithms and hot applications
- Malay K. Ganai, Aarti Gupta, Pranav Ashar:
Beyond safety: customized SAT-based model checking. 738-743 - Domagoj Babic, Jesse D. Bingham, Alan J. Hu:
Efficient SAT solving: beyond supercubes. 744-749 - HoonSang Jin, Fabio Somenzi:
Prime clauses for fast enumeration of satisfying assignments to boolean circuits. 750-753 - Liang Zhang, Mukul R. Prasad, Michael S. Hsiao, Thomas Sidle:
Dynamic abstraction using SAT-based BMC. 754-757
Special session: DFM and variability: Theory and practice
- N. S. Nagaraj, Tom Bonifield, Abha Singh, Clive Bittlestone, Usha Narasimha, Viet Le, Anthony M. Hill:
BEOL variability and impact on RC extraction. 758-759 - Carlo Guardiani, Massimo Bertoletti, Nicola Dragone, Marco Malcotti, Patrick McNamara:
An effective DFM strategy requires accurate process and IP pre-characterization. 760-761 - James W. Tschanz, Keith A. Bowman, Vivek De:
Variation-tolerant circuits: circuit solutions and techniques. 762-763 - Farid N. Najm:
On the need for statistical timing analysis. 764-765 - David T. Blaauw, Kaviraj Chopra:
CAD tools for variation tolerance. 766 - Matt Nowak, Riko Radojcic:
Are there economic benefits in DFM? 767-768
Tools and methods for the verification of processors and processor-based systems
- Allon Adir, Hezi Azatchi, Eyal Bin, Ofer Peled, Kirill Shoikhet:
A generic micro-architectural test plan approach for microprocessor verification. 769-774 - Sudheendra Hangal, Naveen Chandra, Sridhar Narayanan, Sandeep Chakravorty:
IODINE: a tool to automatically infer dynamic invariants for hardware designs. 775-778 - Allon Adir, Yaron Arbetman, Bella Dubrov, Yossi Lichtenstein, Michal Rimon, Michael Vinov, Massimo A. Calligaro, Andrew Cofler, Gabriel Duffy:
VLIW: a case study of parallelism verification. 779-782 - Ilya Wagner, Valeria Bertacco, Todd M. Austin:
StressTest: an automatic approach to test generation via activity monitors. 783-788 - Sadik Ezer, Scott Johnson:
Smart diagnostics for configurable processor verification. 789-794
Electrical optimization for physical synthesis
- Yongseok Cheon, Pei-Hsin Ho, Andrew B. Kahng, Sherief Reda, Qinke Wang:
Power-aware placement. 795-800 - Amit Chowdhary, Karthik Rajagopal, Satish Venkatesan, Tung Cao, Vladimir Tiourin, Yegna Parasuram, Bill Halpin:
How accurately can we model timing in a placement engine? 801-806 - Hiran Tennakoon, Carl Sechen:
Efficient and accurate gate sizing with piecewise convex delay models. 807-812 - Yuantao Peng, Xun Liu:
Freeze: engineering a fast repeater insertion solver for power minimization using the ellipsoid method. 813-818
Optimization techniques in high-level synthesis
- Marc Geilen, Twan Basten, Sander Stuijk:
Minimising buffer requirements of synchronous dataflow graphs with model checking. 819-824 - Fei Su, Krishnendu Chakrabarty:
Unified high-level synthesis and module placement for defect-tolerant microfluidic biochips. 825-830 - Jianwen Zhu:
Towards scalable flow and context sensitive pointer analysis. 831-836 - Dong-U Lee, Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk:
MiniBit: bit-width optimization via affine arithmetic. 837-840 - Bin Wu, Jianwen Zhu, Farid N. Najm:
A non-parametric approach for dynamic range estimation of nonlinear systems. 841-844
Testing for process- and timing-related faults
- Seiji Kajihara, Masayasu Fukunaga, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato:
Path delay test compaction with process variation tolerance. 845-850 - Rasit Onur Topaloglu, Alex Orailoglu:
A DFT approach for diagnosis and process variation-aware structural test of thermometer coded current steering DACs. 851-856 - Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian:
Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies. 857-862 - Yannick Monnet, Marc Renaudin, Régis Leveugle:
Asynchronous circuits transient faults sensitivity evaluation. 863-868
Special session: Hierarchical design and design space exploration of analog integrated circuits
- Daniel Mueller, Guido Stehr, Helmut E. Graeb, Ulf Schlichtmann:
Deterministic approaches to analog performance space exploration (PSE). 869-874 - Fernando De Bernardinis, Pierluigi Nuzzo, Alberto L. Sangiovanni-Vincentelli:
Mixed signal design space exploration through analog platforms. 875-880 - Georges G. E. Gielen, Trent McConaghy, Tom Eeckelaert:
Performance space modeling for hierarchical synthesis of analog integrated circuits. 881-886
Panel
- Ron Wilson, Joe Gianelli, Chris Hamlin, Ken McElvain, Steve Leibson, Ivo Bolson, Rich Tobias, Raul Camposano:
Structured/platform ASIC apprentices: which platform will survive your board room? 887-888
Dynamic voltage scaling
- Luis Alejandro Cortés, Petru Eles, Zebo Peng:
Quasi-static assignment of voltages and optional cycles for maximizing rewards in real-time systems with energy c-onstraints. 889-894 - Yongseok Choi, Naehyuck Chang, Taewhan Kim:
DC-DC converter-aware power management for battery-operated embedded systems. 895-900 - Ravishankar Rao, Sarma B. K. Vrudhula:
Energy optimal speed control of devices with discrete speed sets. 901-904 - Yan Zhang, Zhijian Lu, John C. Lach, Kevin Skadron, Mircea R. Stan:
Optimal procrastinating voltage scheduling for hard real-time systems. 905-908
New directions in FPGA technologies
- Jennifer L. Wong, Farinaz Koushanfar, Miodrag Potkonjak:
Flexible ASIC: shared masking for multiple media processors. 909-914 - Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He:
Device and architecture co-optimization for FPGA power reduction. 915-920 - Aman Gayasen, Narayanan Vijaykrishnan, Mary Jane Irwin:
Exploring technology alternatives for nano-scale FPGA interconnects. 921-926
Reduced-order modeling
- Chirayu S. Amin, Yehea I. Ismail, Florentin Dartu:
Piece-wise approximations of RLCK circuit responses using moment matching. 927-932 - Kin Cheong Sou, Alexandre Megretski, Luca Daniel:
A quasi-convex optimization approach to parameterized model order reduction. 933-938 - Quming Zhou, Kartik Mohanram, Athanasios C. Antoulas:
Structure preserving reduction of frequency-dependent interconnect. 939-942 - Thomas J. Klemas, Luca Daniel, Jacob K. White:
Segregation by primary phase factors: a full-wave algorithm for model order reduction. 943-946
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