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• 
  2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France. IEEE Computer Society 2004, ISBN 0-7695-2085-5

Volume 1 - 2 - Designers Forum

• 
  Gregory S. Spirakis:
  Opportunities and Challenges in Building Silicon Products in 65nm and Beyond. 2-3

• 
  Kihwan Choi, Ramakrishna Soma, Massoud Pedram:
  Fine-Grained Dynamic Voltage and Frequency Scaling for Precise Energy and Performance Trade-Off Based on the Ratio of Off-Chip Access to On-Chip Computation Times. 4-9
• 
  Kevin Skadron:
  Hybrid Architectural Dynamic Thermal Management. 10-15
• 
  Yen-Jen Chang, Chia-Lin Yang, Feipei Lai:
  Value-Conscious Cache: Simple Technique for Reducing Cache Access Power. 16-21
• 
  Yingmin Li, Dharmesh Parikh, Yan Zhang, Karthik Sankaranarayanan, Mircea R. Stan, Kevin Skadron:
  State-Preserving vs. Non-State-Preserving Leakage Control in Caches. 22-29

• 
  Markus Wedler, Dominik Stoffel, Wolfgang Kunz:
  Arithmetic Reasoning in DPLL-Based SAT Solving. 30-35
• 
  Jason Baumgartner, Andreas Kuehlmann:
  Enhanced Diameter Bounding via Structural. 36-41
• 
  Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Chih-Chan Lin:
  Improved Symoblic Simulation by Dynamic Funtional Space Partitioning. 42-49

• 
  Saravanan Padmanaban, Spyros Tragoudas:
  Using BDDs and ZBDDs for Efficient Identification of Testable Path Delay Faults. 50-55
• 
  Irith Pomeranz, Sudhakar M. Reddy:
  Level of Similarity: A Metric for Fault Collapsing. 56-61
• 
  Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
  Design of Routing-Constrained Low Power Scan Chains. 62-67
• 
  Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy, Bharath Seshadri:
  Z-Sets and Z-Detections: Circuit Characteristics that Simplify Fault Diagnosis. 68-75

• 
  Angelo Nagari, Germano Nicollini:
  A 2.7V 350muW 11-b Algorithmic Analog-to-Digital Converter with Single-Ended Multiplexed Inputs. 76-81
• 
  Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda:
  Digital Background Gain Error Correction in Pipeline ADCs. 82-87
• 
  Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man:
  Digital Ground Bounce Reduction by Phase Modulation of the Clock. 88-93
• 
  Francesco Corsi, Cristoforo Marzocca, Gianvito Matarrese, Andrea Baschirotto, Stefano D'Amico:
  Pseudo-Random Sequence Based Tuning System for Continuous-Time Filters. 94-101

• 
  Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin:
  A Crosstalk Aware Interconnect with Variable Cycle Transmission. 102-107
• 
  Nattawut Thepayasuwan, Alex Doboli:
  Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip. 108-113
• 
  Sumit Gupta, Nikil D. Dutt, Rajesh Gupta, Alexandru Nicolau:
  Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow. 114-121

• 
  Donatella Sciuto, Grant Martin, Wolfgang Rosenstiel, Stuart Swan, Frank Ghenassia, Peter Flake, Johny Srouji:
  SystemC and SystemVerilog: Where do They Fit? Where are They Going? 122-129

• 
  Siu-Kei Wong, Chi-Ying Tsui:
  Re-Configurable Bus Encoding Scheme for Reducing Power Consumption of the Cross Coupling Capacitance for Deep Sub-Micron Instruction Bus. 130-135
• 
  Zhiyuan Ren, Bruce H. Krogh, Radu Marculescu:
  Hierarchical Adaptive Dynamic Power Management. 136-141
• 
  Chuanjun Zhang, Frank Vahid, Roman L. Lysecky:
  A Self-Tuning Cache Architecture for Embedded Systems. 142-147
• 
  Jie S. Hu, Narayanan Vijaykrishnan, Soontae Kim, Mahmut T. Kandemir, Mary Jane Irwin:
  Scheduling Reusable Instructions for Power Reduction. 148-155

• 
  Per Bjesse, James H. Kukula:
  Using Counter Example Guided Abstraction Refinement to Find Complex Bugs. 156-161
• 
  Klaus Winkelmann, Hans-Joachim Trylus, Dominik Stoffel, Görschwin Fey:
  Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor. 162-167
• 
  Panagiotis Manolios, Sudarshan K. Srinivasan:
  Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements. 168-175

• 
  José M. Fernandes, Marcelino B. Santos, Arlindo L. Oliveira, João Paulo Teixeira:
  A Probabilistic Method for the Computation of Testability of RTL Constructs. 176-181
• 
  Prabhat Mishra, Nikil D. Dutt:
  Graph-Based Functional Test Program Generation for Pipelined Processors. 182-187
• 
  Olga Goloubeva, Matteo Sonza Reorda, Massimo Violante:
  Automatic Generation of Validation Stimuli for Application-Specific Processors. 188-193
• 
  Michael G. Dimopoulos, Panagiotis Linardis:
  Efficient Static Compaction of Test Sequence Sets through the Application of Set Covering Techniques. 194-201

• 
  Ilya Issenin, Erik Brockmeyer, Miguel Miranda, Nikil D. Dutt:
  Data Reuse Analysis Technique for Software-Controlled Memory Hierarchies. 202-207
• 
  Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt:
  Automatic Tuning of Two-Level Caches to Embedded Applications. 208-213
• 
  Chuanjun Zhang, Jun Yang, Frank Vahid:
  Low Static-Power Frequent-Value Data Caches. 214-219
• 
  Chuanjun Zhang, Frank Vahid:
  Using a Victim Buffer in an Application-Specific Memory Hierarchy. 220-227

• 
  Marc Renaudin, G. Fraidy Bouesse, Ph. Proust, J. P. Tual, Laurent Sourgen, Fabien Germain:
  High Security Smartcards. 228-233

• 
  Jingcao Hu, Radu Marculescu:
  Energy-Aware Communication and Task Scheduling for Network-on-Chip Architectures under Real-Time Constraints. 234-239
• 
  Tom W. Chen, Justin Gregg:
  A Low Cost Individual-Well Adaptive Body Bias (IWABB) Scheme for Leakage Power Reduction and Performance Enhancement in the Presence of Intra-Die Variations. 240-245
• 
  Kris Tiri, Ingrid Verbauwhede:
  A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation. 246-251
• 
  Wei-Chung Cheng, Yu Hou, Massoud Pedram:
  Power Minimization in a Backlit TFT-LCD Display by Concurrent Brightness and Contrast Scaling. 252-259

• 
  Sean Safarpour, Andreas G. Veneris, Rolf Drechsler, Joanne Lee:
  Managing Don't Cares in Boolean Satisfiability. 260-265
• 
  Miroslav N. Velev:
  Exploiting Signal Unobservability for Efficient Translation to CNF in Formal Verification of Microprocessors. 266-271
• 
  Bin Li, Michael S. Hsiao, Shuo Sheng:
  A Novel SAT All-Solutions Solver for Efficient Preimage Computation. 272-279

• 
  Ganesh Srinivasan, Soumendu Bhattacharya, Sasikumar Cherubal, Abhijit Chatterjee:
  Efficient Test Strategy for TDMA Power Amplifiers Using Transient Current Measurements: Uses and Benefit. 280-285
• 
  Chee-Kian Ong, Dongwoo Hong, Kwang-Ting Cheng, Li-C. Wang:
  Random Jitter Extraction Technique in a Multi-Gigahertz Signal. 286-291
• 
  Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin:
  Low Cost Analog Testing of RF Signal Paths. 292-297
• 
  Diego Vázquez, Gildas Léger, Gloria Huertas, Adoración Rueda, José L. Huertas:
  A Method for Parameter Extraction of Analog Sine-Wave Signals for Mixed-Signal Built-In-Self-Test Applications. 298-305

• 
  Sambuddhi Hettiaratchi, Peter Y. K. Cheung:
  A Novel Implementation of Tile-Based Address Mapping. 306-311
• 
  Zhong Wang, Xiaobo Sharon Hu:
  Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks. 312-317
• 
  Radoslaw Szymanek, Francky Catthoor, Krzysztof Kuchcinski:
  Time-Energy Design Space Exploration for Multi-Layer Memory Architectures. 318-323
• 
  Arathi Ramani, Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah:
  Breaking Instance-Independent Symmetries in Exact Graph Coloring. 324-331

• 
  Francky Catthoor, Andrea Cuomo, Grant Martin, Patrick Groeneveld, Rudy Lauwereins, Karen Maex, Patrick van de Steeg, Ron Wilson:
  How Can System-Level Design Solve the Interconnect Technology Scaling Problem? 332-339

• 
  Todor P. Stefanov, Claudiu Zissulescu, Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere:
  System Design Using Kahn Process Networks: The Compaan/Laura Approach. 340-345
• 
  Douglas Densmore, Sanjay Rekhi, Alberto L. Sangiovanni-Vincentelli:
  Microarchitecture Development via Metropolis Successive Platform Refinement. 346-351
• 
  Chulho Shin, Young-Taek Kim, Eui-Young Chung, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo:
  Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design. 352-357
• 
  Jean-Yves Brunel, Marco Di Natale, Alberto Ferrari, Paolo Giusto, Luciano Lavagno:
  SoftContract: an Assertion-Based Software Development Process that Enables Design-by-Contract. 358-363
• 
  D. Quinn, Bruno Lavigueur, Guy Bois, El Mostapha Aboulhamid:
  A System Level Exploration Platform and Methodology for Network Applications Based on Configurable Processors. 364-371

• 
  Christoph Grimm, Wilhelm Heupke, Klaus Waldschmidt:
  Refinement of Mixed-Signal Systems with Affine Arithmetic. 372-377
• 
  Hector Posadas, Fernando Herrera, Pablo Sánchez, Eugenio Villar, Francisco Blasco:
  System-Level Performance Analysis in SystemC. 378-383
• 
  Mohammad Reza Mousavi, Paul Le Guernic, Jean-Pierre Talpin, Sandeep K. Shukla, Twan Basten:
  Modeling and Validating Globally Asynchronous Design in Synchronous Frameworks. 384-389
• 
  Vijay D'Silva, S. Ramesh, Arcot Sowmya:
  Synchronous Protocol Automata: A Framework for Modelling and Verification of SoC Communication Architectures. 390-395
• 
  Tiberiu Seceleanu, Tomi Westerlund:
  Aspects of Formal and Graphical Design of a Bus System. 396-403

• 
  Ozgur Sinanoglu, Alex Orailoglu:
  Scan Power Minimization through Stimulus and Response Transformations. 404-409
• 
  Matthew W. Heath, Wayne P. Burleson, Ian G. Harris:
  Synchro-Tokens: Eliminating Nondeterminism to Enable Chip-Level Test of Globally-Asynchronous Locally-Synchronous SoC?s. 410-415
• 
  Qiang Xu, Nicola Nicolici:
  Wrapper Design for Testing IP Cores with Multiple Clock Domains. 416-421
• 
  Anuja Sehgal, Krishnendu Chakrabarty:
  Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures. 422-427
• 
  Marie-Lise Flottes, Regis Poirier, Bruno Rouzeyre:
  An Arithmetic Structure for Test Data Horizontal Compression. 428-435

• 
  Ewout Martens, Georges G. E. Gielen:
  A Phase-Frequency Transfer Description of Analog and Mixed-Signal Front-End Architectures for System-Level Design. 436-441
• 
  Lutz Näthke, Volodymyr Burkhay, Lars Hedrich, Erich Barke:
  Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques. 442-447
• 
  Tholom Kiely, Georges G. E. Gielen:
  Performance Modeling of Analog Integrated Circuits Using Least-Squares Support Vector Machines. 448-453
• 
  Gerd Vandersteen, Rik Pintelon, Dimitri Linten, Stéphane Donnay:
  Extended Subspace Identification of Improper Linear Systems. 454-459
• 
  Xiaoling Huang, H. Alan Mantooth:
  Identification and Modeling of Nonlinear Dynamic Behavior in Analog Circuits. 460-467

• 
  Aneesh Koorapaty, V. Kheterpal, Padmini Gopalakrishnan, M. Fu, Lawrence T. Pileggi:
  Exploring Logic Block Granularity for Regular Fabrics. 468-473
• 
  Nikhil Bansal, Sumit Gupta, Nikil D. Dutt, Alexandru Nicolau, Rajesh Gupta:
  Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures. 474-479
• 
  Roman L. Lysecky, Frank Vahid:
  A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning. 480-485
• 
  Guilin Chen, Mahmut T. Kandemir, Ugur Sezer:
  Configuration-Sensitive Process Scheduling for FPGA-Based Computing Platforms. 486-493

• 
  Dongwoo Lee, Harmander Deogun, David T. Blaauw, Dennis Sylvester:
  Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization. 494-499
• 
  Pietro Babighian, Luca Benini, Enrico Macii:
  A Scalable ODC-Based Algorithm for RTL Insertion of Gated Clocks. 500-505
• 
  Mahmut T. Kandemir:
  Impact of Data Transformations on Memory Bank Locality. 506-511
• 
  Claudia Kretzschmar, André K. Nieuwland, Dietmar Müller:
  Why Transition Coding for Power Minimization of On-Chip Buses Does Not Work. 512-517
• 
  Alexandru Andrei, Marcus T. Schmitz, Petru Eles, Zebo Peng, Bashir M. Al-Hashimi:
  Overhead-Conscious Voltage Selection for Dynamic and Leakage Energy Reduction of Time-Constrained Systems. 518-525

• 
  Le Cai, Yung-Hsiang Lu:
  Dynamic Power Management Using Data Buffers. 526-531
• 
  David Atienza, Stylianos Mamagkakis, Francky Catthoor, Jose Manuel Mendias, Dimitrios Soudris:
  Dynamic Memory Management Design Methodology for Reduced Memory Footprint in Multimedia and Wireless Network Applications. 532-537
• 
  Hye-On Jang, Minsoo Kang, Myeong-jin Lee, Kwanyeob Chae, Kookpyo Lee, Kyuhyun Shim:
  High-Level System Modeling and Architecture Exploration with SystemC on a Network SoC: S3C2510 Case Study. 538-543
• 
  Guido Post, P. K. Venkataraghavan, Tapan Ray, D. R. Seetharaman:
  A SystemC-Based Verification Methodology for Complex Wireless Software IP. 544-551

• 
  Daniel Gracia Pérez, Gilles Mouchard, Olivier Temam:
  A New Optimized Implemention of the SystemC Engine Using Acyclic Scheduling. 552-557
• 
  Avi Ziv:
  Stimuli Generation with Late Binding of Values. 558-563
• 
  Franco Fummi, Stefano Martini, Giovanni Perbellini, Massimo Poncino:
  Native ISS-SystemC Integration for the Co-Simulation of Multi-Processor SoC. 564-569
• 
  Soumitra Bose, Amit Nandi:
  Extraction of Schematic Array Models for Memory Circuits. 570-577

• 
  Antonis M. Paschalis, Dimitris Gizopoulos:
  Effective Software-Based Self-Test Strategies for On-Line Periodic Testing of Embedded Processors. 578-583
• 
  M. Bellato, Paolo Bernardi, D. Bortolato, A. Candelori, M. Ceschia, Alessandro Paccagnella, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, P. Zambolin:
  Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA. 584-589
• 
  Régis Leveugle, Abdelaziz Ammari:
  Early SEU Fault Injection in Digital, Analog and Mixed Signal Circuits: A Global Flow. 590-595
• 
  Sobeeh Almukhaizim, Petros Drineas, Yiorgos Makris:
  On Concurrent Error Detection with Bounded Latency in FSMs. 596-603

• 
  Mukesh Ranjan, Wim Verhaegen, Anuradha Agarwal, Hemanth Sampath, Ranga Vemuri, Georges G. E. Gielen:
  Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models. 604-609
• 
  Rajeev Murgai, Subodh M. Reddy, Takashi Miyoshi, Takeshi Horie, Mehdi Baradaran Tahoori:
  Sensitivity-Based Modeling and Methodology for Full-Chip Substrate Noise Analysis. 610-615
• 
  Thomas Brandtner, Robert Weigel:
  SubCALM: A Program for Hierarchical Substrate Coupling Simulation on Floorplan Level. 616-621
• 
  Yong Zhan, Sachin S. Sapatnekar:
  Optimization of Integrated Spiral Inductors Using Sequential Quadratic Programming. 622-629

• 
  Abhijit K. Deb, Axel Jantsch, Johnny Öberg:
  System Design for DSP Applications Using the MASIC Methodology. 630-635
• 
  Joseph Zambreno, Alok N. Choudhary, Rahul Simha, Bhagirath Narahari:
  Flexible Software Protection Using Hardware/Software Codesign Techniques. 636-641
• 
  Patrick Schaumont, Ingrid Verbauwhede:
  Interactive Cosimulation with Partial Evaluation. 642-647
• 
  Axel Siebenborn, Oliver Bringmann, Wolfgang Rosenstiel:
  Communication Analysis for System-On-Chip Design. 648-655

• 
  Christian Piguet, Jacques Gautier, Christoph Heer, Ian O'Connor, Ulf Schlichtmann:
  Extremely Low-Power Logic. 656-663

• 
  Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu:
  Decomposition of Instruction Decoder for Low Power Design. 664-665
• 
  Johann Laurent, Nathalie Julien, Eric Senn, Eric Martin:
  Functional Level Power Analysis: An Efficient Approach for Modeling the Power Consumption of Complex Processors. 666-667
• 
  Prasenjit Basu, Sayantan Das, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix:
  Formal Verification Coverage: Are the RTL-Properties Covering the Design's Architectural Intent? 668-669
• 
  Young-Su Kwon, Chong-Min Kyung:
  Functional Coverage Metric Generation from Temporal Event Relation Graph. 670-671
• 
  Aristides Efthymiou, Christos P. Sotiriou, Douglas A. Edwards:
  Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits. 672-673
• 
  Hassan Aboushady, Laurent de Lamarre, Nicolas Beilleau, Marie-Minerve Louërat:
  Automatic Synthesis and Simulation of Continuous-Time [Sigma-Delta] Modulators. 674-675
• 
  Fernando De Bernardinis, Alberto L. Sangiovanni-Vincentelli:
  A Methodology for System-Level Analog Design Space Exploration. 676-677
• 
  Mohammad Taherzadeh-Sani, Reza Lotfi, Omid Shoaei:
  Systematic Design for Optimization of High-Resolution Pipelined ADCs. 678-679
• 
  José C. García, Juan A. Montiel-Nelson, Javier Sosa, Héctor Navarro:
  A Direct Bootstrapped CMOS Large Capacitive-Load Driver Circuit. 680-681
• 
  Ben I. Hounsell, Richard Taylor:
  Co-Processor Synthesis: A New Methodology for Embedded Software Acceleration. 682-683
• 
  María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida:
  Behavioural Bitwise Scheduling Based on Computational Effort Balancing. 684-685
• 
  Andrea Del Re, Alberto Nannarelli, Marco Re:
  A Tool for Automatic Generation of RTL-Level VHDL Description of RNS FIR Filters. 686-687
• 
  Lipeng Cao:
  On Transfer Function and Power Consumption Transient Response. 688-689
• 
  Tarvo Raudvere, Ashish Kumar Singh, Ingo Sander, Axel Jantsch:
  Polynomial Abstraction for Verification of Sequentially Implemented Combinational Circuits. 690-691
• 
  Li-C. Wang:
  Regression Simulation: Applying Path-Based Learning In Delay Test and Post-Silicon Validation. 692-695
• 
  Ali Iranli, Kihwan Choi, Massoud Pedram:
  A Game Theoretic Approach to Low Energy Wireless Video Streaming. 696-697
• 
  Luca Benini, Alessandro Ivaldi, Alberto Macii, Enrico Macii:
  Block-Enabled Memory Macros: Design Space Exploration and Application-Specific Tuning. 698-699
• 
  Kimish Patel, Enrico Macii, Massimo Poncino:
  Synthesis of Partitioned Shared Memory Architectures for Energy-Efficient Multi-Processor SoC. 700-701
• 
  Mladen Nikitovic, Mats Brorsson:
  A Low Power Strategy for Future Mobile Terminals. 702-703
• 
  Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy:
  Trim Bit Setting of Analog Filters Using Wavelet-Based Supply Current Analysis. 704-705
• 
  Luís Rolíndez, Salvador Mir, Guillaume Prenat, Ahcène Bounceur:
  A 0.18 µm CMOS Implementation of On-chip Analogue Test Signal Generation from Digital Test Patterns. 706-707
• 
  Gildas Léger, Adoración Rueda:
  A Digital Test for First-Order [Sigma-Delta] Modulators. 708-709
• 
  James Chin, Mehrdad Nourani:
  SoC Test Scheduling with Power-Time Tradeoff and Hot Spot Avoidance. 710-711
• 
  Mounir Benabdenbi, Alain Greiner, François Pêcheux, Emmanuel Viaud, Matthieu Tuna:
  STEPS: Experimenting a New Software-Based Strategy for Testing SoCs Containing P1500-Compliant IP Cores. 712-713
• 
  Cecilia Metra, T. M. Mak, Martin Omaña:
  Are Our Design for Testability Features Fault Secure? 714-715
• 
  Francis G. Wolff, Christos A. Papachristou, David R. McIntyre:
  Test Compression and Hardware Decompression for Scan-Based SoCs. 716-717
• 
  Ashish Srivastava, Dennis Sylvester, David T. Blaauw:
  Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design. 718-719
• 
  Pietro Babighian, Luca Benini, Enrico Macii:
  Sizing and Characterization of Leakage-Control Cells for Layout-Aware Distributed Power-Gating. 720-723
• 
  Frank P. Burns, Delong Shang, Albert Koelmans, Alexandre Yakovlev:
  An Asynchronous Synthesis Toolset Using Verilog. 724-725
• 
  Gero Dittmann:
  Organizing Libraries of DFG Patterns. 726-727
• 
  Anca Mariana Molnos, Marc J. M. Heijligers, Sorin Cotofana, Jos T. J. van Eijndhoven:
  Compositional Memory Systems for Data Intensive Applications. 728-729
• 
  Juha Alakarhu, Jarkko Niittylahti:
  Scalar Metric for Temporal Locality and Estimation of Cache Performance. 730-731
• 
  James Lapalme, El Mostapha Aboulhamid, Gabriela Nicolescu, Luc Charest, François R. Boyer, J. P. David, Guy Bois:
  .NET Framework - A Solution for the Next Generation Tools for System-Level Modeling and Simulation. 732-733
• 
  Pablo Viana, Edna Barros, Sandro Rigo, Rodolfo Azevedo, Guido Araujo:
  Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology. 734-735
• 
  Peter Green, Salah Essa:
  Integrating the Synchronous Dataflow Model with UML. 736-737
• 
  Matthieu Briere, Laurent Carrel, T. Michalke, Fabien Mieyeville, Ian O'Connor, Frédéric Gaffiot:
  Design and Behavioral Modeling Tools for Optical Network-on-Chip. 738-739
• 
  Sheldon X.-D. Tan, Zhenyu Qi, Hang Li:
  Hierarchical Modeling and Simulation of Large Analog Circuits. 740-741
• 
  Peter R. Wilson, J. Neil Ross, Andrew D. Brown, Tom J. Kazmierski, Jerzy Baranowski:
  Efficient Mixed-Domain Behavioural Modeling of Ferromagnetic Hysteresis Implemented in VHDL-AMS. 742-743
• 
  Manish Handa, Ranga Vemuri:
  A Fast Algorithm for Finding Maximal Empty Rectangles for Dynamic FPGA Placement. 744-745
• 
  Alex Fit-Florea, Miroslav Halás, Fatih Kocan:
  Enhancing Reliability of Operational Interconnections in FPGAs. 746-747
• 
  Miljan Vuletic, Ludovic Righetti, Laura Pozzi, Paolo Ienne:
  Operating System Support for Interface Virtualisation of Reconfigurable Coprocessors. 748

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