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ORCIDDATE 2013: Grenoble, France
- Enrico Macii:
Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013. EDA Consortium San Jose, CA, USA / ACM DL 2013, ISBN 978-1-4503-2153-2
Keynotes
- Benedetto Vigna:
Smart systems for internet of things. 1 - Massoud Pedram:
Creating a sustainable information and communication infrastructure. 2
Acceleration and verification of ESL and analog systems
- Weiwei Chen, Rainer Dömer:
Optimized out-of-order parallel discrete event simulation using predictions. 3-8 - Matthieu Moy:
Parallel programming with SystemC for loosely timed models: a non-intrusive approach. 9-14 - David Novo, Sara El Alaoui, Paolo Ienne:
Accuracy vs speed tradeoffs in the estimation of fixed-point errors on linear time-invariant systems. 15-20 - Seyed Nematollah Ahmadyan, Jayanand Asok Kumar, Shobha Vasudevan:
Runtime verification of nonlinear analog circuits using incremental time-augmented RRT algorithm. 21-26 - Seyed-Hosein Attarzadeh-Niaki, Ingo Sander:
An automated parallel simulation flow for heterogeneous embedded systems. 27-30 - Peter Lisherness, Nicole Lesperance, Kwang-Ting (Tim) Cheng
:
Mutation analysis with coverage discounting. 31-34 - Hoang Minh Le, Daniel Große, Rolf Drechsler:
Scalable fault localization for SystemC TLM designs. 35-38
Energy optimization in multi-core systems
- Bharathwaj Raghunathan, Yatish Turakhia, Siddharth Garg, Diana Marculescu:
Cherry-picking: exploiting process variations in dark-silicon homogeneous chip multi-processors. 39-44 - Gang Chen, Kai Huang, Christian Buckl, Alois C. Knoll:
Energy optimization with worst-case deadline guarantee for pipelined multiprocessor systems. 45-50 - Muhammad Shafique, Benjamin Vogel, Jörg Henkel:
Self-adaptive hybrid dynamic power management for many-core systems. 51-56 - Xueliang Li, Guihai Yan, Yinhe Han, Xiaowei Li:
SmartCap: user experience-oriented power adaptation for smartphone's application processor. 57-60 - Dongwon Kim, Wonwoo Jung, Hojung Cha:
Runtime power estimation of mobile AMOLED displays. 61-64
Memory and cache architectures
- Seokin Hong, Soontae Kim:
AVICA: an access-time variation insensitive L1 cache architecture. 65-70 - Yen-Hao Chen, Yi-Yu Liu:
Dual-addressing memory architecture for two-dimensional memory access patterns. 71-76 - Fazal Hameed, Lars Bauer, Jörg Henkel:
Adaptive cache management for a combined SRAM and DRAM cache hierarchy for multi-cores. 77-82 - Vicente Lorente, Alejandro Valero, Julio Sahuquillo, Salvador Petit, Ramon Canal, Pedro López, José Duato:
Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes. 83-88 - Michel El-Nacouzi, Islam Atta, Myrto Papadopoulou, Jason Zebchuk, Natalie D. Enright Jerger, Andreas Moshovos:
A dual grain hit-miss detector for large die-stacked DRAM caches. 89-92 - Roberto Rodríguez-Rodríguez, Fernando Castro, Daniel Chaver, Luis Piñuel, Francisco Tirado:
Reducing writes in phase-change memory environments by using efficient cache replacement policies. 93-96
Communications, multimedia, and consumer electronics
- Jochen Rust, Frank Ludwig, Steffen Paul:
Low complexity QR-decomposition architecture using the logarithmic number system. 97-102 - Wen Yueh, Minki Cho, Saibal Mukhopadhyay:
Perceptual quality preserving SRAM architecture for color motion pictures. 103-108 - Purushotham Murugappa, Amer Baghdadi, Michel Jézéquel:
Parameterized area-efficient multi-standard turbo decoder. 109-114 - Muhammad Usman Karim Khan, Jan Micha Borrmann, Lars Bauer, Muhammad Shafique, Jörg Henkel:
An H.264 Quad-FullHD low-latency intra video encoder. 115-120 - Ziyuan Zhu, Shan Tang, Yongtao Su, Juan Han, Gang Sun, Jinglin Shi:
A 100 GOPS ASP based baseband processor for wireless communication. 121-124 - Muhammad Usman Karim Khan, Muhammad Shafique, Mateus Grellert, Jörg Henkel:
Hardware-software collaborative complexity reduction scheme for the emerging HEVC intra encoder. 125-128
Hot topic: reliability challenges of real-time systems in forthcoming technology nodes
- Said Hamdioui, Michael Nicolaidis, Dimitris Gizopoulos, Arnaud Grasset, Guido Groeseneken, Philippe Bonnot:
Reliability challenges of real-time systems in forthcoming technology nodes. 129-134
Safety critical real-time systems
- Moritz Neukirchner, Sophie Quinton, Tobias Michaels, Philip Axer, Rolf Ernst:
Sensitivity analysis for arbitrary activation patterns in real-time systems. 135-140 - Qingling Zhao, Zonghua Gu, Haibo Zeng:
PT-AMC: integrating preemption thresholds into mixed-criticality scheduling. 141-146 - Hang Su, Dakai Zhu:
An elastic mixed-criticality task model and its scheduling algorithm. 147-152 - Gonzalo Carvajal, Sebastian Fischmeister:
An open platform for mixed-criticality real-time ethernet. 153-156
Hot topic: IP subsystems: the next productivity wave?
- Pieter van der Wolf, Ruud Derwig:
Modular SoC integration with subsystems: the audio subsystem case. 157-162 - Pierre-Xavier Thomas, Grant Martin, David Heine, Dennis Moolenaar, James Kim:
Configurability in IP subystems: baseband examples. 163-168 - Frank Martin, Peter Bennett:
Configurable I/O integration to reduce system-on-chip time to market: DDR, PCIe examples. 169 - Menno Lindwer, Mark Ruvald Pedersen:
High-performance imaging subsystems and their integration in mobile devices. 170
Panel: the heritage of mead & conway: what has remained the same, what was missed, what has changed, what lies ahead
- Marco Casale-Rossi, Alberto L. Sangiovanni-Vincentelli, Luca P. Carloni, Bernard Courtois, Hugo De Man, Antun Domic, Jan M. Rabaey:
Panel: the heritage of Mead & Conway: what has remained the same, what was missed, what has changed, what lies ahead. 171-175
Addressing process and delay variation in high-level synthesis
- Mengying Zhao, Alex Orailoglu, Chun Jason Xue:
Profit maximization through process variation aware high level synthesis with speed binning. 176-181 - Yuko Hara-Azumi, Farshad Firouzi, Saman Kiamehr, Mehdi Baradaran Tahoori:
Instruction-set extension under process variation and aging effects. 182-187 - Alberto A. Del Barrio, Román Hermida, Seda Ogrenci Memik, Jose Manuel Mendias, María C. Molina:
Multispeculative additive trees in high-level synthesis. 188-193 - Andrew Canis, Jason Helge Anderson, Stephen Dean Brown:
Multi-pumping for resource reduction in FPGA high-level synthesis. 194-197 - Yuankai Chen, Hai Zhou:
Resource-constrained high-level datapath optimization in ASIP design. 198-201
Microarchitectural techniques for reliability
- Yavuz Yetim, Margaret Martonosi, Sharad Malik:
Extracting useful computation from error-prone processors for streaming applications. 202-207 - Xing Hu, Guihai Yan, Yu Hu, Xiaowei Li:
Orchestrator: a low-cost solution to reduce voltage emergencies for multi-threaded applications. 208-213 - Panagiota Nikolaou, Yiannakis Sazeides, Lorena Ndreu, Emre Özer, Sachin Idgunji:
Memory array protection: check on read or check on write? 214-219 - Gulay Yalcin, Osman S. Unsal, Adrián Cristal:
FaulTM: error detection and recovery using hardware transactional memory. 220-225 - Xavier Jimenez, David Novo, Paolo Ienne:
Phœnix: reviving MLC blocks as SLC to extend NAND flash devices lifetime. 226-229
Energy efficient mobile and cloud computing systems
- Roberto Diversi, Andrea Bartolini, Andrea Tilli, Francesco Beneventi, Luca Benini:
SCC thermal model identification via advanced bias-compensated least-squares. 230-235 - Karthik Chandrasekar, Christian Weis, Benny Akesson, Norbert Wehn, Kees Goossens:
System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs. 236-241 - William Lee, Vikas S. Vij, Anthony R. Thatcher, Kenneth S. Stevens:
Design of low energy, high performance synchronous and asynchronous 64-point FFT. 242-247 - Christian de Schryver, Pedro Torruella, Norbert Wehn:
A multi-level Monte Carlo FPGA accelerator for option pricing in the Heston model. 248-253 - Junyoung Park, Ameya Chaudhari, Jacob A. Abraham:
Non-speculative double-sampling technique to increase energy-efficiency in a high-performance processor. 254-257 - Hao Shen, Qinru Qiu:
User-aware energy efficient streaming strategy for smartphone based video playback applications. 258-261 - Muhammad Abdullah Adnan, Rajesh Gupta:
Utility-aware deferred load balancing in the cloud driven by dynamic pricing of electricity. 262-265 - Marina Zapater, José Luis Ayala, José Manuel Moya, Kalyan Vaidyanathan, Kenny C. Gross, Ayse K. Coskun:
Leakage and temperature aware server control for improving energy efficiency in data centers. 266-269
Dealing with timing variation in advanced technologies
- Fabian Oboril, Mehdi Baradaran Tahoori:
MTTF-balanced pipeline design. 270-275 - Marcus Wagner, Hans-Joachim Wunderlich:
Efficient variation-aware statistical dynamic timing analysis for delay test applications. 276-281 - Liangzhen Lai, Vikas Chandra, Robert C. Aitken, Puneet Gupta:
SlackProbe: a low overhead in situ on-line timing slack monitoring methodology. 282-287 - Xiaolin Zhang, Jing Ye, Yu Hu, Xiaowei Li:
Capturing post-silicon variation by layout-aware path-delay testing. 288-291 - Chandra K. H. Suresh, Ender Yilmaz, Sule Ozev, Ozgur Sinanoglu:
Adaptive reduction of the frequency search space for multi-vdd digital circuits. 292-295
Timing analysis
- Nan Guan, Xinping Yang, Mingsong Lv, Wang Yi:
FIFO cache analysis for WCET estimation: a quantitative approach. 296-301 - Mircea Negrean, Sebastian Klawitter, Rolf Ernst:
Timing analysis of multi-mode applications on AUTOSAR conform multi-core systems. 302-307 - Hardik Shah, Alois C. Knoll, Benny Akesson:
Bounding SDRAM interference: detailed analysis vs. latency-rate analysis. 308-313
Hot topic: design for variability, manufacturability, reliability, and debug: many faces of the same coin?
- Rani S. Ghaida, Puneet Gupta:
Role of design in multiple patterning: technology development, design enablement and process control. 314-319 - David Lin, Ted Hong, Yanjing Li, Farzan Fallah, Donald S. Gardner, Nagib Hakim, Subhasish Mitra:
Overcoming post-silicon validation challenges through quick error detection (QED). 320-325 - Georges G. E. Gielen, Elie Maricau:
Stochastic degradation modeling and simulation for analog integrated circuits in nanometer CMOS. 326-331
The quest for better NoCs
- Alberto Ghiribaldi, Davide Bertozzi, Steven M. Nowick:
A transition-signaling bundled data NoC switch architecture for cost-effective GALS multicore systems. 332-337 - Chia-Hsin Owen Chen, Sunghyun Park, Tushar Krishna, Suvinay Subramanian, Anantha P. Chandrakasan, Li-Shiuan Peh:
SMART: a single-cycle reconfigurable NoC for SoC applications. 338-343 - Giorgos Dimitrakopoulos, N. Georgiadis, Chrysostomos Nicopoulos, Emmanouil Kalligeros:
Switch folding: network-on-chip routers with time-multiplexed output ports. 344-349 - Vahideh Akhlaghi, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram:
An efficient network on-chip architecture based on isolating local and non-local communications. 350-353 - Zhiliang Qian, Da-Cheng Juan, Paul Bogdan, Chi-Ying Tsui, Diana Marculescu, Radu Marculescu:
SVR-NoC: a performance analysis tool for network-on-chips using learning-based support vector regression model. 354-357
Embedded tutorial: reliability analysis reloaded: how will we survive?
- Robert C. Aitken, Görschwin Fey, Zbigniew T. Kalbarczyk, Frank Reichenbach, Matteo Sonza Reorda:
Reliability analysis reloaded: how will we survive? 358-367
Emerging solutions to manage energy/performance trade-offs along the memory hierarchy
- Matthias Boettcher, Giacomo Gabrielli, Bashir M. Al-Hashimi, Danny Kershaw:
MALEC: a multiple access low energy cache. 368-373 - Chundong Wang, Weng-Fai Wong:
TreeFTL: efficient RAM management for high performance of NAND flash-based storage systems. 374-379 - Jie Guo, Wujie Wen, Yaojun Zhang, Sicheng Li, Hai Li, Yiran Chen:
DA-RAID-5: a disturb aware data protection technique for NAND flash storage systems. 380-385 - Jianhui Yue, Yifeng Zhu:
Exploiting subarrays inside a bank to improve phase change memory performance. 386-391 - Cedric Nugteren, Gert-Jan van den Braak, Henk Corporaal:
Future of GPGPU micro-architectural parameters. 392-395 - Ahmed Yasir Dogan, Rubén Braojos, Jeremy Constantin, Giovanni Ansaloni, Andreas Burg, David Atienza:
Synchronizing code execution on ultra-low-power embedded multi-channel signal analysis platforms. 396-399 - Ali Jooya, Amirali Baniasadi:
Using synchronization stalls in power-aware accelerators. 400-403
Device identification and protection
- Nikolaus Theißing, Dominik Merli, Michael Smola, Frederic Stumpf, Georg Sigl:
Comprehensive analysis of software countermeasures against fault attacks. 404-409 - Ali Galip Bayrak, Nikola Velickovic, Francesco Regazzoni, David Novo, Philip Brisk, Paolo Ienne:
An EDA-friendly protection scheme against side-channel attacks. 410-415 - Chi-En Daniel Yin, Gang Qu, Qiang Zhou:
Design and implementation of a group-based RO PUF. 416-421 - Yida Yao, MyungBo Kim, Jianmin Li, Igor L. Markov, Farinaz Koushanfar:
ClockPUF: physical unclonable functions based on clock networks. 422-427 - Patrick Koeberl, Ünal Koçabas, Ahmad-Reza Sadeghi:
Memristor PUFs: a new generation of memory-based physically unclonable functions. 428-431 - Álvaro Díaz Suárez, Pablo Sánchez Espeso, Juan Sancho, Juan Rico:
Wireless sensor network simulation for security and performance analysis. 432-435
New techniques for test pattern generation
- Stefan Hillebrecht, Michael A. Kochte, Dominik Erb, Hans-Joachim Wunderlich, Bernd Becker:
Accurate QBF-based test pattern generation in presence of unknown values. 436-441 - Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine:
Test solution for data retention faults in low-power SRAMs. 442-447 - Matthias Sauer, Sven Reimer, Tobias Schubert, Ilia Polian, Bernd Becker:
Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths. 448-453 - Chia-Ling Chang, Charles H.-P. Wen, Jayanta Bhadra:
Process-variation-aware Iddq diagnosis for nano-scale CMOS designs - the first step. 454-457
Hot topic: security challenges in automotive hardware/software architecture design
- Florian Sagstetter, Martin Lukasiewycz, Sebastian Steinhorst, Marko Wolf, Alexandre Bouard, William R. Harris, Somesh Jha, Thomas Peyrin, Axel Poschmann, Samarjit Chakraborty:
Security challenges in automotive hardware/software architecture design. 458-463
Hot topic - system approaches to energy-efficiency
- Nikola Rajovic, Alejandro Rico, James Vipond, Isaac Gelado, Nikola Puzovic, Alex Ramírez:
Experiences with mobile processors for energy efficient HPC. 464-468 - Xavier Vigouroux:
What designs for coming supercomputers? 469 - Wolfgang Lehner:
Energy-efficient in-memory database computing. 470-474 - Luka Stanisic, Brice Videau, Johan Cronsioe, Augustin Degomme, Vania Marangozova-Martin, Arnaud Legrand, Jean-François Méhaut:
Performance analysis of HPC applications on low-power embedded platforms. 475-480
Panel: can energy harvesting deliver enough power for automotive electronics?
- Robert Kappel, Günter Hofer, Gerald Holweg, Thomas Herndl:
Alternative power supply concepts for self-sufficient wireless sensor nodes by energy harvesting. 481 - Paul D. Mitcheson:
Adaptable, high performance energy harvesters: can energy harvesting deliver enough power for automotive electronics? 482 - Christoph Grimm, Javier Moreno, Xiao Pan:
Ultra-low power: an EDA challenge. 483 - Tom J. Kazmierski, Leran Wang, Bashir M. Al-Hashimi, Geoff V. Merrett:
DoE-based performance optimization of energy management in sensor nodes powered by tunable energy-harvesters. 484
Post-silicon debug techniques
- Min Li, Azadeh Davoodi:
A hybrid approach for fast and accurate trace signal selection for post-silicon debug. 485-490 - Andrew DeOrio, Qingkun Li, Matthew Burgess, Valeria Bertacco:
Machine learning-based anomaly detection for post-silicon bug diagnosis. 491-496 - Sandeep Chandran, Smruti R. Sarangi, Preeti Ranjan Panda:
Space sensitive cache dumping for post-silicon validation. 497-502 - Alessandro Cevrero, Nestor E. Evmorfopoulos, Charalampos Antoniadis, Paolo Ienne, Yusuf Leblebici, Andreas Burg, Georgios I. Stamoulis:
Fast and accurate BER estimation methodology for I/O links based on extreme value theory. 503-508 - Rohit Kumar Jain, Praveen Tiwari, Soumen Ghosh:
Automated determination of top level control signals. 509-512
Novel approaches for real-time architectures
- Leonidas Kosmidis, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla:
A cache design for probabilistically analysable real-time systems. 513-518 - Michel A. Kinsy, Ivan Celanovic, Omer Khan, Srinivas Devadas:
MARTHA: architecture for control and emulation of power electronics and smart grid systems. 519-524 - Sven Goossens, Benny Akesson, Kees Goossens:
Conservative open-page policy for mixed time-criticality memory controllers. 525-530 - Farhat Thabet, Yves Lhuillier, Caaliph Andriamisaina, Jean-Marc Philippe, Raphaël David:
An efficient and flexible hardware support for accelerating synchronization operations on the STHORM many-core architecture. 531-534
Error-aware adaptive modern computing architectures
- Zoltán Endre Rákossy, Masayuki Hiromoto, Hiroshi Tsutsui, Takashi Sato, Yukihiro Nakamura, Hiroyuki Ochi:
Hot-swapping architecture with back-biased testing for mitigation of permanent faults in functional unit array. 535-540 - Abbas Rahimi, Andrea Marongiu, Paolo Burgio, Rajesh K. Gupta, Luca Benini:
Variation-tolerant OpenMP tasking on tightly-coupled processor clusters. 541-546 - Zheng Wang, Kapil Singh, Chao Chen, Anupam Chattopadhyay:
Accurate and efficient reliability estimation techniques during ADL-driven embedded processor design. 547-552
Advances in mixed-signal, RF, and MEMS testing
- Ke Huang, Nathan Kupp, John M. Carulli Jr., Yiorgos Makris:
Handling discontinuous effects in modeling spatial correlation of wafer-level analog/RF tests. 553-558 - Kai Hu, Bang-Ning Hsu, Andrew Madison, Krishnendu Chakrabarty, Richard B. Fair:
Fault detection, real-time error recovery, and experimental demonstration for digital microfluidic biochips. 559-564 - Ender Yilmaz, Geoff Shofner, LeRoy Winemberg, Sule Ozev:
Fault analysis and simulation of large scale industrial mixed-signal circuits. 565-570 - Lingfei Deng, Vinay Kundur, Naveen Sai Jangala Naga, Muhlis Kenan Ozel, Ender Yilmaz, Sule Ozev, Bertan Bakkaloglu, Sayfe Kiaei, Divya Pratab, Tehmoor Dar:
Electrical calibration of spring-mass MEMS capacitive accelerometers. 571-574
Compilers and software synthesis for embedded systems
- Christophe Alias, Alain Darte, Alexandru Plesco:
Optimizing remote accesses for offloaded kernels: application to high-level synthesis for FPGA. 575-580 - Reinhard von Hanxleden, Michael Mendler, Joaquín Aguado, Björn Duderstadt, Insa Fuhrmann, Christian Motika, Stephen Mercer, Owen O'Brien:
Sequentially constructive concurrency: a conservative extension of the synchronous model of computation. 581-586 - Zhonglei Wang, Jörg Henkel:
Fast and accurate cache modeling in source-level simulation of embedded software. 587-592 - Ke Bai, Aviral Shrivastava:
Automatic and efficient heap data management for limited local memory multicore architectures. 593-598 - Jingtong Hu, Qingfeng Zhuge, Chun Jason Xue, Wei-Che Tseng, Edwin Hsing-Mean Sha:
Software enabled wear-leveling for hybrid PCM main memory on embedded systems. 599-602 - Leonidas Kosmidis, Charlie Curtsinger, Eduardo Quiñones, Jaume Abella, Emery D. Berger, Francisco J. Cazorla:
Probabilistic timing analysis on conventional cache designs. 603-606
Embedded tutorial - HW-SW architecture approaches to energy-efficiency
- Gasser Ayad, Andrea Acquaviva, Enrico Macii, Brahim Sahbi, Romain Lemaire:
HW-SW integration for energy-efficient/variability-aware computing. 607-611
Hot topic: emerging nanoscale devices: a booster for high performance computing
- Vivek De:
Near-threshold voltage design in nanoscale CMOS. 612 - Edith Beigné, Alexandre Valentian, Bastien Giraud, Olivier Thomas, Thomas Benoist, Yvain Thonnart, Serge Bernard, Guillaume Moritz, Olivier Billoint, Y. Maneglia, Philippe Flatresse, Jean-Philippe Noel, Fady Abouzeid, Bertrand Pelloux-Prayer, Anuj Grover, Sylvain Clerc, Philippe Roche, Julien Le Coz, Sylvain Engels, Robin Wilson:
Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs. 613-618 - Hai Wei, Max M. Shulaker, Gage Hills, Hong-Yu Chen, Chi-Shuen Lee, Luckshitha Liyanage, Jie Zhang, H.-S. Philip Wong, Subhasish Mitra:
Carbon nanotube circuits: opportunities and challenges. 619-624 - Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Shashikanth Bobba, Michele De Marchi, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli:
Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs. 625-630
Verification and simulation support for architecture
- Leandro S. Freitas, Eberle A. Rambo, Luiz C. V. dos Santos:
On-the-fly verification of memory consistency with concurrent relaxed scoreboards. 631-636 - Kun Lu, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
Fast cache simulation for host-compiled simulation of embedded software. 637-642 - Fan-Wei Yu, Bo-Han Zeng, Yu-Hung Huang, Hsin-I Wu, Che-Rung Lee, Ren-Song Tsay:
A critical-section-level timing synchronization approach for deterministic multi-core instruction set simulations. 643-648 - Jiaxin Li, Weihua Zhang, Haibo Chen, Binyu Zang:
Multi-level phase analysis for sampling simulation. 649-654 - Grigorios Lyras, Dimitrios Rodopoulos, Antonis Papanikolaou, Dimitrios Soudris:
Hypervised transient SPICE simulations of large netlists & workloads on multi-processor systems. 655-658
Design space exploration for application specific architectures
- Sotirios Xydis, Gianluca Palermo, Vittorio Zaccaria, Cristina Silvano:
A meta-model assisted coprocessor synthesis framework for compiler/architecture parameters customization. 659-664 - Felipe Sampaio, Bruno Zatt, Muhammad Shafique, Luciano Volcan Agostini, Sergio Bampi, Jörg Henkel:
Energy-efficient memory hierarchy for motion and disparity estimation in multiview video coding. 665-670 - Edoardo Paone, Nazanin Vahabi, Vittorio Zaccaria, Cristina Silvano, Diego Melpignano, Germain Haugou, Thierry Lepley:
Improving simulation speed and accuracy for many-core embedded platforms with ensemble models. 671-676 - Mostafa Rizk, Amer Baghdadi, Michel Jézéquel, Yasser Mohana, Youssef Atat:
Statically-scheduled application-specific processor design: a case-study on MMSE MIMO equalization. 677-680 - Gustavo Girão, Thiago Santini, Flávio Rech Wagner:
Exploring resource mapping policies for dynamic clustering on NoC-based MPSoCs. 681-684 - Vitaly Zakharenko, Tor M. Aamodt, Andreas Moshovos:
Characterizing the performance benefits of fused CPU/GPU systems using FusionSim. 685-688
Reliable multi-processor computing systems design
- Anup Das, Akash Kumar, Bharadwaj Veeravalli:
Reliability-driven task mapping for lifetime extension of networks-on-chip based multiprocessor systems. 689-694 - Yizhuo Wang, Weixing Ji, Feng Shi, Qi Zuo:
A work-stealing scheduling framework supporting fault tolerance. 695-700 - Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato:
A cost-effective selective TMR for heterogeneous coarse-grained reconfigurable architectures based on DFG-level vulnerability analysis. 701-706 - Tuo Li, Muhammad Shafique, Semeen Rehman, Swarnalatha Radhakrishnan, Roshan G. Ragel, Jude Angelo Ambrose, Jörg Henkel, Sri Parameswaran:
CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors. 707-712 - Nico Hellwege, Nils Heidmann, Dagmar Peters-Drolshagen, Steffen Paul:
Reliability analysis for integrated circuit amplifiers used in neural measurement systems. 713-716 - Luca Cassano, Dario Cozzi, Sebastian Korf, Jens Hagemeyer, Mario Porrmann, Luca Sterpone:
On-line testing of permanent radiation effects in reconfigurable systems. 717-720 - Shanker Shreejith, Kizheppatt Vipin, Suhaib A. Fahmy, Martin Lukasiewycz:
An approach for redundancy in FlexRay networks using FPGA partial reconfiguration. 721-724
Hot topic: energy-efficient design and test techniques for future multi-core systems
- Paul Wettin, Jacob Murray, Partha Pratim Pande, Behrooz A. Shirazi, Amlan Ganguly:
Energy-efficient multicore chip design through cross-layer approach. 725-730 - Paul Ampadu, Meilin Zhang, Vladimir Stojanovic:
Breaking the energy barrier in fault-tolerant caches for multicore systems. 731-736 - Xrysovalantis Kavousianos, Krishnendu Chakrabarty:
Testing for SoCs with advanced static and dynamic power-management capabilities. 737-742 - Rajesh Mittal, Lakshmanan Balasubramanian, Y. B. Chethan Kumar, V. R. Devanathan, Mudasir Kawoosa, Rubin A. Parekhji:
Towards adaptive test of multi-core RF SoCs. 743-748
Model-based design and verification for embedded systems
- Pratyush Kumar, Devesh B. Chokshi, Lothar Thiele:
A satisfiability approach to speed assignment for distributed real-time systems. 749-754 - Sofiane Lagraa, Alexandre Termier, Frédéric Pétrot:
Data mining MPSoC simulation traces to identify concurrent memory access patterns. 755-760 - Joost-Pieter Katoen, Thomas Noll, Hao Wu, Thomas Santen, Dirk Seifert:
Model-based energy optimization of automotive control systems. 761-766 - Sophie Quinton, Mircea Negrean, Rolf Ernst:
Formal analysis of sporadic bursts in real-time systems. 767-772
Hot topic - many-core SoC approaches to energy-efficiency
- Takashi Miyamori, Hui Xu, Takeshi Kodaka, Hiroyuki Usui, Toru Sano, Jun Tanabe:
Development of low power many-core SoC for multimedia applications. 773-777 - Nicolas Darbel, Stéphane Lecomte:
SoC low-power practices for wireless applications. 778 - Denis Dutoit, Eric Guthmuller, Ivan Miro Panades:
3D integration for power-efficient computing. 779-784
Formal verification algorithms and models
- Parosh Aziz Abdulla, Sandhya Dwarkadas, Ahmed Rezine, Arrvindh Shriraman, Yunyun Zhu:
Verifying safety and liveness for the FlexTM hybrid transactional memory. 785-790 - Tobias Welp, Andreas Kuehlmann:
QF BV model checking with property directed reachability. 791-796 - Alan Mishchenko, Niklas Eén, Robert K. Brayton, Michael L. Case, Pankaj Chauhan, Nikhil Sharma:
A semi-canonical form for sequential AIGs. 797-802 - Carmelo Loiacono, Marco Palena, Paolo Pasini, Denis Patti, Stefano Quer, Stefano Ricossa, Danilo Vendraminetto, Jason Baumgartner:
Fast cone-of-influence computation and estimation in problems with multiple properties. 803-806 - John D. Backes, Marc D. Riedel:
Using cubes of non-state variables with property directed reachability. 807-810 - Alexandra Goultiaeva, Martina Seidl, Armin Biere:
Bridging the gap between dual propagation and CNF-based QBF solving. 811-814
Dynamic reconfiguration
- Adrian Alin Lifa, Petru Eles, Zebo Peng:
Dynamic configuration prefetching based on piecewise linear prediction. 815-820 - Brahim Al Farisi, Karel Bruneel, João M. P. Cardoso, Dirk Stroobandt:
An automatic tool flow for the combined implementation of multi-mode circuits. 821-826 - Anthony Brandon, Stephan Wong:
Support for dynamic issue width in VLIW processors using generic binaries. 827-832 - Byron Navas, Ingo Sander, Johnny Öberg:
The RecoBlock SoC platform: a flexible array of reusable run-time-reconfigurable IP-blocks. 833-838 - Chih-Ming Hsieh, Zhonglei Wang, Jörg Henkel:
DANCE: distributed application-aware node configuration engine in shared reconfigurable sensor networks. 839-842 - Cuong Pham-Quoc, Jan Heisswolf, Stephan Werner, Zaid Al-Ars, Jürgen Becker, Koen Bertels:
Hybrid interconnect design for heterogeneous hardware accelerators. 843-846
Emerging memory
- Jue Wang, Xiangyu Dong, Yuan Xie:
OAP: an obstruction-aware cache management policy for STT-RAM last-level caches. 847-852 - Xiuyuan Bi, Mohamed Anis Weldon, Hai Li:
STT-RAM designs supporting dual-port accesses. 853-858 - Jie Guo, Jun Yang, Youtao Zhang, Yiran Chen:
Low cost power failure protection for MLC NAND flash storage systems with PRAM/DRAM hybrid buffer. 859-864 - Xiao Sheng, Yiqun Wang, Yongpan Liu, Huazhong Yang:
SPaC: a segment-based parallel compression for backup acceleration in nonvolatile processors. 865-868 - Ping Zhou, Youtao Zhang, Jun Yang:
The design of sustainable wireless sensor network node using solar energy and phase change memory. 869-872 - Zhen Li, Sébastien Le Beux, Christelle Monat, Xavier Letartre, Ian O'Connor:
Optical look up table. 873-876 - Sandeep Miryala, Mehrdad Montazeri, Andrea Calimera, Enrico Macii, Massimo Poncino:
A verilog-a model for reconfigurable logic gates based on graphene pn-junctions. 877-880
Energy-efficient architectures and software design for power-constrained systems
- Yanzhi Wang, Xue Lin, Massoud Pedram, Sangyoung Park, Naehyuck Chang:
Optimal control of a grid-connected hybrid electrical energy storage system for homes. 881-886 - Haisheng Liu, Smaïl Niar:
Radar signature in multiple target tracking system for driver assistant application. 887-892 - Jonas Pistor, Janpeter Hoeffmann, David Rotermund, Elena Tolstosheeva, Tim Schellenberg, Dmitriy Boll, Víctor Gordillo-González, Sunita Mandon, Dagmar Peters-Drolshagen, Andreas K. Kreiter, Martin Schneider, Walter Lang, Klaus Pawelzik, Steffen Paul:
Development of a fully implantable recording system for ECoG signals. 893-898 - Rubén Braojos, Giovanni Ansaloni, David Atienza:
A methodology for embedded classification of heartbeats using random projections. 899-904 - Alex S. Weddell, Michele Magno, Geoff V. Merrett, Davide Brunelli, Bashir M. Al-Hashimi, Luca Benini:
A survey of multi-source energy harvesting systems. 905-908 - Yanzhi Wang, Xue Lin, Massoud Pedram, Jaemin Kim, Naehyuck Chang:
Capital cost-aware design and partial shading-aware architecture optimization of a reconfigurable photovoltaic system. 909-912 - Reza Lotfian, Roozbeh Jafari:
An ultra-low power hardware accelerator architecture for wearable computers using dynamic time warping. 913-916 - Bojan Maric, Jaume Abella, Mateo Valero:
Efficient cache architectures for reliable hybrid voltage operation using EDC codes. 917-920
On-line approaches towards processor resilience
- Hamid Mushtaq, Zaid Al-Ars, Koen Bertels:
Efficient software-based fault tolerance approach on multicore platforms. 921-926 - Yue Gao, Sandeep K. Gupta, Melvin A. Breuer:
Using explicit output comparisons for fault tolerant scheduling (FTS) on modern high-performance processors. 927-932 - Sundaram Ananthanarayanan, Siddharth Garg, Hiren D. Patel:
Low cost permanent fault detection using ultra-reduced instruction set co-processors. 933-938 - Heinz Riener, Stefan Frehse, Görschwin Fey:
Improving fault tolerance utilizing hardware-software-co-synthesis. 939-942 - Luming Yan, Huaguo Liang, Zhengfeng Huang:
A dynamic self-adaptive correction method for error resilient application. 943-946
Embedded tutorial: from multi-core SoC to scale-out processors
- Marcello Coppola, Babak Falsafi, John Goodacre, George Kornaros:
From embedded multi-core SoCs to scale-out processors. 947-951
Hot topic - fabrication technology approaches to energy-efficiency
- Philippe Magarshack, Philippe Flatresse, Giorgio Cesana:
UTBB FD-SOI: a process/design symbiosis for breakthrough energy-efficiency. 952-957 - Gerhard P. Fettweis, Najeeb ul Hassan, Lukas Landau, Erik Fischer:
Wireless interconnect for board and chip level. 958-963 - Yuan Xie:
Future memory and interconnect technologies. 964-969
Scheduling for real-time embedded systems
- Jung-Eun Kim, Man-Ki Yoon, Sungjin Im, Richard M. Bradford, Lui Sha:
Optimized scheduling of multi-IMA partitions with exclusive region for synchronized real-time multi-core systems. 970-975 - Deepak Gangadharan, Samarjit Chakraborty, Roger Zimmermann:
Quality-aware media scheduling on MPSoC platforms. 976-981 - Martin Lukasiewycz, Sebastian Steinhorst, Samarjit Chakraborty:
Priority assignment for event-triggered systems using mathematical programming. 982-987 - Alessandro Cilardo, Luca Gallo, Antonino Mazzeo, Nicola Mazzocca:
Efficient and scalable OpenMP-based system-level design. 988-991 - Xinyu He, Shuangchen Li, Yongpan Liu, Xiaobo Sharon Hu, Huazhong Yang:
Utilizing voltage-frequency islands in C-to-RTL synthesis for streaming applications. 992-995
Logic synthesis techniques
- Anna Bernasconi, Valentina Ciriani, Gabriella Trucco, Tiziano Villa:
Minimization of P-circuits using Boolean relations. 996-1001 - Haoxing Ren, Ruchir Puri, Lakshmi N. Reddy, Smita Krishnaswamy, Cindy Washburn, Joel Earl, Joachim Keinert:
Intuitive ECO synthesis for high performance circuits. 1002-1007 - Yinghai Lu, Hai Zhou:
Retiming for Soft Error Minimization Under Error-Latching Window Constraints. 1008-1013 - Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Biconditional BDD: a novel canonical BDD for logic synthesis targeting XOR-rich circuits. 1014-1017 - Stergios Stergiou, Jawahar Jain:
Optimizing BDDs for time-series dataset manipulation. 1018-1021 - Farshad Firouzi, Saman Kiamehr, Mehdi Baradaran Tahoori, Sani R. Nassif:
Incorporating the impacts of workload-dependent runtime variations into timing analysis. 1022-1025
High-speed robust NoCs
- Ayan Mandal, Sunil P. Khatri, Rabi N. Mahapatra:
Exploring topologies for source-synchronous ring-based network-on-chip. 1026-1031 - Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy:
Proactive aging management in heterogeneous NoCs through a criticality-driven routing approach. 1032-1037 - Davide Zoni, William Fornaciari:
Sensor-wise methodology to face NBTI stress of NoC buffers. 1038-1043 - Jens Sparsø, Evangelia Kasapaki, Martin Schoeberl:
An area-efficient network interface for a TDM-based network-on-chip. 1044-1047 - Masoud Daneshtalab, Masoumeh Ebrahimi, Juha Plosila, Hannu Tenhunen:
CARS: congestion-aware request scheduler for network interfaces in NoC-based manycore systems. 1048-1051
Industrial experiences with embedded system design
- Yves Janin, Valérie Bertin, Hervé Chauvet, Thomas Deruyter, Christophe Eichwald, Olivier-André Giraud, Vincent Lorquet, Thomas Thery:
Designing tightly-coupled extension units for the STxP70 processor. 1052-1053 - Erwan Piriou, Raphaël David, Fahim Rahim, Solaiman Rahim:
A fast and accurate methodology for power estimation and reduction of programmable architectures. 1054-1055 - Smriti Joshi, Anne Lombardot, Marc Belleville, Edith Beigné, Stéphane Girard:
A gate level methodology for efficient statistical leakage estimation in complex 32nm circuits. 1056-1057 - Takeshi Kodaka, Akira Takeda, Shunsuke Sasaki, Akira Yokosawa, Toshiki Kizu, Takahiro Tokuyoshi, Hui Xu, Toru Sano, Hiroyuki Usui, Jun Tanabe, Takashi Miyamori, Nobu Matsumoto:
A near-future prediction method for low power consumption on a many-core processor. 1058-1059 - Damien Chabrol, Didier Roux, Vincent David, Mathieu Jan, Moha Ait Hmid, Patrice Oudin, Gilles Zeppa:
Time- and angle-triggered real-time kernel. 1060-1062 - Josef Schneider, Sri Parameswaran:
An extremely compact JPEG encoder for adaptive embedded systems. 1063-1064
DfT methods
- Sergej Deutsch, Krishnendu Chakrabarty:
Non-invasive pre-bond TSV test using ring oscillators and multiple voltage levels. 1065-1070 - Dhrumeel Bakshi, Michael S. Hsiao:
LFSR seed computation and reduction using SMT-based fault-chaining. 1071-1076 - Sébastien Sarrazin, Samuel Evain, Lirida Alves de Barros Naviner, Yannick Bonhomme, Valentin Gherman:
Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection. 1077-1082 - Irith Pomeranz:
On candidate fault sets for fault diagnosis and dominance graphs of equivalence classes. 1083-1088 - Xiaoyu Huang, Jimson Mathew, Rishad A. Shafik, Subhasis Bhattacharjee, Dhiraj K. Pradhan:
A fast and Effective DFT for test and diagnosis of power switches in SoCs. 1089-1092
Monitoring and control of cyber physical systems
- Amir Aminifar, Petru Eles, Zebo Peng, Anton Cervin:
Control-quality driven design of cyber-physical systems with robustness guarantees. 1093-1098 - Reinhard Schneider, Licong Zhang, Dip Goswami, Alejandro Masrur, Samarjit Chakraborty:
Compositional analysis of switched ethernet topologies. 1099-1104 - Johannes Kloos, Rupak Majumdar:
Supervisor synthesis for controller upgrades. 1105-1110 - Tobias Bund, Benjamin Menhorn, Frank Slomka:
Event density analysis for event triggered control systems. 1111-1116 - Riccardo Muradore, Davide Quaglia, Paolo Fiorini:
Model predictive control over delay-based differentiated services control networks. 1117-1122 - Dip Goswami, Alejandro Masrur, Reinhard Schneider, Chun Jason Xue, Samarjit Chakraborty:
Multirate controller design for resource- and schedule-constrained automotive ECUs. 1123-1126 - Alessandro Perelli, Carlo Caione, Luca De Marchi, Davide Brunelli, Alessandro Marzani, Luca Benini:
Design of an ultra-low power device for aircraft structural health monitoring. 1127-1130
Hot topic: countering counterfeit attacks on micro-electronics
- Nathalie Kae-Nune, Stephanie Pesseguier:
Qualification and testing process to implement anti-counterfeiting technologies into IC packages. 1131-1136 - Vincent van der Leest, Pim Tuyls:
Anti-counterfeiting with hardware intrinsic security. 1137-1142
Hot topic: smart grid and buildings
- Michela Milano:
Sustainable energy policies: research challenges and opportunities. 1143-1148 - Levent Gürgen, Ozan Necati Günalp, Yazid Benazzouz, Mathieu Gallissot:
Self-aware cyber-physical systems and applications in smart buildings and cities. 1149-1154 - Danilo Porcarelli, Domenico Balsamo, Davide Brunelli, Giacomo Paci:
Perpetual and low-cost power meter for monitoring residential and industrial appliances. 1155-1160
System-level analysis and simulation
- Kun Lu, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
Analytical timing estimation for temporally decoupled TLMs considering resource conflicts. 1161-1166 - Maher Fakih, Kim Grüttner, Martin Fränzle, Achim Rettberg:
Towards performance analysis of SDFGs mapped to shared-bus architectures using model-checking. 1167-1172 - Yue Ma, Huafeng Yu, Thierry Gautier, Paul Le Guernic, Jean-Pierre Talpin, Loïc Besnard, Maurice Heitz:
Toward polychronous analysis and validation for timed software architectures in AADL. 1173-1178 - Jan Malburg, Alexander Finder, Görschwin Fey:
Tuning dynamic data flow analysis to support design understanding. 1179-1184 - Claude Helmstetter, Jérôme Cornet, Bruno Galilée, Matthieu Moy, Pascal Vivet:
Fast and accurate TLM simulations using temporal decoupling for FIFO-based communications. 1185-1188 - Julia Seiter, Robert Wille, Mathias Soeken, Rolf Drechsler:
Determining relevant model elements for the verification of UML/OCL specifications. 1189-1192 - Robert Wille, Martin Gogolla, Mathias Soeken, Mirco Kuhlmann, Rolf Drechsler:
Towards a generic verification methodology for system models. 1193-1196
Thermal/power management techniques for energy-efficient systems
- Biswajit Mishra, Cyril Botteron, Gabriele Tasselli, Christian Robert, Pierre-André Farine:
A sub-μa power management circuit in 0.18μm CMOS for energy harvesters. 1197-1202 - Yang Xiao, Kevin M. Irick, Vijaykrishnan Narayanan, Donghwa Shin, Naehyuck Chang:
Saliency aware display power management. 1203-1208 - Andrew B. Kahng, Seokhyeong Kang, Bongil Park:
Active-mode leakage reduction with data-retained power gating. 1209-1214 - Hai Wang, Sheldon X.-D. Tan, Sahana Swarup, Xuexin Liu:
A power-driven thermal sensor placement algorithm for dynamic thermal management. 1215-1220 - Xuan Wang, Jiang Xu, Wei Zhang, Xiaowen Wu, Yaoyao Ye, Zhehui Wang, Mahdi Nikdast, Zhe Wang:
Active power-gating-induced power/ground noise alleviation using parasitic capacitance of on-chip memories. 1221-1224 - Qing Xie, Siyu Yue, Massoud Pedram, Donghwa Shin, Naehyuck Chang:
Adaptive thermal management for portable system batteries by forced convection cooling. 1225-1228
Emerging architectures
- Ying Teng, Baris Taskin:
Sparse-rotary oscillator array (SROA) design for power and skew reduction. 1229-1234 - Alireza Shafaei, Mehdi Saeedi, Massoud Pedram:
Reversible logic synthesis of k-input, m-output lookup tables. 1235-1240 - Tiansheng Zhang, Alessandro Cevrero, Giulia Beanato, Panagiotis Athanasopoulos, Ayse K. Coskun, Yusuf Leblebici:
3D-MMC: a modular 3D multi-core architecture with efficient resource pooling. 1241-1246 - Jianhua Li, Liang Shi, Qing'an Li, Chun Jason Xue, Yiran Chen, Yinlong Xu:
Cache coherence enabled adaptive refresh for volatile STT-RAM. 1247-1250 - Mihai Lefter, George Razvan Voicu, Mottaqiallah Taouil, Marius Enachescu, Said Hamdioui, Sorin Dan Cotofana:
Is TSV-based 3D integration suitable for inter-die memory repair? 1251-1254 - Qiaosha Zou, Tao Zhang, Eren Kursun, Yuan Xie:
Thermomechanical stress-aware management for 3D IC designs. 1255-1258
Manufacturing and design security
- Jeyavijayan Rajendran, Ozgur Sinanoglu, Ramesh Karri:
Is split manufacturing secure? 1259-1264 - Byeongju Cha, Sandeep K. Gupta:
Trojan detection via delay measurements: a new approach to select paths and vectors to maximize effectiveness and minimize cost. 1265-1270 - Kangqiao Hu, Abdullah Nazma Nowroz, Sherief Reda, Farinaz Koushanfar:
High-sensitivity hardware trojan detection using multimodal characterization. 1271-1276 - Pramod Subramanyan, Nestan Tsiskaridze, Kanika Pasricha, Dillon Reisman, Adriana Susnea, Sharad Malik:
Reverse engineering digital circuits using functional analysis. 1277-1280 - Jason Oberg, Sarah Meiklejohn, Timothy Sherwood, Ryan Kastner:
A practical testing framework for isolating hardware timing channels. 1281-1284
Improving IC quality and lifetime though advanced characterization
- Yu Cai, Erich F. Haratsch, Onur Mutlu, Ken Mai:
Threshold voltage distribution in MLC NAND flash memory: characterization, analysis, and modeling. 1285-1290 - Jian Yao, Zuochang Ye, Yan Wang:
Efficient importance sampling for high-sigma yield analysis with adaptive online surrogate modeling. 1291-1296 - Salomon Beer, Ran Ginosar, Jerome Cox, Tom Chaney, David M. Zar:
Metastability challenges for 65nm and beyond: simulation and measurements. 1297-1302 - Peyman Pouyan, Esteve Amat, Francesc Moll, Antonio Rubio:
Design and implementation of an adaptive proactive reconfiguration technique for SRAM caches. 1303-1306
Design and scheduling
- Manil Dev Gomony, Benny Akesson, Kees Goossens:
Architecture and optimal configuration of a real-time multi-channel memory controller. 1307-1312 - Man-Ki Yoon, Jung-Eun Kim, Richard M. Bradford, Lui Sha:
Holistic design parameter optimization of multiple periodic resources in hierarchical scheduling. 1313-1318 - Qi Zhu, Peng Deng, Marco Di Natale, Haibo Zeng:
Robust and extensible task implementations of synchronous finite state machines. 1319-1324 - Mohammed El-Shambakey, Binoy Ravindran:
FBLT: a real-time contention manager with improved schedulability. 1325-1330 - Daniel Mueller-Gritschneder, Kun Lu, Erik Wallander, Marc Greim, Ulf Schlichtmann:
A virtual prototyping platform for real-time systems with a case study for a two-wheeled robot. 1331-1334 - Victor Pollex, Timo Feld, Frank Slomka, Ulrich Margull, Ralph Mader, Gerhard Wirrer:
Sufficient real-time analysis for an engine control unit with constant angular velocities. 1335-1338
Hot topic: smart data centers design and optimization
- Patrick W. Ruch, Thomas Brunschwiler, Stephan Paredes, Gerhard Ingmar Meijer, Bruno Michel:
Roadmap towards ultimately-efficient zeta-scale datacenters. 1339-1344 - Jungsoo Kim, Martino Ruggiero, David Atienza, Marcel Lederberger:
Correlation-aware virtual machine allocation for energy-efficient datacenters. 1345-1350 - Christos Kozyrakis:
Resource efficient computing for warehouse-scale datacenters. 1351-1356
Embedded tutorial: on the use of GP-GPUs for accelerating computing intensive EDA applications
- Valeria Bertacco, Debapriya Chatterjee, Nicola Bombieri, Franco Fummi, Sara Vinco, Anirudh M. Kaushik, Hiren D. Patel:
On the use of GP-GPUs for accelerating compute-intensive EDA applications. 1357-1366
Thermal analysis and power optimization techniques
- Swagath Venkataramani, Kaushik Roy, Anand Raghunathan:
Substitute-and-simplify: a unified design paradigm for approximate and quality configurable circuits. 1367-1372 - Thidapat Chantem, Xiang Yun, Xiaobo Sharon Hu, Robert P. Dick:
Enhancing multicore reliability through wear compensation in online assignment and scheduling. 1373-1378 - Yu-Min Lee, Tsung-Heng Wu, Pei-Yu Huang, Chi-Ping Yang:
NUMANA: a hybrid <u>num</u>erical and <u>ana</u>lytical thermal simulator for 3-D ICs. 1379-1384 - Alain Fourmigue, Giovanni Beltrame, Gabriela Nicolescu:
Explicit transient thermal simulation of liquid-cooled 3D ICs. 1385-1390 - Francesco Paterna, Sherief Reda:
Mitigating dark-silicon problems using superlattice-based thermoelectric coolers. 1391-1394 - Jia Zhao, Shiting (Justin) Lu, Wayne P. Burleson, Russell Tessier:
Run-time probabilistic detection of miscalibrated thermal sensors in many-core systems. 1395-1398
Abstraction techniques and SAT/SMT-based optimizations
- Alan Mishchenko, Niklas Eén, Robert K. Brayton, Jason Baumgartner, Hari Mony, Pradeep Kumar Nalla:
GLA: gate-level abstraction revisited. 1399-1404 - Florian Pigorsch, Christoph Scholl:
Lemma localization: a practical method for downsizing SMT-interpolants. 1405-1410 - Anton Belov, Huan Chen, Alan Mishchenko, João Marques-Silva:
Core minimization in SAT-based abstraction. 1411-1416 - Gianpiero Cabodi, Carmelo Loiacono, Danilo Vendraminetto:
Optimization techniques for craig interpolant compaction in unbounded model checking. 1417-1422 - Osman Hasan, Muhammad Ahmad:
Formal analysis of steady state errors in feedback control systems using HOL-light. 1423-1426 - Mahmoud Elbayoumi, Michael S. Hsiao, Mustafa Y. ElNainay:
A novel concurrent cache-friendly binary decision diagram construction for multi-core platforms. 1427-1430
Design and verification of mixed-signal circuits
- Jelle Van Rethy, Hans Danneels, Valentijn De Smedt, Wim Dehaene, Georges G. E. Gielen:
A low-power and low-voltage BBPLL-based sensor interface in 130nm CMOS for wireless sensor networks. 1431-1435 - Seyed Nematollah Ahmadyan, Shobha Vasudevan:
Reachability analysis of nonlinear analog circuits through iterative reachable set reduction. 1436-1441 - Merritt Miller, Forrest Brewer:
Formal verification of analog circuit parameters across variation utilizing SAT. 1442-1447 - Dimitri de Jonghe, Dirk Deschrijver, Tom Dhaene, Georges G. E. Gielen:
Extracting analytical nonlinear models from analog circuits by recursive vector fitting of transfer function trajectories. 1448-1453 - Li Yu, Lan Wei, Dimitri A. Antoniadis, Ibrahim M. Elfadel, Duane S. Boning:
Statistical modeling with the virtual source MOSFET model. 1454-1457 - Yen-Lung Chen, Wan-Rong Wu, Guan-Ruei Lu, Chien-Nan Jimmy Liu:
Automatic circuit sizing technique for the analog circuits with flexible TFTs considering process variation and bending effects. 1458-1461
On-line testing techniques
- Paolo Bernardi, Michele Bonazza, Ernesto Sánchez, Matteo Sonza Reorda, Oscar Ballan:
On-line functionally untestable fault identification in embedded processor cores. 1462-1467 - Javier Carretero, Enric Herrero, Matteo Monchiero, Tanausú Ramírez, Xavier Vera:
Capturing vulnerability variations for register files. 1468-1473 - Salvatore Pontarelli, Marco Ottavi, Adrian Evans, Shi-Jie Wen:
Error detection in ternary CAMs using bloom filters. 1474-1479 - Michail Maniatakos, Maria K. Michael, Yiorgos Makris:
AVF-driven parity optimization for MBU protection of in-core memory arrays. 1480-1485 - Hsiu-Chuan Shih, Cheng-Wen Wu:
An enhanced double-TSV scheme for defect tolerance in 3D-IC. 1486-1489 - Kartik Mohanram, Matthew Wartell, Sundar Iyer:
Mempack: an order of magnitude reduction in the cost, risk, and time for memory compiler certification. 1490-1493 - Fahrettin Koc, Kenan Bozdas, Burak Karsli, Oguz Ergin:
Exploiting replicated checkpoints for soft error detection and correction. 1494-1497
Embedded software for many-core architectures
- Stefan Wildermann, Tobias Ziermann, Jürgen Teich:
Game-theoretic analysis of decentralized core allocation schemes on many-core systems. 1498-1503 - Paolo Burgio, Giuseppe Tagliavini, Andrea Marongiu, Luca Benini:
Enabling fine-grained OpenMP tasking on tightly-coupled shared memory clusters. 1504-1509 - Maroun Ojail, Raphaël David, Yves Lhuillier, Alexandre Guerre:
ARTM: a lightweight fork-join framework for many-core embedded systems. 1510-1515 - Janmartin Jahn, Jörg Henkel:
Pipelets: self-organizing software pipelines for many-core architectures. 1516-1521 - Sungjin Lee, Taejin Kim, Jisung Park, Jihong Kim:
An integrated approach for managing the lifetime of flash-based SSDs. 1522-1525
Panel: will 3D-IC remain a technology of the future... even in the future?
- Marco Casale-Rossi, Patrick Leduc, Giovanni De Micheli, Patrick Blouet, Brendan Farley, Anna Fontanelli, Dragomir Milojevic, Steve Smith:
Panel: "will 3D-IC remain a technology of the future... even in the future?". 1526-1530
Hot topic: smart health
- Daniela De Venuto, Alberto L. Sangiovanni-Vincentelli:
Dr. Frankenstein's dream made possible: implanted electronic devices. 1531-1536 - Chris Van Hoof, Julien Penders:
Addressing the healthcare cost dilemma by managing health instead of managing illness: an opportunity for wearable wireless sensors. 1537-1539 - Jacopo Olivo, Sara S. Ghoreishizadeh, Sandro Carrara, Giovanni De Micheli:
Electronic implants: power delivery and management. 1540-1545 - Joshua Paul van Kleef, Travis L. Massey, Peter Ledochowitsch, Rikky Muller, R. Tiefenauer, Timothy J. Blanche, Hirotaka Sato, Michel M. Maharbiz:
Cyborg insects, neural interfaces and other things: building interfaces between the synthetic and the multicellular. 1546
High-level synthesis and coarse-grained reconfigurable architectures
- Alex Kondratyev, Luciano Lavagno, Mike Meyer, Yosinori Watanabe:
Share with care: a quantitative evaluation of sharing approaches in high-level synthesis. 1547-1552 - Daniel Gomez-Prado, Maciej J. Ciesielski, Russell Tessier:
FPGA latency optimization using system-level transformations and DFG restructuring. 1553-1558 - Mateus B. Rutzig, Antonio Carlos Schneider Beck, Luigi Carro:
A transparent and energy aware reconfigurable multiprocessor platform for simultaneous ILP and TLP exploitation. 1559-1564 - Xiaolin Chen, Shuai Li, Jochen Schleifer, Thomas Coenen, Anupam Chattopadhyay, Gerd Ascheid, Tobias G. Noll:
High-level modeling and synthesis for embedded FPGAs. 1565-1570 - Vito Giovanni Castellana, Fabrizio Ferrandi:
Scheduling independent liveness analysis for register binding in high level synthesis. 1571-1574 - Jongeun Lee, Yeonghun Jeong, Sungsok Seo:
Fast shared on-chip memory architecture for efficient hybrid computing with CGRAs. 1575-1578 - Kyuseung Han, Kiyoung Choi, Jongeun Lee:
Compiling control-intensive loops for CGRAs with state-based full predication. 1579-1582
Efficient NoC routing mechanisms
- John Jose, Bhawna Nayak, Damarla Kranthi Kumar, Madhu Mutyam:
DeBAR: deflection based adaptive router with minimal buffering. 1583-1588 - Luca Ramini, Paolo Grani, Sandro Bartolini, Davide Bertozzi:
Contrasting wavelength-routed optical NoC topologies for power-efficient 3D-stacked multicore processors using physical-layer analysis. 1589-1594 - Eduardo Wächter, Augusto Erichsen, Alexandre M. Amory, Fernando Moraes:
Topology-agnostic fault-tolerant NoC routing method. 1595-1600 - Masoumeh Ebrahimi, Masoud Daneshtalab, Juha Plosila:
Fault-tolerant routing algorithm for 3D NoC using Hamiltonian path strategy. 1601-1604 - Abbas BanaiyanMofrad, Nikil D. Dutt, Gustavo Girão:
Modeling and analysis of fault-tolerant distributed memories for networks-on-chip. 1605-1608
System-level modelling for physical properties
- Tayeb Bouhadiba, Matthieu Moy, Florence Maraninchi:
System-level modeling of energy in TLM for early validation of power and thermal management. 1609-1614 - Chang-Chih Chen, Linda Milor:
System-level modeling and microprocessor reliability analysis for backend wearout mechanisms. 1615-1620 - Hananeh Aliee, Michael Glaß, Felix Reimann, Jürgen Teich:
Automatic success tree-based reliability analysis for the consideration of transient and permanent faults. 1621-1626 - Ehsan Saboori, Samar Abdi:
Hybrid prototyping of multicore embedded systems. 1627-1630
Energy challenges for multi-core and NoC architectures
- Anup Das, Akash Kumar, Bharadwaj Veeravalli:
Communication and migration energy aware design space exploration for multicore systems with intermittent faults. 1631-1636 - Sunghyun Park, Masood Qazi, Li-Shiuan Peh, Anantha P. Chandrakasan:
40.4fJ/bit/mm low-swing on-chip signaling with self-resetting logic repeaters embedded within a mesh NoC in 45nm SOI CMOS. 1637-1642 - Kanwen Wang, Hao Yu, Benfei Wang, Chun Zhang:
3D reconfigurable power switch network for demand-supply matching between multi-output power converters and many-core microprocessors. 1643-1648 - Sotirios Xydis, Gianluca Palermo, Cristina Silvano:
Thermal-aware datapath merging for coarse-grained reconfigurable processors. 1649-1654
Modelling and design for signal and power integrity
- Pingqiang Zhou, Vivek Mishra, Sachin S. Sapatnekar:
Placement optimization of power supply pads based on locality. 1655-1660 - Kuangya Zhai, Wenjian Yu, Hao Zhuang:
GPU-friendly floating random walk algorithm for capacitance extraction of VLSI interconnects. 1661-1666 - Nicholas Tzou, Debesh Bhatta, Sen-Wen Hsiao, Abhijit Chatterjee:
Periodic jitter and bounded uncorrelated jitter decomposition using incoherent undersampling. 1667-1672 - Rajeev Kumar, Sunil P. Khatri:
Crosstalk avoidance codes for 3D VLSI. 1673-1678 - Zhuo Feng:
Large-scale flip-chip power grid reduction with geometric templates. 1679-1682
Powerful aging
- Tuck-Boon Chan, Wei-Ting Jonas Chan, Andrew B. Kahng:
Impact of adaptive voltage scaling on aging-aware signoff. 1683-1688 - Konstantis Daloukas, Alexia Marnari, Nestor E. Evmorfopoulos, Panagiota E. Tsompanopoulou, George I. Stamoulis:
A parallel fast transform-based preconditioning approach for electrical-thermal co-simulation of power delivery networks. 1689-1694 - Abbas Rahimi, Luca Benini, Rajesh K. Gupta:
Hierarchically focused guardbanding: an adaptive approach to mitigate PVT variations and aging. 1695-1700 - Shih-Ying Sean Liu, Chieh-Jui Lee, Chuan-Chia Huang, Hung-Ming Chen, Chang-Tzu Lin, Chia-Hsin Lee:
Effective power network prototyping via statistical-based clustering and sequential linear programming. 1701-1706 - Shih-Ying Sean Liu, Ren-Guo Luo, Hung-Ming Chen:
A network-flow based algorithm for power density mitigation at post-placement stage. 1707-1710 - B. N. Bhramar Ray, Shankar Balachandran:
An efficient wirelength model for analytical placement. 1711-1714
Embedded tutorial: advances in asynchronous logic: from principles to GALS & NoC, recent industry applications, and commercial CAD tools
- Alex Yakovlev, Pascal Vivet, Marc Renaudin:
Advances in asynchronous logic: from principles to GALS & NoC, recent industry applications, and commercial CAD tools. 1715-1724
Hot topic: internet of energy - connecting smart mobility in the cloud
- Randolf Mock, Tullio Salmon Cinotti, Johannes Reinschke, Luciano Bononi:
Interactions of large scale EV mobility and virtual power plants. 1725-1729 - Kevin Green, Salvador Rodríguez González, Ruud Wijtvliet:
Innovative energy storage solutions for future electromobility in smart cities. 1730-1734 - Peter Hank, Steffen Müller, Ovidiu Vermesan, Jeroen Van den Keybus:
Automotive ethernet: in-vehicle networking and smart mobility. 1735-1739 - Ovidiu Vermesan, Lars-Cyril Julin Blystad, Reiner John, Peter Hank, Roy Bahr, Alessandro Moscatelli:
Smart, connected and mobile: architecting future electric mobility ecosystems. 1740-1744 - Roberto Zafalon, Giovanni Coppola, Ovidiu Vermesan:
e-Mobility the next frontier for automotive industry. 1745-1748 - Reiner John, Martin Schulz, Ovidiu Vermesan, Kai Kriegel:
Semiconductor technologies for smart mobility management. 1749-1752
Methodologies to improve yield, reliability and security in embedded systems
- Yue Gao, Melvin A. Breuer, Yanzhi Wang:
A new paradigm for trading off yield, area and performance to enhance performance per wafer. 1753-1758 - Semeen Rehman, Muhammad Shafique, Pau Vilimelis Aceituno, Florian Kriebel, Jian-Jia Chen, Jörg Henkel:
Leveraging variable function resilience for selective software reliability on unreliable hardware. 1759-1764 - Ke Jiang, Petru Eles, Zebo Peng:
Optimization of secure embedded systems with dynamic task sets. 1765-1770
NoC mapping and synthesis
- Timo Schönwald, Alexander Viehl, Oliver Bringmann, Wolfgang Rosenstiel:
Shared memory aware MPSoC software deployment. 1771-1776 - Haoyuan Ying, Thomas Hollstein, Klaus Hofmann:
Fast and optimized task allocation method for low vertical link density 3-dimensional networks-on-chip based many core systems. 1777-1782 - Vladimir Todorov, Daniel Mueller-Gritschneder, Helmut Reinig, Ulf Schlichtmann:
A spectral clustering approach to application-specific network-on-chip synthesis. 1783-1788
Emerging logic
- Ying-Yu Chen, Artem Rogachev, Amit Sangai, Giuseppe Iannaccone, Gianluca Fiori, Deming Chen:
A SPICE-compatible model of graphene nano-ribbon field-effect transistors enabling circuit-level delay and power analysis under process variation. 1789-1794 - Indranil Palit, Xiaobo Sharon Hu, Joseph Nahas, Michael T. Niemier:
Systematic design of nanomagnet logic circuits. 1795-1800 - Yehua Su, Wenjing Rao:
Defect-tolerant logic hardening for crossbar-based nanosystems. 1801-1806 - Chang-En Chiang, Li-Fu Tang, Chun-Yao Wang, Ching-Yi Huang, Yung-Chih Chen, Suman Datta, Vijaykrishnan Narayanan:
On reconfigurable single-electron transistor arrays synthesis using reordering techniques. 1807-1812
Emerging technology architectures for energy-efficient memories
- Hiroki Noguchi, Kumiko Nomura, Keiko Abe, Shinobu Fujita, Eishi Arima, Kyundong Kim, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura:
D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory. 1813-1818 - James Boley, Vikas Chandra, Robert C. Aitken, Benton H. Calhoun:
Leveraging sensitivity analysis for fast, accurate estimation of SRAM dynamic write VMIN. 1819-1824 - Rangharajan Venkatesan, Mrigank Sharad, Kaushik Roy, Anand Raghunathan:
DWM-TAPESTRI - an energy efficient all-spin cache using domain wall shift based writes. 1825-1830
Clock distribution and analogue circuit synthesis
- Wen-Pin Tu, Shih-Hsu Huang, Chun-Hua Cheng:
Co-synthesis of data paths and clock control paths for minimum-period clock gating. 1831-1836 - Chia-Chieh Lu, Rung-Bin Lin:
Slack budgeting and slack to length converting for multi-bit flip-flop merging. 1837-1842 - Ahmet Unutulmaz, Günhan Dündar, Francisco V. Fernández:
Area optimization on fixed analog floorplans using convex area functions. 1843-1848 - Po-Cheng Pan, Hung-Ming Chen, Chien-Chih Lin:
PAGE: parallel agile genetic exploration towards utmost performance for analog circuit design. 1849-1854
Physical design
- Vinicius S. Livramento, Chrystian Guth, José Luís Güntzel, Marcelo O. Johann:
Fast and efficient lagrangian relaxation-based discrete gate sizing. 1855-1860 - Andrew B. Kahng, Bill Lin, Siddhartha Nath:
Enhanced metamodeling techniques for high-dimensional IC design estimation problems. 1861-1866 - Markus Struzyna:
Sub-quadratic objectives in quadratic placement. 1867-1872 - Yaoguang Wei, Zhuo Li, Cliff C. N. Sze, Shiyan Hu, Charles J. Alpert, Sachin S. Sapatnekar:
CATALYST: planning layer directives for effective design closure. 1873-1878
Embedded tutorial: closed-loop control for power and thermal management in multi-core processors: formal methods and industrial practice
- Ibrahim M. Elfadel, Radu Marculescu, David Atienza:
Closed-loop control for power and thermal management in multi-core processors: formal methods and industrial practice. 1879-1881
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