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ORCID22. FPGA 2014: Monterey, CA, USA
- Vaughn Betz, George A. Constantinides:
The 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA '14, Monterey, CA, USA - February 26 - 28, 2014. ACM 2014, ISBN 978-1-4503-2671-1
Physical design
- Hongbin Zheng, Swathi T. Gurumani, Kyle Rupnow
, Deming Chen:
Fast and effective placement and routing directed high-level synthesis for FPGAs. 1-10 - Safeen Huda, Jason Helge Anderson, Hirotaka Tamura:
Optimizing effective interconnect capacitance for FPGA power reduction. 11-20 - Jason Luu, Jonathan Rose, Jason Helge Anderson:
Towards interconnect-adaptive packing for FPGAs. 21-30 - Wenyi Feng, Jonathan W. Greene, Kristofer Vorwerk, Val Pevzner, Arun Kundu:
Rent's rule based FPGA packing for routability optimization. 31-34
Architecture
- Ameer Abdelhadi, Guy G. F. Lemieux:
Modular multi-ported SRAM-based memories. 35-44 - Grace Zgheib, Liqun Yang, Zhihong Huang, David Novo, Hadi Parandeh-Afshar, Haigang Yang, Paolo Ienne:
Revisiting and-inverter cones. 45-54 - Sang Woo Jun, Ming Liu, Kermin Elliott Fleming, Arvind:
Scalable multi-access flash store for big data analytics. 55-64
Tools and methods
- Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung:
Dynamic voltage & frequency scaling with online slack measurement. 65-74 - André Hahn Pereira, Vaughn Betz:
Cad and routing architecture for interposer-based multi-FPGA systems. 75-84 - Keita Ito, Tomokazu Yoneda, Yuta Yamato, Kazumi Hatayama, Michiko Inoue:
Memory block based scan-BIST architecture for application-dependent FPGA testing. 85-88
Applications 1
- Georgios Smaragdos, Sebastián Isaza, Martijn F. van Eijk, Ioannis Sourdis, Christos Strydis:
FPGA-based biophysically-meaningful modeling of olivocerebellar neurons. 89-98 - Simin Xu, Suhaib A. Fahmy, Ian Vince McLoughlin:
Square-rich fixed point polynomial evaluation on FPGAs. 99-108 - Yuliang Sun, Zilong Wang, Sitao Huang, Lanjun Wang, Yu Wang, Rong Luo, Huazhong Yang:
Accelerating frequent item counting with FPGA. 109-112 - Brad L. Hutchings, Joshua S. Monson, Danny Savory, Jared Keeley:
A power side-channel-based digital to analog converterfor Xilinx FPGAs. 113-116
Processors and systems
- Aaron Severance, Joe Edwards, Hossein Omidian, Guy Lemieux:
Soft vector processors with streaming pipelines. 117-126 - Artjom Grudnitsky, Lars Bauer, Jörg Henkel:
MORP: makespan optimization for processors with an embedded reconfigurable fabric. 127-136 - Antonio Filgueras, Eduard Gil, Daniel Jiménez-González, Carlos Álvarez, Xavier Martorell, Jan Langer, Juanjo Noguera, Kees A. Vissers:
OmpSs@Zynq all-programmable SoC ecosystem. 137-146 - Hanyang Xu, Jian Wang, Meilai Jin:
A FPGA prototype design emphasis on low power technique. 147-150
Applications 2
- Jared Casper, Kunle Olukotun:
Hardware acceleration of database operations. 151-160 - Richard Dorrance, Fengbo Ren, Dejan Markovic:
A scalable sparse matrix-vector multiplication kernel for energy-efficient sparse-blas on FPGAs. 161-170 - Yanzi Zhu, Peiran Suo, Kia Bazargan:
Binary stochastic implementation of digital logic. 171-180 - Ce Guo, Wayne Luk:
Accelerating parameter estimation for multivariate self-exciting point processes. 181-184 - Mohammed Alawad, Yu Bai, Ronald F. DeMara, Mingjie Lin:
Energy-efficient multiplier-less discrete convolver through probabilistic domain transformation. 185-188
Tools and models 1
- André DeHon:
Wordwidth, instructions, looping, and virtualization: the role of sharing in absolute energy minimization. 189-198 - Yuxin Wang, Peng Li, Jason Cong:
Theory and algorithm for generalized memory partitioning in high-level synthesis. 199-208 - Lee W. Lerner, Zane R. Franklin, William T. Baumann, Cameron D. Patterson:
Using high-level synthesis and formal analysis to predict and preempt attacks on industrial control systems. 209-212
Tools and models 2
- Jason Cong, Muhuan Huang, Peng Zhang:
Combining computation and communication optimizations in system synthesis for streaming applications. 213-222 - Kevin E. Murray, Vaughn Betz:
Quantifying the cost and benefit of latency insensitive communication on FPGAs. 223-232 - Jasmina Vasiljevic, Paul Chow:
MPack: global memory optimization for stream applications in high-level synthesis. 233-236 - Aitzan Sari, Dimitris Agiakatsikas, Mihalis Psarakis:
A soft error vulnerability analysis framework for Xilinx FPGAs. 237-240
Poster session 1
- Monther Abusultan, Sunil P. Khatri:
FPGA LUT design for wide-band dynamic voltage and frequency scaled operation (abstract only). 241 - Christoforos Kachris, Georgios Ch. Sirakoulis, Dimitrios Soudris:
A configurable mapreduce accelerator for multi-core FPGAs (abstract only). 241 - Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Giovanni De Micheli:
A new basic logic structure for data-path computation (abstract only). 241 - Farnaz Gharibian, Lesley Shannon, Peter Jamieson:
A methodology for identifying and placing heterogeneous cluster groups based on placement proximity data (abstract only). 242 - Ka-Chun Lam, Wai-Chung Tang, Evangeline F. Y. Young:
A scalable routability-driven analytical placer with global router integration for FPGAs (abstract only). 242 - Karim M. Abdellatif, Roselyne Chotin-Avot, Zied Marrakchi, Habib Mehrez, Qingshan Tang:
Towards high performance GHASH for pipelined AES-GCM using FPGAs (abstract only). 242 - Hao Liang, Yi-Chung Chen, Wei Zhang, Hai Li:
Hierarchical library-based power estimator for versatile FPGAs (abstract only). 243
Poster session 2
- Peng Li, Louis-Noël Pouchet, Deming Chen, Jason Cong:
Transformations for throughput optimization in high-level synthesis (abstract only). 245 - Qian Zhang, Chenfei Ma, Qiang Xu:
On hybrid memory allocation for FPGA behavioral synthesis (abstract only). 245 - Rui Policarpo Duarte, Christos-Savvas Bouganis:
Pushing the performance boundary of linear projection designs through device specific optimisations (abstract only). 245 - Chunming Zhang, Wen Tang, Guangming Tan:
Accelerating massive short reads mapping for next generation sequencing (abstract only). 246 - Viktor Pus, Pavel Benácek:
Application specific processor with high level synthesized instructions (abstract only). 246 - Yu Bai, Mohammed Alawad, Mingjie Lin:
Optimally mitigating BTI-induced FPGA device aging with discriminative voltage scaling (abstract only). 246 - Devu Manikantan Shila, Vivek Venugopal:
Design, implementation and security analysis of hardware trojan threats in FPGA (abstract only). 247 - Yuhui Bai, Syed Zahid Ahmed, Bertrand Granado:
A power-efficient adaptive heapsort for fpga-based image coding application (abstract only). 247 - Chao Wang, Xi Li, Xuehai Zhou, Yunji Chen, Ray C. C. Cheung:
Big data genome sequencing on Zynq based clusters (abstract only). 247 - Fubing Mao, Yi-Chung Chen, Wei Zhang, Hai Li:
BMP: a fast B*-tree based modular placer for FPGAs (abstract only). 248 - Venkatasubramanian Viswanathan, Rabie Ben Atitallah, Jean-Luc Dekeyser, Benjamin Nakache, Maurice Nakache:
Redefining the role of FPGAs in the next generation avionic systems (abstract only). 248 - Chao Wang, Xi Li, Xuehai Zhou, Yunji Chen, Koen Bertels:
Co-processing with dynamic reconfiguration on heterogeneous MPSoC: practices and design tradeoffs (abstract only). 248 - Yu Wang, Donghoon Yeo, Muhammad Sohail, Hyunchul Shin:
Control signal aware slice-level window based legalization method for FPGA placement (abstract only). 249
Poster session 3
- Qingshan Tang, Matthieu Tuna, Habib Mehrez:
Future inter-FPGA communication architecture for multi-FPGA based prototyping (abstract only). 251 - Yosi Ben-Asher, Jacob Gendel, Gadi Haber, Oren Segal, Yousef Shajrawi:
1K manycore FPGA shared memory architecture for SOC (abstract only). 251 - Ahmad Alzahrani, Ronald F. DeMara:
Non-adaptive sparse recovery and fault evasion using disjunct design configurations (abstract only). 251 - Lei Li, Jian Wang, Jinmei Lai:
Novel FPGA clock network with low latency and skew (abstract only). 252 - Roshan Silwal, Mohammed Y. Niamat:
Asynchronous physical unclonable function using FPGA-based self-timed ring oscillator (abstract only). 252 - Tassadaq Hussain, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero, Santhosh Kumar Rethinagiri:
APMC: advanced pattern based memory controller (abstract only). 252 - Sen Ma, David Andrews:
On energy efficiency and amdahl's law in FPGA based chip heterogeneous multiprocessor systems (abstract only). 253 - Tao Ai, Mir Adnan Ali, J. Gregory Steffan, Kalin Ovtcharov, Sarmad Zulfiqar, Steve Mann:
Producing high-quality real-time HDR video system with FPGA (abstract only). 253 - James Lamberti, Devu Manikantan Shila, Vivek Venugopal:
xDEFENSE: an extended DEFENSE for mitigating next generation intrusions (abstract only). 253 - Fan Zhang, Lei Chen, Wenyao Xu, Yuanfu Zhao, Zhiping Wen:
Coordinating routing resources for hex pips test in island-style FPGAs (abstract only). 254 - Lin Meng, Keisuke Matsuyama, Naoto Nojiri, Tomonori Izumi, Katsuhiro Yamazaki:
Pipelining FPPGA-based defect detction in FPDs (abstract only). 254
Poster session 4
- Jian Gong, Jiahua Chen, Haoyang Wu, Fan Ye, Songwu Lu, Jason Cong, Tao Wang:
EPEE: an efficient PCIe communication library with easy-host-integration property for FPGA accelerators (abstract only). 255 - Zhibin Wang, Wenmin Yang, Jin Yu, Zhilei Chai:
Implementing FPGA-based energy-efficient dense optical flow computation with high portability in C (abstract only). 255 - Nick Ni:
Methodology to generate multi-dimensional systolic arrays for FPGAs using openCL (abstract only). 255 - Alessandro Antonio Nacci, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto:
Improving the security and the scalability of the AES algorithm (abstract only). 256 - Santhosh Kumar Rethinagiri, Oscar Palomar, Adrián Cristal, Osman S. Unsal:
Power estimation tool for system on programmable chip based platforms (abstract only). 256 - Viktor Pus, Lukas Kekely, Tomás Závodník:
Using DSP blocks to compute CRC hash in FPGA (abstract only). 256 - Bernhard Schmidt, Daniel Ziener, Jürgen Teich:
An automatic netlist and floorplanning approach to improve the MTTR of scrubbing techniques (abstract only). 257 - Matthias Hinkfoth, Ralf Joost, Ralf Salomon:
Exploring duty cycle distortions along signal paths in FPGAs (abstract only). 257
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