default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID13. ACM Great Lakes Symposium on VLSI 2003: Washington, DC, USA
- Mircea R. Stan, David Garrett, Kazuo Nakajima:
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003. ACM 2003, ISBN 1-58113-677-3
CAD
- Chris Coulston:
Constructing exact octagonal steiner minimal trees. 1-6 - Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas:
Bounding the efforts on congestion optimization for physical synthesis. 7-10 - Weidong Wang, Tat Kee Tan, Jiong Luo, Yunsi Fei, Li Shang, Keith S. Vallerio, Lin Zhong, Anand Raghunathan, Niraj K. Jha:
A comprehensive high-level synthesis system for control-flow intensive behaviors. 11-14
VLSI circuits
- Saied Hemati, Amir H. Banihashemi:
Iterative decoding in analog CMOS. 15-20 - Payam Heydari:
Design issues in low-voltage high-speed current-mode logic buffers. 21-26 - Magdy A. El-Moursy, Eby G. Friedman:
Optimum wire sizing of RLC interconnect with repeaters. 27-32 - Roy Mader, Ivan S. Kourtev:
Reduced dynamic swing domino logic. 33-36 - Chao You, Jong-Ru Guo, Russell P. Kraft, Kuan Zhou, Michael Chu, John F. McDonald:
A 5-20 GHz, low power FPGA implemented by SiGe HBT BiCMOS technology. 37-40 - Manuel Salim Maza, Mónico Linares Aranda:
Interconnected rings and oscillators as gigahertz clock distribution nets. 41-44
VLSI in the nanometer era
- Paul-Peter Sotiriadis
:
Information storage capacity of crossbar switching networks. 45-49 - Paul Beckett:
Exploiting multiple functionality for nano-scale reconfigurable systems. 50-55 - Jincheol Yoo, Kyusun Choi, Jahan Ghaznavi:
CMOS flash analog-to-digital converter for high speed and low voltage applications. 56-59 - Nadine Gergel, Shana Craft, John C. Lach:
Modeling QCA for area minimization in logic synthesis. 60-63
Poster session 1
- Jia Di, Jiann-Shiun Yuan:
Power-aware pipelined multiplier design based on 2-dimensional pipeline gating. 64-67 - Menahem Lowy, Neal Butler, Rosanne Tinkler:
Low power VLSI sequential circuit architecture using critical race control. 68-71 - Aiyappan Natarajan, David Jasinski, Wayne P. Burleson, Russell Tessier:
A hybrid adiabatic content addressable memory for ultra low-power applications. 72-75 - Timm Ostermann, Bernd Deutschmann:
TEM-cell and surface scan to identify the electromagnetic emission of integrated circuits. 76-79 - Rolf Drechsler, Junhao Shi, Görschwin Fey:
MuTaTe: an efficient design for testability technique for multiplexor based circuits. 80-83 - Vamsee K. Pamula, Krishnendu Chakrabarty:
Cooling of integrated circuits using droplet-based microfluidics. 84-87 - Fang Wang, Sofiène Tahar:
Language emptiness checking using MDGs. 88-91 - Gianluca Palermo, Cristina Silvano, S. Valsecchi, Vittorio Zaccaria:
A system-level methodology for fast multi-objective design space exploration. 92-95 - Arindam Mukherjee, Krishna Reddy Dusety, Rajsaktish Sankaranarayan:
A practical CAD technique for reducing power/ground noise in DSM circuits. 96-99 - Chandrasekar Rajagopal, Karthik Sridhar, Adrian Nunez:
RF CMOS circuit optimizing procedure and synthesis tool. 100-103 - Charles C. Chiang, Qing Su, Ching-Shoei Chiang:
Wirelength reduction by using diagonal wire. 104-107 - Xiaoning Qi, Goetz Leonhardt, Daniel Flees, Xiaodong Yang, Sangwoo Kim, Stephan Mueller, Hendrik T. Mau, Lawrence T. Pileggi:
A fast simulation approach for inductive effects of VLSI interconnects. 108-111 - Chang Woo Kang, Soroush Abbaspour, Massoud Pedram:
Buffer sizing for minimum energy-delay product by using an approximating polynomial. 112-115 - Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah:
FORCE: a fast and easy-to-implement variable-ordering heuristic. 116-119 - Atsushi Sakai, Takashi Yamada, Yoshifumi Matsushita, Hiroto Yasuura:
Routing methodology for minimizing 1nterconnect energy dissipation. 120-123 - Jiwei Chen, Bingxue Shi:
Circuit design of a wide tuning range CMOS VCO with automatic amplitude control. 124-127 - Li Yang, J. S. Yuan:
A decoupling technique for CMOS strong-coupled structures. 128-131 - Ilias Tagkopoulos, Charles A. Zukowski, German Cavelier, Dimitris Anastassiou:
A custom FPGA for the simulation of gene regulatory networks. 132-135
VLSI design
- Luca Benini, Alberto Macii, Enrico Macii, Elvira Omerbegovic, Massimo Poncino, Fabrizio Pro:
A novel architecture for power maskable arithmetic units. 136-140 - John Mayega, Okan Erdogan, Paul M. Belemjian, Kuan Zhou, John F. McDonald, Russell P. Kraft:
3D direct vertical interconnect microprocessors test vehicle. 141-146 - Adarsh K. Jain, Lin Yuan, Pushkin R. Pari, Gang Qu:
Zero overhead watermarking technique for FPGA designs. 147-152 - Geoff Knagge, David Garrett, Sivarama Venkatesan, Chris Nicol:
Matrix datapath architecture for an iterative 4x4 MIMO noise whitening algorithm. 153-156 - Rajkiran Gottumukkal, Vijayan K. Asari:
System level design of real time face recognition architecture based on composite PCA. 157-160 - Jianhua Gan, Shouli Yan, Jacob A. Abraham:
Design and modeling of a 16-bit 1.5MSPS successive approximation ADC with non-binary capacitor array. 161-164
VLSI circuits
- Magdy A. El-Moursy, Eby G. Friedman:
Shielding effect of on-chip interconnect inductance. 165-170 - Bhushan A. Shinkre, James E. Stine:
A pipelined clock-delayed domino carry-lookahead adder. 171-175 - Atanu Chattopadhyay, Zeljko Zilic:
A globally asynchronous locally dynamic system for ASICs and SoCs. 176-181 - Michael I. Fuller, James P. Mabry, John A. Hossack, Travis N. Blalock:
40 MHz 0.25 um CMOS embedded 1T bit-line decoupled DRAM FIFO for mixed-signal applications. 182-185
CAD
- Shyam Ramji, Nagu R. Dhanwada:
Design topology aware physical metrics for placement analysis. 186-191 - Bharat Krishna, C. Y. Roger Chen, Naresh Sehgal:
A novel ultra-fast heuristic for VLSI CAD steiner trees. 192-197 - Enrico Macii, Massimo Poncino, Sabino Salerno:
Combining wire swapping and spacing for low-power deep-submicron buses. 198-202 - Eric S. H. Wong, Evangeline F. Y. Young, Wai-Kei Mak:
Clustering based acyclic multi-way partitioning. 203-206 - Hua Tang, Hui Zhang, Alex Doboli:
Synthesis of continuous-time filters and analog to digital converters by integrated constraint transformation, floorplanning and routing. 207-210 - Ameya R. Agnihotri, Patrick H. Madden:
Congestion reduction in traditional and new routing architectures. 211-214
Low power
- Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi:
Simultaneous peak and average power minimization during datapath scheduling for DSP processors. 215-220 - Noureddine Chabini, Ismaïl Chabini, El Mostapha Aboulhamid, Yvon Savaria:
Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs. 221-224 - Gianluca Palermo, Mariagiovanna Sami, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon:
Branch prediction techniques for low-power VLIW processors. 225-228
Poster session 2
- Boris D. Andreev, Edward L. Titlebaum, Eby G. Friedman:
Orthogonal code generator for 3G wireless transceivers. 229-232 - Ki-seon Cho, Jong-on Park, Jin-seok Hong, Goang-Seog Choi:
54x54-bit radix-4 multiplier based on modified booth algorithm. 233-236 - Adnan Abdul-Aziz Gutub, Mohammad K. Ibrahim:
Power-time flexible architecture for GF(2k) elliptic curve cryptosystem computation. 237-240 - Yeshwant Kolla, Yong-Bin Kim, John Carter:
A novel 32-bit scalable multiplier architecture. 241-244 - Yanni Chen, Keshab K. Parhi:
High throughput overlapped message passing for low density parity check codes. 245-248 - Edward Merlo, Kwang-Hyun Baek, Myung-Jun Choe:
Exponential split accumulator for high-speed reduced area low-power direct digital frequency synthesizers. 249-252 - Jung-Lin Yang, Erik Brunvand:
Using dynamic domino circuits in self-timed systems. 253-256 - Frank Grassert, Dirk Timmermann:
Dynamic single-rail self-timed logic structures for power efficient synchronous pipelined designs. 257-260 - David Money Harris, Genevieve Breed, Matt Erler, David Diaz:
Comparison of noise tolerant precharge (NTP) to conventional feedback keepers for dynamic logic. 261-264 - Ahmed Emira, Edgar Sánchez-Sinencio:
Variable gain amplifier with offset cancellation. 265-268 - Atul Maheshwari, Wayne P. Burleson:
Repeater and current-sensing hybrid circuits for on-chip interconnects. 269-272 - Ram Suryanarayan, Anubhav Gupta, Travis N. Blalock:
A slew rate enhancement technique for operational amplifiers based on a tunable active Gm-based capacitance multiplication circuit. 273-276 - Yun Cheol Han, Kwang Il Kim, Jun Kim, Kwang Sub Yoon:
A dual band CMOS VCO with a balanced duty cycle buffer. 277-280 - Jiwei Chen, Bingxue Shi:
New approach to CMOS current reference with very low temperature coefficient. 281-284 - Mohamed A. Elgamel, Sumeer Goel, Magdy A. Bayoumi:
Noise tolerant low voltage XOR-XNOR for fast arithmetic. 285-288
Testing
- Indradeep Ghosh, Srivaths Ravi:
On automatic generation of RTL validation test benches using circuit testing techniques. 289-294 - Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos:
A highly regular multi-phase reseeding technique for scan-based BIST. 295-298 - Zhen Guo:
Coefficient-based parametric faults detection in analog circuits. 299-302 - Alessandro Fin, Franco Fummi, Graziano Pravadelli:
Mixing ATPG and property checking for testing HW/SW interfaces. 303-306
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-02-25 23:35 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
