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ORCID5th VLSI Design 1992: Bangalore, India
- Proceedings of the Fifth International Conference on VLSI Design, VLSI Design 1992, Bangalore, India, January 4-7, 1992. IEEE Computer Society 1992, ISBN 0-8186-2465-5
1. Advanced Test Methods
- Prathima Agrawal, Vishwani D. Agrawal, Sharad C. Seth:
A New Method for Generating Tests for Delay Faults in Non-Scan Circuits. 4-11 - Marie-Lise Flottes, Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
A New Reliable Method for Delay-Fault Diagnosis. 12-16 - James Jacob, Vishwani D. Agrawal:
Functional Test Generation for Sequential Circuits. 17-24
2. Physical Design
- Kyunrak Chong, Sartaj Sahni:
Minimizing Total Wire Length By Flipping Modules. 25-30 - Ching-Ting Wu, Andrew Lim
, David H. C. Du:
An Effective Timing-Driven Placement Algorithm For Macro Cells. 31-36 - Jai-Shen Huang, Yeh-Hao Chin:
The k-layer Topological Via Minimization Problem on a Circular Channel. 37-42
3. New Modeling and Test Techniques
- Kent L. Einspahr, Sharad C. Seth:
A Switch-Level Test Generation System. 43-48 - Sreejit Chakravarty:
On Computing Tests for Bridging and Leakage Faults: Complexity Results and Universal Test Sets. 49-54 - Sankaran M. Menon, Anura P. Jayasumana, Yashwant K. Malaiya:
On Bridging Faults in ECL Circuits. 55-60
4. Design and Fabrication
- Y. B. Dhong, Chi Ping Tsang:
Single Phase Dynamic CMOS POS PLA. 61-67 - Soumitra De Sirkar, Raghuram S. Tupuri, C. Sudha Madhuri, G. Rajagopalan, Kalpesh D. Mehta, C. G. Madhukar, Giridhar Bajpe:
Design Migration Across Technology - Making It Work. 68-72 - Rita Cucchiara, Giovanni Neri, G. Rustichelli, Tullio Salmon Cinotti:
Analysis of Design Methodology with Logic Cell Arrays. 73-79
5. Logic and High-Level Synthesis
- Marek A. Perkowski, William Zhao, Douglas V. Hall:
Concurrent Two-Dimensional State Minimization and State Assignment of finite State Machines. 80-84 - Chittaranjan A. Mandal, Partha Pratim Chakrabarti, Sujoy Ghose:
Interconnect Optimization Techniques in Data Path Synthesis. 85-90 - Ahmed Amine Jerraya, Kevin O'Brien, Inhag Park, Bernard Courtois:
Towards System level modeling and synthesis. 91-96 - Donald A. Lobo, Barry M. Pangrle:
Optimization Techniques for Pipelined Scheduling. 97-102 - Sanjiv Narayan, Frank Vahid, Daniel D. Gajski:
System Level Specification and Synthesis. 103-108
6. VLSI Tools and Technology
- C. P. Ravikumar:
Solving Physical Design Problems on a Vector Machine. 109-116 - N. S. Nagaraj:
OPSYN - OASYS Based Pseudosynthesis Tool. 117-123 - Mohan Kumar, Sharada Satrasala, Richard Goldman:
Mirroring Silicon Behaviour in ASIC models- The Issues Involved. 124-127 - Harsh, B. K. Sehgal, V. R. Balakrishnan, S. Mohan, A. A. Naik, P. Agarwal, R. Gulati, R. K. Purohit, Ishwar Chandra:
Design And Fabrication Of GaAs 2-input Nor Gate. 128-132 - Dipanwita Roy Chowdhury, Saugata Basu, Idranil Sen Gupta, Parimal Pal Chaudhuri:
A Novel Scheme for Designing Error Correcting Codes Using Cellular Automata. 133-136
7. Testing
- Ajay Khoche, Sunil D. Sherlekar, G. Venkatesh:
A Behavioral Fault Simulator For Ideal. 137-143 - Rochit Rajsuman:
An Architecture To Test Random Access Memories. 144-147 - Irith Pomeranz, Sudhakar M. Reddy:
3-Weight Pseudo-Random Test Generation Based on a Deterministic Test Set. 148-153 - Oommen Tharakan, James Jacob, Mandyam-Komar Srinivas:
An Efficient Rule Based Fault Simulator. 154-156
8. VLSI Architectures
- Dipanwita Roy Chowdhury, Idranil Sen Gupta, Parimal Pal Chaudhuri:
A Low-Cost High-Capacity Associative Memory Design Using Cellular Automata. 157-160 - Kanad Ghose, Arun Gupta:
Scalable, Pipelined, Cmos VLSI Content Addressable Memory Chips - Architecture And Implementation. 161-166 - Anindya Sundar Dhar:
An Array Architecture for Computing KLT Basis Vectors. 167-170 - Kalpesh D. Mehta, V. R. Sudershan:
Design and Implementation of High Speed RNS Input-Output Converters. 171-174
9. Control and Datapath Synthesis
- Biswadip Mitra, Preeti Ranjan Panda, Parimal Pal Chaudhuri:
Estimating the Complexity of Synthesized Designs from FSM Specifications. 175-180 - Manu Lauria, Shashi Kumar, Anshul Kumar:
A Partitioning Scheme For Multiple Pla Based Control Part Synthesis In Ideas. 181-186 - Biswadip Mitra, Parimal Pal Chaudhuri:
Combined Synthesis of Easily Testable Datapath and Control Designs. 187-192 - Susanta Misra, Biswadip Mitra, S. Sengupta, Parimal Pal Chaudhuri:
Synthesis of Self-Testable Sequential Logic Using Programmable Cellular Automata. 193-198 - Biswadip Mitra, Parimal Pal Chaudhuri:
An Efficient State Assignment Technique using Least Commitment and Constraint Propagation Techniques. 199-202
10. Signal Processing Applications
- Anantha P. Chandrakasan, Samuel Sheng, Robert W. Brodersen:
Low Power Techniques for Portable Real-time DSP Applications. 203-208 - N. Ranganathan, Rajiv Mehrotra, S. Kurji:
A CMOS VLSI Chip for Motion Detection. 209-214 - N. Ranganathan, Minesh I. Patel, Patrick McCabe:
A Two-dimensional Systolic Array Processor for Image Processing. 215-220 - Mohan Vishwanath, Robert Michael Owens, Mary Jane Irwin:
ECube: An Efficient Architecture for Analyzing Time-Varying Spectra. 221-226
11. Design for Testability
- Dong Xiang, Daozheng Wei, Shisong Chen:
A Global Test Point Placement Algorithm of Combinational Circuits. 227-232 - Nageswara S. V. Rao, Shunichi Toida:
Computational Complexity of Test-Point Insertions and Decompositions. 233-238 - M. Jamoussi, B. Kaminaka, D. Mukhedkar:
A New Variable Testability Measure: a Concept for Data-Flow Testability Evaluation. 239-244 - Chin-Foo See, Kewal K. Saluja:
An Efficient Method for Computation of Signatures. 245-250
12. Layout
- Rajib Mall, Lalit M. Patnaik:
A Force Directed Hill-Climbing Placement Algorithm. 251-254 - Subba Rao V. Kalari, M. M. Hasan:
An Algorithm for M Shortest Routes for a Net. 255-258 - Rajat Kumar Pal, Ajit Pal:
An Efficient Graph-Theoretic Algorithm for Three-Layer Channel Routing. 259-262 - B. Naveen, A. Savargaonkar, K. S. Raghunathan:
N2S: An Automatic Netlist to Schematic generator. 263-267 - K. R. Rao, K. S. Raghunathan:
Constrained Via Minimisation In Greedy Channel Routing. 268-272 - Pei-Yung Hsiao, Chiao-Yi Lin, Chia-Chun Tsai:
Minimum Partition for the Space Region of VLSI Layout. 273-276
13. Verification
- Ram Singh Rana, A. B. Bhattacharyya:
CPM Pole-Zero Computation Using The Generalized Eigenproblem Approach. 277-280 - Shen Lin, Ernest S. Kuh, Malgorzata Marek-Sadowska:
A New Accurate and Efficient Timing Simulator. 281-286 - Chandu Visweswariah:
Stepsize Control in Piecewise Approximate Circuit Simulation. 287-292
14. Industrial Applications
- Chandra Shekhar, A. S. Mandal:
Design of an Efficient ASIC for the Control of Microwave Ovens. 293-296 - S. Nagaraj, N. Padmini, N. S. Nagaraj, R. Ramesh, V. Sachidanand:
WCS - A CAD Solution for Worst Case Performance Analysis of Integrated Circuits. 297-302 - Fabian Klass, Johannes M. Mulder:
Use of CMOS Technology in Wave Pipelining. 303-308 - Vason P. Srini:
Field Programmable Gate Array (FPGA) Implementation of Digital Systems: An Alternative to ASIC. 309-314 - Jaisimha Bannur:
A Designer's Perspective on VLSI Tools and Methodology. 315-319
15. Synthesis and Design Posters
- Mahesh Mehendale:
A System for Behavior Extraction from FPGA Implementations of Synchronous Designs. 320-321 - Prashant P. Nedungadi, M. Balakrishnan, Anshul Kumar:
Data Path Synthesis With Global Time Constraint. 322-323 - Venkatesh Akella, Ganesh Gopalakrishnan:
From Process-Oriented Functional Specifications to Efficient Asynchronous Circuits. 324-325 - Jukka Lahti, Jorma Kivelä:
Logic Design and Synthesis with IEEE Logic Symbols in the DEMET System. 326-327 - K. V. S. H. Rao, A. Kansal, Chandra Shekhar, M. Srinivas, V. N. S. N. Rao:
An ASIC for High Performance Stepper Motor Control. 328-329 - Uma. H. L.:
EPLDs - a Milestone in the World of Logic Design. 330-331
16. Design Verification Posters
- Chinmay K. Maiti:
Optimization Of Cut-off Frequency Of High Speed Bipolar Transistors Fabricated In The N-well Of A C-mos Process At Low Temperature. 332-333 - K. V. S. H. Rao, Raj Singh, Chandra Shekhar:
Using Dedicated Functional Simulator for ASIC Design in Indian Context. 334-335 - R. Ghosh, S. Dasgupta:
A Simple Model for Lindhard Continuum Potential useful for Channeling Simulation. 336-338 - Abhijit Dharchoudhury, S. M. Kang:
Identification of Correlated Device Model Parameter Values for Worst-Case Circuit Performance Analysis. 339-340 - P. A. Subrahmanyam:
A Verification Guide for the Perplexed Designer: Matching Verification Techniques and Design Tasks. 341-342
17. Testing Posters
- Yunhuan Sheng, Shaoqing Li:
The "G-F" 2-Valued Formula Generating Complete Set of Tests to Multiple Faults. 343-349 - Lew Fock Chong Lew Yan Voon, Christian Dufaza, Christian Landrault:
Quasi-Linear FSMS and their Application to the Generation of Deterministic and Pseudo-random Test Vectors. 350-351 - Michel Renovell, M. Ildevert, Yves Bertrand:
A Low Overhead and High Coverage BIST Scheme for Dynamic CMOS PLAs. 352-353 - Anupam Basu, Thomas Charles Wilson, Dilip K. Banerji, Jayanti C. Majithia:
An Approach to Minimize Testability Overhead for BILBO based Built-In-Self-Test. 354-355
18. Design and Fabrication Posters
- S. S. Janaki, C. Sudha Madhuri, T. S. Raghuram, Soumitra De Sirkar:
An Efficient Method For Characterization Of ASIC Compilers. 356-357 - S. Uma Mahesh, Marty Long, Laura Simmons:
Quad Asynchronous Communication Element (ACE) with FIFO. 358-361 - Samiha Mourad:
Benchmarking Array Comparators. 362-363 - Khaled M. Elleithy:
Systolic Arithmetic Architectures. 364-365 - Mahesh Siddappa:
Design Considerations for a Flat Panel Controller. 366-367
19. Layout Posters
- Chunduri Rama Mohan, Partha Pratim Chakrabarti, Sujoy Ghose:
A New algorithm for combined PLA folding. 368-369 - Pei-Yung Hsiao, Lih-Der Jang:
Using a Balanced Quad List Quad Tree to Speed Up a Hierarchical VLSI Compaction Scheme. 370-371 - R. Shanker:
DEFLAN- A delay estimator for floorplanner. 372-373 - M. V. V. Satyanarayana:
Structured Construction of VLSI Circuits Using Adjacency Lists. 374-375
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