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ORCIDMicroprocessors and Microsystems, Volume 37
Volume 37, Number 1, February 2013
- François Duhem, Nicolas Marques, Fabrice Muller, Hassan Rabah
, Serge Weber, Philippe Lorenzini:
Dynamically reconfigurable entropy coder for multi-standard video adaptation using FaRM. 1-8 - Amir Muhammad, Michael J. Pont:
Improving flexibility and fault-management in CAN-based "Shared-Clock" architectures. 9-23 - Gyu Sang Choi, Byung-Won On, Kwonhue Choi, Sungwon Yi:
PTL: PRAM translation layer. 24-32 - T. Nandha Kumar, Haider A. F. Almurib, New Chin-Ee:
Fine grain faults diagnosis of FPGA interconnect. 33-40 - Qi Guo, Tianshi Chen, Yunji Chen, Ling Li, Weiwu Hu:
Microarchitectural design space exploration made fast. 41-51 - Slami Saadi, Abderrezak Guessoum, Maamar Bettayeb:
ABC optimized neural network model for image deblurring with its FPGA implementation. 52-64 - Ciprian Radu, Md. Shahriar Mahbub, Lucian Vintan:
Developing Domain-Knowledge Evolutionary Algorithms for Network-on-Chip Application Mapping. 65-78 - Boppana Lakshmi, A. S. Dhar:
VLSI architecture for parallel radix-4 CORDIC. 79-86 - Sébastien Le Beux, Ian O'Connor, Gabriela Nicolescu, Guy Bois, Pierre G. Paulin:
Reduction methods for adapting optical network on chip topologies to 3D architectures. 87-98 - Jing Mei, Kenli Li, Jingtong Hu, Shu Yin, Edwin Hsing-Mean Sha:
Energy-aware preemptive scheduling algorithm for sporadic tasks on DVS platform. 99
Volume 37, Number 2, March 2013
- Hana Kubátová, Paris Kitsos:
Editorial of special issue: Digital System Safety and Security. 113-114 - Weiyun Lu, Martin Radetzki:
Concurrent and comparative fault simulation in SystemC and its application in robustness evaluation. 115-128 - Muhammad Aqeel Wahlah, Kees Goossens:
TeMNOT: A test methodology for the non-intrusive online testing of FPGA with hardwired network on chip. 129-146 - Alireza Rohani, Hans G. Kerkhoff:
Rapid transient fault insertion in large digital systems. 147-154 - Martin Straka, Jan Kastil, Zdenek Kotásek, Lukas Miculka:
Fault tolerant system design and SEU injection based testing. 155-173 - Carthik A. Sharma, Alireza Sarvi, Ahmad Alzahrani, Ronald F. DeMara:
Self-healing reconfigurable logic using autonomous group testing. 174-184 - Jiri Balcarek, Petr Fiser, Jan Schmidt:
Techniques for SAT-based constrained test pattern generation. 185-195 - Roland Dobai, Marcel Baláz:
SAT-based generation of compressed skewed-load tests for transition delay faults. 196-205 - Mehdi Dehbashi, André Sülflow, Görschwin Fey:
Automated design debugging in a testbench-based verification environment. 206-217 - Johannes Grinschgl, Armin Krieg, Christian Steger, Reinhold Weiss, Holger Bock, Josef Haid, Thomas Aichinger, Christiane Ulbricht:
Case study on multiple fault dependability and security evaluations. 218-227 - Junfeng Chu, Mohammed Benaissa:
Error detecting AES using polynomial residue number systems. 228-234 - Paris Kitsos, Nicolas Sklavos, George Provelengios, Athanassios N. Skodras:
FPGA-based performance analysis of stream ciphers ZUC, Snow3g, Grain V1, Mickey V2, Trivium and E0. 235-245 - Meeta Srivastav, Xu Guo, Sinan Huang, Dinesh Ganta, Michael B. Henry, Leyla Nazhandali, Patrick Schaumont:
Design and benchmarking of an ASIC with five SHA-3 finalist candidates. 246-257
Volume 37, Number 3, May 2013
- Alok Prakash, Siew Kei Lam, Christopher T. Clarke, Thambipillai Srikanthan:
FPGA-aware techniques for rapid generation of profitable custom instructions. 259-269 - Gokhan Koray Gultekin, Afsar Saranli:
An FPGA based high performance optical flow hardware design for computer vision applications. 270-286 - Osama Daifallah Al-Khaleel, Zakaria Al-Qudah, Mohammad Al-Khaleel, Christos A. Papachristou:
High performance FPGA-based decimal-to-binary conversion schemes for decimal arithmetic. 287-298 - Zheng Ding, Qiang Wu, Yizhong Zhang, Linjie Zhu:
Deriving an NCD file from an FPGA bitstream: Methodology, architecture and evaluation. 299-312 - Farouk Smith:
A new methodology for single event transient suppression in flash FPGAs. 313-318 - José L. Núñez-Yáñez, Geza Lore:
Enabling accurate modeling of power and energy consumption in an ARM-based System-on-Chip. 319-332 - Basavaraj Talwar, Bharadwaj Amrutur:
Traffic engineered NoC for streaming applications. 333-344 - Ning Lu, In-Sung Choi, Shin-Dug Kim:
A flash-aware write buffer scheme to enhance the performance of superblock-based NAND flash storage systems. 345-357 - Maamar Touiza, Gilberto Ochoa-Ruiz, El-Bay Bourennane, Abderrezak Guessoum, Kamel Messaoudi:
A novel methodology for accelerating bitstream relocation in partially reconfigurable systems. 358-372 - Jin-Hong Park, Il-San Kim, Woo-Chan Park, Yong-Jin Park, Tack-Don Han:
A pixel pipeline architecture with selective z-test scheme for 3D graphics processors. 373-380
Volume 37, Numbers 4-5, June - July 2013
- Slobodan M. Simic, Aleksa J. Zejak, Zoran Golubicic:
Hardware implementation of DIRLS mismatched compressor applied to a pulse-Doppler radar system. 381-393 - K. C. Cinnati Loi, Seok-Bum Ko:
High performance scalable elliptic curve cryptosystem processor for Koblitz curves. 394-406 - Michele Fabiano, Marco Indaco, Stefano Di Carlo, Paolo Prinetto:
Design and optimization of adaptable BCH codecs for NAND flash memories. 407-419 - M. Maheswari, G. Seetharaman:
Multi bit random and burst error correction code with crosstalk avoidance for reliable on chip interconnection links. 420-429
- Peeter Ellervee, Jari Nurmi:
Guest Editorial. 430-431 - Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen:
Design and implementation of reconfigurable FIFOs for Voltage/Frequency Island-based Networks-on-Chip. 432-445 - Antti Alhonen, Erno Salminen, Lasse Lehtonen, Timo D. Hämäläinen:
A scalable, non-interfering, synthesizable Network-on-Chip monitor - Extended version. 446-459 - Bo Yang, Liang Guang, Tero Säntti, Juha Plosila:
Mapping multiple applications with unbounded and bounded number of cores on many-core networks-on-chip. 460-471 - Flavius Gruian, Martin Schoeberl:
Hardware support for CSP on a Java chip multiprocessor. 472-481 - Clément Foucher, Fabrice Muller, Alain Giulieri:
Online codesign on reconfigurable platform for parallel computing. 482-493 - S. M. Yasser Sherazi, Joachim Neves Rodrigues, Omer Can Akgun, Henrik Sjöland, Peter Nilsson:
Ultra low energy design exploration of digital decimation filters in 65 nm dual-VT CMOS in the sub-VT domain. 494-504 - Jaan Raik, Urmas Repinski, Anton Chepurov, Hanno Hantson, Raimund Ubar, Maksim Jenihhin:
Automated design error debug using high-level decision diagrams and mutation operators. 505-513
Volume 37, Numbers 6-7, August - October 2013
- Onur Derin, Emanuele Cannella, Giuseppe Tuveri, Paolo Meloni, Todor P. Stefanov, Leandro Fiorin, Luigi Raffo, Mariagiovanna Sami:
A system-level approach to adaptivity and fault-tolerance in NoC-based MPSoCs: The MADNESS project. 515-529 - Haytham Elmiligi, M. Watheq El-Kharashi, Fayez Gebali:
Power consumption of 3D networks-on-chips: Modeling and optimization. 530-543 - Nikolaos Zompakis, Alexandros Bartzas, Francky Catthoor, Dimitrios Soudris:
System scenarios-based architecture level exploration of SDR application using a network-on-chip simulation framework. 544-553 - In-Sung Choi, Sung-In Jang, Chang-Hoon Oh, Charles C. Weems, Shin-Dug Kim:
A dynamic adaptive converter and management for PRAM-based main memory. 554-561 - Hau T. Ngo, Robert W. Ives, Ryan N. Rakvic, Randy P. Broussard:
Real-time video surveillance on an embedded, programmable platform. 562-571 - Marcin Rogawski, Kris Gaj, Ekawat Homsirikamol:
A high-speed unified hardware architecture for 128 and 256-bit security levels of AES and the SHA-3 candidate Grøstl. 572-582 - K. Prescilla, A. Immanuel Selvakumar:
Modified Binary Particle Swarm optimization algorithm application to real-time task assignment in heterogeneous multiprocessor. 583-589 - Chao Jing, Yanmin Zhu, Minglu Li:
Energy-efficient scheduling on multi-FPGA reconfigurable systems. 590-600 - Xuexin Zheng, An Wang, Wei Wei:
First-order collision attack on protected NTRU cryptosystem. 601-609 - B. Bala Tripura Sundari, T. R. Padmanabhan:
A direct method for optimal VLSI realization of deeply nested n-D loop problems. 610-628 - Laavanya Sridhar, V. Lakshmi Prabha:
RFID based access control protection scheme for SRAM FPGA IP cores. 629-640 - Jan Schmidt, Petr Fiser, Jiri Balcarek:
The influence of implementation type on dependability parameters. 641-648 - M. Bhaskar, A. Jaswanth, B. Venkataramani:
Design of a novel differential on-chip wave-pipelined serial interconnect with surfing. 649-660
- Debora Matos, Caroline Concatto, Anelise Kologeski, Luigi Carro, Márcio Eduardo Kreutz, Fernanda Gusmão de Lima Kastensmidt, Altamiro Amadeu Susin:
A NOC closed-loop performance monitor and adapter. 661-671
- Nadia Nedjah, Lech Józwiak, Luiza de Macedo Mourelle:
Application-specific processors and system-on-chips for embedded and pervasive applications. 672-673 - Hrishikesh Sharma, Sachin Patkar:
A design methodology for optimally folded, pipelined architectures in VLSI applications using projective space lattices. 674-683 - Alexandre Solon Nery, Lech Józwiak, Menno Lindwer, Mauro Cocco, Nadia Nedjah, Felipe M. G. França:
Hardware reuse in modern application-specific processors and accelerators. 684-692 - Krzysztof Marcinek, Witold A. Pleskacz:
ELEON3LP - Superscalar and low-power enhancements of single issue general purpose processor model. 693-700 - Pierre-Henri Horrein, Christine Hennebert, Frédéric Pétrot:
An environment for (re)configuration and execution management of heterogeneous flexible radio platforms. 701-712 - Mehdi Kamal, Ali Afzali-Kusha, Saeed Safari, Massoud Pedram:
Considering the effect of process variations during the ISA extension design flow. 713-724 - Yisong Chang, Jizeng Wei, Wei Guo, Jizhou Sun:
A high performance, area efficient TTA-like vertex shader architecture with optimized floating point arithmetic unit for embedded graphics applications. 725-738 - Alexandre Solon Nery, Nadia Nedjah, Felipe M. G. França, Lech Józwiak:
Parallel processing of intersections for ray-tracing in application-specific processors and GPGPUs. 739-749 - Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido, Miguel Morales-Sandoval:
FPGA-based implementation alternatives for the inner loop of the Secure Hash Algorithm SHA-256. 750-757
Volume 37, Number 8-A, November 2013
- Smaïl Niar, Cristina Silvano:
Special issue DSD 2012 on Reliability and dependability in MPSoC Technologies. 759 - Ahmed M. Eltawil, Michael Engel, Bibiche M. Geuskens, Amin Khajeh Djahromi, Fadi J. Kurdahi, Peter Marwedel, Smaïl Niar, Mazen A. R. Saghir:
A survey of cross-layer power-reliability tradeoffs in multi and many core systems-on-chip. 760-771
- Varadan Savulimedu Veeravalli, Thomas Polzer, Ulrich Schmid, Andreas Steininger, Michael Hofbauer, Kurt Schweiger, Horst Dietrich, Kerstin Schneider-Hornstein, Horst Zimmermann, Kay-Obbe Voss, Bruno Merk, Michael Hajek:
An infrastructure for accurate characterization of single-event transients in digital circuits. 772-791 - Halil Kükner, Pieter Weckx, Praveen Raghavan, Ben Kaczer, Francky Catthoor, Liesbet Van der Perre, Rudy Lauwereins, Guido Groeseneken:
Impact of duty factor, stress stimuli, gate and drive strength on gate delay degradation with an atomistic trap-based BTI model. 792-800 - Omid Assare, Mahmoud Momtazpour, Maziar Goudarzi:
Leak-Gauge: A late-mode variability-aware leakage power estimation framework. 801-810
- Syed M. A. H. Jafri, Liang Guang, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen:
Energy-aware fault-tolerant network-on-chips for addressing multiple traffic classes. 811-822 - Felix Miller, Thomas Wild, Andreas Herkersdorf:
Virtualized and fault-tolerant inter-layer-links for 3D-ICs. 823-835 - Anna Bernasconi, Valentina Ciriani, Gabriella Trucco, Tiziano Villa:
SOP restructuring by exploiting don't cares. 836-847
- Selma Saidi, Pranav Tendulkar, Thierry Lepley, Oded Maler:
Optimizing two-dimensional DMA transfers for scratchpad Based MPSoCs platforms. 848-857 - Da He, Wolfgang Mueller:
A heuristic energy-aware approach for hard real-time systems on multi-core platforms. 858-870 - Chiraz Trabelsi, Samy Meftali, Jean-Luc Dekeyser:
Decentralized control for dynamically reconfigurable FPGA systems. 871-884
Volume 37, Number 8-B, November 2013
- J. Morris Chang, Marco D. Santambrogio, Pao-Ann Hsiung:
Embedded multicore systems: Architecture, performance and application. 885-886 - Yi-Gang Tai, Chia-Tien Dan Lo, Kleanthis Psarris:
Scalable matrix decompositions with multiple cores on FPGAs. 887-898 - Wen-Chung Tsai, Kuo-Chih Chu, Yu Hen Hu, Sao-Jie Chen:
Non-minimal, turn-model based NoC routing. 899-914 - Libo Huang, Zhiying Wang, Nong Xiao:
VBON: Toward efficient on-chip networks via hierarchical virtual bus. 915-928 - Jih-Ching Chiu, Kai-Ming Yang, Yu-Liang Chou:
A hyperscalar dual-core architecture for embedded systems. 929-940 - Kai Feng, Yaoyao Ye, Jiang Xu:
A formal study on topology and floorplan characteristics of mesh and torus-based optical networks-on-chip. 941-952 - Mahmoud Momtazpour, Maziar Goudarzi, Esmaeil Sanaei:
Static statistical MPSoC power optimization by variation-aware task and communication scheduling. 953-963
Volume 37, Number 8-C, November 2013
- Francesco Leporati, Lech Józwiak:
Preface. 965 - Kim Grüttner, Philipp A. Hartmann, Kai Hylla, Sven Rosinger, Wolfgang Nebel, Fernando Herrera, Eugenio Villar, Carlo Brandolese, William Fornaciari, Gianluca Palermo, Chantal Ykman-Couvreur, Davide Quaglia, Francisco Ferrero, Raúl Valencia:
The COMPLEX reference framework for HW/SW co-design and power management supporting platform-based design-space exploration. 966-980 - Ioannis Sourdis, Christos Strydis, Antonino Armato, Christos-Savvas Bouganis, Babak Falsafi, Georgi Nedeltchev Gaydadjiev, Sebastián Isaza, Alirad Malek, R. Mariani, Dionisios N. Pnevmatikatos, Dhiraj K. Pradhan, Gerard K. Rauwerda, Robert M. Seepers, Rishad A. Shafik, Kim Sunesen, Dimitris Theodoropoulos, Stavros Tzilis, Michalis Vavouras:
DeSyRe: On-demand system reliability. 981-1001 - Lech Józwiak, Menno Lindwer, Rosilde Corvino, Paolo Meloni, Laura Micconi, Jan Madsen, Erkan Diken, Deepak Gangadharan, Roel Jordans, Sebastiano Pomata, Paul Pop, Giuseppe Tuveri, Luigi Raffo, Giuseppe Notarangelo:
ASAM: Automatic architecture synthesis and application mapping. 1002-1019 - Christian El Salloum, Martin Elshuber, Oliver Höftberger, Haris Isakovic, Armin Wasicek:
The ACROSS MPSoC - A new generation of multi-core processors designed for safety-critical embedded systems. 1020-1032 - Timo Stripf, Oliver Oey, Thomas Bruckschlögl, Jürgen Becker, Gerard K. Rauwerda, Kim Sunesen, George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Steven Derrien, Olivier Sentieys, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Dimitrios Kritharidis, Nikolaos Mitas, Thomas Perschke:
Compiling Scilab to high performance embedded multicore systems. 1033-1049 - Luciano Lavagno, Mihai T. Lazarescu, Ioannis Papaefstathiou, Andreas Brokalakis, Johan Walters, Bart Kienhuis, Florian Schäfer:
HEAP: A Highly Efficient Adaptive multi-Processor framework. 1050-1062 - Gian Mario Bertolotti, Andrea Cristiani, Nikola B. Serbedzija:
The REFLECT project and the implementation of a seat adaptation system in an automotive environment. 1063-1072 - João M. P. Cardoso, Tiago Carvalho, José Gabriel F. Coutinho, Ricardo Nobre, Razvan Nane, Pedro C. Diniz, Zlatko Petrov, Wayne Luk, Koen Bertels:
Controlling a complete hardware synthesis toolchain with LARA aspects. 1073-1089 - Raphael Poss, Mike Lankamp, Qiang Yang, Jian Fu, Michiel W. van Tol, Muhammad Irfan Uddin, Chris R. Jesshope:
Apple-CORE: Harnessing general-purpose many-cores with hardware concurrency management. 1090-1101
Volume 37, Number 8-D, November 2013
- Juan Antonio Maestro, Pedro Reviriego, Sanghyeon Baeg, Shi-Jie Wen, Richard Wong:
Soft error tolerant Content Addressable Memories (CAMs) using error detection codes and duplication. 1103-1107 - Bijan Alizadeh, Payman Behnam:
Formal equivalence verification and debugging techniques with auto-correction mechanism for RTL designs. 1108-1121 - Vassilios A. Chouliaras, Konstantia Koutsomyti, Simon Parr, David J. Mulvaney, Mark Milward:
Architecture, performance modeling and VLSI implementation methodologies for ASIC vector processors: A case study in telephony workloads. 1122-1143 - Paolo Zicari:
Efficient and high performance FPGA-based rectification architecture for stereo vision. 1144-1154 - Lech Józwiak, Yahya Jan:
Design of massively parallel hardware multi-processors for highly-demanding embedded applications. 1155-1172 - Jie Tang, Chen Liu, Shaoshan Liu, Jean-Luc Gaudiot:
Practical models for energy-efficient prefetching in mobile embedded systems. 1173-1182 - Xianyang Jiang, Peng Xiao, Meikang Qiu, Gaofeng Wang:
Performance effects of pipeline architecture on an FPGA-based binary32 floating point multiplier. 1183-1191 - Faisal Hamady, Ayman I. Kayssi, Ali Chehab, Nitin Gupte:
Effects of workload variation on the energy distribution in a mobile platform. 1192-1199 - José Manuel Bande Serrano, José Hernández Palancar, René Cumplido:
Multi-character cost-effective and high throughput architecture for content scanning. 1200-1207 - Xiaofang Wang, Leeladhar Bandi:
X-Network: An area-efficient and high-performance on-chip wormhole interconnect network. 1208-1218
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