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2020 – today
- 2024
[c10]Duy-Hieu Bui, Duc-Manh Tran, Daniele D. Caviglia, Orazio Aiello:
Fully Synthesizable Dynamic Voltage Comparator across technology nodes and scaled supply voltages. ISCAS 2024: 1-5- 2023
- [j5]Sy-Nam Tran
, Van-Thuc Hoang, Duy-Hieu Bui:
A Hardware Architecture of NIST Lightweight Cryptography Applied in IPSec to Secure High-Throughput Low-Latency IoT Networks. IEEE Access 11: 89240-89248 (2023) - [c9]Hiep Manh Dao, Vincent Beroulle, Yann Kieffer, Xuan-Tu Tran, Duy-Hieu Bui:
Low-cost Low-Power Implementation of Binary Edwards Curve for Secure Passive RFID Tags. MCSoC 2023: 494-500 - 2022
- [c8]Ngo-Doanh Nguyen, Duy-Hieu Bui, Fawnizu Azmadi Hussin, Xuan-Tu Tran:
An Adaptive Hardware Architecture using Quantized HOG Features for Object Detection. ICICDT 2022: 113-116 - 2020
- [j4]Xuan-Tu Tran, Ngoc-Sinh Nguyen, Duy-Hieu Bui, Minh-Trien Pham, Hung K. Nguyen, Cong-Kha Pham:
Reducing Bitrate and Increasing the Quality of Inter Frame by Avoiding Quantization Errors in Stationary Blocks. EAI Endorsed Trans. Ind. Networks Intell. Syst. 7(22): e2 (2020) - [c7]Ngo-Doanh Nguyen, Duy-Hieu Bui, Xuan-Tu Tran:
A Lightweight AEAD encryption core to secure IoT applications. APCCAS 2020: 35-38
2010 – 2019
- 2019
- [c6]Ngo-Doanh Nguyen, Duy-Hieu Bui, Xuan-Tu Tran:
A Novel Hardware Architecture for Human Detection using HOG-SVM Co-Optimization. APCCAS 2019: 33-36 - [c5]Duy-Anh Nguyen, Duy-Hieu Bui, Francesca Iacopi, Xuan-Tu Tran:
An Efficient Event-driven Neuromorphic Architecture for Deep Spiking Neural Networks. SoCC 2019: 144-149 - 2017
- [j3]Xuan-Tu Tran, Tung Nguyen, Hai-Phong Phan, Duy-Hieu Bui:
AXI-NoC: High-Performance Adaptation Unit for ARM Processors in Network-on-Chip Architectures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(8): 1650-1660 (2017) - [j2]Marc Belleville, Anca Molnos, Gilles Sicard, Jean-Frédéric Christmann, Dominique Morche, Duy-Hieu Bui, Diego Puschini, Suzanne Lesecq, Edith Beigné:
Adaptive Architectures, Circuits and Technology Solutions for Future IoT Systems. J. Low Power Electron. 13(3): 298-309 (2017) - [j1]Duy-Hieu Bui, Diego Puschini, Simone Bacles-Min, Edith Beigné, Xuan-Tu Tran:
AES Datapath Optimization Strategies for Low-Power Low-Energy Multisecurity-Level Internet-of-Things Applications. IEEE Trans. Very Large Scale Integr. Syst. 25(12): 3281-3290 (2017) - 2016
- [c4]Duy-Hieu Bui, Diego Puschini, Simone Bacles-Min, Edith Beigné, Xuan-Tu Tran:
Ultra low-power and low-energy 32-bit datapath AES architecture for IoT applications. ICICDT 2016: 1-4 - 2014
- [c3]Ngoc-Sinh Nguyen, Duy-Hieu Bui, Xuan-Tu Tran:
Reducing temporal redundancy in MJPEG using Zipfian estimation techniques. APCCAS 2014: 65-68 - [c2]Ngoc-Mai Nguyen, Edith Beigné, Suzanne Lesecq, Duy-Hieu Bui, Nam-Khanh Dang, Xuan-Tu Tran:
H.264/AVC hardware encoders and low-power features. APCCAS 2014: 77-80 - 2013
- [c1]Tung Nguyen, Duy-Hieu Bui, Hai-Phong Phan, Trong-Trinh Dang, Xuan-Tu Tran:
High-performance adaption of ARM processors into Network-on-Chip architectures. SoCC 2013: 222-227
Coauthor Index
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