default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDBevan M. Baas
Person information
- affiliation: University of California, Davis, USA
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2023
[j29]Satyabrata Sarangi
, Bevan M. Baas:
Energy-efficient canonical Huffman decoders on many-core processor arrays and FPGAs. Integr. 88: 156-165 (2023)- [c46]Thomas Abbott, Bevan M. Baas:
A Scalable JPEG Encoder on a Many-Core Array. MCSoC 2023: 411-418 - [c45]Shifu Wu, Bevan M. Baas:
Many-Core Display Stream Compression Decoders With Simplified Pixel Prediction. MWSCAS 2023: 957-961 - 2022
- [c44]Peiyao Shi, Aaron Stillmaker, Bevan M. Baas:
Efficient and High-Performance Sparse Matrix-Vector Multiplication on a Many-Core Array. MCSoC 2022: 187-194 - [c43]Brent Bohnenstiehl, Aaron Stillmaker, Timothy Andreas, Bevan M. Baas:
A Low-Overhead Method for the Accurate Estimation of the Maximum Operating Clock Frequency. VLSI-SoC 2022: 1-5 - [c42]Renjie Chen, Aaron Stillmaker, Bevan M. Baas:
Architecture and 28 nm CMOS Design of a 1886 MBin/sec Context-Adaptive Binary Arithmetic Coder (CABAC) Encoder. VLSI-SoC 2022: 1-6 - 2021
- [j28]Shifu Wu, Bevan M. Baas:
Display Stream Compression Decoders for Fine-Grained Many-Core Processor Arrays. IEEE Trans. Circuits Syst. II Express Briefs 68(5): 1730-1734 (2021) - [c41]Satyabrata Sarangi, Bevan M. Baas:
Canonical Huffman Decoder on Fine-grain Many-core Processor Arrays. ASP-DAC 2021: 512-517 - [c40]Shifu Wu, K. De Silva, Snehlata Gutgutia, Bevan M. Baas, Massimo Alioto:
A 1448-Mpixel/s, 84-pJ/Pixel Display Stream Compression Encoder in 28 nm for 4K Video Resolution. A-SSCC 2021: 1-3 - [c39]Satyabrata Sarangi, Bevan M. Baas:
DeepScaleTool: A Tool for the Accurate Estimation of Technology Scaling in the Deep-Submicron Era. ISCAS 2021: 1-5 - [i1]Satyabrata Sarangi, Bevan M. Baas:
DeepScaleTool : A Tool for the Accurate Estimation of Technology Scaling in the Deep-Submicron Era. CoRR abs/2102.10195 (2021) - 2020
- [j27]Aaron Stillmaker, Brent Bohnenstiehl, Lucas Stillmaker, Bevan M. Baas:
Scalable energy-efficient parallel sorting on a fine-grained many-core processor array. J. Parallel Distributed Comput. 138: 32-47 (2020) - [j26]Tokunbo Ogunfunmi, John McAllister, Bevan M. Baas, Mrityunjoy Chakraborty:
Guest Editorial: JSPS Special Issue on 2018 IEEE Signal Processing Systems (SiPS) Workshop. J. Signal Process. Syst. 92(10): 1039-1041 (2020) - [j25]Tokunbo Ogunfunmi, John McAllister, Bevan M. Baas, Mrityunjoy Chakraborty:
Correction to: Guest Editorial: JSPS Special Issue on 2018 IEEE Signal Processing Systems (SiPS) Workshop. J. Signal Process. Syst. 92(10): 1043 (2020) - [c38]Shifu Wu, Bevan M. Baas:
Indexed Color History Many-Core Engines for Display Stream Compression Decoders. ICECS 2020: 1-4
2010 – 2019
- 2019
- [j24]Aaron Stillmaker, Bevan M. Baas:
Corrigendum to "Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7 nm" [Integr. VLSI J. 58. (2017) 74-81]. Integr. 67: 170 (2019) - 2018
- [c37]Shifu Wu, Snehlata Gutgutia, Massimo Alioto, Bevan M. Baas:
Display Stream Compression Encoder Architectures for Real-time 4K and 8K Video Encoding. ACSSC 2018: 251-255 - [c36]Shifu Wu, Bevan M. Baas:
A Low-Cost Slice Interleaving DSC Decoder Architecture for Real-Time 8K Video Decoding. MWSCAS 2018: 364-367 - 2017
- [j23]Aaron Stillmaker, Bevan M. Baas:
Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7 nm. Integr. 58: 74-81 (2017) - [j22]Brent Bohnenstiehl, Aaron Stillmaker, Jon J. Pimentel, Timothy Andreas, Bin Liu, Anh Tran, Emmanuel Adeagbo, Bevan M. Baas:
KiloCore: A 32-nm 1000-Processor Computational Array. IEEE J. Solid State Circuits 52(4): 891-902 (2017) - [j21]Brent Bohnenstiehl, Aaron Stillmaker, Jon J. Pimentel, Timothy Andreas, Bin Liu, Anh Tran, Emmanuel Adeagbo, Bevan M. Baas:
KiloCore: A Fine-Grained 1, 000-Processor Array for Task-Parallel Applications. IEEE Micro 37(2): 63-69 (2017) - [j20]Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark M. Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson:
Editorial. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 1-20 (2017) - [j19]Jon J. Pimentel, Brent Bohnenstiehl, Bevan M. Baas:
Hybrid Hardware/Software Floating-Point Implementations for Optimized Area and Throughput Tradeoffs. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 100-113 (2017) - [c35]Michael Braly, Aaron Stillmaker, Bevan M. Baas:
A configurable H.265-compatible motion estimation accelerator architecture for realtime 4K video encoding in 65 nm CMOS. DSC 2017: 79-85 - 2016
- [c34]Brent Bohnenstiehl, Aaron Stillmaker, Jon J. Pimentel, Timothy Andreas, Bin Liu, Anh Tran, Emmanuel Adeagbo, Bevan M. Baas:
KiloCore: A 32 nm 1000-processor array. Hot Chips Symposium 2016: 1-23 - [c33]Brent Bohnenstiehl, Aaron Stillmaker, Jon J. Pimentel, Timothy Andreas, Bin Liu, Anh Tran, Emmanuel Adeagbo, Bevan M. Baas:
A 5.8 pJ/Op 115 billion ops/sec, to 1.78 trillion ops/sec 32nm 1000-processor array. VLSI Circuits 2016: 1-2 - 2015
- [c32]Brent Bohnenstiehl, Bevan M. Baas:
A software LDPC decoder implemented on a many-core array of programmable processors. ACSSC 2015: 192-196 - [c31]Jon J. Pimentel, Aaron Stillmaker, Brent Bohnenstiehl, Bevan M. Baas:
Area efficient backprojection computation with reduced floating-point word width for SAR image formation. ACSSC 2015: 732-726 - [c30]Bin Liu, Mohammad H. Foroozannejad, Soheil Ghiasi, Bevan M. Baas:
Optimizing power of many-core systems by exploiting dynamic voltage, frequency and core scaling. MWSCAS 2015: 1-4 - 2014
- [j18]Mohammad H. Foroozannejad, Matin Hashemi, Alireza Mahini, Bevan M. Baas, Soheil Ghiasi:
Time-Scalable Mapping for Circuit-Switched GALS Chip Multiprocessor Platforms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(5): 752-762 (2014) - [j17]Zhibin Xiao, Bevan M. Baas:
Processor Tile Shapes and Interconnect Topologies for Dense On-Chip Networks. IEEE Trans. Very Large Scale Integr. Syst. 22(6): 1377-1390 (2014) - [j16]Anh Thien Tran, Bevan M. Baas:
Achieving High-Performance On-Chip Networks With Shared-Buffer Routers. IEEE Trans. Very Large Scale Integr. Syst. 22(6): 1391-1403 (2014) - [c29]Jon J. Pimentel, Bevan M. Baas:
Hybrid floating-point modules with low area overhead on a fine-grained processing core. ACSSC 2014: 1829-1833 - [c28]Bin Liu, Brent Bohnenstiehl, Bevan M. Baas:
Scalable hardware-based power management for many-core systems. ACSSC 2014: 1834-1838 - 2013
- [j15]Bin Liu, Bevan M. Baas:
Parallel AES Encryption Engines for Many-Core Processor Arrays. IEEE Trans. Computers 62(3): 536-547 (2013) - [j14]Tinoosh Mohsenin, Houshmand Shirani-mehr, Bevan M. Baas:
LDPC Decoder with an Adaptive Wordwidth Datapath for Energy and BER Co-Optimization. VLSI Design 2013: 913018:1-913018:14 (2013) - 2012
- [c27]Aaron Stillmaker, Lucas Stillmaker, Bevan M. Baas:
Fine-Grained Energy-Efficient Sorting on a Many-Core Processor Array. ICPADS 2012: 652-659 - [c26]Zhibin Xiao, Bevan M. Baas:
A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks. VLSI-SoC (Selected Papers) 2012: 125-143 - [c25]Zhibin Xiao, Bevan M. Baas:
A hexagonal shaped processor and interconnect topology for tightly-tiled many-core architecture. VLSI-SoC 2012: 153-158 - 2011
- [j13]Zhibin Xiao, Bevan M. Baas:
A 1080p H.264/AVC Baseline Residual Encoder for a Fine-Grained Many-Core System. IEEE Trans. Circuits Syst. Video Technol. 21(7): 890-902 (2011) - [c24]Bin Liu, Bevan M. Baas:
A high-performance area-efficient AES cipher on a many-core platform. ACSCC 2011: 2058-2062 - [c23]Zhibin Xiao, Stephen Le, Bevan M. Baas:
A fine-grained parallel implementation of a H.264/AVC encoder on a 167-processor computational platform. ACSCC 2011: 2067-2071 - [c22]Houshmand Shirani-mehr, Tinoosh Mohsenin, Bevan M. Baas:
A reduced routing network architecture for partial parallel LDPC decoders. ACSCC 2011: 2192-2196 - [c21]Anh Thien Tran, Bevan M. Baas:
RoShaQ: High-performance on-chip router with shared queues. ICCD 2011: 232-238 - [c20]Tinoosh Mohsenin, Houshmand Shirani-mehr, Bevan M. Baas:
Low power LDPC decoder with efficient stopping scheme for undecodable blocks. ISCAS 2011: 1780-1783 - 2010
- [j12]Anh Thien Tran, Dean Nguyen Truong, Bevan M. Baas:
A Reconfigurable Source-Synchronous On-Chip Network for GALS Many-Core Platforms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(6): 897-910 (2010) - [j11]Tinoosh Mohsenin, Dean Nguyen Truong, Bevan M. Baas:
A Low-Complexity Message-Passing Algorithm for Reduced Routing Congestion in LDPC Decoders. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(5): 1048-1061 (2010) - [j10]Zhiyi Yu, Bevan M. Baas:
A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors. IEEE Trans. Very Large Scale Integr. Syst. 18(5): 750-762 (2010) - [j9]Tinoosh Mohsenin, Bevan M. Baas:
A Split-Decoding Message Passing Algorithm for Low Density Parity Check Decoders. J. Signal Process. Syst. 61(3): 329-345 (2010) - [c19]Dean Truong, Bevan M. Baas:
Circuit modeling for practical many-core architecture design exploration. DAC 2010: 627-628
2000 – 2009
- 2009
- [j8]Dean Nguyen Truong, Wayne H. Cheng, Tinoosh Mohsenin, Zhiyi Yu, Anthony T. Jacobson, Gouri Landge, Michael J. Meeuwsen, Christine Watnik, Anh Thien Tran, Zhibin Xiao, Eric W. Work, Jeremy W. Webb, Paul Vincent Mejia, Bevan M. Baas:
A 167-Processor Computational Platform in 65 nm CMOS. IEEE J. Solid State Circuits 44(4): 1130-1144 (2009) - [j7]Zhiyi Yu, Bevan M. Baas:
High Performance, Energy Efficiency, and Scalability With GALS Chip Multiprocessors. IEEE Trans. Very Large Scale Integr. Syst. 17(1): 66-79 (2009) - [c18]Tinoosh Mohsenin, Dean Truong, Bevan M. Baas:
An Improved Split-Row Threshold Decoding Algorithm for LDPC Codes. ICC 2009: 1-5 - [c17]Anh Thien Tran, Dean Nguyen Truong, Bevan M. Baas:
A Low-cost High-speed Source-synchronous Interconnection Technique for GALS Chip Multiprocessors. ISCAS 2009: 996-999 - [c16]Anthony T. Jacobson, Dean Nguyen Truong, Bevan M. Baas:
The Design of a Reconfigurable Continuous-flow Mixed-radix FFT Processor. ISCAS 2009: 1133-1136 - [c15]Tinoosh Mohsenin, Dean Nguyen Truong, Bevan M. Baas:
Multi-Split-Row Threshold Decoding Implementations for LDPC Codes. ISCAS 2009: 2449-2452 - [c14]Anh Thien Tran, Dean Truong, Bevan M. Baas:
A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network. NOCS 2009: 214-223 - 2008
- [j6]Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, Omar Sattari, Michael A. Lai, Jeremy W. Webb, Eric W. Work, Dean Truong, Tinoosh Mohsenin, Bevan M. Baas:
AsAP: An Asynchronous Array of Simple Processors. IEEE J. Solid State Circuits 43(3): 695-705 (2008) - [j5]Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, Omar Sattari, Michael A. Lai, Jeremy W. Webb, Eric W. Work, Tinoosh Mohsenin, Bevan M. Baas:
Architecture and Evaluation of an Asynchronous Array of Simple Processors. J. Signal Process. Syst. 53(3): 243-259 (2008) - [c13]Anh Thien Tran, Dean Nguyen Truong, Bevan M. Baas:
A complete real-time 802.11a baseband receiver implemented on an array of programmable processors. ACSCC 2008: 165-170 - [c12]Tinoosh Mohsenin, Pascal Urard, Bevan M. Baas:
A thresholding algorithm for improved Split-Row decoding of LDPC codes. ACSCC 2008: 448-451 - [c11]Zhibin Xiao, Bevan M. Baas:
A high-performance parallel CAVLC encoder on a fine-grained many-core system. ICCD 2008: 248-254 - [c10]Wayne H. Cheng, Bevan M. Baas:
Dynamic voltage and frequency scaling circuits with two supply voltages. ISCAS 2008: 1236-1239 - [c9]Zhiyi Yu, Bevan M. Baas:
A low-area interconnect architecture for chip multiprocessors. ISCAS 2008: 2857-2860 - 2007
- [j4]Michael J. Meeuwsen, Zhiyi Yu, Bevan M. Baas:
A Shared Memory Module for Asynchronous Arrays of Processors. EURASIP J. Embed. Syst. 2007 (2007) - [j3]Bevan M. Baas, Zhiyi Yu, Michael J. Meeuwsen, Omar Sattari, Ryan W. Apperson, Eric W. Work, Jeremy W. Webb, Michael A. Lai, Tinoosh Mohsenin, Dean Truong, Jason Cheung:
AsAP: A Fine-Grained Many-Core Platform for DSP Applications. IEEE Micro 27(2): 34-45 (2007) - [j2]Ryan W. Apperson, Zhiyi Yu, Michael J. Meeuwsen, Tinoosh Mohsenin, Bevan M. Baas:
A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains. IEEE Trans. Very Large Scale Integr. Syst. 15(10): 1125-1134 (2007) - [c8]Tinoosh Mohsenin, Bevan M. Baas:
High-Throughput LDPC Decoders Using A Multiple Split-Row Method. ICASSP (2) 2007: 13-16 - 2006
- [c7]Bevan M. Baas, Zhiyi Yu, Michael J. Meeuwsen, Omar Sattari, Ryan W. Apperson, Eric W. Work, Jeremy W. Webb, Michael A. Lai, Daniel Gurman, Chi Chen, Jason Cheung, Dean Truong, Tinoosh Mohsenin:
Hardware and applications of AsAP: An asynchronous array of simple processors. Hot Chips Symposium 2006: 1-31 - [c6]Zhiyi Yu, Bevan M. Baas:
Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles. ICCD 2006: 174-179 - [c5]Tinoosh Mohsenin, Bevan M. Baas:
Split-Row: A Reduced Complexity, High Throughput LDPC Decoder Architecture. ICCD 2006: 320-325 - [c4]Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, Omar Sattari, Michael A. Lai, Jeremy W. Webb, Eric W. Work, Tinoosh Mohsenin, Mandeep Singh, Bevan M. Baas:
An asynchronous array of simple processors for dsp applications. ISSCC 2006: 1696-1705 - [c3]Zhiyi Yu, Bevan M. Baas:
Performance and Power Analysis of Globally Asynchronous Locally Synchronous Multi-Processor Systems. ISVLSI 2006: 378-383 - 2005
- [c2]Bevan M. Baas:
A generalized cached-FFT algorithm. ICASSP (5) 2005: 89-92
1990 – 1999
- 1999
- [j1]Bevan M. Baas:
A low-power, high-performance, 1024-point FFT processor. IEEE J. Solid State Circuits 34(3): 380-387 (1999) - 1998
- [c1]Bevan M. Baas:
A 9.5 mW 330 μsec 1024-point FFT processor. CICC 1998: 127-130
Coauthor Index
Dean Nguyen Truong
aka: Dean Truong
aka: Dean Truong
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2025-01-20 22:59 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
