Wideband Tunable N-Path Mixer With Calibrated Harmonic Rejection Including the 7th LO Harmonic - Sana Ibrahim; Ali Al Shakoush; Serge Subias; Loic Vincent; Manuel J. Barragan Asian; Laurent Fesquet; Florence Podevin; Sylvain Bourdel (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Data-driven Processing Element for Sparse Convolutional Neural Networks - Xavier Lesage; Cristiano Merio; Fernando Welzel; Luca Sauer de Araujo; Sylvain Engels; Laurent Fesquet (22nd IEEE Interregional NEWCAS Conference, NEWCAS 2024, Sherbrooke, QC, Canada, June 16-19, 2024, 2024)

Time-to-Digital Converter Based Self-Timed Ring Oscillator: An FPGA Implementation - Assia El-Hadbi; Oussama Elissati; Laurent Fesquet (32nd IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2024, Tanger, Morocco, October 6-9, 2024, 2024)

A New Control Law for N-Path Mixer Switches Enhancing Harmonic Rejection - Hasan Moussa; Estelle Lauga-Larroze; Laurent Fesquet (32nd IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2024, Tanger, Morocco, October 6-9, 2024, 2024)

Velocity and Color Estimation Using Event-Based Clustering - Xavier Lesage; Rosalie Tran; Stéphane Mancini; Laurent Fesquet (Sensors, 2023)

Low-Throughput Event-Based Image Sensors and Processing - Laurent Fesquet; Rosalie Tran; Xavier Lesage; Mohamed Akrarai; Stéphane Mancini; Gilles Sicard (Design, Automation & Test in Europe Conference & Exhibition, DATE 2023, Antwerp, Belgium, April 17-19, 2023, 2023)

Making Digital N-Path Mixers - Hasan Moussa; Jessica Gonsalves; Estelle Lauga-Larroze; Sana Ibrahim; Florence Podevin; Sylvain Bourdel; Laurent Fesquet (38th Conference on Design of Circuits and Integrated Systems, DCIS 2023, Málaga, Spain, November 15-17, 2023, 2023)

A Generic CDC Modeling for Data Stability Verification - Diana Kalel; Jean-Christophe Brignone; Laurent Fesquet; Katell Morin-Allory (30th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2023, Istanbul, Turkey, December 4-7, 2023, 2023)

Method for Data-Driven Pruning in Micropipeline Circuits - Cristiano Merio; Xavier Lesage; Ali Naimi; Sylvain Engels; Katell Morin-Allory; Laurent Fesquet (31st IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023, 2023)

An improved event-by-event clustering algorithm for noisy acquisition - Xavier Lesage; Rosalie Tran; Stéphane Mancini; Laurent Fesquet (8th International Conference on Event-Based Control, Communication, and Signal Processing, EBCCSP 2022, Krakow, Poland, June 22-24, 2022, 2022)

A Novel Event-Based Method for ASK Demodulation - Alexis Rodrigo Iga Jadue; Sylvain Engels; Laurent Fesquet (13th IEEE Latin America Symposium on Circuits and System, LASCAS 2022, Puerto Varas, Chile, March 1-4, 2022, 2022)

N-Path Mixer with Wide Rejection Including the 7\(^th\) Harmonic for Low Power Multi-standard Receivers - Ali Al Shakoush; Sana Ibrahim; Serge Subias; Florence Podevin; Manuel J. Barragán; Dayana A. Pino-Monroy; Imadeddine Bendjeddou; Estelle Lauga-Larroze; Laurent Fesquet; Thierry Taris; Sylvain Bourdel (20th IEEE Interregional NEWCAS Conference, NEWCAS 2022, Quebec City, QC, Canada, June 19-22, 2022, 2022)

Self-Timed Ring Oscillators for Non-Overlapping and Overlapping Phases Synthesis - Hasan Moussa; Sana Ibrahim; Estelle Lauga-Larroze; Florence Podevin; Sylvain Bourdel; Laurent Fesquet (20th IEEE Interregional NEWCAS Conference, NEWCAS 2022, Quebec City, QC, Canada, June 19-22, 2022, 2022)

An Area- and Power-Efficient Stochastic Number Generator for Bayesian Sensor Fusion Circuits - Jérémy Belot; Abdelkarim Cherkaoui; Raphaël Laurent; Laurent Fesquet (IEEE Des. Test, 2021)

Design and Characterization of an Asynchronous Fixed Priority Tree Arbiter for SPAD Array Readout - Enagnon Aguénounon; Safa Razavinejad; Jean-Baptiste Schell; Mohammadreza Dolatpoor Lakeh; Wassim Khaddour; Foudil Dadouche; Jean-Baptiste Kammerer; Laurent Fesquet; Wilfried Uhring (Sensors, 2021)

An asynchronous hybrid pixel image sensor - Mohamed Akrarai; Nils Margotat; Gilles Sicard; Laurent Fesquet (27th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2021, Beijing, China, September 7-10, 2021, 2021)

Comparison between an ASK Event-Based Demodulation and a Digital IQ Demodulation - Alexis Rodrigo Iga Jadue; Sylvain Engels; Laurent Fesquet (7th International Conference on Event-Based Control, Communication, and Signal Processing, EBCCSP 2021, Krakow, Poland, June 22-25, 2021, 2021)

Self-Timed Ring Oscillator based Time-to-Digital Converter: A 0.35\(μ\) m CMOS Proof-of-Concept Prototype - Assia El-Hadbi; Oussama Elissati; Laurent Fesquet (IEEE International Instrumentation and Measurement Technology Conference, I2MTC 2021, Glasgow, United Kingdom, May 17-20, 2021, 2021)

A hybrid event-based pixel for low-power image sensing - Mohamed Akrarai; Nils Margotat; Gilles Sicard; Laurent Fesquet (28th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2021, Dubai, United Arab Emirates, November 28 - Dec. 1, 2021, 2021)

An Energy Efficient Multi-Rail Architecture for Stochastic Computing: A Bayesian Sensor Fusion Case Study - Jérémy Belot; Abdelkarim Cherkaoui; Raphaël Laurent; Laurent Fesquet (28th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2021, Dubai, United Arab Emirates, November 28 - Dec. 1, 2021, 2021)

A High-Level Design Flow for Locally Body Biased Asynchronous Circuits - Yoan Decoudu; Katell Morin-Allory; Laurent Fesquet (29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, 2021)

Trojan Detection Test for Clockless Circuits - Ricardo Aquino Guazzelli; Matheus Garay Trindade; Leonel Acunha Guimaraes; Thiago Ferreira de Paiva Leite; Laurent Fesquet; Rodrigo Possamai Bastos (J. Electron. Test., 2020)

A Self-Timed Ring based PUF - Grégoire Gimenez; Abdelkarim Cherkaoui; Laurent Fesquet (26th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2020, Salt Lake City, UT, USA, May 17-20, 2020, 2020)

Arbiterless Event-Based Imager Architecture with temporal and spatial redundancies suppression - Mohamed Akrarai; Nils Margotat; Gilles Sicard; Laurent Fesquet (6th International Conference on Event-Based Control, Communication, and Signal Processing, EBCCSP 2020, Krakow, Poland, September 23-25, 2020, 2020)

An Effective QRS Selection Based on the Level-Crossing Sampling and Activity Selection - Saeed Mian Qaisar; Laurent Fesquet (6th International Conference on Event-Based Control, Communication, and Signal Processing, EBCCSP 2020, Krakow, Poland, September 23-25, 2020, 2020)

At-speed DfT Architecture for Bundled-data Design - Ricardo Aquino Guazzelli; Laurent Fesquet (IEEE International Test Conference, ITC 2020, Washington, DC, USA, November 1-6, 2020, 2020)

Improved \pi-Delayed Harmonic Rejection N-Path Mixer for Low Power Consumption and Multistandard Receiver - Ali Al Shakoush; Estelle Lauga-Larroze; Florence Podevin; Sana Ibrahim; Laurent Fesquet; Sylvain Bourdel (18th IEEE International New Circuits and Systems Conference, NEWCAS 2020, Montréal, QC, Canada, June 16-19, 2020, 2020)

A Novel Event Based Image Sensor with spacial and temporal redundancy suppression - Mohamed Akrarai; Nils Margotat; Gilles Sicard; Laurent Fesquet (18th IEEE International New Circuits and Systems Conference, NEWCAS 2020, Montréal, QC, Canada, June 16-19, 2020, 2020)

From High-Level Synthesis to Bundled-Data Circuits - Yoan Decoudu; Jean Simatic; Katell Morin-Allory; Laurent Fesquet (Embedded Computer Systems: Architectures, Modeling, and Simulation - 20th International Conference, SAMOS 2020, Samos, Greece, July 5-9, 2020, Proceedings, 2020)

From Signal Transition Graphs to Timing Closure: Application to Bundled-Data Circuits - Grégoire Gimenez; Jean Simatic; Laurent Fesquet (25th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2019, Hirosaki, Japan, May 12-15, 2019, 2019)

On-Line Adjustable Precision Computing - Ali Skaf; Mona Ezzadeen; Mounir Benabdenbi; Laurent Fesquet (14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, DTIS 2019, Mykonos, Greece, April 16-18, 2019, 2019)

A new synthesis approach for non-uniform filters in the log-scale: Proof of concept - Brigitte Bidégaray-Fesquet; Laurent Fesquet (5th International Conference on Event-Based Control, Communication, and Signal Processing, EBCCSP 2019, Vienna, Austria, May 27-29, 2019, 2019)

Comparison of Synchronous and Asynchronous FIR Filter Architectures - Yoan Decoudu; Jean Simatic; Pauline Alexandre; Katell Morin-Allory; Laurent Fesquet (5th International Conference on Event-Based Control, Communication, and Signal Processing, EBCCSP 2019, Vienna, Austria, May 27-29, 2019, 2019)

Time-to-Digital Converters: A Literature Review and New Perspectives - Assia El-Hadbi; Oussama Elissati; Laurent Fesquet (5th International Conference on Event-Based Control, Communication, and Signal Processing, EBCCSP 2019, Vienna, Austria, May 27-29, 2019, 2019)

An Event-Based Strategy for ASK demodulation - Alexis Rodrigo Iga Jadue; Sylvain Engels; Laurent Fesquet (5th International Conference on Event-Based Control, Communication, and Signal Processing, EBCCSP 2019, Vienna, Austria, May 27-29, 2019, 2019)

Skilled manpower shortage in microelectronics: a challenge for the French education microelectronics network - Olivier Bonnaud; Laurent Fesquet; Ahmad Bsiesy (18th International Conference on Information Technology Based Higher Education and Training, ITHET 2019, Magdeburg, Germany, September 26-27, 2019, 2019)

A Distributed Body-Biasing Strategy for Asynchronous Circuits - Laurent Fesquet; Yoan Decoudu; Alexis Rodrigo Iga Jadue; Thiago Ferreira de Paiva Leite; Otto Aureliano Rolloff; M. Diallo; Rodrigo Possamai Bastos; Katell Morin-Allory; Sylvain Engels (27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, 2019)

A Digital Event-Based Strategy for ASK demodulation - Alexis Rodrigo Iga Jadue; Sylvain Engels; Laurent Fesquet (27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, 2019)

Architectures of bulk built-in current sensors for detection of transient faults in integrated circuits - Rodrigo Possamai Bastos; Leonel Acunha Guimaraes; Frank Sill Torres; Laurent Fesquet (Microelectron. J., 2018)

A body built-in cell for detecting transient faults and dynamically biasing subcircuits of integrated systems - Thiago Ferreira de Paiva Leite; Laurent Fesquet; Rodrigo Possamai Bastos (Microelectron. Reliab., 2018)

A Cognitive Stochastic Machine Based on Bayesian Inference: A Behavioral Analysis - Raphael Frisch; Marvin Faix; Emmanuel Mazer; Laurent Fesquet; Augustin Lux (17th IEEE International Conference on Cognitive Informatics & Cognitive Computing, ICCI*CC 2018, Berkeley, CA, USA, July 16-18, 2018, 2018)

A Design Flow for Shaping Electromagnetic Emissions in Micropipeline Circuits - Sophie Germain; Sylvain Engels; Laurent Fesquet (24th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2018, Vienna, Austria, May 13-16, 2018, 2018)

Static Timing Analysis of Asynchronous Bundled-Data Circuits - Gregoire Gimenez; Abdelkarim Cherkaoui; Guillaume Cogniard; Laurent Fesquet (24th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2018, Vienna, Austria, May 13-16, 2018, 2018)

Subthreshold logic for low-area and energy efficient true random number generator - Mathieu Coustans; Abdelkarim Cherkaoui; Laurent Fesquet; Christian Terrier; Stephanie Salgado; Thomas Eberhardt; Maher Kayal (2018 IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2018, Yokohama, Japan, April 18-20, 2018, 2018)

Non-intrusive testing technique for detection of Trojans in asynchronous circuits - Leonel Acunha Guimaraes; Thiago Ferreira de Paiva Leite; Rodrigo Possamai Bastos; Laurent Fesquet (2018 Design, Automation & Test in Europe Conference & Exhibition, DATE 2018, Dresden, Germany, March 19-23, 2018, 2018)

Low Phase-Noise CMOS Quadrature Oscillator based on (N exttimes 4)-stage Self-Timed Ring - Oussama Elissati; Assia El-Hadbi; Abdelkarim Cherkaoui; Sébastien Rieubon; Laurent Fesquet (Conference on Design of Circuits and Integrated Systems, DCIS 2018, Lyon, France, November 14-16, 2018, 2018)

An Asynchronous Fixed Priority Arbiter for High througput Time Correlated Single Photon Counting Systems - Timothe Turko; Wilfried Uhring; Foudil Dadouche; Laurent Fesquet (25th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2018, Bordeaux, France, December 9-12, 2018, 2018)

Level Shifter Architecture for Dynamically Biasing Ultra-Low Voltage Subcircuits of Integrated Systems - Alexis Rodrigo Iga Jadue; Rodrigo Possamai Bastos; Thiago Ferreira de Paiva Leite; Otto Aureliano Rolloff; M. Diallo; Laurent Fesquet (IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy, 2018)

Strategy for higher education in electronic circuits and systems in the perspective of the up-coming digital society - Olivier Bonnaud; Laurent Fesquet; Luc Hébrard (9th IEEE Latin American Symposium on Circuits & Systems, LASCAS 2018, Puerto Vallarta, Mexico, February 25-28, 2018, 2018)

A Practical Framework for Specification, Verification, and Design of Self-Timed Pipelines - Jean Simatic; Abdelkarim Cherkaoui; François Bertrand; Rodrigo Possamai Bastos; Laurent Fesquet (23rd IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2017, San Diego, CA, USA, May 21-24, 2017, 2017)

Event-driven image sensor application: Event-driven image segmentation - Amani Darwish; Hassan Abbass; Laurent Fesquet; Gilles Sicard (3rd International Conference on Event-Based Control, Communication and Signal Processing, EBCCSP 2017, Funchal, Portugal, May 24-26, 2017, 2017)

Event-based design strategy for circuit electromagnetic compatibility - Sophie Germain; Sylvain Engels; Laurent Fesquet (3rd International Conference on Event-Based Control, Communication and Signal Processing, EBCCSP 2017, Funchal, Portugal, May 24-26, 2017, 2017)

High-level synthesis of an event-driven windowing process - Saeed Mian Qaisar; Jean Simatic; Laurent Fesquet (3rd International Conference on Event-Based Control, Communication and Signal Processing, EBCCSP 2017, Funchal, Portugal, May 24-26, 2017, 2017)

Towards consistency checking between HDL and UPF descriptions - Arthur Kalsing; Laurent Fesquet; Chouki Aktouf (2017 Forum on Specification and Design Languages, FDL 2017, Verona, Italy, September 18-20, 2017, 2017)

A Methodology for Automated Consistency Checking Between Different Power-Aware Descriptions - Arthur Kalsing; Laurent Fesquet; Chouki Aktouf (Languages, Design Methods, and Tools for Electronic System Design - Selected Contributions from FDL 2017 [Verona, Italy, September 18-20, 2017], 2017)

CAR: On the highway towards de-synchronization - François Bertrand; Abdelkarim Cherkaoui; Jean Simatic; Anthony Maure; Laurent Fesquet (24th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2017, Batumi, Georgia, December 5-8, 2017, 2017)

A Bayesian Stochastic Machine for Sound Source Localization - Raphael Frisch; Raphaël Laurent; Marvin Faix; Laurent Girin; Laurent Fesquet; Augustin Lux; Jacques Droulez; Pierre Bessière; Emmanuel Mazer (IEEE International Conference on Rebooting Computing, ICRC 2017, Washington, DC, USA, November 8-9, 2017, 2017)

Seeking low-power synchronous/asynchronous systems: A FIR implementation case study - Ali Skaf; Jean Simatic; Laurent Fesquet (IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017, 2017)

Detection of Layout-Level Trojans by Monitoring Substrate with Preexisting Built-in Sensors - Leonel Acunha Guimaraes; Rodrigo Possamai Bastos; Laurent Fesquet (2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017, Bochum, Germany, July 3-5, 2017, 2017)

Self-timed Ring based True Random Number Generator: Threat model and countermeasures - Gregoire Gimenez; Abdelkarim Cherkaoui; Raphael Frisch; Laurent Fesquet (IEEE 2nd International Verification and Security Workshop, IVSW 2017, Thessaloniki, Greece, July 3-5, 2017, 2017)

Innovative practice in the French microelectronics education targeting the industrial needs - Olivier Bonnaud; Laurent Fesquet (2017 IEEE International Conference on Microelectronic Systems Education, MSE 2017, Lake Louise, AB, Canada, May 11-12, 2017, 2017)

On-the-fly and sub-gate-delay resolution TDC based on self-timed ring: A proof of concept - Assia El-Hadbi; Abdelkarim Cherkaoui; Oussama Elissati; Jean Simatic; Laurent Fesquet (15th IEEE International New Circuits and Systems Conference, NEWCAS 2017, Strasbourg, France, June 25-28, 2017, 2017)

Simple tri-state logic Trojans able to upset properties of ring oscillators - Leonel Acunha Guimaraes; Rodrigo Possamai Bastos; Thiago Ferreira de Paiva Leite; Laurent Fesquet (2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2016, Istanbul, Turkey, April 12-14, 2016, 2016)

Asynchronous implementation of an event-driven adaptive FIR filter - Taha Beyrouthy; Ahmed Roshdy; Mohammad Salman; Saeed Mian Qaisar; Laurent Fesquet (Second International Conference on Event-based Control, Communication, and Signal Processing, EBCCSP 2016, Krakow, Poland, June 13-15, 2016, 2016)

Levels, peaks, slopes... which sampling for which purpose? - Brigitte Bidégaray-Fesquet; Laurent Fesquet (Second International Conference on Event-based Control, Communication, and Signal Processing, EBCCSP 2016, Krakow, Poland, June 13-15, 2016, 2016)

High-level synthesis for event-based systems - Jean Simatic; Rodrigo Possamai Bastos; Laurent Fesquet (Second International Conference on Event-based Control, Communication, and Signal Processing, EBCCSP 2016, Krakow, Poland, June 13-15, 2016, 2016)

Delay partitioning helps reducing variability in 3DVLSI - A. Ayres; Olivier Rozeau; B. Borot; Laurent Fesquet; Maud Vinet (ESSCIRC Conference 2016: 42\(^nd\) European Solid-State Circuits Conference, Lausanne, Switzerland, September 12-15, 2016, 2016)

Practice in microelectronics education as a mandatory supplement to the future digital-based pedagogy: Strategy of the French national network - Olivier Bonnaud; Laurent Fesquet (11th European Workshop on Microelectronics Education, EWME 2016, Southampton, UK, May 11-13, 2016, 2016)

MOOC and practices in electrical and information engineering: Complementary approaches - Olivier Bonnaud; Laurent Fesquet (15th International Conference on Information Technology Based Higher Education and Training, ITHET 2016, Istanbul, Turkey, September 8-10, 2016, 2016)

Comparison of low-voltage scaling in synchronous and asynchronous FD-SOI circuits - Thiago Ferreira de Paiva Leite; Rodrigo Possamai Bastos; Rodrigo Iga Jadue; Laurent Fesquet (26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016, Bremen, Germany, September 21-23, 2016, 2016)

New asynchronous protocols for enhancing area and throughput in bundled-data pipelines - Jean Simatic; Abdelkarim Cherkaoui; Rodrigo Possamai Bastos; Laurent Fesquet (29th Symposium on Integrated Circuits and Systems Design, SBCCI 2016, Belo Horizonte, Brazil, August 29 - September 3, 2016, 2016)

Exploiting reliable features of asynchronous circuits for designing low-voltage components in FD-SOI technology - Otto Aureliano Rolloff; Rodrigo Possamai Bastos; Laurent Fesquet (Microelectron. Reliab., 2015)

A method to automatically determine the level-crossing thresholds in non-uniform sampling and processing - Cansu Arslan; Julien Poujaud; Laurent Fesquet (International Conference on Event-based Control, Communication, and Signal Processing, EBCCSP 2015, Krakow, Poland, June 17-19, 2015, 2015)

Data sampling and processing: Uniform vs. non-uniform schemes - Taha Beyrouthy; Laurent Fesquet; Robin Rolland (International Conference on Event-based Control, Communication, and Signal Processing, EBCCSP 2015, Krakow, Poland, June 17-19, 2015, 2015)

RTL simulation of an asynchronous reading architecture for an event-driven image sensor - Amani Darwish; Laurent Fesquet; Gilles Sicard (International Conference on Event-based Control, Communication, and Signal Processing, EBCCSP 2015, Krakow, Poland, June 17-19, 2015, 2015)

Communicating and smart objects: Multidisciplinary topics for the innovative education in microelectronics and its applications - Olivier Bonnaud; Laurent Fesquet (2015 International Conference on Information Technology Based Higher Education and Training, ITHET 2015, Lisbon, Portugal, June 11-13, 2015, 2015)

Towards multidisciplinarity for microelectronics education: A strategy of the French national network - Olivier Bonnaud; Laurent Fesquet (2015 IEEE International Conference on Microelectronics Systems Education, MSE 2015, Pittsburgh, PA, USA, May 20-21, 2015, 2015)

A generic clock controller for low power systems: Experimentation on an AXI bus - Chadi Al Khatib; Claire Aupetit; Cyril Chevalier; Chouki Aktouf; Gilles Sicard; Laurent Fesquet (2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, 2015)

Adaptive rate filtering a computationally efficient signal processing approach - Saeed Mian Qaisar; Laurent Fesquet; Marc Renaudin (Signal Process., 2014)

Low data rate architecture for smart image sensor - Amani Darwish; Gilles Sicard; Laurent Fesquet (Image Sensors and Imaging Systems 2014, San Francisco, California, USA, February 2-6, 2014, 2014)

Trends in nanoelectronic education from FDSOI and FinFET technologies to circuit design specifications - Olivier Bonnaud; Laurent Fesquet (10th European Workshop on Microelectronics Education (EWME), Tallinn, Estonia, May 14-16, 2014, 2014)

Distributed asynchronous controllers for clock management in low power systems - Chadi Al Khatib; Claire Aupetit; Alejandro Chagoya; Cyril Chevalier; Gilles Sicard; Laurent Fesquet (21st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2014, Marseille, France, December 7-10, 2014, 2014)

FINMINA: A French national project to promote innovation in higher education in microelectronics and nanotechnologies - Olivier Bonnaud; Pascal Nouet; Laurent Fesquet; Taieb Mohammed-Brahim (2014 Information Technology Based Higher Education and Training, ITHET 2014, York, United Kingdom, September 11-13, 2014, 2014)

1-Level crossing sampling scheme for low data rate image sensors - Amani Darwish; Laurent Fesquet; Gilles Sicard (IEEE 12th International New Circuits and Systems Conference, NEWCAS 2014, Trois-Rivieres, QC, Canada, June 22-25, 2014, 2014)

Self-timed rings as low-phase noise programmable oscillators - Laurent Fesquet; Abdelkarim Cherkaoui; Oussama Elissati (IEEE 12th International New Circuits and Systems Conference, NEWCAS 2014, Trois-Rivieres, QC, Canada, June 22-25, 2014, 2014)

Designing ultra-low power systems with non-uniform sampling and event-driven logic - Giuseppe Roa; Tugdual Le Pelleter; Agnès Bonvilain; Alejandro Chagoya; Laurent Fesquet (Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, Aracaju, Brazil, September 1-5, 2014, 2014)

An Asynchronous FPGA Block with Its Tech-Mapping Algorithm Dedicated to Security Applications - Taha Beyrouthy; Laurent Fesquet (Int. J. Reconfigurable Comput., 2013)

Empirical Recovery of Input Nonlinearity in Distributed Element Models - Przemyslaw Sliwinski; Krzysztof S. Berezowski; Pawel Wachel; Gilles Sicard; Laurent Fesquet (11th IFAC International Workshop on Adaptation and Learning in Control and Signal Processing, ALCOSP 2013, Caen, France, July 3-5, 2013, 2013)

Statistical Static Timing Analysis of Conditional Asynchronous Circuits Using Model-Based Simulation - Eslam Yahya; Laurent Fesquet; Yehea I. Ismail; Marc Renaudin (19th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2013, Santa Monica, CA, USA, May 19-22, 2013, 2013)

A Self-Timed Ring Based True Random Number Generator - Abdelkarim Cherkaoui; Viktor Fischer; Alain Aubert; Laurent Fesquet (19th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2013, Santa Monica, CA, USA, May 19-22, 2013, 2013)

A Very High Speed True Random Number Generator with Entropy Assessment - Abdelkarim Cherkaoui; Viktor Fischer; Laurent Fesquet; Alain Aubert (Cryptographic Hardware and Embedded Systems - CHES 2013 - 15th International Workshop, Santa Barbara, CA, USA, August 20-23, 2013. Proceedings, 2013)

Innovating projects as a pedagogical strategy for the French network for education in microélectronics and nanotechnologies - Olivier Bonnaud; Laurent Fesquet (2013 IEEE International Conference on Microelectronic Systems Education, MSE 2013, Austin, TX, USA, June 2-3, 2013, 2013)

Comparison of Self-Timed Ring and Inverter Ring Oscillators as entropy sources in FPGAs - Abdelkarim Cherkaoui; Viktor Fischer; Alain Aubert; Laurent Fesquet (2012 Design, Automation & Test in Europe Conference & Exhibition, DATE 2012, Dresden, Germany, March 12-16, 2012, 2012)

New pedagogical experiment leading to awareness in nanosciences and nanotechnologies for young generations at secondary school - Evelyne Excoffon; Francine Papillon; Laurent Fesquet; Ahmad Bsiesy; Olivier Bonnaud (2012 International Conference on Information Technology Based Higher Education and Training, ITHET 2012, Istanbul, Turkey, June 21-23, 2012, 2012)

Designing a Process Variability Robust Energy-Efficient Control for Complex SoCs - Hatem Zakaria; Laurent Fesquet (IEEE J. Emerg. Sel. Topics Circuits Syst., 2011)

Formal Verification of C-element Circuits - Chao Yan; Florent Ouchet; Laurent Fesquet; Katell Morin-Allory (17th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2011, Cornell University, Ithaca, New York, USA, 27-29 April 2011, 2011)

Does asynchronous technology bring robustness in synchronous circuit monitoring? - Alexandre Porcher; Katell Morin-Allory; Laurent Fesquet; Alejandro Chagoya (2011 Forum on Specification & Design Languages, FDL 2011, Oldenburg, Germany, September 13-15, 2011, 2011)

C-elements for Hardened Self-timed Circuits - Florent Ouchet; Katell Morin-Allory; Laurent Fesquet (Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - 21st International Workshop, PATMOS 2011, Madrid, Spain, September 26-29, 2011. Proceedings, 2011)

An event-driven FIR filter: Design and implementation - Taha Beyrouthy; Laurent Fesquet (Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, RSP 2011, Karlsruhe, Germany, 24-27 May, 2011, 2011)

A Secure Asynchronous FPGA Architecture, Experimental Results and Some Debug Feedback - Sumanta Chaudhuri; Sylvain Guilley; Philippe Hoogvorst; Jean-Luc Danger; Taha Beyrouthy; Alin Razafindraibe; Laurent Fesquet; Marc Renaudin (CoRR, 2011)

IIR digital filtering of non-uniformly sampled signals via state representation - Laurent Fesquet; Brigitte Bidégaray-Fesquet (Signal Process., 2010)

Delay Insensitivity Does Not Mean Slope Insensitivity! - Florent Ouchet; Katell Morin-Allory; Laurent Fesquet (16th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2010, Grenoble, France, 3-6 May 2010, 2010)

Synthesis of asynchronous monitors for critical electronic systems - Alexandre Porcher; Katell Morin-Allory; Laurent Fesquet (13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010, Vienna, Austria, April 14-16, 2010, 2010)

Targeting ultra-low power consumption with non-uniform sampling and filtering - Laurent Fesquet; Gilles Sicard; Brigitte Bidégaray-Fesquet (International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France, 2010)

Optimizing and Comparing CMOS Implementations of the C-Element in 65nm Technology: Self-Timed Ring Case - Oussama Elissati; Eslam Yahya; Sébastien Rieubon; Laurent Fesquet (Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - 20th International Workshop, PATMOS 2010, Grenoble, France, September 7-10, 2010, Revised Selected Papers, 2010)

Self-Timed Rings: A Promising Solution for Generating High-Speed High-Resolution Low-Phase Noise Clocks - Oussama Elissati; Sébastien Rieubon; Eslam Yahya; Laurent Fesquet (VLSI-SoC: Forward-Looking Trends in IC and Systems Design - 18th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2010, Madrid, Spain, September 27-29, 2010, Revised Selected Papers, 2010)

A high-speed high-resolution low-phase noise oscillator using self-timed rings - Oussama Elissati; Eslam Yahya; Sébastien Rieubon; Laurent Fesquet (18th IEEE/IFIP VLSI-SoC 2010, IEEE/IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Madrid, Spain, 27-29 September 2010, 2010)

Adaptive Rate Sampling and Filtering Based on Level Crossing Sampling - Saeed Mian Qaisar; Laurent Fesquet; Marc Renaudin (EURASIP J. Adv. Signal Process., 2009)

Constrained Asynchronous Ring Structures for Robust Digital Oscillators - Jérémie Hamon; Laurent Fesquet; Benoit Miscopein; Marc Renaudin (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Controlling energy and process variability in System-on-Chips: needs for control theory - Laurent Fesquet; Hatem Zakaria (Proceedings of the IEEE International Conference on Control Applications, CCA 2009 and of the International Symposium on Intelligent Control, ISIC 2009, Saint Petersburg, Russia, July 8-10, 2009, 2009)

Programmable/Stoppable Oscillator Based on Self-Timed Rings - Eslam Yahya; Oussama Elissati; Hatem Zakaria; Laurent Fesquet; Marc Renaudin (15th IEEE Symposium on Asynchronous Circuits and Systems, ASYNC 2009, Chapel Hill, NC, USA, May 17-20, 2009, 2009)

RAT-based formal verification of QDI asynchronous controllers - Khaled Alsayeg; Katell Morin-Allory; Laurent Fesquet (Forum on specification and Design Languages, FDL 2009, September 22-24, 2009, Sophia Antipolis, France, Proceedings, 2009)

Asynchronous design: A promising paradigm for electronic circuits and systems - Eslam Yahya; Laurent Fesquet (16th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2009, Yasmine Hammamet, Tunisia, 13-19 December, 2009, 2009)

Updates on the potential of clock-less logics to strengthen cryptographic circuits against side-channel attacks - Sylvain Guilley; Sumanta Chaudhuri; Laurent Sauvage; Jean-Luc Danger; Taha Beyrouthy; Laurent Fesquet (16th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2009, Yasmine Hammamet, Tunisia, 13-19 December, 2009, 2009)

An Adaptive Resolution Computationally Efficient Short-Time Fourier Transform - Saeed Mian Qaisar; Laurent Fesquet; Marc Renaudin (J. Electr. Comput. Eng., 2008)

Physical Design of FPGA Interconnect to Prevent Information Leakage - Sumanta Chaudhuri; Sylvain Guilley; Philippe Hoogvorst; Jean-Luc Danger; Taha Beyrouthy; Alin Razafindraibe; Laurent Fesquet; Marc Renaudin (Reconfigurable Computing: Architectures, Tools and Applications, 4th International Workshop, ARC 2008, London, UK, March 26-28, 2008. Proceedings, 2008)

High-Level Time-Accurate Model for the Design of Self-Timed Ring Oscillators - Jérémie Hamon; Laurent Fesquet; Benoit Miscopein; Marc Renaudin (14th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2008, Newcastle upon Tyne, UK, April 7-10, 2008, 2008)

A Reconfigurable Programmable Logic Block for a Multi-Style Asynchronous FPGA resistant to Side-Channel Attacks - Philippe Hoogvorst; Sylvain Guilley; Sumanta Chaudhuri; Jean-Luc Danger; Taha Beyrouthy; Laurent Fesquet (CoRR, 2008)

Computationally efficient adaptive rate sampling and filtering - Saeed Mian Qaisar; Laurent Fesquet; Marc Renaudin (15th European Signal Processing Conference, EUSIPCO 2007, Poznan, Poland, September 3-7, 2007, 2007)

Asynchronous online-monitoring of logical and temporal assertions - Katell Morin-Allory; Laurent Fesquet; Benjamin Roustan; Dominique Borrione (Forum on specification and Design Languages, FDL 2007, September 18-20, 2007, Barcelona, Spain, Proceedings, 2007)

A Novel Asynchronous e-FPGA Architecture for Security Applications - Taha Beyrouthy; Alin Razafindraibe; Laurent Fesquet; Marc Renaudin; Sumanta Chaudhuri; Sylvain Guilley; Jean-Luc Danger; Philippe Hoogvorst (2007 International Conference on Field-Programmable Technology, ICFPT 2007, Kitakyushu, Japan, December 12-14, 2007, 2007)

Adaptive Rate Filtering Fora Signal Driven Sampling Scheme - Saeed Mian Qaisar; Laurent Fesquet; Marc Renaudin (Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2007, Honolulu, Hawaii, USA, April 15-20, 2007, 2007)

A Reconfigurable Cell for a Multi-Style Asynchronous FPGA - Philippe Hoogvorst; Sylvain Guilley; Sumanta Chaudhuri; Alin Razafindraibe; Taha Beyrouthy; Laurent Fesquet (Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2007, Montpellier, France, June 2007, 2007)

FPGA Architecture for Multi-Style Asynchronous Logic - N. Huot; H. Dubreuil; Laurent Fesquet; Marc Renaudin (CoRR, 2007)

Spectral analysis of a signal driven sampling scheme - Saeed Mian Qaisar; Laurent Fesquet; Marc Renaudin (14th European Signal Processing Conference, EUSIPCO 2006, Florence, Italy, September 4-8, 2006, 2006)

Asynchronous Assertion Monitors for multi-Clock Domain System Verification - Katell Morin-Allory; Laurent Fesquet; Dominique Borrione (17th IEEE International Workshop on Rapid System Prototyping (RSP 2006), 14-16 June 2006, Chania, Crete, Greece, 2006)

State-holding in Look-Up Tables: application to asynchronous logic - Laurent Fesquet; Bertrand Folco; Mathieu Steiner; Marc Renaudin (IFIP VLSI-SoC 2006, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Nice, France, 16-18 October 2006, 2006)

FPGA Architecture for Multi-Style Asynchronous Logic - N. Huot; H. Dubreuil; Laurent Fesquet; Marc Renaudin (2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, 2005)

PSL-based online monitoring of digital systems - D. Borionne; M. Liu; P. Ostier; Laurent Fesquet (Forum on specification and Design Languages, FDL 2005, September 27-30, 2005, Lausanne, Switzerland, Proceedings, 2005)

A Programmable Logic Architecture for Prototyping Clockless Circuits - Laurent Fesquet; Marc Renaudin (Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005, 2005)

GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips - Jerome Quartana; Salim Renane; Arnaud Baixas; Laurent Fesquet; Marc Renaudin (Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005, 2005)

Asynchronous Systems on Programmable Logic - Laurent Fesquet; Jerome Quartana; Marc Renaudin (Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2005, Montpellier, France, June 2005, 2005)

Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits - Bertrand Folco; Vivian Brégier; Laurent Fesquet; Marc Renaudin (VLSI-SoC: From Systems To Silicon, Proceedings of IFIP TC 10, WG 10.5, Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005, Perth, Australia, 2005)

Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping - Jerome Quartana; Laurent Fesquet; Marc Renaudin (VLSI-SoC: From Systems To Silicon, Proceedings of IFIP TC 10, WG 10.5, Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005, Perth, Australia, 2005)

Proceedings of the 31st European Solid-State Circuits Conference, ESSCIRC 2005, Grenoble, France, 12-16 September 2005 - Laurent Fesquet; Andreas Kaiser; Sorin Cristoloveanu; Michel Brillouët (IEEE, 2005)

La technologie asynchrone au service de la réduction d'énergie dans les systèmes embarqués - Laurent Fesquet; Mohammed Es Salhiene; Marc Renaudin (Ann. des Télécommunications, 2004)

Asynchronous FIR Filters: Towards a New Digital Processing Chain - F. Aeschlimann; Emmanuel Allier; Laurent Fesquet; Marc Renaudin (10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 19-23 April 2004, Crete, Greece, 2004)

A New Class of Asynchronous A/D Converters Based on Time Quantization - Emmanuel Allier; Gilles Sicard; Laurent Fesquet; Marc Renaudin (9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 12-16 May 2003, Vancouver, BC, Canada, 2003)

High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems - Jean-Baptiste Rigaud; Laurent Fesquet; Marc Renaudin; Jerome Quartana (2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, 2002)

Implementing Asynchronous Circuits on LUT Based FPGAs - Quoc Thai Ho; Jean-Baptiste Rigaud; Laurent Fesquet; Marc Renaudin; Robin Rolland (Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, 2002)

Synthesis of QDI Asynchronous Circuits from DTL-Style Petri-Net - Anh Vu Dihn Duc; Laurent Fesquet; Marc Renaudin (11th IEEE/ACM International Workshop on Logic & Synthesis, IWLS 2002, June 4-7, 2002, New Orleans, Louisiana, USA, 2002)

Low-Power Asynchronous A/D Conversion - Emmanuel Allier; Laurent Fesquet; Marc Renaudin; Gilles Sicard (Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation, 12th International Workshop, PATMOS 2002, Seville, Spain, September 11-13, 2002, 2002)

Dynamic Voltage Scheduling for Real Time Asynchronous Systems - Mohammed Es Salhiene; Laurent Fesquet; Marc Renaudin (Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation, 12th International Workshop, PATMOS 2002, Seville, Spain, September 11-13, 2002, 2002)

Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems - Jean-Baptiste Rigaud; Jerome Quartana; Laurent Fesquet; Marc Renaudin (SOC Design Methodologies, IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on/Chip (VLSI-SOC'01), December 3-5, 2001, Montpellier, France, 2001)

Implementing Snoop-Coherence Protocol for Future SMP Architectures - Wissam Hlayhel; Jacques Henri Collet; Laurent Fesquet (Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31 - September 3, 1999, Proceedings, 1999)

Optical versus Electronic Bus for Address-Transactions in Future SMP Architectures - Wissam Hlayhel; Daniel Litaize; Laurent Fesquet; Jacques Henri Collet (Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques, Paris, France, October 12-18, 1998, 1998)