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"A Verification Algorithm for Logic Circuits with Internal Variables."

Toshihiro Nakaoa et al. (1995)

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DOI: 10.1109/ISCAS.1995.523794

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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  dblp key:
  - conf/iscas/NakaoaWKY95
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  - https://dblp.org/rec/conf/iscas/NakaoaWKY95
Toshihiro Nakaoa, Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida:
A Verification Algorithm for Logic Circuits with Internal Variables. ISCAS 1995: 1920-1923

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