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ORCIDIEEE Journal of Solid-State Circuits, Volume 45
Volume 45, Number 1, January 2010
- Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli, Sujal Vora:
A 45 nm 8-Core Enterprise Xeon¯ Processor. 7-14 - Hideaki Saito, Masayuki Nakajima, Takumi Okamoto, Yusuke Yamada, Akira Ohuchi, Noriyuki Iguchi, Toshitsugu Sakamoto, Koichi Yamaguchi, Masayuki Mizuno:
A Chip-Stacked Memory for On-Chip SRAM-Rich SoCs and Processors. 15-22 - Carlos Tokunaga
, David T. Blaauw:
Securing Encryption Systems With a Switched Capacitor Current Equalizer. 23-31 - Joo-Young Kim, Minsu Kim, Seungjin Lee, Jinwook Oh, Kwanho Kim, Hoi-Jun Yoo:
A 201.4 GOPS 496 mW Real-Time Multi-Object Recognition Processor With Bio-Inspired Neural Perception Engine. 32-45 - Li-Fu Ding, Wei-Yin Chen, Pei-Kuei Tsung, Tzu-Der Chuang, Pai-Heng Hsiao, Yu-Han Chen, Hsu-Kuang Chiu, Shao-Yi Chien, Liang-Gee Chen:
A 212 MPixels/s 4096 ˟ 2160p Multiview Video Encoder Chip for 3D/Quad Full HDTV Applications. 46-58 - Kenichi Iwata, Takahiro Irita, Seiji Mochizuki, Hiroshi Ueda, Masakazu Ehama, Motoki Kimura, Jun Takemura, Keiji Matsumoto, Eiji Yamamoto, Tadashi Teranuma, Katsuji Takakubo, Hiromi Watanabe, Shinichi Yoshioka, Toshihiro Hattori:
A 342 mW Mobile Application Processor With Full-HD Multi-Standard Video Codec and Tile-Based Address-Translation Circuits. 59-68 - Nick Van Helleputte, Marian Verhelst, Wim Dehaene, Georges G. E. Gielen:
A Reconfigurable, 130 nm CMOS 108 pJ/pulse, Fully Integrated IR-UWB Receiver for Communication and Precise Ranging. 69-83 - Pierre Busson, Nitin Chawla, Jérôme Bach, Stéphane Le Tual, Harvinder Singh, Vineet Gupta, Pascal Urard:
A 1 GHz Digital Channel Multiplexer for Satellite Outdoor Unit. 84-94 - Himanshu Kaul, Mark A. Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar:
A 300 mV 494GOPS/W Reconfigurable Dual-Supply 4-Way SIMD Vector Processing Accelerator in 45 nm CMOS. 95-102 - Yih Wang, Uddalak Bhattacharya, Fatih Hamzaoglu, Pramod Kolar, Yong-Gee Ng, Liqiong Wei, Ying Zhang, Kevin Zhang, Mark Bohr:
A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management. 103-110 - Uksong Kang, Hoeju Chung, Seongmoo Heo, Dukha Park, Hoon Lee, Jin Ho Kim, Soon-Hong Ahn, Sooho Cha, Jaesung Ahn, Dukmin Kwon, Jaewook Lee, Han-Sung Joo, Woo-Seop Kim, Dong Hyeon Jang, Nam-Seog Kim, Jung-Hwan Choi, Tae-Gyeong Chung, Jei-Hwan Yoo, Joo-Sun Choi, Changhyun Kim, Young-Hyun Jun:
8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology. 111-119 - Rex Kho, David Boursin, Martin Brox, Peter Gregorius, Heinz Hoenigschmid, Bianka Kho, Sabine Kieser, Daniel Kehrer, Maksim Kuzmenka, Udo Moeller, Pavel Veselinov Petkov, Manfred Plan, Michael Richter, Ian Russell, Kai Schiller, Ronny Schneider, Kartik Swaminathan, Bradley Weber, Julien Weber, Ingo Bormann, Fabien Funfrock, Mario Gjukic, Wolfgang Spirkl, Holger Steffens, Jörg Weller, Thomas Hein:
A 75 nm 7 Gb/s/pin 1 Gb GDDR5 Graphics Memory Device With Bandwidth Improvement Techniques. 120-133 - Mitsuko Saito, Yasufumi Sugimori, Yoshinori Kohama, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda:
2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking. 134-141 - Hidehiro Shiga, Daisaburo Takashima, Shinichiro Shiratake, Katsuhiko Hoya, Tadashi Miyakawa, Ryu Ogiwara, Ryo Fukuda, Ryosuke Takizawa, Kosuke Hatsuda, Fumiyoshi Matsuoka, Yasushi Nagadomi, Daisuke Hashimoto, Hisaaki Nishimura, Takeshi Hioka, Sumiko M. Doumae, Shoichi Shimizu, Mitsumo Kawano, Toyoki Taguchi, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Yoshinori Kumura, Yoshiro Shimojo, Yuki Yamada, Yoshihiro Minami, Susumu Shuto, Koji Yamakawa, Soichi Yamazaki, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama, Tohru Furuyama:
A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes. 142-152 - Denis C. Daly, Patrick P. Mercier, Manish Bhardwaj, Alice L. Stone, Zane N. Aldworth, Thomas L. Daniel, Joel Voldman, John G. Hildebrand, Anantha P. Chandrakasan:
A Pulsed UWB Receiver SoC for Insect Motion Control. 153-166 - Martin Flatscher, Markus Dielacher, Thomas Herndl, Thomas Lentsch, Rainer Matischek, Josef Prainsack, Wolfgang Pribyl, Horst Theuss, Werner Weber:
A Bulk Acoustic Wave (BAW) Based Transceiver for an In-Tire-Pressure Monitoring Sensor Node. 167-177 - Jerald Yoo, Long Yan, Seulki Lee, Yongsang Kim, Hoi-Jun Yoo:
A 5.2 mW Self-Configured Wearable Body Sensor Network Controller and a 12 μ W Wirelessly Powered Sensor for a Continuous Health Monitoring System. 178-188 - Yogesh K. Ramadass, Anantha P. Chandrakasan:
An Efficient Piezoelectric Energy Harvesting Interface Circuit Using a Bias-Flip Rectifier and Shared Inductor. 189-204 - Mirko Frank, Matthias Kuhl, Gilbert Erdler, Ingo Freund, Yiannos Manoli, Claas Müller, Holger Reinecke:
An Integrated Power Supply System for Low Power 3.3 V Electronics Using On-Chip Polymer Electrolyte Membrane (PEM) Fuel Cells. 205-213 - Patrick Villard, Ursula Ebels, Dimitri Houssameddine, Jordan A. Katine, Daniele Mauri, Bertrand Delaet, Pierre Vincent, Marie Claire Cyrille, Bernard Viala, Jean-Philippe Michel, Jérôme Prouvée, Franck Badets:
A GHz Spintronic-Based RF Oscillator. 214-223 - David Ruffieux, François Krummenacher, Aurélie Pezous, Guido Spinola-Durante:
Silicon Resonator Based 3.2 muW Real Time Clock With pm10 ppm Frequency Accuracy. 224-234 - Ian A. Young, Edris Mohammed, Jason T. S. Liao, Alexandra M. Kern, Samuel Palermo, Bruce A. Block, Miriam R. Reshotko, Peter L. D. Chang:
Optical I/O Technology for Tera-Scale Computing. 235-248 - Koichi Ishida, Naoki Masunaga, Zhiwei Zhou, Tadashi Yasufuku, Tsuyoshi Sekitani, Ute Zschieschang, Hagen Klauk, Makoto Takamiya, Takao Someya, Takayasu Sakurai:
Stretchable EMI Measurement Sheet With 8 ˟ 8 Coil Array, 2 V Organic CMOS Decoder, and 0.18 μ m Silicon CMOS LSIs for Electric and Magnetic Field Detection. 249-259
Volume 45, Number 2, February 2010
- Jri Lee, Yentso Chen, Yenlin Huang:
A Low-Power Low-Cost Fully-Integrated 60-GHz Transceiver System With OOK Modulation and On-Board Antenna Assembly. 264-275 - Roman Staszewski, Robert Bogdan Staszewski, Tom Jung, Thomas Murphy, Imran Bashir, Oren E. Eliezer, Khurram Muhammad, Mitch Entezari:
Software Assisted Digital RF Processor (DRP™) for Single-Chip GSM Radio in 90 nm CMOS. 276-288 - Mohamed El-Nozahi, Edgar Sánchez-Sinencio, Kamran Entesari:
A Millimeter-Wave (23-32 GHz) Wideband BiCMOS Low-Noise Amplifier. 289-299 - Xueyang Geng, Fa Foster Dai, J. David Irwin, Richard C. Jaeger:
An 11-Bit 8.6 GHz Direct Digital Synthesizer MMIC With 10-Bit Segmented Sine-Weighted DAC. 300-313 - Wei Liu, Wei (Ruth) Li, Peng Ren, Chinglong Lin, Shengdong Zhang, Yangyuan Wang:
A PVT Tolerant 10 to 500 MHz All-Digital Phase-Locked Loop With Coupled TDC and DCO. 314-321 - Nelson Lam, Bosco H. Leung:
Dynamic Quadrant Swapping Scheme Implemented in a Post Conversion Block for I, Q Mismatch Reduction in a DQPSK Receiver. 322-337 - Horng-Yuan Shih, Chien-Nan Kuo, Wei-Hsien Chen, Tzu-Yi Yang, Kai-Chenug Juang:
A 250 MHz 14 dB-NF 73 dB-Gain 82 dB-DR Analog Baseband Chain With Digital-Assisted DC-Offset Calibration for Ultra-Wideband. 338-350 - Mohamed Mobarak, Marvin Onabajo, José Silva-Martínez, Edgar Sánchez-Sinencio:
Attenuation-Predistortion Linearization of CMOS OTAs With Digital Correction of Process Variations in OTA-C Filter Applications. 351-367 - Yun-Shiang Shu, Junpei Kamiishi, Koji Tomioka, Koichi Hamashita, Bang-Sup Song:
LMS-Based Noise Leakage Calibration of Cascaded Continuous-Time Delta Sigma Modulators. 368-379 - Michael Chu, Philip Jacob, Jin Woo Kim, Mitchell R. LeRoy, Russell P. Kraft, John F. McDonald:
A 40 Gs/s Time Interleaved ADC Using SiGe BiCMOS Technology. 380-390 - Charles T. Peach, Un-Ku Moon, David J. Allstot:
An 11.1 mW 42 MS/s 10 b ADC With Two-Step Settling in 0.18 μ m CMOS. 391-400 - Ik Joon Chang, Sang Phill Park, Kaushik Roy:
Exploring Asynchronous Design Techniques for Process-Tolerant and Energy-Efficient Subthreshold Operation. 401-410 - Chun-Hao Liao, To-Ping Wang, Tzi-Dar Chiueh:
A 74.8 mW Soft-Output Detector IC for 8 , ˟, 8 Spatial-Multiplexing MIMO Communications. 411-421 - Cheng-Chi Wong, Ming-Wei Lai, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee:
Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture. 422-432 - Jian-Hao Lu, Shen-Iuan Liu:
A Merged CMOS Digital Near-End Crosstalk Canceller and Analog Equalizer for Multi-Lane Serial-Link Receivers. 433-446 - Eisse Mensink, Daniël Schinkel, Eric A. M. Klumperink, Ed van Tuijl, Bram Nauta:
Power Efficient Gigabit Communication Over Capacitively Driven RC-Limited On-Chip Interconnects. 447-457 - Pui Ying Or, Ka Nang Leung:
An Output-Capacitorless Low-Dropout Regulator With Direct Voltage-Spike Detection. 458-466 - Urs Frey, Jan Sedivý, Flavio Heer, René Pedron, Marco Ballini, Jan Mueller, Douglas J. Bakkum, Sadik Hafizovic, Francesca D. Faraci, Frauke Greve, Kay-Uwe Kirstein, Andreas Hierlemann:
Switch-Matrix-Based High-Density Microelectrode Array in CMOS Technology. 467-482 - Erick O. Torres, Gabriel A. Rincón-Mora:
A 0.7- μ m BiCMOS Electrostatic Energy-Harvesting System IC. 483-496 - Kwang-Il Oh, Lee-Sup Kim, Kwang-Il Park, Young-Hyun Jun, Joo-Sun Choi, Kinam Kim:
Correction on "A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme" [Aug 09 2222-2232]. 497 - Barbara Baggini, Philipp Basedau, Rolf Becker, Peter Bode, Farzad Esfahani, Willem H. Groeneweg, Markus Helfenstein, Alexander Lampe, Roland Ryter, Ralph Stephan:
Correction to "Baseband and Audio Mixed-Signal Front-End IC for GSM/EDGE Applications" [Jun 06 1364-1379]. 498
Volume 45, Number 3, March 2010
- Yueh-Hua Yu, Yong-Sian Yang, Yi-Jan Emery Chen:
A Compact Wideband CMOS Low Noise Amplifier With Gain Flatness Enhancement. 502-509 - Kuang-Wei Cheng, Karthik Natarajan, David J. Allstot:
A Current Reuse Quadrature GPS Receiver in 0.13 μ m CMOS. 510-523 - Masum Hossain, Anthony Chan Carusone:
5-10 Gb/s 70 mW Burst Mode AC Coupled Receiver in 90-nm CMOS. 524-537 - Ajay Balankutty, Shih-An Yu, Yiping Feng, Peter R. Kinget:
A 0.6-V Zero-IF/Low-IF Receiver With Integrated Fractional-N Synthesizer for 2.4-GHz ISM-Band Applications. 538-553 - Wei L. Chan, John R. Long:
A 58-65 GHz Neutralized CMOS Power Amplifier With PAE Above 10% at 1-V Supply. 554-564 - Mohamed El-Nozahi, Ahmed Amer, Joselyn Torres, Kamran Entesari, Edgar Sánchez-Sinencio:
High PSR Low Drop-Out Regulator With Feed-Forward Ripple Cancellation Technique. 565-577 - Song-Yu Yang, Wei-Zen Chen, Tai-You Lu:
A 7.1 mW, 10 GHz All Digital Frequency Synthesizer With Dynamically Reconfigured Digital Loop Filter in 90 nm CMOS Technology. 578-586 - Chi Fat Chan, Kong-Pang Pun, Ka Nang Leung, Jianping Guo, Lincoln Lai Kan Leung, Oliver Chiu-sing Choy:
A Low-Power Continuously-Calibrated Clock Recovery Circuit for UHF RFID EPC Class-1 Generation-2 Transponders. 587-599 - Poki Chen, Chun-Chi Chen, Yu-Han Peng, Kai-Ming Wang, Yu-Shin Wang:
A Time-Domain SAR Smart Temperature Sensor With Curvature Compensation and a 3σ Inaccuracy of -0.4°C ∼ +0.6°C Over a 0°C to 90°C Range. 600-609 - Yen-Chuan Huang, Tai-Cheng Lee:
A 0.02-mm 2 9-Bit 50-MS/s Cyclic ADC in 90-nm Digital CMOS Technology. 610-619 - Young-Ju Kim, Hee-Cheol Choi, Gil-Cho Ahn, Seung-Hoon Lee:
A 12 bit 50 MS/s CMOS Nyquist A/D Converter With a Fully Differential Class-AB Switched Op-Amp. 620-628 - Afshin Momtaz, Michael M. Green:
An 80 mW 40 Gb/s 7-Tap T/2-Spaced Feed-Forward Equalizer in 65 nm CMOS. 629-639 - Nigel Drego, Anantha P. Chandrakasan, Duane S. Boning:
All-Digital Circuits for Measurement of Spatial Variation in Digital Circuits. 640-651 - Seok-Hoon Kim, Hong-Yun Kim, Young-Jun Kim, Kyusik Chung, Donghyun Kim, Lee-Sup Kim:
A 116 fps/74 mW Heterogeneous 3D-Media Processor for 3-D Display Applications. 652-667 - Yu Pu, José de Jesus Pineda de Gyvez, Henk Corporaal, Yajun Ha:
An Ultra-Low-Energy Multi-Standard JPEG Co-Processor in 65 nm CMOS With Sub/Near Threshold Supply Voltage. 668-680
Volume 45, Number 4, April 2010
- Kazuo Matsukawa, Yosuke Mitani, Masao Takayama, Koji Obata, Shiro Dosho, Akira Matsuzawa:
A Fifth-Order Continuous-Time Delta-Sigma Modulator With Single-Opamp Resonator. 697-706 - Yuji Nakajima, Akemi Sakaguchi, Toshio Ohkido, Norihito Kato, Tetsuya Matsumoto, Michio Yotsuyanagi:
A Background Self-Calibrated 6b 2.7 GS/s ADC With Cascade-Calibrated Folding-Interpolating Architecture. 707-718 - Omid Rajaee, Tawfiq Musah, Nima Maghari, Seiji Takeuchi, Mitsuru Aniya, Koichi Hamashita, Un-Ku Moon:
Design of a 79 dB 80 MHz 8X-OSR Hybrid Delta-Sigma/Pipelined ADC. 719-730 - Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin:
A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure. 731-740 - Eric J. Carlson, Kai Strunz, Brian P. Otis:
A 20 mV Input Boost Converter With Efficient Digital Control for Thermoelectric Energy Harvesting. 741-750 - Dinesh Somasekhar, Balaji Srinivasan, Gunjan Pandya, Fatih Hamzaoglu, Muhammad M. Khellah, Tanay Karnik, Kevin Zhang:
Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process. 751-758 - Scott Hanson, Zhiyoong Foo, David T. Blaauw, Dennis Sylvester:
A 0.5 V Sub-Microwatt CMOS Image Sensor With Pulse-Width Modulation Read-Out. 759-767 - Heng-Yu Jian, Zhiwei Xu, Yi-Cheng Wu, Mau-Chung Frank Chang:
A Fractional- PLL for Multiband (0.8-6 GHz) Communications Using Binary-Weighted D/A Differentiator and Offset-Frequency Δ-Σ Modulator. 768-780 - Ping-Hsuan Hsieh, Jay Maxey, Chih-Kong Ken Yang:
A Phase-Selecting Digital Phase-Locked Loop With Bandwidth Tracking in 65-nm CMOS Technology. 781-792 - Wei-Hsiang Ma, Jerry C. Kao, Visvesh S. Sathe, Marios C. Papaefthymiou:
187 MHz Subthreshold-Supply Charge-Recovery FIR. 793-803 - Naveen Verma, Ali H. Shoeb, Jose L. Bohorquez, Joel L. Dawson, John V. Guttag, Anantha P. Chandrakasan:
A Micro-Power EEG Acquisition SoC With Integrated Feature Extraction Processor for a Chronic Seizure Detection System. 804-816 - John Keane, Xiaofei Wang, Devin Persaud, Chris H. Kim:
An All-In-One Silicon Odometer for Separately Monitoring HCI, BTI, and TDDB. 817-829 - Jianjun Yu, Fa Foster Dai, Richard C. Jaeger:
A 12-Bit Vernier Ring Time-to-Digital Converter in 0.13 μm CMOS Technology. 830-842 - Zhengya Zhang, Venkat Anantharam, Martin J. Wainwright, Borivoje Nikolic:
An Efficient 10GBASE-T Ethernet LDPC Decoder Design With Low Error Floors. 843-855 - Makoto Saen, Kenichi Osada, Yasuyuki Okuma, Kiichi Niitsu, Yasuhisa Shimazaki, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Itaru Nonomura, Naohiko Irie, Toshihiro Hattori, Atsushi Hasegawa, Tadahiro Kuroda:
3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link. 856-862 - Sarvesh H. Kulkarni, Zhanping Chen, Jun He, Lei Jiang, Brian Pedersen, Kevin Zhang:
A 4 kb Metal-Fuse OTP-ROM Macro Featuring a 2 V Programmable 1.37 μ m 2 1T1R Bit Cell in 32 nm High-k Metal-Gate CMOS. 863-868 - Riichiro Takemura, Takayuki Kawahara, Katsuya Miura, Hiroyuki Yamamoto, Jun Hayakawa, Nozomu Matsuzaki, Kazuo Ono, Michihiko Yamanouchi, Kenchi Ito, Hiromasa Takahashi, Shoji Ikeda, Haruhiro Hasegawa, Hideyuki Matsuoka, Hideo Ohno:
A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and '1'/'0' Dual-Array Equalized Reference Scheme. 869-879 - Ki-Whan Song, Jinyoung Kim, Jae-Man Yoon, Sua Kim, Huijung Kim, Hyun-Woo Chung, Hyungi Kim, Kanguk Kim, Hwan-Wook Park, Hyun Chul Kang, Nam-Kyun Tak, Dukha Park, Woo-Seop Kim, Yeong-Taek Lee, Yong Chul Oh, Gyo-Young Jin, Jei-Hwan Yoo, Donggun Park, Kyungseok Oh, Changhyun Kim, Young-Hyun Jun:
A 31 ns Random Cycle VCAT-Based 4F 2 DRAM With Manufacturability and Enhanced Cell Efficiency. 880-888 - Brian S. Leibowitz, Robert Palmer, John Poulton, Yohan Frans, Simon Li, John M. Wilson, Michael Bucher, Andrew M. Fuller, John G. Eyles, Marko Aleksic, Trey Greer, Nhat Nguyen:
A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling. 889-898 - Kangmin Hu, Tao Jiang, Jingguang Wang, Frank O'Mahony, Patrick Yin Chiang:
A 0.6 mW/Gb/s, 6.4-7.2 Gb/s Serial Link Receiver Using Local Injection-Locked Ring Oscillators in 90 nm CMOS. 899-908 - Huaide Wang, Jri Lee:
A 21-Gb/s 87-mW Transceiver With FFE/DFE/Analog Equalizer in 65-nm CMOS Technology. 909-920 - Haruya Ishizaki, Masayuki Mizuno:
A 0.2 mm 2 , 27 Mbps 3 mW ADC/FFT-Less FDM BAN Receiver With Energy Exploitation Capability. 921-927 - Toshiya Mitomo, Naoko Ono, Hiroaki Hoshino, Yoshiaki Yoshihara, Osamu Watanabe, Ichiro Seto:
A 77 GHz 90 nm CMOS Transceiver for FMCW Radar Applications. 928-937
Volume 45, Number 5, May 2010
- Xueyang Geng, Fa Foster Dai, J. David Irwin, Richard C. Jaeger:
24-Bit 5.0 GHz Direct Digital Synthesizer RFIC With Direct Digital Modulations in 0.13 μ m SiGe BiCMOS Technology. 944-954 - Ali Afsahi, Arya Behzad, Vikram Magoon, Lawrence E. Larson:
Linearized Dual-Band Power Amplifiers With Integrated Baluns in 65 nm CMOS for a 2 , ˟ , 2 802.11n MIMO WLAN SoC. 955-966 - Zhiyu Ru, Eric A. M. Klumperink, Carlos E. Saavedra, Bram Nauta:
A 300-800 MHz Tunable Filter and Linearized LNA Applied in a Low-Noise Harmonic-Rejection RF-Sampling Receiver. 967-978 - Francois Rivet, Yann Deval, Jean-Baptiste Bégueret, Dominique Dallet, Philippe Cathelin, Didier Belot:
The Experimental Demonstration of a SASP-Based Full Software Radio Receiver. 979-988 - Tobias D. Werth, Christoph Schmits, Ralf Wunderlich, Stefan Heinen:
An Active Feedback Interference Cancellation Technique for Blocker Filtering in RF Receiver Front-Ends. 989-997 - Usha Gogineni, Hongmei Li, Jesús A. del Alamo, Susan L. Sweeney, Jing Wang, Basanth Jagannathan:
Effect of Substrate Contact Shape and Placement on RF Characteristics of 45 nm Low Power CMOS Devices. 998-1006 - Michiel van Elzakker, Ed van Tuijl, Paul F. J. Geraedts, Daniël Schinkel, Eric A. M. Klumperink, Bram Nauta:
A 10-bit Charge-Redistribution ADC Consuming 1.9 μ W at 1 MS/s. 1007-1015 - Imran Ahmed, Jan Mulder, David A. Johns:
A Low-Power Capacitive Charge Pump Based Pipelined ADC. 1016-1027 - Yi-Chuan Tarn, Po-Chih Ku, Hsieh-Hung Hsieh, Liang-Hung Lu:
An Amorphous-Silicon Operational Amplifier and Its Application to a 4-Bit Digital-to-Analog Converter. 1028-1035 - Jinn-Shyan Wang, Chun-Yuan Cheng, Je-Ching Liu, Yu-Chia Liu, Yi-Ming Wang:
A Duty-Cycle-Distortion-Tolerant Half-Delay-Line Low-Power Fast-Lock-in All-Digital Delay-Locked Loop. 1036-1047 - Davide De Caro, Carlo Alberto Romani, Nicola Petra, Antonio G. M. Strollo, Claudio Parrella:
A 1.27 GHz, All-Digital Spread Spectrum Clock Generator/Synthesizer in 65 nm CMOS. 1048-1060 - Mohamed M. Elsayed, Edgar Sánchez-Sinencio:
A Low THD, Low Power, High Output-Swing Time-Mode-Based Tunable Oscillator Via Digital Harmonic-Cancellation Technique. 1061-1071 - Hsin-Ta Wu, Ruonan Han, Wuttichai Lerdsitsomboon, Changhua Cao, Kenneth K. O:
Multi-Level Amplitude Modulation of a 16.8-GHz Class-E Power Amplifier With Negative Resistance Enhanced Power Gain for 400-Mbps Data Transmission. 1072-1079 - Toshishige Shimamura, Hiroki Morimura, Satoshi Shigematsu, Mamoru Nakanishi, Katsuyuki Machida:
Capacitive-Sensing Circuit Technique for Image Quality Improvement on Fingerprint Sensor LSIs. 1080-1087
Volume 45, Number 6, June 2010
- Oleksiy Tyshchenko, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune, Hisakatsu Yamaguchi, Junji Ogawa:
A 5-Gb/s ADC-Based Feed-Forward CDR in 65 nm CMOS. 1091-1098 - Ali Agah, Katelijn Vleugels, Peter B. Griffin, Mostafa Ronaghi, James D. Plummer, Bruce A. Wooley:
A High-Resolution Low-Power Incremental Sigma Delta ADC With Extended Range for Biosensor Arrays. 1099-1110 - Yan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti:
A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS. 1111-1121 - Cho-Ying Lu, Jose Fabian Silva-Rivas, Praveena Kode, José Silva-Martínez, Sebastian Hoyos:
A Sixth-Order 200 MHz IF Bandpass Sigma-Delta Modulator With Over 68 dB SNDR in 10 MHz Bandwidth. 1122-1136 - Wei-Hao Chiu, Yu-Hsiang Huang, Tsung-Hsien Lin:
A Dynamic Phase Error Compensation Technique for Fast-Locking Phase-Locked Loops. 1137-1149 - Yusuke Tokunaga, Shiro Sakiyama, Akinori Matsumoto, Shiro Dosho:
An On-Chip CMOS Relaxation Oscillator With Voltage Averaging Feedback. 1150-1158 - Pieter Crombez, Geert Van der Plas, Michiel Steyaert, Jan Craninckx:
A Single-Bit 500 kHz-10 MHz Multimode Power-Performance Scalable 83-to-67 dB DR CTΔΣ for SDR in 90 nm Digital CMOS. 1159-1171 - Jun Cao, Bo Zhang, Ullas Singh, Delong Cui, Anand Vasani, Adesh Garg, Wei Zhang, Namik Kocaman, Deyi Pi, Bharath Raghavan, Hui Pan, Ichiro Fujimori, Afshin Momtaz:
A 500 mW ADC-Based CMOS AFE With Digital Calibration for 10 Gb/s Serial Links Over KR-Backplane and Multimode Fiber. 1172-1185 - Byungsub Kim, Vladimir Stojanovic:
An Energy-Efficient Equalized Transceiver for RC-Dominant Channels. 1186-1197 - Lynn Bos, Gerd Vandersteen, Pieter Rombouts, Arnd Geis, Alonso Morgado, Yves Rolain, Geert Van der Plas, Julien Ryckaert:
Multirate Cascaded Discrete-Time Low-Pass ΔΣ Modulator for GSM/Bluetooth/UMTS. 1198-1208 - Patrick P. Mercier, Manish Bhardwaj, Denis C. Daly, Anantha P. Chandrakasan:
A Low-Voltage Energy-Sampling IR-UWB Digital Baseband Employing Quadratic Correlation. 1209-1219 - Bart R. Zeydel, Dursun Baran, Vojin G. Oklobdzija:
Energy-Efficient Design Methodologies: High-Performance VLSI Adders. 1220-1233 - Meng-Fan Chang, Jui-Jen Wu, Kuang-Ting Chen, Yung-Chi Chen, Yen-Hui Chen, Robin Lee, Hung-Jen Liao, Hiroyuki Yamauchi:
A Differential Data-Aware Power-Supplied (D 2 AP) 8T SRAM Cell With Expanded Write/Read Stabilities for Lower VDDmin Applications. 1234-1245 - Man Kay Law, Amine Bermak, Howard C. Luong:
A Sub- μ W Embedded CMOS Temperature Sensor for RFID Food Monitoring Application. 1246-1255 - Hiva Hedayati, Waleed Khalil, Bertan Bakkaloglu:
Correction to "A 1 MHz Bandwidth, 6 GHz 0.18 μ m CMOS Type-I Delta Sigma Fractional-N Synthesizer for WiMAX Applications" [Dec 09 3244-3252]. 1256
Volume 45, Number 7, July 2010
- Christophe De Roover, Michiel Steyaert:
Energy Supply and ULP Detection Circuits for an RFID Localization System in 130 nm CMOS. 1273-1285 - Alexandre Siligaris, Yasuhiro Hamada, Christopher Mounet, Christine Raynaud, Baudouin Martineau, Nicolas Deparis, Nathalie Rolland, Muneo Fukaishi, Pierre Vincent:
A 60 GHz Power Amplifier With 14.5 dBm Saturation Power and 25% Peak PAE in CMOS 65 nm SOI. 1286-1294 - Stefano Dal Toso, Andrea Bevilacqua, Marc Tiebout, Nicola Da Dalt, Andrea Gerosa, Andrea Neviani:
A 0.06 mm 2 11 mW Local Oscillator for the GSM Standard in 65 nm CMOS. 1295-1304 - Salvatore Drago, Domine Leenaerts, Bram Nauta, Fabio Sebastiano, Kofi A. A. Makinwa, Lucien J. Breems:
A 200 μA Duty-Cycled PLL for Wireless Sensor Nodes in 65 nm CMOS. 1305-1315 - Le Ye, Huailin Liao, Fei Song, Jiang Chen, Chen Li, Jinshu Zhao, Ruiqiang Liu, Chuan Wang, Congyin Shi, Junhua Liu, Ru Huang, Yangyuan Wang:
A Single-Chip CMOS UHF RFID Reader Transceiver for Chinese Mobile Applications. 1316-1329 - Salam Elahmadi, Matthias Bussmann, Dalius Baranauskas, Denis Zelenin, Jomo Edwards, Kelvin Tran, Lloyd F. Linder, Christopher A. Gill, Harry Tan, Devin Ng, Siraj El-Ahmadi:
An 11.1 Gbps Analog PRML Receiver for Electronic Dispersion Compensation of Fiber Optic Communications. 1330-1344 - Gerald Zach, Milos Davidovic, Horst Zimmermann:
A 16 , ˟ 16 Pixel Distance Sensor With In-Pixel Circuitry That Tolerates 150 klx of Ambient Light. 1345-1353 - Oreste Sgrott, Daniel Mosconi, Matteo Perenzoni, Gianmaria Pedretti, Lorenzo Gonzo, David Stoppa:
A 134-Pixel CMOS Sensor for Combined Time-of-Flight and Optical Triangulation 3-D Imaging. 1354-1364 - Shanthi Pavan, Prabu Sankar:
Power Reduction in Continuous-Time Delta-Sigma Modulators Using the Assisted Opamp Technique. 1365-1379 - Wei Xiong, Yang Guo, Ute Zschieschang, Hagen Klauk, Boris Murmann:
A 3-V, 6-Bit C-2C Digital-to-Analog Converter Using Complementary Organic Thin-Film Transistors on Glass. 1380-1388 - Benno Krabbenborg, Marco Berkhout:
Closed-Loop Class-D Amplifier With Nonlinear Loop Integrators. 1389-1398 - Joo-Young Kim, Junyoung Park, Seungjin Lee, Minsu Kim, Jinwook Oh, Hoi-Jun Yoo:
A 118.4 GB/s Multi-Casting Network-on-Chip With Hierarchical Star-Ring Combined Topology for Real-Time Object Recognition. 1399-1409 - Paolo Madoglio, Ashoke Ravi, Luis Cuellar, Stefano Pellerano, Parmoon Seddighrad, Ismael Lomeli, Yorgos Palaskas:
A 2.5-GHz, 6.9-mW, 45-nm-LP CMOS, ΔΣ Modulator Based on Standard Cell Design With Time-Interleaving. 1410-1420
Volume 45, Number 8, August 2010
- Minsheng Wang, Xicheng Jiang, Jungwoo Song, Todd Brooks:
A 120 dB Dynamic Range 400 mW Class-D Speaker Driver With Fourth-Order PWM Modulator. 1427-1435 - Yoshinori Kusuda:
Auto Correction Feedback for Ripple Suppression in a Chopper Amplifier. 1436-1445 - Patrick Y. Wu, Sam Y. S. Tsui, Philip K. T. Mok:
Area- and Power-Efficient Monolithic Buck Converters With Pseudo-Type III Compensation. 1446-1455 - David Gubbins, Bumha Lee, Pavan Kumar Hanumolu, Un-Ku Moon:
Continuous-Time Input Pipeline ADCs. 1456-1468 - Jing Yang, Thura Lin Naing, Robert W. Brodersen:
A 1 GS/s 6 Bit 6.7 mW Successive Approximation ADC Using Asynchronous Processing. 1469-1478 - Mohammad Ranjbar, Arash Mehrabi, Omid Oliaei, Frederic Carrez:
A 3.1 mW Continuous-Time ΔΣ Modulator With 5-Bit Successive Approximation Quantizer for WCDMA. 1479-1491 - Dennis Michael Fischette, Alvin Leng Sun Loke, Richard Joseph DeSantis, Gerry R. Talbot:
An Embedded All-Digital Circuit to Measure PLL Response. 1492-1503 - Luca Vercesi, Antonio Liscidini, Rinaldo Castello:
Two-Dimensions Vernier Time-to-Digital Converter. 1504-1512 - Liangge Xu, Saska Lindfors, Kari Stadius, Jussi Ryynänen:
A 2.4-GHz Low-Power All-Digital Phase-Locked Loop. 1513-1521 - Tzu-Chien Hsueh, Pin-En Su, Sudhakar Pamarti:
A 3 , ˟, 3.8 Gb/s Four-Wire High Speed I/O Link Based on CDMA-Like Crosstalk Cancellation. 1522-1532 - Mahmoud Reza Ahmadi, Amir Amirkhany, Ramesh Harjani:
A 5 Gbps 0.13 μ m CMOS Pilot-Based Clock and Data Recovery Scheme for High-Speed Links. 1533-1541 - Behzad Razavi:
Cognitive Radio Design Challenges and Techniques. 1542-1553 - Eunyoung Seok, Dongha Shim, Chuying Mao, Ruonan Han, Swaminathan Sankaran, Changhua Cao, Wojciech Knap, Kenneth K. O:
Progress and Challenges Towards Terahertz CMOS Integrated Circuits. 1554-1564 - Enrico Monaco, Massimo Pozzoni, Francesco Svelto, Andrea Mazzanti:
Injection-Locked CMOS Frequency Doublers for μ -Wave and mm-Wave Applications. 1565-1574 - Burak Çatli, Mona Mostafa Hella:
Triple-Push Operation for Combined Oscillation/Divison Functionality in Millimeter-Wave Frequency Synthesizers. 1575-1589 - Himanshu Khatri, Prasad S. Gudem, Lawrence E. Larson:
An Active Transmitter Leakage Suppression Technique for CMOS SAW-Less CDMA Receivers. 1590-1601 - Dae Hyun Kwon, Hao Li, Yuchun Chang, Richard Tseng, Yun Chiu:
Digitally Equalized CMOS Transmitter Front-End With Integrated Power Amplifier. 1602-1614 - Davide Rossi, Fabio Campi, Simone Spolzino, Stefano Pucillo, Roberto Guerrieri:
A Heterogeneous Digital Signal Processor for Dynamically Reconfigurable Computing. 1615-1626 - Stefano Pellerano, Javier Alvarado Jr., Yorgos Palaskas:
A mm-Wave Power-Harvesting RFID Tag in 90 nm CMOS. 1627-1637 - Kyehyung Lee, Matthew R. Miller, Gabor C. Temes:
Correction to "An 8.1 mW, 82 dB Delta-Sigma ADC With 1.9 MHz BW and - 98 dB THD" [Aug 09 2202-2211]. 1638
Volume 45, Number 9, September 2010
- Klaus Schmalz, Wolfgang Winkler, Johannes Borngräber, Wojciech Debski, Bernd Heinemann, Christoph Scheytt:
A Subharmonic Receiver in SiGe Technology for 122 ~ GHz Sensor Applications. 1644-1656 - Sabbir A. Osmany, Frank Herzel, Christoph Scheytt:
An Integrated 0.6-4.6 GHz, 5-7 GHz, 10-14 GHz, and 20-28 GHz Frequency Synthesizer for Software-Defined Radio Applications. 1657-1668 - Xueyang Geng, Fa Foster Dai:
An X-Band Transformer-Coupled Varactor-Less Quadrature Current-Controlled Oscillator in 0.18 μm SiGe BiCMOS Technology. 1669-1677 - Holger Rücker, Bernd Heinemann, Wolfgang Winkler, Rainer Barth, Johannes Borngräber, Jürgen Drews, Gerhard G. Fischer, Alexander Fox, Thomas Grabolla, Ulrich Haak, Dieter Knoll, Falk Korndörfer, Andreas Mai, Steffen Marschmeyer, Peter Schley, Detlef Schmidt, J. Schmidt, Markus Andreas Schubert, K. Schulz, Bernd Tillack, Dirk Wolansky, Yuji Yamamoto:
A 0.13 µm SiGe BiCMOS Technology Featuring fT/fmax of 240/330 GHz and Gate Delays Below 3 ps. 1678-1686 - Hans Tuinhout, Nicole Wils, Pietro Andricciola:
Parametric Mismatch Characterization for Mixed-Signal Technologies. 1687-1696 - Yikun Yu, Peter G. M. Baltus, Anton de Graauw, Edwin van der Heijden, Cicero S. Vaucher, Arthur H. M. van Roermund:
A 60 GHz Phase Shifter Integrated With LNA and PA in 65 nm CMOS for Phased Array Systems. 1697-1709 - Marika Tedeschi, Antonio Liscidini, Rinaldo Castello:
Low-Power Quadrature Receivers for ZigBee (IEEE 802.15.4) Applications. 1710-1719 - Kai Kang, Fujiang Lin, Duy-Dong Pham, James Brinkhoff, Chun-Huat Heng, Yongxin Guo, Xiaojun Yuan:
A 60-GHz OOK Receiver With an On-Chip Antenna in 90 nm CMOS. 1720-1731 - Zhiyu Ru, Eric A. M. Klumperink, Bram Nauta:
Discrete-Time Mixing Receiver Architecture for RF-Sampling Software-Defined Radio. 1732-1745 - Soheil Radiom, Majid Baghaei Nejad, Karim Aghdam, Guy A. E. Vandenbosch, Li-Rong Zheng, Georges G. E. Gielen:
Far-Field On-Chip Antennas Monolithically Integrated in a Wireless-Powered 5.8-GHz Downlink/UWB Uplink RFID Tag in 0.18-μm Standard CMOS. 1746-1758 - James Ayers, Kartikeya Mayaram, Terri S. Fiez:
An Ultralow-Power Receiver for Wireless Sensor Networks. 1759-1769 - Alberto Pirola, Antonio Liscidini, Rinaldo Castello:
Current-Mode, WCDMA Channel Filter With In-Band Noise Shaping. 1770-1780 - Arindam Basu, Stephen Brink, Craig Schlottmann, Shubha Ramakrishnan, Csaba Petre, Scott Koziol, I. Faik Baskaya, Christopher M. Twigg, Paul E. Hasler:
A Floating-Gate-Based Field-Programmable Analog Array. 1781-1794 - Cho-Ying Lu, Marvin Onabajo, Venkata Gadde, Yung-Chung Lo, Hsien-Pu Chen, Vijayaramalingam Periasamy, José Silva-Martínez:
A 25 MHz Bandwidth 5th-Order Continuous-Time Low-Pass Sigma-Delta Modulator With 67.7 dB SNDR Using Time-Domain Quantization and Feedback. 1795-1808 - Xiang Gao, Eric A. M. Klumperink, Gerard Socci, Mounir Bohsali, Bram Nauta:
Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector. 1809-1821 - Guansheng Li, Ehsan Afshari:
A Low-Phase-Noise Multi-Phase Oscillator Based on Left-Handed LC-Ring. 1822-1833 - Wooram Lee, Ehsan Afshari:
Distributed Parametric Resonator: A Passive CMOS Frequency Divider. 1834-1844 - Hong Chang Yeoh, Jae-Hun Jung, Yun-Hwan Jung, Kwang-Hyun Baek:
A 1.3-GHz 350-mW Hybrid Direct Digital Frequency Synthesizer in 90-nm CMOS. 1845-1855 - Nobutaro Shibata, Mayumi Watanabe, Hideomi Okiyama:
A High-Speed Low-Power Multi-VDD CMOS/SIMOX SRAM With LV-TTL Level Input/Output Pins - Write/Read Assist Techniques for 1-V Operated Memory Cells. 1856-1869 - Shahrzad Naraghi, Matthew Courcy, Michael P. Flynn:
A 9-bit, 14 μW and 0.06 mm 2 Pulse Position Modulation ADC in 90 nm Digital CMOS. 1870-1880 - Yong-Joon Jeon, Jinyong Jeon, Young-Suk Son, Jin Huh, Gyu-Hyeong Cho:
A High-Speed Current-Mode Data Driver With Push-Pull Transient Current Feedforward for Full-HD AMOLED Displays. 1881-1895 - Jianping Guo, Ka Nang Leung:
A 6- μ W Chip-Area-Efficient Output-Capacitorless LDO in 90-nm CMOS Technology. 1896-1905 - Xiwen Zhang, Hoi Lee:
An Efficiency-Enhanced Auto-Reconfigurable 2 ˟ /3 ˟ SC Charge Pump for Transcutaneous Power Transmission. 1906-1922 - Wai Pan Chan, Bhusana Premanode, Christofer Toumazou:
An Integrated ISFETs Instrumentation System in Standard CMOS Technology. 1923-1934 - Jongwoo Lee, Hyo-Gyuem Rhew, Daryl R. Kipke, Michael P. Flynn:
A 64 Channel Programmable Closed-Loop Neurostimulator With 8 Channel Neural Amplifier and Logarithmic ADC. 1935-1945 - Kuanfu Chen, Zhi Yang, Linh Hoang, James D. Weiland, Mark S. Humayun, Wentai Liu:
An Integrated 256-Channel Epiretinal Prosthesis. 1946-1956
Volume 45, Number 10, October 2010
- Stefan Koch, Marc Guthoerl, Ingmar Kallfass, Arnulf Leuther, Shin Saito:
A 120-145 GHz Heterodyne Receiver Chipset Utilizing the 140 GHz Atmospheric Window for Passive Millimeter-Wave Imaging Applications. 1961-1967 - Ioannis Sarkas, Sean T. Nicolson, Alexander Tomkins, Ekaterina Laskin, Pascal Chevalier, Bernard Sautreuil, Sorin P. Voinigescu:
An 18-Gb/s, Direct QPSK Modulation SiGe BiCMOS Transceiver for Last Mile Links in the 70-80 GHz Band. 1968-1980 - Alexander Tomkins, Patrice Garcia, Sorin P. Voinigescu:
A Passive W-Band Imaging Receiver in 65-nm Bulk CMOS. 1981-1991 - Matt D'Amore, Cedric Monier, Steven Taiyu Lin, Bert K. Oyama, Dennis W. Scott, Eric N. Kaneshiro, Ping-Chih Chang, Kenneth F. Sato, Alex Niemi, Linh Dang, Abdullah Cavus, Augusto Gutierrez-Aitken, Aaron K. Oki:
A 0.25 μ m InP DHBT 200 GHz+ Static Frequency Divider. 1992-2002 - Mehmet Uzunkol, Gabriel M. Rebeiz:
A Low-Loss 50-70 GHz SPDT Switch in 90 nm CMOS. 2003-2007 - Walter Ciccognani, Ernesto Limiti, Patrick E. Longhi, Michel Renvoise:
MMIC LNAs for Radioastronomy Applications Using Advanced Industrial 70 nm Metamorphic Technology. 2008-2015 - Nikola Nedovic, Anders Kristensson, Samir Parikh, Subodh M. Reddy, Scott McLeod, Nestoras Tzartzanis, Kouichi Kanda, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Takayuki Shibasaki, Yasumoto Tomita, Takayuki Hamada, Mariko Sugawara, Tadashi Ikeuchi, Naoki Kuwata, Hirotaka Tamura, Junji Ogawa, William W. Walker:
A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS. 2016-2029 - Shu-Hsien Liao, Yuanxun Ethan Wang:
High Efficiency WCDMA Power Amplifier With Pulsed Load Modulation (PLM). 2030-2037 - Kyunggon Choi, Min-Su Kim, Hyungchul Kim, Sung-Chan Jung, Jaeyong Cho, Sungchul Yoo, Yong Hwan Kim, Hyungmo Yoo, Youngoo Yang:
A Highly Linear Two-Stage Amplifier Integrated Circuit Using InGaP/GaAs HBT. 2038-2043 - Michiel A. P. Pertijs, Wilko J. Kindt:
A 140 dB-CMRR Current-Feedback Instrumentation Amplifier Employing Ping-Pong Auto-Zeroing and Chopping. 2044-2056 - Yoichi Yoshida, Koichi Nose, Yoshihiro Nakagawa, Koichiro Noguchi, Yasuhiro Morita, Masamoto Tago, Masayuki Mizuno, Tadahiro Kuroda:
An Inductive-Coupling DC Voltage Transceiver for Highly Parallel Wafer-Level Testing. 2057-2065 - Yao-Hong Liu, Tsung-Hsien Lin:
A Delta-Sigma Pulse-Width Digitization Technique for Super-Regenerative Receivers. 2066-2079 - Bob Verbruggen, Jan Craninckx, Maarten Kuijk, Piet Wambacq, Geert Van der Plas:
A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS. 2080-2090 - Chi Ho Law, Paul J. Hurst, Stephen H. Lewis:
A Four-Channel Time-Interleaved ADC With Digital Calibration of Interchannel Timing and Memory Errors. 2091-2103 - Andrea Mazzanti, Mohammad B. Vahidfar, Marco Sosio, Francesco Svelto:
A Low Phase-Noise Multi-Phase LO Generator for Wideband Demodulators Based on Reconfigurable Sub-Harmonic Mixers. 2104-2115 - Jonathan Borremans, Kameswaran Vengattaramane, Vito Giannini, Björn Debaillie, Wim Van Thillo, Jan Craninckx:
A 86 MHz-12 GHz Digital-Intensive PLL for Software-Defined Radios, Using a 6 fJ/Step TDC in 40 nm Digital CMOS. 2116-2129 - Dong Jiao, Jie Gu, Chris H. Kim:
Circuit Design and Modeling Techniques for Enhancing the Clock-Data Compensation Effect Under Resonant Supply Noise. 2130-2141 - Meng-Fan Chang, Shu-Meng Yang, Chih-Wei Liang, Chih-Chyuang Chiang, Pi-Feng Chiu, Ku-Feng Lin:
Noise-Immune Embedded NAND-ROM Using a Dynamic Split Source-Line Scheme for VDDmin and Speed Improvements. 2142-2155 - Teruyoshi Hatanaka, Ryoji Yajima, Takeshi Horiuchi, Shouyu Wang, Xizhen Zhang, Mitsue Takahashi, Shigeki Sakai, Ken Takeuchi:
Ferroelectric (Fe)-NAND Flash Memory With Batch Write Algorithm and Smart Data Store to the Nonvolatile Page Buffer for Data Center Application High-Speed and Highly Reliable Enterprise Solid-State Drives. 2156-2164 - Ki-Tae Park, Youngsun Song, Myounggon Kang, Sungsoo Lee, Youngho Lim, Kang-Deog Suh, Chilhee Chung:
Dynamic Vpass Controlled Program Scheme and Optimized Erase Vth Control for High Program Inhibition in MLC NAND Flash Memories. 2165-2172 - Byung-Do Yang:
A Low-Power SRAM Using Bit-Line Charge-Recycling for Read and Write Operations. 2173-2183 - Ockgoo Lee, Jeonghu Han, Kyu Hwan An, Dong Ho Lee, Kun-Seok Lee, Songcheol Hong, Chang-Ho Lee:
A Charging Acceleration Technique for Highly Efficient Cascode Class-E CMOS Power Amplifiers. 2184-2197 - Daniel J. Yeager, Fan Zhang, Azin Zarrasvand, Nicole T. George, Thomas Daniel, Brian P. Otis:
A 9 μ A, Addressable Gen2 Sensor Tag for Biosignal Acquisition. 2198-2209 - Michael Chu, Philip Jacob, Jin Woo Kim, Mitchell R. LeRoy, Russell P. Kraft, John F. McDonald:
Correction to "A 40 GS/s Time Interleaved ADC Using SiGe BiCMOS Technology". 2210 - Man Kay Law, Amine Bermak, Howard C. Luong:
Correction to "A Sub- μ W Embedded CMOS Temperature Sensor for RFID Food Monitoring Application" [Jun 10 1246-1255]. 2210 - Wooram Lee, Ehsan Afshari:
Correction to "Distributed Parametric Resonator: A Passive CMOS Frequency Divider" [Sep 10 1834-1844]. 2210
Volume 45, Number 11, November 2010
- Yung-Hui Chung, Jieh-Tsorng Wu:
A CMOS 6-mW 10-bit 100-MS/s Two-Step ADC. 2217-2226 - Yu-Huei Lee, Yao-Yi Yang, Ke-Horng Chen, Ying-Hsi Lin, Shih-Jung Wang, Kuo-Lin Zheng, Po-Fung Chen, Chun-Yu Hsieh, Yu-Zhou Ke, Yi-Kuang Chen, Chen-Chih Huang:
A DVS Embedded Power Management for High Efficiency Integrated SoC in UWB System. 2227-2238 - Chun-Yen Tseng, Li-Wen Wang, Po-Chiun Huang:
An Integrated Linear Regulator With Fast Output Voltage Transition for Dual-Supply SRAMs in DVFS Systems. 2239-2249 - Ha Le-Thai, Huy-Hieu Nguyen, Hoai-Nam Nguyen, Hong-Soon Cho, Jeong-Seon Lee, Sang-Gug Lee:
An IF Bandpass Filter Based on a Low Distortion Transconductor. 2250-2261 - Richard Tseng, Hao Li, Dae Hyun Kwon, Yun Chiu, Ada S. Y. Poon:
A Four-Channel Beamforming Down-Converter in 90-nm CMOS Utilizing Phase-Oversampling. 2262-2272 - Ting-Yueh Chin, Sheng-Fuh Chang, Jen-Chieh Wu, Chia-Chan Chang:
A 25-GHz Compact Low-Power Phased-Array Receiver With Continuous Beam Steering in CMOS Technology. 2273-2282 - Yi-Da Wu, Chang-Ming Lai, Chao-Cheng Lee, Po-Chiun Huang:
A Quantization Error Minimization Method Using DDS-DAC for Wideband Fractional-N Frequency Synthesizer. 2283-2291 - Tee Hui Teo, Xinbo Qian, Pradeep Kumar Gopalakrishnan, Yee Shan Hwan, Kuruveettil Haridas, Chin Yann Pang, Hyouk-Kyu Cha, Minkyu Je:
A 700- μ W Wireless Sensor Node SoC for Continuous Real-Time Health Monitoring. 2292-2299 - Deok-Soo Kim, Heesoo Song, Taeho Kim, Suhwan Kim, Deog-Kyoon Jeong:
A 0.3-1.4 GHz All-Digital Fractional-N PLL With Adaptive Loop Gain Controller. 2300-2311 - Masafumi Onouchi, Yusuke Kanno, Makoto Saen, Shigenobu Komatsu, Yoshihiko Yasu, Koichiro Ishibashi:
A Low-Power Wide-Range Clock Synchronizer With Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS. 2312-2320 - Tse-Wei Chen, Chi-Sun Tang, Sung-Fang Tsai, Chen-Han Tsai, Shao-Yi Chien, Liang-Gee Chen:
Tera-Scale Performance Machine Learning SoC (MLSoC) With Dual Stream Processor Architecture for Multimedia Content Analysis. 2321-2329 - Yi-Min Lin, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
A 26.9 K 314.5 Mb/s Soft (32400, 32208) BCH Decoder Chip for DVB-S2 System. 2330-2340 - Atsushi Kawasumi, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Yuki Fujimura, Tomoaki Yabe:
A Low-Supply-Voltage-Operation SRAM With HCI Trimmed Sense Amplifiers. 2341-2347 - Akira Kotabe, Yoshimitsu Yanagawa, Satoru Akiyama, Tomonori Sekiguchi:
0.5-V Low- V T CMOS Preamplifier for Low-Power and High-Speed Gigabit-DRAM Arrays. 2348-2355 - Long Yan, Jerald Yoo, Binhee Kim, Hoi-Jun Yoo:
A 0.5-μ Vrms 12-μ W Wirelessly Powered Patch-Type Healthcare Sensor for Wearable Body Sensor Network. 2356-2365 - Seulki Lee, Kiseok Song, Jerald Yoo, Hoi-Jun Yoo:
A Low-Energy Inductive Coupling Transceiver With Cm-Range 50-Mbps Data Communication in Mobile Device Applications. 2366-2374 - Arnd Geis, Julien Ryckaert, Lynn Bos, Gerd Vandersteen, Yves Rolain, Jan Craninckx:
A 0.5 mm 2 Power-Scalable 0.5-3.8-GHz CMOS DT-SDR Receiver With Second-Order RF Band-Pass Sampler. 2375-2387 - Murli U. Nair, Yuanjin Zheng, Chyuen-Wei Ang, Yong Lian, Xiaojun Yuan, Chun-Huat Heng:
A Low SIR Impulse-UWB Transceiver Utilizing Chirp FSK in 0.18 μm CMOS. 2388-2403 - Jun Yin, Jun Yi, Matthew K. Law, Yunxiao Ling, Man Chiu Lee, Kwok Ping Ng, Bo Gao, Howard C. Luong, Amine Bermak, Mansun Chan, Wing-Hung Ki, Chi-Ying Tsui, Matthew M. F. Yuen:
A System-on-Chip EPC Gen-2 Passive UHF RFID Tag With Embedded Temperature Sensor. 2404-2420 - Ke-Chung Wu, Jri Lee:
A 2 , ˟, 25-Gb/s Receiver With 2: 5 DMUX for 100-Gb/s Ethernet. 2421-2432 - Koji Takinami, Rich Walsworth:
Phase Error Calibration Technique for Rotary Traveling Wave Oscillators. 2433-2444 - San-Jeow Cheng, Lin Qiu, Yuanjin Zheng, Chun-Huat Heng:
50-250 MHz ΔΣ DLL for Clock Synchronization. 2445-2456 - Zhiming Deng, Ali M. Niknejad:
The Speed-Power Trade-Off in the Design of CMOS True-Single-Phase-Clock Dividers. 2457-2465 - Marco Ho, Ka Nang Leung, Ki-Leung Mak:
A Low-Power Fast-Transient 90-nm Low-Dropout Regulator With Multiple Small-Gain Stages. 2466-2475 - Chih-Ting Yeh, Ming-Dou Ker:
Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection. 2476-2486
Volume 45, Number 12, December 2010
- Mahdi Kashmiri, Michiel A. P. Pertijs, Kofi A. A. Makinwa:
A Thermal-Diffusivity-Based Frequency Reference in Standard CMOS With an Absolute Inaccuracy of ±0.1% From - 55°C to 125°C. 2510-2520 - Massimiliano Belloni, Edoardo Bonizzoni, Andrea Fornasari, Franco Maloberti:
A Micropower Chopper - CDS Operational Amplifier. 2521-2529 - Alex Lollio, Giacomino Bollati, Rinaldo Castello:
A Class-G Headphone Amplifier in 65 nm CMOS Technology. 2530-2542 - Patrick Y. Wu, Philip K. T. Mok:
A Two-Phase Switching Hybrid Supply Modulator for RF Power Amplifiers With 9% Efficiency Improvement. 2543-2556 - Yogesh K. Ramadass, Ayman A. Fayed, Anantha P. Chandrakasan:
A Fully-Integrated Switched-Capacitor Step-Down DC-DC Converter With Digital Capacitance Modulation in 45 nm CMOS. 2557-2565 - Michael H. Perrott, Sudhakar Pamarti, Eric G. Hoffman, Fred S. Lee, Shouvik Mukherjee, Cathy Lee, Vadim Tsinker, Sathi Perumal, Benjamin Soto, Niveditha Arumugam, Bruno W. Garlepp:
A Low Area, Switched-Resistor Based Fractional-N Synthesizer Applied to a MEMS-Based Programmable Oscillator. 2566-2581 - Takashi Tokairin, Mitsuji Okada, Masaki Kitsunezuka, Tadashi Maeda, Muneo Fukaishi:
A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter. 2582-2590 - Fabio Sebastiano, Lucien J. Breems, Kofi A. A. Makinwa, Salvatore Drago, Domine Leenaerts, Bram Nauta:
A 1.2-V 10-μ W NPN-Based Temperature Sensor in 65-nm CMOS With an Inaccuracy of 0.2°C (3 Sigma ) From - 70°C to 125°C. 2591-2601 - Ahmed M. A. Ali, Andrew S. Morgan, Christopher Dillon, Greg Patterson, Scott Puckett, Paritosh Bhoraskar, Hüseyin Dinc, Mike Hensley, Russell Stop, Scott Bardsley, David Lattimore, Jeff Bray, Carroll Speir, Robert Sneed:
A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background Calibration. 2602-2612 - Robert Payne, Marco Corsi, David Smith, Tien-Ling Hsieh, Scott Kaylor:
A 16-Bit 100 to 160 MS/s SiGe BiCMOS Pipelined ADC With 100 dBFS SFDR. 2613-2622 - Benjamin P. Hershberg, Skyler Weaver, Un-Ku Moon:
Design of a Split-CLS Pipelined ADC With Full Signal Swing Using an Accurate But Fractional Signal Swing Opamp. 2623-2633 - Gerry Taylor, Ian Galton:
A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC. 2634-2646 - Christopher P. Hurrell, Colin Lyden, David Laing, Derek Hummerston, Mark Vickery:
An 18 b 12.5 MS/s ADC With 93 dB SNR. 2647-2654 - Kenichi Kawasaki, Yoshiyuki Akiyama, Kenji Komori, Masahiro Uno, Hidenori Takeuchi, Tomoari Itagaki, Yasufumi Hino, Yoshinobu Kawasaki, Katsuhisa Ito, Ali Hajimiri:
A Millimeter-Wave Intra-Connect Solution. 2655-2666 - Amin Arbabian, Steven Callender, Shinwon Kang, Bagher Afshar, Jun-Chau Chien, Ali M. Niknejad:
A 90 GHz Hybrid Switching Pulsed-Transmitter for Medical Imaging. 2667-2681 - Wei L. Chan, John R. Long:
A 60-GHz Band 2 , ˟, 2 Phased-Array Transmitter in 65-nm CMOS. 2682-2695 - Caroline Andrews, Alyosha C. Molnar:
A Passive Mixer-First Receiver With Digitally Controlled and Widely Tunable RF Interface. 2696-2708 - Hua Wang, Constantine Sideris, Ali Hajimiri:
A CMOS Broadband Power Amplifier With a Transformer-Based High-Order Output Matching Network. 2709-2722 - Enrico Temporiti, Colin Weltin-Wu, Daniele Baldi, Marco Cusmai, Francesco Svelto:
A 3.5 GHz Wideband ADPLL With Fractional Spur Suppression Through TDC Dithering and Feedforward Compensation. 2723-2736 - Luca Fanori, Antonio Liscidini, Rinaldo Castello:
Capacitive Degeneration in LC-Tank Oscillator for DCO Fine-Frequency Tuning. 2737-2745 - Jri Lee, Yi-An Li, Meng-Hsiung Hung, Shih-Jou Huang:
A Fully-Integrated 77-GHz FMCW Radar Transceiver in 65-nm CMOS Technology. 2746-2756 - Alberto Valdes-Garcia, Sean T. Nicolson, Jie-Wei Lai, Arun Natarajan, Ping-Yu Chen, Scott K. Reynolds, Jing-Hong Conan Zhan, Dong Gun Kam, Duixian Liu, Brian A. Floyd:
A Fully Integrated 16-Element Phased-Array Transmitter in SiGe BiCMOS for 60-GHz Communications. 2757-2773 - Jun Deguchi, Daisuke Miyashita, Yosuke Ogasawara, Gaku Takemura, Masaomi Iwanaga, Kenichi Sami, Rui Ito, Junji Wadatsumi, Yuki Tsuda, Shoko Oda, Shunji Kawaguchi, Nobuyuki Itoh, Mototsugu Hamada:
A Fully Integrated 2 ˟ 1 Dual-Band Direct-Conversion Mobile WiMAX Transceiver With Dual-Mode Fractional Divider and Noise-Shaping Transimpedance Amplifier in 65 nm CMOS. 2774-2784 - Hiroaki Ishihara, Masahiro Hosoya, Shoji Otaka, Osamu Watanabe:
A 10-MHz Signal Bandwidth Cartesian Loop Transmitter Capable of Off-Chip PA Linearization. 2785-2793 - Mark Ingels, Vito Giannini, Jonathan Borremans, Gunjan Mandal, Björn Debaillie, Peter Van Wesemael, Tomohiro Sano, Takaya Yamamoto, Dries Hauspie, Joris Van Driessche, Jan Craninckx:
A 5 mm2 40 nm LP CMOS Transceiver for a Software-Defined Radio Platform. 2794-2806 - Kimmo Koli, Sami Kallioinen, Jarkko Jussila, Pete Sivonen, Aarno Pärssinen:
A 900-MHz Direct Delta-Sigma Receiver in 65-nm CMOS. 2807-2818 - Mike Shuo-Wei Chen, David K. Su, Srenik S. Mehta:
A Calibration-Free 800 MHz Fractional-N Digital PLL With Embedded TDC. 2819-2827 - Frank O'Mahony, James E. Jaussi, Joseph T. Kennedy, Ganesh Balamurugan, Mozhgan Mansuri, Clark Roberts, Sudip Shekhar, Randy Mooney, Bryan Casper:
A 47 , ˟, 10 Gb/s 1.4 mW/Gb/s Parallel Interface in 45 nm CMOS. 2828-2837 - Koji Fukuda, Hiroki Yamashita, Goichi Ono, Ryo Nemoto, Eiichi Suzuki, Noboru Masuda, Takashi Takemoto, Fumio Yuki, Tatsuya Saito:
A 12.3-mW 12.5-Gb/s Complete Transceiver in 65-nm CMOS Process. 2838-2849 - Robert Reutemann, Michael Ruegg, Fran Keyser, John Bergkvist, Daniel Dreps, Thomas Toifl, Martin L. Schmatz:
A 4.5 mW/Gb/s 6.4 Gb/s 22+1-Lane Source Synchronous Receiver Core With Optional Cleanup PLL in 65 nm CMOS. 2850-2860 - Dongmyung Lee, Jung-Won Han, Gunhee Han, Sung Min Park:
An 8.5-Gb/s Fully Integrated CMOS Optoelectronic Receiver Using Slope-Detection Adaptive Equalizer. 2861-2873 - Seon-Kyoo Lee, Young Hun Seo, Hong-June Park, Jae-Yoon Sim:
A 1 GHz ADPLL With a 1.25 ps Minimum-Resolution Sub-Exponent TDC in 0.18 μ m CMOS. 2874-2881
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