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ORCIDIEEE Transactions on Very Large Scale Integration Systems, Volume 33
Volume 33, Number 1, January 2025
- Hyoseok Song
, Kwangmin Kim, Gain Kim, Byungsub Kim:
A Fast Design Optimization of On-Chip Equalizing Links Using Particle Swarm Optimization. 1-9 - Jie Ding, Fuming Liu, Kuan Deng, Zihan Zheng, Jingnan Zheng, Yongzhen Chen, Jiangfeng Wu:
A 16-bit 1-MS/s SAR ADC With Capacitor Mismatch Self-Calibration. 10-20 - Haitao Du, Hairui Zhu, Song Chen, Yi Kang:
CR-DRAM: Improving DRAM Refresh Energy Efficiency With Inter-Subarray Charge Recycling. 21-34 - Haiyue Yan, Yan Ye, Wenjia Li, Xuefei Bai:
A 0.05-1.5-GHz PVT-Insensitive Digital-to-Time Converter for QKD Applications. 35-46 - Yu Liu, Yupeng Shen, Mingliang Chen, Hui Xu, Xubin Chen, Jiarui Liu, Zhiyu Wang, Faxin Yu:
A Single-Stage Gain-Boosted Cascode Amplifier With Three-Layer Cascode Feedback Amplifier for Front-End SHA in High-Linearity Pipelined ADC. 47-51 - Tianzhu Xiong, Yuyang Ye, Xin Si, Jun Yang:
A Hybrid Domain and Pipelined Analog Computing Chain for MVM Computation. 52-65 - Zhen Gao, Yanmao Qi, Jinchang Shi, Qiang Liu, Guangjun Ge, Yu Wang, Pedro Reviriego:
Detect and Replace: Efficient Soft Error Protection of FPGA-Based CNN Accelerators. 66-74 - Seung-Hwan Bae, Hyuk-Jae Lee, Hyun Kim:
MCM-SR: Multiple Constant Multiplication-Based CNN Streaming Hardware Architecture for Super-Resolution. 75-87 - Jie Li, Chuanlun Zhang, Wenxuan Yang, Heng Li, Xiaoyan Wang, Chuanjun Zhao, Shuangli Du, Yiguang Liu:
FPGA-Based Low-Bit and Lightweight Fast Light Field Depth Estimation. 88-101 - Zhichao Chen, Ali H. Hassan, Rhesa Ramadhan, Yingheng Li, Chih-Kong Ken Yang, Sudhakar Pamarti, Puneet Gupta:
A Comparative Analysis of Low Temperature and Room Temperature Circuit Operation. 102-113 - Anawin Opasatian, Makoto Ikeda:
Manipulated Lookup Table Method for Efficient High-Performance Modular Multiplier. 114-127 - Ken Li, Tian Xie, Tzu-Han Wang, Shaolan Li:
VSAGE: An End-to-End Automated VCO-Based ΔΣ ADC Generator. 128-139 - Tianning Gao, Yifan Wang, Ming Zhu, Xiulong Wu, Dian Zhou, Zhaori Bi:
An RISC-V PPA-Fusion Cooperative Optimization Framework Based on Hybrid Strategies. 140-153 - Jinghai Wang, Shanlin Xiao, Jilong Luo, Bo Li, Lingfeng Zhou, Zhiyi Yu:
An End-to-End Bundled-Data Asynchronous Circuits Design Flow: From RTL to GDS. 154-167 - Jhe-En Lin, Shen-Iuan Liu:
A 0.875-0.95-pJ/b 40-Gb/s PAM-3 Baud-Rate Receiver With One-Tap DFE. 168-178 - Dhandeep Challagundla, Ignatius Bezzam, Riadul Islam:
ArXrCiM: Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory. 179-192 - Dongkwun Kim, Zhaoqing Wang, Paul Xuanyuanliang Huang, Pavan Kumar Chundi, Suhwan Kim, Andres A. Blanco, Ram K. Krishnamurthy, Mingoo Seok:
A 4.2-to-0.5-V, 0.8-μA-0.8-mA, Power-Efficient Three-Level SIMO Buck Converter for a Quad-Voltage RISC-V Microprocessor. 193-206 - Chuanning Wang, Chao Fang, Xiao Wu, Zhongfeng Wang, Jun Lin:
SPEED: A Scalable RISC-V Vector Processor Enabling Efficient Multiprecision DNN Inference. 207-220 - Zhe Huang, Xingyao Chen, Feng Gao, Ruige Li, Xiguang Wu, Fan Zhang:
Sophon: A Time-Repeatable and Low-Latency Architecture for Embedded Real-Time Systems Based on RISC-V. 221-233 - Zhaolin Yang, Jing Jin, Xiaoming Liu, Jianjun Zhou:
A 0.2-2.6 GHz Reconfigurable Receiver Using RF-Gain-Adapted Impedance Matching and Gm-Separated IQ-Leakage Suppression Structure in 40-nm CMOS. 234-247 - Shuming Guo, Yinyin Lin, Hao Wang, Yao Li, Chongyan Gu, Weiqiang Liu, Yijun Cui:
A 0.09-pJ/Bit Logic-Compatible Multiple-Time Programmable (MTP) Memory-Based PUF Design for IoT Applications. 248-260 - Xingye Liu, Paul Ampadu:
A Fast Transient Response Distributed Power Supply With Dynamic Output Switching for Power Side-Channel Attack Mitigation. 261-274 - Alexandre Almeida da Silva, Lucas Nogueira, Alexandre Coelho, Jarbas A. N. Silveira, César A. M. Marcon:
Securet3d: An Adaptive, Secure, and Fault-Tolerant Aware Routing Algorithm for Vertically-Partially Connected 3D-NoC. 275-287 - Lakshmi Bhanuprakash Reddy Konduru, Vikramkumar Pudi, Balasubramanyam Appina:
Design of Low-Complexity Quantized Compressive Sensing Using Measurement Predictive Coding. 288-292 - Zhihao Zhou, Wei Zhang, Xinyi Guo, Jianhan Zhao, Yanyan Liu:
High-Performance Error and Erasure Decoding With Low Complexities Using SPC-RS Concatenated Codes. 293-297 - Yiwei Chang, Zhichuan Guo:
RosebudVirt: A High-Performance and Partially Reconfigurable FPGA Virtualization Framework for Multitenant Networks. 298-302
Volume 33, Number 2, February 2025
- Zhan Qu, Zhenjiao Chen, Xingqiang Shi, Ya Zhao, Guohe Zhang, Feng Liang:
Multiobjective Optimization of Class-F Oscillators. 303-314 - Shiro Dosho, Ludovico Minati, Kazuki Maari, Shungo Ohkubo, Hiroyuki Ito:
A Compact 0.9μ W Direct-Conversion Frequency Analyzer for Speech Recognition With Wide- Range Q-Controllable Bandpass Rectifier. 315-325 - Chiara Venezia, Andrea Ballo, Alfio Dario Grasso, Alessandro Rizzo, Calogero Ribellino, Salvatore Pennisi:
46-nA High-PSR CMOS Buffered Voltage Reference With 1.2-5 V and -40 ◦C to 125 ◦C Operating Range. 326-336 - Ebenezer C. Usih, Naimul Hassan, Alexander J. Edwards, Felipe García-Sánchez, Pedram Khalili Amiri, Joseph S. Friedman:
Toggle SOT-MRAM Architecture With Self-Terminating Write Operation. 337-345 - Sudipta Das, Samuel Riedel, Mohamed Naeim, Moritz Brunion, Marco Bertuletti, Luca Benini, Julien Ryckaert, James Myers, Dwaipayan Biswas, Dragomir Milojevic:
Bandwidth-Latency-Thermal Co-Optimization of Interconnect-Dominated Many-Core 3D-IC. 346-357 - Gauthaman Murali, Min Gyu Park, Sung Kyu Lim:
3DNN-Xplorer: A Machine Learning Framework for Design Space Exploration of Heterogeneous 3-D DNN Accelerators. 358-370 - Lixun Wang, Yuejun Zhang, Pengjun Wang, Jianguo Yang, Huihong Zhang, Gang Li, Qikang Li:
A 578-TOPS/W RRAM-Based Binary Convolutional Neural Network Macro for Tiny AI Edge Devices. 371-383 - Tiancheng Cao, Weihao Yu, Yuan Gao, Chen Liu, Tantan Zhang, Shuicheng Yan, Wang Ling Goh:
Edge PoolFormer: Modeling and Training of PoolFormer Network on RRAM Crossbar for Edge-AI Applications. 384-394 - Shushi Chen, Leilei Huang, Zhao Zan, Xiaoyang Zeng, Yibo Fan:
An Interpolation-Free Fractional Motion Estimation Algorithm and Hardware Implementation for VVC. 395-407 - Yazheng Tu, Shi Bai, Jinjun Xiong, Jiafeng Xie:
SCOPE: Schoolbook-Originated Novel Polynomial Multiplication Accelerators for NTRU-Based PQC. 408-420 - Ruichang Jiang, Wenbin Ye:
Hardware-Algorithm Codesigned Low-Latency and Resource-Efficient OMP Accelerator for DOA Estimation on FPGA. 421-434 - Chao Ji, Xiaohu You, Chuan Zhang, Christoph Studer:
Efficient ORBGRAND Implementation With Parallel Noise Sequence Generation. 435-448 - Ruijun Ma, Stefan Holst, Hui Xu, Xiaoqing Wen, Senling Wang, Jiuqi Li, Aibin Yan:
Highly Defect Detectable and SEU-Resilient Robust Scan-Test-Aware Latch Design. 449-461 - Seung Ho Shin, Hayoung Lee, Sungho Kang:
Effective Parallel Redundancy Analysis Using GPU for Memory Repair. 462-474 - Shuo Cai, Xinjie Liang, Zhu Huang, Weizheng Wang, Fei Yu:
Low-Power and High-Speed SRAM Cells With Double-Node Upset Self-Recovery for Reliable Applications. 475-487 - Youngki Moon, Seung Ho Shin, Seokjun Jang, Duyeon Won, Sungho Kang:
A Novel Prediction-Based Two-Tiered ECC for Mitigating SWD Errors in HBM. 488-498 - Huarun Chen, Yijun Liu, Wujian Ye, Jialiang Ye, Yuehai Chen, Shaozhen Chen, Chao Han:
Research on Hardware Acceleration of Traffic Sign Recognition Based on Spiking Neural Network and FPGA Platform. 499-511 - Zhiquan Wan, Zhipeng Cao, Shunbin Li, Peijie Li, Qingwen Deng, Weihao Wang, Kun Zhang, Guandong Liu, Ruyun Zhang, Qinrang Liu:
Architectural Exploration for Waferscale Switching System. 512-524 - Yuanbo Wang, Liang Chang, Jingke Wang, Pan Zhao, Jiahao Zeng, Xin Zhao, Wuyang Hao, Liang Zhou, Haining Tan, Yinhe Han, Jun Zhou:
PIPECIM: Energy-Efficient Pipelined Computing-in-Memory Computation Engine With Sparsity-Aware Technique. 525-536 - Akhil Reddy Pakala, Zhiyu Chen, Kaiyuan Yang:
MBSNTT: A Highly Parallel Digital In-Memory Bit-Serial Number Theoretic Transform Accelerator. 537-545 - Jia-Li Duan, Chi Zhang, Li-Hui Wang, Lei Shen:
SMBHA: A System-Level Multicore BGV Hardware Accelerator Based on FPGA. 546-557 - Pedro Tauã Lopes Pereira, Patrícia Ücker Leleu da Costa, Eduardo A. C. da Costa, Paulo F. Flores, Sergio Bampi:
ReAdapt-II: Energy-Quality Optimizations for VLSI Adaptive Filters Through Automatic Reconfiguration and Built-In Iterative Dividers. 558-562 - Dingyang Zou, Gaoche Zhang, Xu Zhang, Meiqi Wang, Zhongfeng Wang:
An Efficient and Precision-Reconfigurable Digital CIM Macro for DNN Accelerators. 563-567 - Wanbin Zha, Jiangtao Xu, Kaiming Nie, Zhiyuan Gao:
A Double-Data-Rate Ripple Counter With Calibration Circuits for Correlated Multiple Sampling in CMOS Image Sensors. 568-572 - Yuxin Ji, Yuhang Zhang, Changyan Chen, Jian Zhao, Fakhrul Zaman Rokhani, Yehea Ismail, Yongfu Li:
A 0.4 V, 12.2 pW Leakage, 36.5 fJ/Step Switching Efficiency Data Retention Flip-Flop in 22 nm FDSOI. 573-577 - Chenjia Xie, Zhuang Shao, Ning Zhao, Xingyuan Hu, Yuan Du, Li Du:
A Fast-Convergence Near-Memory-Computing Accelerator for Solving Partial Differential Equations. 578-582 - Quanzhen Liang, Xiao Wang, Kuisong Wang, Yuepeng Yan, Xiaoxin Liang:
Analysis and Design of Wideband GaAs Digital Step Attenuators. 583-587 - Zihang Wang, Yushu Yang, Jianfei Wang, Jia Hou, Yang Su, Chen Yang:
A Scalable and Efficient NTT/INTT Architecture Using Group-Based Pairwise Memory Access and Fast Interstage Reordering. 588-592 - Jiliang Liu, Huidong Zhao, Zhi Li, Kangning Wang, Shushan Qiao:
A Self-Calibrated Unified Voltage-and-Frequency Regulator System Design Based on Universal Logic Line Circuit. 593-597 - Jahyun Koo, Hyunwoo Son, Jae-Yoon Sim:
A 9.6-nW Wake-Up Timer With RC-Referenced Subharmonic Locking Using Dual Leakage-Based Oscillators. 598-602
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