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ORCIDSung-Mo Kang
This is just a disambiguation page, and is not intended to be the bibliography of an actual person. The links to all actual bibliographies of persons of the same or a similar name can be found below. Any publication listed on this page has not been assigned to an actual author yet. If you know the true author of one of the publications listed below, you are welcome to contact us.
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Other persons with the same name
- Sung-Mo Kang 0001
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(aka: Sung Mo Kang 0001, Sung-Mo Steve Kang 0001) — University of California, Santa Cruz, Department of Electrical and Computer Engineering, CA, USA
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2020 – today
- 2023
[j70]Seung-Bo Shim, Seong-Won Lee, Gye-Chun Cho, Jin Kim, Sung-Mo Kang:
Remote robotic system for 3D measurement of concrete damage in tunnel with ground vehicle and manipulator. Comput. Aided Civ. Infrastructure Eng. 38(15): 2180-2201 (2023)
2010 – 2019
- 2019
- [j69]Byung-Hun Lee, Sung-Mo Kang, Hyo-Sung Ahn:
Distributed Orientation Estimation in SO(d) and Applications to Formation Control and Network Localization. IEEE Trans. Control. Netw. Syst. 6(4): 1302-1312 (2019) - [c124]Sung-Mo Kang, Chan-Jun Chun, Seung-Bo Shim, Seung-Ki Ryu, Jong-Dae Baek:
Real Time Image Processing System for Detecting Infrastructure Damage: Crack. ICCE 2019: 1-3 - 2018
- [j68]Sung-Mo Kang, Hyo-Sung Ahn:
Shape and orientation control of moving formation in multi-agent systems without global reference frame. Autom. 92: 210-216 (2018) - [c123]Sung-Mo Kang, Jae-Gyeong Lee, Hyo-Sung Ahn:
Shape and Orientation Control of Moving Formation with Local Measurements in Three-Dimensional Space. CCTA 2018: 1052-1057 - [c122]Yoo-Bin Bae, Young-Hun Lim, Sung-Mo Kang, Hyo-Sung Ahn:
Disturbance Attenuation in Distance-Based Formation Control: A Linear Matrix Inequality Approach. CCTA 2018: 1609-1614 - 2017
- [j67]Sung-Mo Kang, Myoung-Chul Park, Hyo-Sung Ahn:
Distance-Based Cycle-Free Persistent Formation: Global Convergence and Experimental Test With a Group of Quadcopters. IEEE Trans. Ind. Electron. 64(1): 380-389 (2017) - [c121]Sung-Mo Kang, Jin-Hee Son, Hyo-Sung Ahn:
Global convergence of formation without global information in three-dimensional space. ASCC 2017: 233-238 - 2016
- [j66]Sung-Mo Kang, Hyo-Sung Ahn:
Design and Realization of Distributed Adaptive Formation Control Law for Multi-Agent Systems With Moving Leader. IEEE Trans. Ind. Electron. 63(2): 1268-1279 (2016) - [c120]Le Zheng, Sangho Shin, G. Scott Lloyd, Maya B. Gokhale, Kyungmin Kim, Sung-Mo Kang:
RRAM-based TCAMs for pattern search. ISCAS 2016: 1382-1385 - 2014
- [j65]Taegeun Yoo, Hong Chang Yeoh, Yun-Hwan Jung, Seong Jin Cho, Yong Sin Kim, Sung-Mo Kang, Kwang-Hyun Baek:
A 2 GHz 130 mW Direct-Digital Frequency Synthesizer With a Nonlinear DAC in 55 nm CMOS. IEEE J. Solid State Circuits 49(12): 2976-2989 (2014) - [j64]Amirkoushyar Ziabari, Je-Hyoung Park, Ehsan K. Ardestani, Jose Renau, Sung-Mo Kang, Ali Shakouri:
Power Blurring: Fast Static and Transient Thermal Analysis Method for Packaged Integrated Circuits and Power Devices. IEEE Trans. Very Large Scale Integr. Syst. 22(11): 2366-2379 (2014) - [c119]Sung-Mo Kang, Myoung-Chul Park, Byung-Hun Lee, Hyo-Sung Ahn:
Distance-based formation control with a single moving leader. ACC 2014: 305-310 - [c118]Taegeun Yoo, Yun-Hwan Jung, Hong Chang Yeoh, Yong Sin Kim, Sung-Mo Kang, Kwang-Hyun Baek:
21.3 A 2GHz 130mW direct-digital frequency synthesizer with a nonlinear DAC in 55nm CMOS. ISSCC 2014: 364-365 - 2013
- [j63]Sangho Shin, Kyungmin Kim, Sung-Mo Kang:
Resistive Computing: Memristors-Enabled Signal Multiplication. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(5): 1241-1249 (2013) - [c117]Sung-Mo Kang, Yun-Tae Kim, Hyo-Sung Ahn:
Sliding mode controller design for spacecraft with manipulator. ASCC 2013: 1-5 - 2012
- [j62]Sangho Shin, Sung-Mo Kang:
Fast settling frequency synthesizer with two-point channel control paths. Int. J. Circuit Theory Appl. 40(10): 1071-1083 (2012) - [j61]Pinaki Mazumder, Sung-Mo Kang, Rainer Waser:
Memristors: Devices, Models, and Applications [Scanning the Issue]. Proc. IEEE 100(6): 1911-1919 (2012) - [j60]Sangho Shin, Kyungmin Kim, Sung-Mo Kang:
Analysis of Passive Memristive Devices Array: Data-Dependent Statistical Model and Self-Adaptable Sense Resistance for RRAMs. Proc. IEEE 100(6): 2021-2032 (2012) - [c116]Sangho Shin, Kyungmin Kim, Sung-Mo Kang:
Memristive computing- multiplication and correlation. ISCAS 2012: 1608-1611 - [c115]Yong Sin Kim, Sung-Mo Kang, Roland Winston:
Maximizing power harvest in a distributed photovoltaic system. ISCAS 2012: 2275-2278 - 2011
- [j59]Ji-Hye Bong, Kwan-Hee Jo, Kyeong-Sik Min, Sung-Mo Kang:
Oxide-Tunneling Leakage Suppressed SRAM for Sub-65-nm Very Large Scale Integrated Circuits. J. Low Power Electron. 7(1): 87-95 (2011) - [j58]Kyosun Kim, Sangho Shin, Sung-Mo Kang:
Field Programmable Stateful Logic Array. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(12): 1800-1813 (2011) - [j57]Sangho Shin, Kyosun Kim, Sung-Mo Kang:
Reconfigurable Stateful nor Gate for Large-Scale Logic-Array Integrations. IEEE Trans. Circuits Syst. II Express Briefs 58-II(7): 442-446 (2011) - [c114]Sangho Shin, Kyungmin Kim, Sung-Mo Kang:
Complementary structure of memristive devices based passive memory arrays. ISCAS 2011: 321-324 - [c113]Kyosun Kim, Sangho Shin, Sung-Mo Kang:
Stateful logic pipeline architecture. ISCAS 2011: 2497-2500 - 2010
- [j56]Sangho Shin, Kyungmin Kim, Sung-Mo Kang:
Compact Models for Memristors Based on Charge-Flux Constitutive Relationships. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(4): 590-598 (2010) - [j55]Sangho Shin, Kyungmin Kim, Sung-Mo Kang:
Data-Dependent Statistical Memory Model for Passive Array of Memristive Devices. IEEE Trans. Circuits Syst. II Express Briefs 57-II(12): 986-990 (2010)
2000 – 2009
- 2009
- [j54]Kwan-Hee Jo, Ji-Hye Bong, Kyeong-Sik Min, Sung-Mo Kang:
A compact Verilog-A model for Multi-Level-Cell Phase-change RAMs. IEICE Electron. Express 6(19): 1414-1420 (2009) - [c112]Ji-Hye Bong, Yong-Jin Kwon, Kyeong-Sik Min, Sung-Mo Kang:
New word-line driving scheme for suppressing oxide-tunneling leakage in sub-65-nm SRAMs. ISQED 2009: 459-464 - 2008
- [c111]Sangho Shin, Seokoh Yun, Sanghyun Cho, Jongmoon Kim, Minseok Kang, Wonkab Oh, Sung-Mo Kang:
0.18um CMOS integrated chipset for 5.8GHz DSRC systems with +10dBm output power. ISCAS 2008: 1958-1961 - [c110]Jae-Jin Jung, Kwang-Hyun Baek, Shin-Il Lim, Suki Kim, Sung-Mo Kang:
Design of a 6 bit 1.25 GS/s DAC for WPAN. ISCAS 2008: 2262-2265 - [c109]Yong Sin Kim, Sung-Mo Kang:
A 8-Gb/s/pin current mode multi-level simultaneous bidirectional I/O. ISCAS 2008: 3069-3072 - [c108]Je-Hyoung Park, Ali Shakouri, Sung-Mo Kang:
Fast Evaluation Method for Transient Hot Spots in VLSI ICs in Packages. ISQED 2008: 600-603 - 2007
- [j53]Sangho Shin, Kyungmin Kim, Kwyro Lee, Sung-Mo Kang:
Fast- Frequency Offset Cancellation Loop Using Low-IF Receiver and Fractional-N PLL. IEEE Trans. Circuits Syst. II Express Briefs 54-II(3): 272-276 (2007) - [c107]Andrew B. Kahng, Sung-Mo Kang, Wei Li, Bao Liu:
Analytical thermal placement for VLSI lifetime improvement and minimum performance variation. ICCD 2007: 71-77 - [c106]Yong Sin Kim, Sung-Mo Kang:
Programmable High Speed Multi-Level Simultaneous Bidirectional I/O. ISQED 2007: 416-419 - 2006
- [j52]Jeng-Liang Tsai, Charlie Chung-Ping Chen, Guoqiang Chen, Brent Goplen, Haifeng Qian, Yong Zhan, Sung-Mo Kang, Martin D. F. Wong, Sachin S. Sapatnekar:
Temperature-Aware Placement for SOCs. Proc. IEEE 94(8): 1502-1518 (2006) - [c105]Yong Sin Kim, Sangho Shin, Sung-Mo Kang:
A 4-Gb/s/pin current mode 4-level simultaneous bidirectional I/O with current mismatch calibration. ISCAS 2006 - [c104]Sangho Shin, Kwyro Lee, Sung-Mo Kang:
2.4GHz ZigBee radio architecture with fast frequency offset cancellation loop. ISCAS 2006 - [c103]Sangho Shin, Kwyro Lee, Sung-Mo Kang:
Low-power 2.4GHz CMOS frequency synthesizer with differentially controlled MOS varactors. ISCAS 2006 - 2005
- [j51]Ge Yang, Seong-Ook Jung, Kwang-Hyun Baek, Soo Hwan Kim, Suki Kim, Sung-Mo Kang:
A 32-bit carry lookahead adder using dual-path all-N logic. IEEE Trans. Very Large Scale Integr. Syst. 13(8): 992-996 (2005) - [c102]Ge Yang, Yong Sin Kim, Sung-Mo Kang:
Current mode multi-level simultaneous bidirectional I/O scheme for chip-to-chip communications. ISCAS (6) 2005: 5493-5496 - [c101]Sangho Shin, Kwyro Lee, Sung-Mo Kang:
3.48mW 2.4GHz range Frequency Synthesizer Architecture with Two-Point Channel Control for Fast Settling Performance. SoCC 2005: 1-6 - 2004
- [j50]In-Chul Hwang, Chulwoo Kim, Sung-Mo Kang:
A CMOS self-regulating VCO with low supply sensitivity. IEEE J. Solid State Circuits 39(1): 42-48 (2004) - [j49]Jaesik Lee, Yoonjong Huh, Peter Bendix, Sung-Mo Kang:
Design of ESD power protection with diode structures for mixed-power supply systems. IEEE J. Solid State Circuits 39(1): 260-264 (2004) - [c100]Ge Yang, Seong-Ook Jung, Kwang-Hyun Baek, Soo Hwan Kim, Suki Kim, Sung-Mo Kang:
A low-power 1.85 GHz 32-bit carry lookahead adder using Dual Path All-N-Logic. ISCAS (2) 2004: 781-784 - [c99]Ge Yang, Zhongda Wang, Sung-Mo Kang:
Low Power and High Performance Circuit Techniques for High Fan-In Dynamic Gates. ISQED 2004: 421-424 - [c98]Sung-Mo Kang:
Message from the General Chair. SoCC 2004: 0 - [c97]Ge Yang, Zhongda Wang, Sung-Mo Kang:
Leakage-Proof Domino Circuit Design for Deep Sub-100nm Technologies. VLSI Design 2004: 222-227 - 2003
- [j48]Jaesik Lee, Ki-Wook Kim, Yoonjong Huh, Peter Bendix, Sung-Mo Kang:
Chip-level charged-device modeling and simulation in CMOS integrated circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(1): 67-81 (2003) - [j47]Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang:
Timing constraints for domino logic gates with timing-dependent keepers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(1): 96-103 (2003) - [j46]Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Sung-Mo Kang:
Minimum delay optimization for domino circuits - a coupling-aware approach. ACM Trans. Design Autom. Electr. Syst. 8(2): 202-213 (2003) - [j45]Chulwoo Kim, Ki-Wook Kim, Sung-Mo Kang:
Energy-efficient skewed static logic with dual Vt: design and synthesis. IEEE Trans. Very Large Scale Integr. Syst. 11(1): 64-70 (2003) - [j44]Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang:
Noise-aware interconnect power optimization in domino logic synthesis. IEEE Trans. Very Large Scale Integr. Syst. 11(1): 79-89 (2003) - [c96]Kwang-Hyun Baek, Myung-Jun Choe, Edward Merlo, Sung-Mo Kang:
1-GS/s, 12-bit SiGe BiCMOS D/A converter for high-speed DDFs. ISCAS (1) 2003: 901-904 - [c95]Sung-Mo Kang:
Elements of low power design for integrated systems. ISLPED 2003: 205-210 - [c94]Kwang-Hyun Baek, Myung-Jun Choe, Sung-Mo Kang:
An Efficient Calibration Technique for Systematic Current-Mismatch of D/A Converters. ISVLSI 2003: 80-86 - [c93]Yong Sin Kim, Soo Hwan Kim, Kwang-Hyun Baek, Suki Kim, Sung-Mo Kang:
Multiple Trigonometric Approximation of Sine-Amplitude with Small ROM Size for Direct Digital Frequency Synthesizers. VLSI Design 2003: 261- - 2002
- [j43]Chulwoo Kim, Sung-Mo Kang:
A low-swing clock double-edge triggered flip-flop. IEEE J. Solid State Circuits 37(5): 648-652 (2002) - [j42]Chulwoo Kim, In-Chul Hwang, Sung-Mo Kang:
A low-power small-area ±7.28-ps-jitter 1-GHz DLL-based clock generator. IEEE J. Solid State Circuits 37(11): 1414-1420 (2002) - [j41]Ki-Wook Kim, Taewhan Kim, C. L. Liu, Sung-Mo Kang:
Domino logic synthesis based on implication graph. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(2): 232-240 (2002) - [j40]Ki-Wook Kim, Taewhan Kim, TingTing Hwang, Sung-Mo Kang, C. L. Liu:
Logic transformation for low-power synthesis. ACM Trans. Design Autom. Electr. Syst. 7(2): 265-283 (2002) - [j39]Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang:
Noise constrained transistor sizing and power optimization for dual Vst domino logic. IEEE Trans. Very Large Scale Integr. Syst. 10(5): 532-541 (2002) - [c92]Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang:
Low-swing clock domino logic incorporating dual supply and dual threshold voltages. DAC 2002: 467-472 - [c91]Jaesik Lee, Ki-Wook Kim, Sung-Mo Kang:
VeriCDF: a new verification methodology for charged device failures. DAC 2002: 874-879 - [c90]Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang:
Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constrain. DATE 2002: 260-265 - [c89]Robert K. Grube, Qi Wang, Sung-Mo Kang:
Design limitations in deep sub-0.1µm CMOS SRAM. ACM Great Lakes Symposium on VLSI 2002: 94-97 - [c88]Kwang-Hyun Baek, Myung-Jun Choe, Sung-Mo Kang:
A low-voltage high-speed BiCMOS current switch with enhanced-spectral performance. ISCAS (5) 2002: 53-56 - [c87]Sung-Mo Kang:
On-chip thermal engineering for peta-scale integration. ISPD 2002: 76-76 - [c86]Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang:
Optimal Timing for Skew-Tolerant High-Speed Domino Logic. ISVLSI 2002: 41-46 - 2001
- [j38]José E. Schutt-Ainé, Sung-Mo Kang:
Interconnections-addressing the next challenge of IC technology (part I: integration and packaging trends). Proc. IEEE 89(4): 423-425 (2001) - [j37]José E. Schutt-Ainé, Sung-Mo Kang:
Scanning the issue interconnections - addressing the next challenge of IC technology (part II: design, characterization, and modeling). Proc. IEEE 89(5): 583-585 (2001) - [j36]Ki-Wook Kim, Sung-Mo Kang:
Crosstalk noise minimization in domino logic design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(9): 1091-1100 (2001) - [c85]Ki-Wook Kim, Seong-Ook Jung, Prashant Saxena, C. L. Liu, Sung-Mo Kang:
Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique. DAC 2001: 732-737 - [c84]Edward Ahn, Seung-Moon Yoo, Sung-Mo Kang:
Effective algorithms for cache-level compression. ACM Great Lakes Symposium on VLSI 2001: 89-92 - [c83]Seung-Moon Yoo, Seong-Ook Jung, Sung-Mo Kang:
2-level LFSR scheme with asynchronous test pattern transfer for low cost and high efficiency build-in-self-test. ACM Great Lakes Symposium on VLSI 2001: 93-96 - [c82]Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang:
Transistor sizing for reliable domino logic design in dual threshold voltage technologies. ACM Great Lakes Symposium on VLSI 2001: 133-138 - [c81]Jaesik Lee, Yoonjong Huh, Peter Bendix, Sung-Mo Kang:
Understanding and Addressing the Noise Induced By Electrostatic Discharge in Multiple Power Supply Systems. ICCD 2001: 406-414 - [c80]Seung-Moon Yoo, Seong-Ook Jung, Sung-Mo Kang:
Low cost and high efficiency BIST scheme with 2-level LFSR and ATPT. ISCAS (4) 2001: 1-4 - [c79]Seong-Ook Jung, Seung-Moon Yoo, Ki-Wook Kim, Sung-Mo Kang:
Skew-tolerant high-speed (STHS) domino logic. ISCAS (4) 2001: 154-157 - [c78]Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang:
Noise constrained power optimization for dual VT domino logic. ISCAS (4) 2001: 158-161 - [c77]Ki-Wook Kim, Seong-Ook Jung, Sung-Mo Kang:
Coupling-aware minimum delay optimization for domino logic circuits. ISCAS (5) 2001: 371-374 - [c76]Jinghong Chen, Sung-Mo Kang:
Model-order reduction of nonlinear MEMS devices through arclength-based Karhunen-Loeve decomposition. ISCAS (3) 2001: 457-460 - [c75]Q. Li, Sung-Mo Kang:
Trapezoid-to-simple polygon recomposition for resistance extraction. ISCAS (5) 2001: 495-498 - [c74]Q. Li, Yoonjong Huh, Jau-Wen Chen, Peter Bendix, Sung-Mo Kang:
ESD design rule checker. ISCAS (5) 2001: 499-502 - [c73]Q. Li, Yoonjong Huh, Jau-Wen Chen, Peter Bendix, Sung-Mo Kang:
Full chip ESD design rule checking. ISCAS (5) 2001: 503-506 - [c72]Jaesik Lee, Yoonjong Huh, Peter Bendix, Sung-Mo Kang:
Design-for-ESD-reliability for high-frequency I/O interface circuits in deep-submicron CMOS technology. ISCAS (4) 2001: 746-749 - [c71]Chulwoo Kim, Sung-Mo Kang:
A low-power reduced swing single clock flip-flop. ISCAS (4) 2001: 806-809 - [c70]Chulwoo Kim, Ki-Wook Kim, Sung-Mo Kang:
Energy-efficient skewed static logic design with dual Vt. ISCAS (4) 2001: 882-885 - [c69]Seung-Moon Yoo, Chulwoo Kim, Seong-Ook Jung, Kwang-Hyun Baek, Sung-Mo Kang:
New current-mode sense amplifiers for high density DRAM and PIM architectures. ISCAS (4) 2001: 938-941 - [e1]Kaushik Roy, Sung-Mo Kang, Cheng-Kok Koh:
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, West Lafayette, Indiana, USA, 2001. ACM 2001, ISBN 1-58113-351-0 [contents] - 2000
- [j35]Danqing Chen, Erhong Li, Elyse Rosenbaum, Sung-Mo Kang:
Interconnect thermal modeling for accurate simulation of circuittiming and reliability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(2): 197-205 (2000) - [j34]Ching-Han Tsai, Sung-Mo Kang:
Cell-level placement for improving substrate thermal distribution. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(2): 253-266 (2000) - [j33]Yi-Kan Cheng, Sung-Mo Kang:
A temperature-aware simulation environment for reliable ULSI chipdesign. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(10): 1211-1220 (2000) - [c68]Ki-Wook Kim, Unni Narayanan, Sung-Mo Kang:
Domino logic synthesis minimizing crosstalk. DAC 2000: 280-285 - [c67]N. S. Nagaraj, Andrzej J. Strojwas, Sani R. Nassif, Ray Hokinson, Tak Young, Wonjae L. Kang, David Overhauser, Sung-Mo Kang:
When bad things happen to good chips (panel session). DAC 2000: 736-737 - [c66]Ching-Han Tsai, Sung-Mo Kang:
Fast temperature calculation for transient electrothermal simulation by mixed frequency/time domain thermal model reduction. DAC 2000: 750-755 - [c65]Stefan Bucheli, Jay R. Moorman, John W. Lockwood, Sung-Mo Kang:
Compensation modeling for QoS support on a wireless network. GLOBECOM 2000: 198-202 - [c64]Qiao Li, Sung-Mo Kang:
Technology independent arbitrary device extractor. ACM Great Lakes Symposium on VLSI 2000: 143-146 - [c63]Qiao Li, Sung-Mo Kang:
Efficient algorithms for polygon to trapezoid decomposition and trapezoid corner stitching. ACM Great Lakes Symposium on VLSI 2000: 183-188 - [c62]Ki-Wook Kim, Kwang-Hyun Baek, Naresh R. Shanbhag, C. L. Liu, Sung-Mo Kang:
Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design. ICCAD 2000: 318-321 - [c61]Chulwoo Kim, Jaesik Lee, Kwang-Hyun Baek, Eric Martina, Sung-Mo Kang:
High-Performance, Low-Power Skewed Static Logic in Very Deep-Submicron (VDSM) Technology. ICCD 2000: 59-64 - [c60]Seung-Moon Yoo, Sung-Mo Kang:
New high performance sub-1 V circuit technique with reduced standby current and robust data holding. ISCAS 2000: 65-68 - [c59]Jinghong Chen, Sung-Mo Kang:
An algorithm for automatic model-order reduction of nonlinear MEMS devices. ISCAS 2000: 445-448 - [c58]Li-Pen Yuan, Sung-Mo Kang:
Detection and elimination of initial transient for accurate power analysis. ISCAS 2000: 463-466 - [c57]Chulwoo Kim, Seong-Ook Jung, Kwang-Hyun Baek, Sung-Mo Kang:
Parallel dynamic logic (PDL) with speed-enhanced skewed static (SSS) logic. ISCAS 2000: 756-759 - [c56]Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang:
Noise-aware power optimization for on-chip interconnect. ISLPED 2000: 108-113 - [c55]Jay R. Moorman, John W. Lockwood, Sung-Mo Kang:
Real-time prioritized call admission control in a base station scheduler. WOWMOM 2000: 28-37
1990 – 1999
- 1999
- [j32]Ashfaq Hossain, Sung-Mo Kang, Robert Horst:
ServerNet and ATM interconnects: Comparison for compressed video transmission. J. Commun. Networks 1(2): 134-142 (1999) - [c54]Tong Li, Ching-Han Tsai, Elyse Rosenbaum, Sung-Mo Kang:
Substrate Modeling and Lumped Substrate Resistance Extraction for CMOS ESD/Latchup Circuit Simulation. DAC 1999: 549-554 - [c53]Ki-Wook Kim, Sung-Mo Kang, TingTing Hwang, C. L. Liu:
Logic Transformation for Low Power Synthesis. DATE 1999: 158-162 - [c52]Seung-Moon Yoo, Sung-Mo Kang:
No-Race Charge-Recycling Differential Logic (NCDL). Great Lakes Symposium on VLSI 1999: 202-205 - [c51]Chulwoo Kim, Seung-Moon Yoo, Sung-Mo Kang:
NMOS Energy Recovery Logic. Great Lakes Symposium on VLSI 1999: 310-313 - [c50]Ki-Wook Kim, C. L. Liu, Sung-Mo Kang:
Implication graph based domino logic synthesis. ICCAD 1999: 111-114 - [c49]Yi-Kan Cheng, Sung-Mo Kang:
An efficient method for hot-spot identification in ULSI circuits. ICCAD 1999: 124-127 - [c48]Jinghong Chen, Sung-Mo Kang:
A mixed frequency-time approach for quasi-periodic steady-state simulation of multi-level modeled circuits. ISCAS (6) 1999: 194-197 - [c47]Yi-Kan Cheng, Sung-Mo Kang:
Temperature-driven power and timing analysis for CMOS ULSI circuits. ISCAS (6) 1999: 214-217 - [c46]Seung-Moon Yoo, Sung-Mo Kang:
CMOS Pass-gate No-race Charge-recycling Logic (CPNCL). ISCAS (1) 1999: 226-229 - [c45]Ching-Han Tsai, Sung-Mo Kang:
Macrocell placement with temperature profile optimization. ISCAS (6) 1999: 390-393 - [c44]Danqing Chen, Erhong Li, Elyse Rosenbaum, Sung-Mo Kang:
Interconnect thermal modeling for determining design limits on current density. ISPD 1999: 172-178 - [c43]Ching-Han Tsai, Sung-Mo Kang:
Standard cell placement for even on-chip thermal distribution. ISPD 1999: 179-184 - 1998
- [j31]Haoran Duan, John W. Lockwood, Sung-Mo Kang:
Matrix unit cell scheduler (MUCS) for input-buffered ATM switches. IEEE Commun. Lett. 2(1): 20-23 (1998) - [j30]Yoonjong Huh, Yungkwon Sung, Sung-Mo Kang:
A study of hot-carrier-induced mismatch drift: a reliability issue for VLSI circuits. IEEE J. Solid State Circuits 33(6): 921-927 (1998) - [j29]Yi-Kan Cheng, Prasun Raha, Chin-Chi Teng, Elyse Rosenbaum, Sung-Mo Kang:
ILLIADS-T: an electrothermal timing simulator for temperature-sensitive reliability diagnosis of CMOS VLSI chips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(8): 668-681 (1998) - [j28]Li-Pen Yuan, Chin-Chi Teng, Sung-Mo Kang:
Statistical estimation of average power dissipation using nonparametric techniques. IEEE Trans. Very Large Scale Integr. Syst. 6(1): 65-73 (1998) - [c42]Tong Li, Sung-Mo Kang:
Layout Extraction and Verification Methodology CMOS I/O Circuits. DAC 1998: 291-296 - [c41]Tong Li, Ching-Han Tsai, Sung-Mo Kang:
Efficient transient electrothermal simulation of CMOS VLSI circuits under electrical overstress. ICCAD 1998: 6-11 - 1997
- [j27]Brent K. Whitlock, Petar K. Pepeljugoski, Daniel M. Kuchta, John D. Crow, Sung-Mo Kang:
Computer Modeling and Simulation of the Optoelectronic Technology Consortium (OETC) Optical Bus. IEEE J. Sel. Areas Commun. 15(4): 717-730 (1997) - [j26]Chin-Chi Teng, Yi-Kan Cheng, Elyse Rosenbaum, Sung-Mo Kang:
iTEM: a temperature-dependent electromigration reliability diagnosis tool. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(8): 882-893 (1997) - [c40]Li-Pen Yuan, Chin-Chi Teng, Sung-Mo Kang:
Statistical Estimation of Average Power Dissipation in Sequential Circuits. DAC 1997: 377-382 - [c39]Jaewon Kim, Sung-Mo Kang:
An Efficient Transistor Folding Algorithm for Row-Based CMOS Layout Design. DAC 1997: 456-459 - [c38]Sueng-Yong Park, Vaduvur Bharghavan, Sung-Mo Kang:
Data Link Level Support for Handoff in Wireless ATM Network. ICC (2) 1997: 765-769 - [c37]Ashfaq Hossain, Sung-Mo Kang, Bob Horst:
Performance Comparison of Video Transport over ATM and ServerNet Interconnects. ICMCS 1997: 612-613 - [c36]Haoran Duan, John W. Lockwood, Sung-Mo Kang, J. D. Will:
A High-Performance OC-12/OC-48 Queue Design Prototype for Input-buffered ATM Switches. INFOCOM 1997: 20-28 - [c35]Li-Pen Yuan, Sung-Mo Kang:
A sequential procedure for average power analysis of sequential circuits. ISLPED 1997: 231-234 - 1996
- [j25]Anthony M. Hill, Sung-Mo Kang:
Determining accuracy bounds for simulation-based switching activity estimation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(6): 611-618 (1996) - [j24]Jaewon Kim, Sung-Mo Kang:
A new triple-layer OTC channel router. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(9): 1059-1070 (1996) - [c34]Yi-Kan Cheng, Chin-Chi Teng, Abhijit Dharchoudhury, Elyse Rosenbaum, Sung-Mo Kang:
iCET: A Complete Chip-Level Thermal Reliability Diagnosis Tool for CMOS VLSI Chips. DAC 1996: 548-551 - [c33]Chin-Chi Teng, Yi-Kan Cheng, Elyse Rosenbaum, Sung-Mo Kang:
Hierarchical Electromigration Reliability Diagnosis for VLSI Interconnects. DAC 1996: 752-757 - [c32]Yi-Kan Cheng, Elyse Rosenbaum, Sung-Mo Kang:
ETS-A: A New Electrothermal Simulator for CMOS VLSI Circuits. ED&TC 1996: 566-570 - [c31]Li-Pen Yuan, Chin-Chi Teng, Sung-Mo Kang:
Statistical estimation of average power dissipation in CMOS VLSI circuits using nonparametric techniques. ISLPED 1996: 73-78 - 1995
- [j23]Abhijit Dharchoudhury, Sung-Mo Kang:
Worst-case analysis and optimization of VLSI circuit performances. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(4): 481-492 (1995) - [j22]Mysore Sriram, Sung-Mo Kang:
Efficient approximation of the time domain response of lossy coupled transmission line trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(8): 1013-1024 (1995) - [j21]Elizabeth J. Brauer, Sung-Mo Kang:
An algorithm for functional verification of digital ECL circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(12): 1546-1556 (1995) - [c30]Tanay Karnik, Sung-Mo Kang:
An empirical model for accurate estimation of routing delay in FPGAs. ICCAD 1995: 328-331 - [c29]Chin-Chi Teng, Anthony M. Hill, Sung-Mo Kang:
Estimation of maximum transition counts at internal nodes in CMOS VLSI circuits. ICCAD 1995: 366-370 - [c28]Jaewon Kim, Sung-Mo Kang:
A timing-driven data path layout synthesis with integer programming. ICCAD 1995: 716-719 - [c27]Elizabeth J. Brauer, Sung-Mo Kang:
Estimating Node Voltages in Bipolar Circuits Using Linear Programming. ISCAS 1995: 901-903 - [c26]Yi-Kan Cheng, Sung-Mo Kang:
Chip-Level Thermal Simulator to Predict VLSI Chip Temperature. ISCAS 1995: 1392-1395 - [c25]Elizabeth J. Brauer, Sung-Mo Kang:
An Analytic Method to Calculate Emitter Follower Delay Using Trial Functions in Coupled Node Equations. ISCAS 1995: 1580-1583 - [c24]Myong H. Cynn, Sung-Mo Kang:
Incremental Node Extraction Algorithms for Incremental Layout System. ISCAS 1995: 1691-1694 - [c23]Anthony M. Hill, Sung-Mo Kang:
Determining accuracy bounds for simulation-based switching activity estimation. ISLPD 1995: 215-220 - 1994
- [j20]Carlos H. Díaz, Sung-Mo Kang, Charvaka Duvvury:
Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(4): 482-493 (1994) - [j19]Sachin S. Sapatnekar, Pravin M. Vaidya, Sung-Mo Kang:
Convexity-based algorithms for design centering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(12): 1536-1549 (1994) - [c22]Abhijit Dharchoudhury, Sung-Mo Kang, K. H. (Kane) Kim, S. H. Lee:
Fast and accurate timing simulation with regionwise quadratic models of MOS I-V characteristics. ICCAD 1994: 190-194 - [c21]Abhijit Dharchoudhury, Sung-Mo Kang, Hungse Cha, Janak H. Patel:
Fast timing simulation of transient faults in digital circuits. ICCAD 1994: 719-722 - [c20]Eby G. Friedman, Sung-Mo Kang, Eric A. Vittoz, David J. Allstot, Erik P. Harris, Ran-Hong Yan:
Forum: From 100 Milliwatts/MIPS to 10 Microwatts/MIPS. ISCAS 1994: 1-6 - [c19]Jaewon Kim, Sung-Mo Kang, Sachin S. Sapatnekar:
High Performance CMOS Macromodule Layout Synthesis. ISCAS 1994: 179-182 - [c18]Anthony M. Hill, Sung-Mo Kang:
Genetic Algorithm Based Design Optimization Of CMOS VLSI Circuits. PPSN 1994: 546-555 - 1993
- [j18]Jun Dong Cho, Majid Sarrafzadeh, Mysore Sriram, Sung-Mo Kang:
High-Performance MCM Routing. IEEE Des. Test Comput. 10(4): 27-37 (1993) - [j17]Yusuf Leblebici, Sung-Mo Kang:
Modeling and simulation of hot-carrier-induced device degradation in MOS circuits. IEEE J. Solid State Circuits 28(5): 585-595 (1993) - [j16]Yung-Ho Shih, Yusuf Leblebici, Sung-Mo Kang:
ILLIADS: a fast timing and reliability simulator for digital MOS circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(9): 1387-1402 (1993) - [j15]Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya, Sung-Mo Kang:
An exact solution to the transistor sizing problem for CMOS circuits using convex optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(11): 1621-1634 (1993) - [c17]Abhijit Dharchoudhury, Sung-Mo Kang:
Performance-Constrained Worst-Case Variability Minimization of VLSI Circuits. DAC 1993: 154-158 - [c16]Mysore Sriram, Sung-Mo Kang:
Fast Approximation of the Transient Response of Lossy Transmision Line Trees. DAC 1993: 691-696 - [c15]Carlos H. Díaz, Charvaka Duvvury, Sung-Mo Kang:
Thermal Failure Simulation for Electrical Overstress in Semiconductor Devices. ISCAS 1993: 1389-1392 - [c14]Elizabeth J. Brauer, Sung-Mo Kang:
Functional Verification of ECL Circuits Including Voltage Regulators. ISCAS 1993: 1710-1713 - [c13]Sachin S. Sapatnekar, Pravin M. Vaidya, Sung-Mo Kang:
Feasible Region Approximation Using Convex Polytopes. ISCAS 1993: 1786-1789 - 1992
- [j14]G. M. Tharakan, Sung-Mo Kang:
A new design of a fast barrel switch network. IEEE J. Solid State Circuits 27(2): 217-221 (1992) - [j13]Yusuf Leblebici, Sung-Mo Kang:
Modeling of nMOS transistors for simulation of hot-carrier-induced device and circuit degradation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(2): 235-246 (1992) - [j12]Yung-Ho Shih, Sung-Mo Kang:
Analytic transient solution of general MOS circuit primitives. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(6): 719-731 (1992) - [j11]Carlos H. Díaz, Sung-Mo Kang:
New algorithms for circuit simulation of device breakdown. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(11): 1344-1354 (1992) - [j10]Richard W. Thaik, Ngee Lek, Sung-Mo Kang:
A new global router using zero-one integer linear programming techniques for sea-of-gates and custom logic arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(12): 1479-1494 (1992) - [c12]Abhijit Dharchoudhury, Sung-Mo Kang:
An Integrated Approach to Realistic Worst-Case Design Optimization of MOS Analog Circuits. DAC 1992: 704-709 - [c11]Mysore Sriram, Sung-Mo Kang:
Detailed layer assignment for MCM routing. ICCAD 1992: 386-389 - 1991
- [j9]Tat-Kwan Yu, Sung-Mo Kang, Jerome Sacks, William J. Welch:
Parametric yield optimization of CMOS analogue circuits by quadratic statistical circuit performance models. Int. J. Circuit Theory Appl. 19(6): 579-592 (1991) - [j8]H. Y. Chen, Sung-Mo Kang:
iCOACH: A circuit optimization aid for CMOS high-performance circuits. Integr. 10(2): 185-212 (1991) - [j7]Carlos H. Díaz, Sung-Mo Kang, Yusuf Leblebici:
An accurate analytical delay model for BiCMOS driver circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(5): 577-588 (1991) - [j6]H. Y. Chen, Sung-Mo Kang:
A new circuit optimization technique for high performance CMOS circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(5): 670-677 (1991) - [c10]Yung-Ho Shih, Sung-Mo Kang:
ILLIADS: A New Fast MOS Timing Simulator Using Direct Equation-Solving Approach. DAC 1991: 20-25 - [c9]Yung-Ho Shih, Yusuf Leblebici, Sung-Mo Kang:
New Simulation Methods for MOS VLSI Timing and Reliability. ICCAD 1991: 162-165 - 1990
- [j5]Sung-Mo Kang, H. Y. Chen:
A global delay model for domino cmos circuits with application to transistor sizing. Int. J. Circuit Theory Appl. 18(3): 289-306 (1990) - [c8]Yusuf Leblebici, Sung-Mo Kang:
An Integrated Hot-Carrier Degradation Simulator for VLSI Reliability Analysis. ICCAD 1990: 400-403
1980 – 1989
- 1989
- [c7]P. Gee, Ibrahim N. Hajj, Sung-Mo Kang:
A custom cell generation system for double-metal CMOS technology. ICCAD 1989: 140-143 - [c6]Tat-Kwan Yu, Sung-Mo Kang, Jerome Sacks, William J. Welch:
An efficient method for parametric yield optimization of MOS integrated circuits. ICCAD 1989: 190-193 - [c5]Yusuf Leblebici, Sung-Mo Kang:
Simulation of MOS circuit performance degradation with emphasis on VLSI design-for-reliability. ICCD 1989: 492-495 - 1988
- [c4]Tat-Kwan Yu, Sung-Mo Kang, Ibrahim N. Hajj, Timothy N. Trick:
iEDISON: an interactive statistical design tool for MOS VLSI circuits. ICCAD 1988: 20-23 - [c3]Sung-Mo Kang, Yusuf Leblebici:
An efficient method for circuit sensitivity calculation using piecewise linear waveform models. ICCAD 1988: 24-27 - [c2]H. Y. Chen, Sung-Mo Kang:
iCOACH: a circuit optimization aid for CMOS high-performance circuits. ICCAD 1988: 372-375 - 1987
- [j4]D. K. Hwang, W. Kent Fuchs, Sung-Mo Kang:
An Efficient Approach to Gate Matrix Layout. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(5): 802-809 (1987) - [j3]Sung-Mo Kang:
Metal--Metal Matrix (M3) for High-Speed MOS VLSI Layout. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(5): 886-891 (1987) - [j2]Tat-Kwan Yu, Sung-Mo Kang, I. N. Haji, Timothy N. Trick:
Statistical Performance Modeling and Parametric Yield Estimation of MOS VLSI. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(6): 1013-1022 (1987) - 1983
- [j1]Sung-Mo Kang, Robert H. Krambeck, Hung-Fai Stephen Law, Alexander D. Lopez:
Gate Matrix Layout of Random Control Logic in a 32-bit CMOS CPU Chip Adaptable to Evolving Logic Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2(1): 18-29 (1983) - 1982
- [c1]Sung-Mo Kang, Robert H. Krambeck, Hung-Fai Stephen Law:
Gate matrix layout of random control logic in a 32-bit CMOS CPU chip adaptable to evolving logic design. DAC 1982: 170-174
Coauthor Index
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