Abstract
We present a blackbox approach to model leakage currents of RTL data-path components. The model inputs are temperature, V DD , body voltage of NMOS and PMOS and the bitvector at the input. Additionally, the model accepts a statistical Gaussian variation introduced by intra-die and systematic variation introduced by inter-die. Both variations can be given independently for each BSIM-level process parameter; in this work we evaluate variation of channel length, gate-oxide thickness and channel doping. Model output is the sum of subthreshold, gate, and pn-junction leakage. The evaluation of an RT component can be done in milliseconds and the result for the 45nm and 65nm BPTM technology is within 2% against single BSIM4.40 evaluation and within 5% against statistical BSIM4.40 evaluation assuming 1% variation of the process parameters.
This is a preview of subscription content, log in via an institution to check access.
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Roy, K., Mukhopadhyay, S., Mahmoodi-Meimand, H.: Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits. Proc. of the IEEE 91(2) (2003)
Helms, D., Schmidt, E., Nebel, W.: Leakage in CMOS Circuits – An Introduction. In: Macii, E., Paliouras, V., Koufopavlou, O. (eds.) PATMOS 2004. LNCS, vol. 3254, pp. 17–35. Springer, Heidelberg (2004)
The Berkeley Device Group, www-device.eecs.berkeley.edu
Narendra, S., De, V., Borkar, S., Antoniadis, D., Chandrakasan, A.: Full-Chip Sub-threshold Leakage Power Prediction Model for sum-0.18μm CMOS. In: ISLPED (2002)
Borkar, S., Karnik, T., Narendra, S., Tschanz, J., Keshavari, A., De, V.: Parameter Variations and Impact on Microarchitecture. In: DAC (2003)
Banerjee, K., Lin, S.-C., Keshavarzi, A., Narendra, S., De, V.: A Self-Consistent Junction Temperature Estimation Methodology for Nanometer Scale ICs with Implications for Performance and Thermal Management. IEEE, Los Alamitos (2003)
Ashouei, M., Chatterjee, A., Singh, A.D., De, V., Mak, T.M.: Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design. In: VLSI Design (2006)
Rao, R.M., Burns, J.L., Devgan, A., Brown, R.B.: Efficient techniques for gate leakage estimation. In: ISLPED (2003)
Su, H., Liu, F., Devgan, A., Acar, E., Nassif, S.R.: Full chip leakage estimation considering power supply and temperature variations. In: ISLPED (2003)
Acar, E., Devgan, A., Rao, R., Liu, Y., Su, H., Nassif, S.R., Burns, J.L.: Leakage and leakage sensitivity computation for combinational circuits. In: ISLPED (2003)
Srivastava, A., Bai, R., Blaauw, D., Sylvester, D.: Modeling and analysis of leakage power considering within-die process variations. In: ISLPED (2002)
Rao, R.R., Srivastava, A., Blaauw, D., Sylvester, D.: Statistical estimation of leakage current considering inter- and intra-die process variation. In: ISLPED (2005)
Rao, R.R., Srivastava, A., Blaauw, D., Sylvester, D.: Statistical analysis of subthreshold leakage current for VLSI circuits. IEEE Trans. VLSI Syst. (2004)
Rao, R.R., Devgan, A., Blaauw, D., Sylvester, D.: Parametric yield estimation considering leakage variability. In: DAC (2004)
Srivastava, A., Shah, S., Agarwal, K., Sylvester, D., Blaauw, D., Director, S.W.: Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance. In: DAC (2005)
Lee, D., Kwong, W., Blaauw, D., Sylvester, D.: Analysis and minimization techniques for total leakage considering gate oxide leakage. In: DAC (2003)
Mukhopadhyay, S., Raychowdhury, A., Roy, K.: Accurate Estimation of Total Leakage Current in Scaled CMOS Logic Circuits Based on Compact Current Modeling. In: DAC (2003)
Mukhopadhyay, S., Roy, K.: Modeling and Estimation of Total Leakage Current in Nano-scaled CMOS Devices Considering the Effect of Parameter Variation. In: ISLPED (2003)
Helms, D., Ehmen, G., Nebel, W.: Analysis and Modeling of Subthreshold Leakage of RT-Components under PTV and State Variation. In: ISLPED (2006)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2006 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Helms, D., Hoyer, M., Nebel, W. (2006). Accurate PTV, State, and ABB Aware RTL Blackbox Modeling of Subthreshold, Gate, and PN-Junction Leakage. In: Vounckx, J., Azemard, N., Maurine, P. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2006. Lecture Notes in Computer Science, vol 4148. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11847083_6
Download citation
DOI: https://doi.org/10.1007/11847083_6
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-39094-7
Online ISBN: 978-3-540-39097-8
eBook Packages: Computer ScienceComputer Science (R0)