Abstract
The top-down design of VLSI-systems typically features a step-wise refinement of intermediate solutions. Even though these refinements do usually not preserve time-scales, current formal verification approaches are largely based on the assumption that both specification and implementation utilize the same scales of time. In this paper, a symbolic methodology is presented to verify the step-wise refinement of finite state machines, allowing for possible differences in timing-granularity.
Acknowledgment
The research presented in this paper was supported by a scholarship from the Flemish Institute for the promotion of Scientific-Technological Research in Industry (IWT).
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S. Hendricx and L. Claesen. Symbolic Multi-Level Verification of Refinement. In Nineth Great Lakes Symposium on VLSIAnn ArborMI 4-6 March 1999. IEEE Computer Society Press.
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© 1999 Springer-Verlag Berlin Heidelberg
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Hendricx, S., Claesen, L. (1999). Verification of Finite-State-Machine Refinements Using a Symbolic Methodology. In: Pierre, L., Kropf, T. (eds) Correct Hardware Design and Verification Methods. CHARME 1999. Lecture Notes in Computer Science, vol 1703. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-48153-2_26
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DOI: https://doi.org/10.1007/3-540-48153-2_26
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