Abstract
The Advanced Encryption Standard (AES) is widely accepted as the de-facto standard for symmetric-key encryption, and it is going to be used in the coming decades because of its resistance against Post-Quantum Cryptography. For this reason, it is the subject of many research works, and almost all converge on the usage of composite/tower fields for the hardware implementation of the S-box, the most expensive circuit in terms of both area and critical delay. Anyway, the debate is still open on applying isomorphic fields also to the other AES algorithm operations. In the attempt to give an answer, it is analyzed the application of the two approaches to the most recent and performing solutions from the state-of-the-art with the synthesis of the corresponding circuits on a 7 nm standard-cell technology. In addition, the presented work constitutes also a guideline for implementing hardware AES modules that execute all operations over composite/tower fields.
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Acknowledgments
This work was partially funded by the European Union’s Horizon 2020 research and innovation programme “European Processor Initiative” (grant agreement No. 101036168, EPI SGA2) and partially supported by the Italian Ministry of University and Research (MUR) with the project CN4-CN00000023 of Recovery and Resilience Plan (PNRR) program, grant agreement No. I53C22000720001, and in the framework of the FoReLab project (Departments of Excellence).
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Crocetti, L., Saponara, S. (2024). On the Usage of Isomorphic Fields in Hardware AES Modules for Optimizing the Efficiency. In: Bellotti, F., et al. Applications in Electronics Pervading Industry, Environment and Society. ApplePies 2023. Lecture Notes in Electrical Engineering, vol 1110. Springer, Cham. https://doi.org/10.1007/978-3-031-48121-5_8
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DOI: https://doi.org/10.1007/978-3-031-48121-5_8
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