Abstract
The need to consider fault tolerance in quantum circuits has led to recent work on the optimization of circuits composed of Clifford+T gates. The primary optimization objectives are to minimize the T-count (number of T gates) and the T-depth (the number of groupings of parallel T gates). These objectives arise due to the high cost of the fault tolerant implementation of the T gate compared to Clifford gates. In this paper, we consider the mapping of a circuit composed of NOT, Controlled-NOT and square-root of NOT (NCV) gates to an equivalent circuit composed of Clifford+T gates. Our approach is heuristic and proceeds through three phases: (i) mapping a circuit of NCV gates to a Clifford+T circuit; (ii) optimization of the placement of the T gates in the Clifford+T circuit; and (iii) optimization of the subcircuits between T gate groupings. The approach takes advantage of earlier work on the optimization of NCV circuits. Examples are presented to show the approach presented here compares well with other approaches. Our approach does not add ancilla lines.
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References
AlFailakawi, M., AlTerkawi, L., Ahmad, I., Hamdan, S.: Line ordering of reversible circuits for linear nearest neighbour realization. Qunatum Inf. Process. 12, 3319–3339 (2013)
Amy, M., Maslov, D., Mosca, M.: Polynomial-time T-depth optimization of Clifford+T circuits via matroid partitioning, arXiv:quant-ph/1303.2042v2 (2013)
Amy, M., Maslov, D., Mosca, M., Roetteler, M.: A meet-in-the-middle algorithm for fast synthesis of depth-optimal quantum circuits. IEEE Trans. on CAD 32(6), 818–830 (2013)
Barenco, A., Bennett, C.H., Cleve, R., DiVincenzo, D.P., Margolus, N., Shor, P., Sleator, T., Smolin, J.A., Weinfurter, H.: Elementary gates for quantum computation. Phys. Rev. A 52(5), 3457–3467 (1995)
Buhrman, H., Cleve, R., Laurent, M., Linden, N., Schrijver, A., Unger, F.: New limits on fault-tolerant quantum computation. In: Foundations of Computer Science, vol. 27, pp. 411–419. IEEE Computer Society (2006)
Chakrabarti, A., Sur-Kolay, S., Chaudhury, A.: Linear nearest neighbor synthesis of reversible circuits by graph partitioning. CoRR, arXiv:1112.0564v2 (2012)
DiVincenzo, D.P., Bacon, D., Kempe, J., Burkard, G., Whaley, K.B.: Universal quantum computation with the exchange interaction. Nature 408, 339–342 (2000)
Khan, M.H.A.: Cost reduction in nearest neighbour based synthesis of quantum Boolean circuits. Engineering Letters 16, 1–5 (2008)
Lukac, M.: Quantum Inductive Learning and Quantum Logic Synthesis. BiblioLabsII (2011)
Maslov, D., Dueck, G.W., Miller, D.M., Negrevergne, C.: Quantum circuit simplification and level compaction. IEEE Trans. CAD 27(3), 436–444 (2008)
Nielsen, M.A., Chuang, I.L.: Quantum Computation and Quantum Information. Cambridge University Press (2000)
Patel, K., Markov, I.L., Hayes, J.P.: Optimal synthesis of linear reversible circuits. Quantum Information and Computation 8(3&4), 282–294 (2008)
Sasanian, Z., Miller, D.M.: Mapping a multiple-control Toffoli gate cascade to an elementary quantum gate circuit. Multiple-Valued Logic and Soft Computing 18(1), 83–98 (2012)
Selinger, P.: Quantum circuits of T-depth one. Phys. Rev. AÂ 87, 042302 (2013)
Shende, V.V., Bullock, S.S., Markov, I.L.: Synthesis of quantum logic circuits. IEEE Trans. on CAD 25(6), 1000–1010 (2006)
Soeken, M., Miller, D.M., Drechsler, R.: Quantum circuits employing roots of the Pauli matrices. Phys. Rev. AÂ 88, 042322 (2013)
Soeken, M., Thomsen, M.K.: White dots do matter: Rewriting reversible logic circuits. In: Dueck, G.W., Miller, D.M. (eds.) RC 2013. LNCS, vol. 7948, pp. 196–208. Springer, Heidelberg (2013)
Weinstein, Y.S.: Non-fault tolerant T-gates for the [7,1,3] quantum error correction code. Phys. Rev. AÂ 87, 032320 (2013)
Wille, R., Große, D., Teuber, L., Dueck, G.W., Drechsler, R.: RevLib: An online resource for reversible functions and reversible circuits. In: Int’l Symp. on Multi-Valued Logic, pp. 220–225 (2008), RevLib is available at www.revlib.org
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Miller, D.M., Soeken, M., Drechsler, R. (2014). Mapping NCV Circuits to Optimized Clifford+T Circuits. In: Yamashita, S., Minato, Si. (eds) Reversible Computation. RC 2014. Lecture Notes in Computer Science, vol 8507. Springer, Cham. https://doi.org/10.1007/978-3-319-08494-7_13
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DOI: https://doi.org/10.1007/978-3-319-08494-7_13
Publisher Name: Springer, Cham
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