Abstract
In this chapter, we will highlight the peculiar features of one of the most popular implementations of the embedded flash cell: the so-called 1Tr-NOR. The one-transistor cell has been by far the most adopted cell architecture in the world of flash NOR stand-alone memory. As an almost natural consequence, 1Tr-NOR architecture has also been considered the first, and for sure one of the best, solutions in embedded non-volatile memory (NVM) applications and has been progressively replacing EEPROM cells. In this chapter, only embedded multi-megabit flash implementation will be reviewed: different solutions for 1Tr-NOR flash cell structure and design architectures have been successfully implemented and will be described. In particular, the focus hereinafter is based on the description of how the unique features offered by that cell can be efficiently and effectively integrated into MCUs , which represent one of the major fields fueled by embedded flash capability. In the following sections, after a short introduction devoted to highlighting some peculiar technology features related to 1Tr-NOR integration with state-of-the-art CMOS, three different kind of MCU products will be thoroughly analysed:
-
the secure MCU.
-
the general-purpose/low-power MCU.
-
the automotive MCU.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Similar content being viewed by others
References
L. Baldi, A. Maurelli, Embedded non volatile memories in deep-submicron CMOS, ESSDERC (1999)
A. Maurelli, F. Piazza, Embedded memories. ESSDERC/ESSCIRC, Short Course (2005)
S. Marangon, A. Maurelli, M. Moroni, L. Baldi, A salicided flash EEPROM for embedded memory applications. ESSDERC (1996)
F. Piazza, P. Colombo, P. Ghezzi, V. Lista, A. Maurelli, E. Palumbo, D. Peschiaroli, S. Soleri, A. Di Biase, A. Silvagni, C. Torti, M. Olivo, L. Baldi, 1.8 µm2 high density flash memory for 0.35 µm embedded applications. ESSDERC (1999)
L. Larcher, P. Pavan, A. Maurelli, Flash memories for SoC: an overview on system constraints and technology issues. IWSOC Tech. Dig. (2005)
F. Piazza, C. Boccaccio, S. Bruyere, R. Cea, B. Clark, N. Degors, C. Collins, A. Gandolfo, A. Gilardini, E. Gomiero, PM. Mans, G. Mastracchio, D. Pacelli, N. Planes, J. Simon, M. Weybright, A. Maurelli, High performance flash memory for 65Â nm embedded automotive application. 2010 IEEE international memory workshop
P. Cappelletti, A. Maurelli, US Patent No 6,410,387 (2002)
D. Peschiaroli, A. Maurelli, E. Palumbo, F. Piazza, US Patent No 6,482,698 (2002)
P. Cappelletti, A. Maurelli, US Patent No 6,713,347 (2004)
A. Maurelli, D. Belot, G. Campardo, SoC and SiP, the Yin and Yang of the Tao for the New Electronic Era. Proceedings of IEEE, vol. 97, no. 1 (2009)
A. Maurelli, Status and perspectives of embedded non-volatile memories. 2013 International Conference on IC Design & Technology (ICICDT)
S. Yamada et al., Degradation mechanism of flash EEPROM programming after program/erase cycles. IEDM, pp. 23–26 (1993)
R.S. Scott, R.A. Dumin et al., Properties of high-voltage generated traps in thin silicon oxide. IEEE Trans. Electr. Devices 43(7), 1133–1143
G. Matranga, M. Micciché, R.R. Grasso, Managing of the erasing of operative pages of a flash memory device through service pages. US Patent No 20130272068 (2013)
D. Esseni, A. Della Strada, P. Cappelletti, B. Riccó, A new flexible scheme for hot electron programming of non volatile memory cell. IEEE Trans. Electr. Devices 46(1) (1999)
C. Ucciardello, A. Conte, S. Pagano, Charge pump circuit using low voltage transistors. US Patent No 20120250421 (2012)
A. Conte, M. Giaquinta, High performance digital to analog converter. US Patent No 20150263758 (2015)
M. Giaquinta, A. Conte, R.R. Grasso, F.N. Mammoliti, Background power consumption reduction of electronic devices. US Patent No 8675411 (2014)
F. La Rosa, Sense amplifier with fast bitline precharge means. US Patent No 8305815 (2012)
F. La Rosa, Bitline bias circuit for non-volatile memory devices. US Patent No 6049491 (2000)
G. Campardo, Sense amplifier having capacitively coupled input for offset compensation. US Patent No 5729492 (1998)
F. La Rosa, Self-timed low power sense amplifier. US Patent No 8363499 (2013)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2018 Springer International Publishing AG
About this chapter
Cite this chapter
Conte, A., Disegni, F., La Rosa, F., Maurelli, A. (2018). Floating-Gate 1Tr-NOR eFlash Memory. In: Hidaka, H. (eds) Embedded Flash Memory for Embedded Systems: Technology, Design for Sub-systems, and Innovations. Integrated Circuits and Systems. Springer, Cham. https://doi.org/10.1007/978-3-319-55306-1_4
Download citation
DOI: https://doi.org/10.1007/978-3-319-55306-1_4
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-55305-4
Online ISBN: 978-3-319-55306-1
eBook Packages: EngineeringEngineering (R0)