Abstract
This paper presents a shift-register architecture or SRA, for data sorting applications. The operations performed by the proposed architecture are (1)shift right, (2)shift left, (3)load, and (4)initialize. Sorting operations, such as insert and delete, can be realized by the combination of these 4 basic operations. The architecture is very regular and mainly composed of two basic cells,sort-cell and compare-cell. The latter is designed to generate control signals orchestrating the operation of sort cells which contain the sorted input sequences. Experimental results show that a single chip solution can achieve real-time performance based on 1.2Μm CMOS double-metal technology.
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References
R. Sedgewich,Algorithms in C, Addison Wesley, 1990.
A.L. Fisher, “Systolic Algorithm for Running Order Statistics,” inSignaland Image Processing, Dept. Comp. Science, Carnegie Mellon Univ., Pittsburgh, July 1981.
E. Ataman, V.K. Aatre, and K.M. Wong, “A Fast Method for Real-Time Median Filtering,”IEEE Trans. on ASSP, Vol. ASSP-23, pp. 552–557, Dec. 1975.
V.V. Bapeswara Rao and K. Sankara Rao, “A New Algorithm for Real-Time Median Filtering,”IEEE Trans. on ASSP, Vol. ASSP-34, No. 6, Dec. 1986.
S.Y. Kung, P.S. Lewis, and S.C. Lo, “On Optimally Mapping Algorithms to Systolic Arrays With Applications to the Transitive Closure Problem,”Proc. IEEE Circuits and Systems, San Jose Ca. pp. 1316–1322, May 1986.
F. Catthoor and H. De Man, “Application-Specific Architectural Methodologies for High-Throughput Digital Signal and Image Processing,”IEEE Trans. on ASSP, Vol. 38, No. 2, Feb. 1990.
Neil Weste and Kamran Eshraghian,Principles of CMOS VLSI Design: A Systems Perspective, Addison-Wesley, 1984.
C.Y. Lee, J.M. Tsai, and S.C. Hsu, “VLSI Implementation of an M-Array Median Filter Based on Shift Register Arrays,”Integration, the VLSI Journal, Vol. 16, No. 1, pp. 91–104, Nov. 1993.
P.W. Hsieh, J.M. Tsai, and C.Y. Lee, “An Area-Efficient Median Filtering IC for Image/Video Applications,”IEEE Trans. on Consumer Electronics, pp. 504–509, Aug. 1993.
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Work support by the National Science Council of Taiwan, ROC under grant NSC82-0404-E009-184.
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Lee, C.Y., Tsai, J.M. A shift register architecture for high-speed data sorting. Journal of VLSI Signal Processing 11, 273–280 (1995). https://doi.org/10.1007/BF02107058
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DOI: https://doi.org/10.1007/BF02107058