Abstract
Efficient utilization of the inherent parallelism of multi-core architectures is a grand challenge in the field of electronic design automation (EDA). One EDA algorithm associated with a high computational cost is automatic test pattern generation (ATPG). We present the ATPG tool TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully chosen mix of various optimization techniques, multi-million-gate industrial circuits are handled without aborts. TIGUAN supports both conventional single-stuck-at faults and sophisticated conditional multiple stuck-at faults which allows to generate patterns for non-standard fault models. We demonstrate how TIGUAN can be combined with conventional structural ATPG to extract full benefit of the intrinsic strengths of both approaches.
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Czutro, A., Polian, I., Lewis, M. et al. Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis. Int J Parallel Prog 38, 185–202 (2010). https://doi.org/10.1007/s10766-009-0124-7
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DOI: https://doi.org/10.1007/s10766-009-0124-7