Skip to main content

Advertisement

Springer Nature Link
Log in

Analysis of Combinational Circuit Failure Rate based on Graph Partitioning and Probabilistic Binomial Approach

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

This paper studies the fault propagation and the correctness rate calculation of combinatorial circuits. We rely on circuit partitioning and on a probabilistic approach close to a binomial distribution, assuming some simultaneous faults have a certain probability to occur in the circuit’s gates. We extend the results of our Clusterized Probabilistic Binomial Reliability model (CPBR), in which we obtained the results for several combinatorial multiplier designs, as seen in our previous publication. We now target non-arithmetic combinatorial netlists and, among them, a few circuits with flip-flop instances. We use the graph representation of the combinatorial netlists and we generalize our approach with a generic algorithm for CPBR. To develop this algorithm, we use some existing work on multilevel acyclic hypergraph partitioning, that we adapt to acyclic directed graphs. Furthermore, we address the problem of calculating correctness rates of circuits in cases where sequential flip-flops induce cycles in the graph. Our experiments show that our approach is capable of analysing the error and the correctness rates of significant non-arithmetic circuits, with an automatized and generic tool.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Algorithm 1
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7

Similar content being viewed by others

Data Availability

The Verilog benchmarks ISCAS85 and ISCAS89 are available at [19] online.

References

  1. Auth C, Aliyarukunju A, Asoro M, Bergstrom D, Bhagwat V, Birdsall J, Bisnik N, Buehler M, Chikarmane V, Ding G, Fu Q, Gomez H, Han W, Hanken D, Haran M, Hattendorf M, Heussner R, Hiramatsu H, Ho B, Jaloviar S, Jin I, Joshi S, Kirby S, Kosaraju S, Kothari H, Leatherman G, Lee K, Leib J, Madhavan A, Marla K, Meyer H, Mule T, Parker C, Parthasarathy S, Pelto C, Pipes L, Post I, Prince M, Rahman A, Rajamani S, Saha A, Santos JD, Sharma M, Sharma V, Shin J, Sinha P, Smith P, Sprinkle M, Amour AS, Staus C, Suri R, Towner D, Tripathi A, Tura A, Ward C, Yeoh A (2017) A 10nm high performance and low-power CMOS technology featuring 3rd generation FINFET transistors, self-aligned quad patterning, contact over active gate and cobalt local interconnects. Proceedings of 2017 IEEE International Electron Devices Meeting (IEDM). pp 29–112914. https://doi.org/10.1109/IEDM.2017.8268472

    Chapter  Google Scholar 

  2. Bottoni C, Coeffic B, Daveau J-M, Gasiot G, Naviner LADB, Roche P (2015) A layout-aware approach to fault injection for improving failure mode prediction. Proceedings of Workshop on Silicon Errors in Logic - System Effects (SELSE), Austin, United States. https://www.researchgate.net/publication/277140022_A_Layout-Aware_Approach_to_Fault_Injection_for_Improving_Failure_Mode_Prediction

  3. Cai J, Chen C (2017) Circuit reliability analysis using signal reliability correlations. Proceedings of 2017 IEEE International Conference on Software Quality, Reliability and Security Companion (QRS-C). pp 171–176. https://doi.org/10.1109/QRS-C.2017.34

    Chapter  Google Scholar 

  4. Cai S, He B, Wang W (2020) Soft error reliability evaluation of nanoscale logic circuits in the presence of multiple transient faults. J Electron Test 36:469–483. https://doi.org/10.1007/s10836-020-05898-x

    Article  Google Scholar 

  5. Cai S, He B, Wu S (2022) An accurate estimation algorithm for failure probability of logic circuits using correlation separation. J Electron Test 38:165–180. https://doi.org/10.1007/s10836-022-05996-y

    Article  Google Scholar 

  6. Chen C, Cai J, Zhan S (2018) A triple-point model for circuit-level reliability analysis. Proceedings of 2018 IEEE International Symposium on Circuits and Systems (ISCAS). pp 1–4. https://doi.org/10.1109/ISCAS.2018.8350987

    Chapter  Google Scholar 

  7. Coeffic B, Daveau J-M, Gasiot G, Pricco AE, Parini S, Scholastique T, Naviner LAB, Roche P (2016) Radiation hardening improvement of a SerDes under heavy ions up to 60 MeV.cm2/mg by layout-aware fault injection. Proceedings of IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE), Austin, Texas, United States. https://www.researchgate.net/publication/299603733_Radiation_Hardening_Improvement_of_a_SerDes_under_Heavy_Ions_up_to_60_MeVcm2mg_by_Layout-Aware_Fault_Injection

  8. de Vasconcelos MCR, Franco DT, Naviner DB, Lirida A, Naviner J-F (2008) Reliability analysis of combinational circuits based on a probabilistic binomial model. Proceedings of 2008 Joint 6th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference. pp 310–313. https://doi.org/10.1109/NEWCAS.2008.4606383

    Chapter  Google Scholar 

  9. Farias CR, Schvittz RB, Balen TR, Butzen PF (2022) Evaluating soft error reliability of combinational circuits using a Monte Carlo based method. Proceedings of 2022 IEEE 23rd Latin American Test Symposium (LATS). pp 1–6. https://doi.org/10.1109/LATS57337.2022.9936911

    Chapter  Google Scholar 

  10. Flaquer JT, Daveau JM, Naviner L, Roche P (2010) Fast reliability analysis of combinatorial logic circuits using conditional probabilities. Microelectron Reliab 50(9):1215–1218. https://doi.org/10.1016/j.microrel.2010.07.058. 21st European Symposium on the Reliability of Electron Devices, Failure Physics and Analysis

    Article  Google Scholar 

  11. Flaquer JT, Daveau JM, Naviner L, Roche P (2011) An approach to reduce computational cost in combinatorial logic netlist reliability analysis using circuit clustering and conditional probabilities. Proceedings of 2011 IEEE 17th International On-Line Testing Symposium. pp 98–103. https://doi.org/10.1109/IOLTS.2011.5993818

    Chapter  Google Scholar 

  12. Franco DT, Vasconcelos MC, Naviner L, Naviner J-F (2008) Reliability of logic circuits under multiple simultaneous faults. Proceedings of 2008 51st Midwest Symposium on Circuits and Systems. pp 265–268. https://doi.org/10.1109/MWSCAS.2008.4616787

    Chapter  Google Scholar 

  13. Franco DT, Correia Vasconcelos M, Naviner L, Naviner J-F (2008) Reliability analysis of logic circuits based on signal probability. Proceedings of 2008 15th IEEE International Conference on Electronics, Circuits and Systems. pp 670–673. https://doi.org/10.1109/ICECS.2008.4674942

    Chapter  Google Scholar 

  14. Goudet E, Treviño LP, Naviner L, Daveau J-M, Roche P (2023) Fast analysis of combinatorial netlists correctness rate based on binomial law and partitioning. Proceedings of 2023 IEEE 24th Latin American Test Symposium (LATS). pp 1–6. https://doi.org/10.1109/LATS58125.2023.10154491

    Chapter  Google Scholar 

  15. Goudet E, Naviner L, Daveau J-M, Roche P (2023) Fast and accurate estimation of correctness rate in combinatorial circuits based on clustering. Proceedings of the 19th IEEE Workshop on Silicon Errors in Logic–System Effects (SELSE). pp 1–6

  16. Herrmann J, Özkaya YM, Uçar B, Kaya K, Ümit V (2019) Çatalyürek: Multilevel algorithms for acyclic partitioning of directed acyclic graphs. SIAM J Sci Comput 41(4):2117–2145. https://doi.org/10.1137/18M1176865

    Article  MathSciNet  Google Scholar 

  17. BuDDy C++ library. https://buddy.sourceforge.net/manual/main.html. Online; Accessed 5 May 2024

  18. https://github.com/steveicarus/iverilog. Accessed 5 May 2024

  19. https://pld.ttu.ee/~maksim/benchmarks/. Accessed 5 May 2024

  20. https://www.arteris.com/blog/top-35-iso-26262-acronyms-andabbreviations#:~:text=The%20single%20point%20fault%20metric,the%20other%20hardware%20architectural%20metric. Accessed 5 May 2024

  21. https://www.boost.org/doc/libs/1_80_0/libs/graph/doc/index.html. Accessed 5 May 2024

  22. ISO (2018) Road vehicles - functional safety. https://www.iso.org. Accessed 5 May 2024

  23. Jahanirad H (2019) CC-SPRA: correlation coefficients approach for signal probability-based reliability analysis. IEEE Trans Very Large Scale Integr VLSI Syst 27(4):927–939. https://doi.org/10.1109/TVLSI.2018.2886027

    Article  Google Scholar 

  24. Jahanirad H, Hosseini M (2020) Reliability estimation of CNTFET-based combinational logic circuits. Proceedings of 2020 28th Iranian Conference on Electrical Engineering (ICEE). pp 1–5. https://doi.org/10.1109/ICEE50131.2020.9260712

    Chapter  Google Scholar 

  25. Jamil M, Mukhopadhay S, Ghoneim M, Shailos A, Prasad C, Meric I, Ramey S (2023) Reliability studies on advanced FINFET transistors of the intel 4 CMOS technology. Proceedings of 2023 IEEE International Reliability Physics Symposium (IRPS). pp 1–5. https://doi.org/10.1109/IRPS48203.2023.10117992

    Chapter  Google Scholar 

  26. Krishnaswamy S, Viamontes GF, Markov IL, Hayes JP (2005) Accurate reliability evaluation and enhancement via probabilistic transfer matrices. Proceedings of Design, Automation and Test in Europe (DATE). pp 282–2871. https://doi.org/10.1109/DATE.2005.47

    Chapter  Google Scholar 

  27. Liu S-E, Li J, Nayak D, Marathe A, Balamukundhan K, Gosavi V, Prajapati A, Kilic B, Pang M, Mittal A (2022) Reliability qualification challenges of SOCS in advanced CMOS process nodes (invited). Proceedings of 2022 IEEE International Reliability Physics Symposium (IRPS). pp 8–11816. https://doi.org/10.1109/IRPS48227.2022.9764426

    Chapter  Google Scholar 

  28. Marques EC, Paiva NM, Naviner LAB, Naviner J-F (2010) A new fault generator suitable for reliability analysis of digital circuits. Proceedings of 2010 Argentine School of Micro-Nanoelectronics, Technology and Applications (EAMTA). pp 41–45

  29. Mohammadi K, Jahanirad H, Attarsharghi P (2011) Fast reliability analysis method for sequential logic circuits. Proceedings of 2011 21st International Conference on Systems Engineering. pp 352–356. https://doi.org/10.1109/ICSEng.2011.70

    Chapter  Google Scholar 

  30. Normand E, Wert JL, Quinn H, Fairbanks TD, Michalak S, Grider G, Iwanchuk P, Morrison J, Wender S, Johnson S (2010) First record of single-event upset on ground, cray-1 computer at Los Alamos in 1976. IEEE Trans Nucl Sci 57(6):3114–3120. https://doi.org/10.1109/TNS.2010.2083687

    Article  Google Scholar 

  31. O’Gorman TJ, Ross JM, Taber AH, Ziegler JF, Muhlfeld HP, Montrose CJ, Curtis HW, Walsh JL (1996) Field testing for cosmic ray soft errors in semiconductor memories. IBM J Res Dev 40(1):41–50. https://doi.org/10.1147/rd.401.0041

    Article  Google Scholar 

  32. Papa D, Markov I (2007) Handbook of approximation algorithms and metaheuristics. https://doi.org/10.1201/9781420010749.ch61

    Book  Google Scholar 

  33. Patel KN, Markov IL, Hayes JP (2003) Evaluating circuit reliability under probabilistic gate-level fault models. Proceedings of the International Workshop on Logic and Synthesis (IWLS). pp 59–64. https://api.semanticscholar.org/CorpusID:6600768

  34. Pontes MF, Butzen PF, Schvittz RB, Rosa SL, Franco DT (2018) The suitability of the SPR-MP method to evaluate the reliability of logic circuits. Proceedings of 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS). pp 433–436. https://doi.org/10.1109/ICECS.2018.8617852

    Chapter  Google Scholar 

  35. Pontes M, Farias CR, Schvittz R, Butzen P, Rosa LS (2021) Survey on reliability estimation in digital circuits. J Integr Circuits Syst. https://doi.org/10.29292/jics.v16i3.568

    Article  Google Scholar 

  36. Pontes MF, Oliveira IFV, Schvittz RB, Rosa LS, Butzen PF (2022) The impact of logic gates susceptibility in overall circuit reliability analysis. Proceedings of 2022 IEEE International Symposium on Circuits and Systems (ISCAS). pp 1610–1614. https://doi.org/10.1109/ISCAS48785.2022.9937573

    Chapter  Google Scholar 

  37. Popp M, Schlag S, Schulz C, Seemaier D (2021) Multilevel acyclic hypergraph partitioning. 2021 Proceedings of the Symposium on Algorithm Engineering and Experiments (ALENEX). pp 1–15. https://doi.org/10.1137/1.9781611976472.1

    Chapter  Google Scholar 

  38. Roy TR, Sadi MS (2021) An efficient approach to tolerate soft errors in combinational circuits. Proceedings of 2021 5th International Conference on Intelligent Computing and Control Systems (ICICCS)(ICICCS). pp 648–655. https://doi.org/10.1109/ICICCS51141.2021.9432122

    Chapter  Google Scholar 

  39. Schivittz RB, Franco DT, Meinhardt C, Butzen PF (2016) A probabilistic model for stuck-on faults in combinational logic gates. Proceedings of 2016 17th Latin-American Test Symposium (LATS). https://doi.org/10.1109/LATW.2016.7483337

    Article  Google Scholar 

  40. Schlag S, Henne V, Heuer T, Meyerhenke H, Sanders P, Schulz C (2016) k-way hypergraph partitioning via n-level recursive bisection. 2016 Proceedings of the Meeting on Algorithm Engineering and Experiments (ALENEX). pp 53–67. https://doi.org/10.1137/1.9781611974317.5

    Chapter  Google Scholar 

  41. Srinivasu B, Sridharan K (2017) A transistor-level probabilistic approach for reliability analysis of arithmetic circuits with applications to emerging technologies. IEEE Trans Reliab 66(2):440–457. https://doi.org/10.1109/TR.2016.2642168

    Article  Google Scholar 

  42. Stempkovskiy A, Telpukhov D, Nadolenko V (2019) Accurate soft error rate reduction using modified resolution method. Proceedings of 2019 IEEE East-West Design & Test Symposium (EWDTS). pp 1–6. https://doi.org/10.1109/EWDTS.2019.8884417

    Chapter  Google Scholar 

  43. Teixeira Franco D (2008) Fiabilité du signal des circuits logiques combinatoires sous fautes simultanées multiples. Theses, Télécom ParisTech. https://pastel.archives-ouvertes.fr/pastel-00005125. Accessed 5 May 2024

  44. Torras Flaquer J, Daveau J-M, Naviner L, Roche P (2010) Handling reconvergent paths using conditional probabilities in combinatorial logic netlist reliability estimation. Proceedings of 2010 17th IEEE International Conference on Electronics, Circuits and Systems. pp 263–267. https://doi.org/10.1109/ICECS.2010.5724504

    Chapter  Google Scholar 

  45. Torras Flaquer J (2011) Méthodes probabilistes d’analyse de fiabilité dans la logique combinatoire. Theses, Télécom ParisTech. https://pastel.archives-ouvertes.fr/pastel-00678275. Accessed 5 May 2024

  46. Wang Z, Zhang G, Ye J, Jiang J (2021) Reliability evaluation of approximate arithmetic circuits based on signal probability. Proceedings of 2021 IEEE International Test Conference in Asia (ITC-Asia). pp 1–6. https://doi.org/10.1109/ITC-Asia53059.2021.9808704

    Chapter  Google Scholar 

  47. Xiao J, Shi Z, Yang X, Lou J (2022) BM-RCGL: benchmarking approach for localization of reliability-critical gates in combinational logic blocks. IEEE Trans Comput 71(5):1063–1076. https://doi.org/10.1109/TC.2021.3071253

    Article  Google Scholar 

  48. Xiao J, Chen W, Lou J, Jiang J, Zhou Q (2022) Identifying reliability-critical primary inputs of combinational circuits based on the model of gate-sensitive attributes. IEEE Trans Comput Aided Des Integr Circuits Syst 41(11):4708–4720. https://doi.org/10.1109/TCAD.2022.3142194

    Article  Google Scholar 

  49. Xiao J, Zhu W, Shen Q, Long H, Lou J (2022) A pruning and feedback strategy for locating reliability-critical gates in combinational circuits. IEEE Trans Reliab. https://doi.org/10.1109/TR.2022.3197787

    Article  Google Scholar 

  50. Yu Z, Zhipeng J, Min W, Hudi P, Shuhua P, Changhong Y (2015) Optimize the PTM circuit calculation using deo algorithm. Proceedings of 2015 Seventh International Conference on Measuring Technology and Mechatronics Automation. pp 757–759. https://doi.org/10.1109/ICMTMA.2015.187

    Chapter  Google Scholar 

  51. Zhan S, Chen C (2022) An efficient method for sequential circuit reliability estimation. Proceedings of 2022 IEEE 65th International Midwest Symposium on Circuits and Systems (MWSCAS). pp 1–4. https://doi.org/10.1109/MWSCAS54063.2022.9859273

    Chapter  Google Scholar 

  52. Ziegler JF, Muhlfeld HP, Montrose CJ, Curtis HW, O’Gorman TJ, Ross JM (1996) Accelerated testing for cosmic soft-error rate. IBM J Res Dev 40(1):51–72. https://doi.org/10.1147/rd.401.0051

    Article  Google Scholar 

  53. Zimpeck A, Meinhardt C, Artola L, Reis R (2021) Reliability challenges in FinFETs. Springer, Cham, pp 29–63. https://doi.org/10.1007/978-3-030-68368-9_3

    Book  Google Scholar 

Download references

Acknowledgements

The authors whish to thank Thomas Fourier for his careful proofreading and technical advices. He was an intern student at STMicroelectronics from June to August 2023, during his second year at École Polytechnique, Palaiseau, France.

Funding

This work was supported by Télécom Paris (Palaiseau, France), and STMicroelectronics (Crolles, France). The authors declare that no funds, grants, or other support were received during the preparation of this manuscript.

Author information

Authors and Affiliations

  1. LTCI, Télécom Paris, Institut Polytechnique de Paris, Palaiseau, France

    Esther Goudet, Luis Peña Treviño & Lirida Naviner

  2. Technology Design Platforms, STMicroelectronics, Crolles, France

    Esther Goudet, Fabio Sureau, Paul Breuil, Luis Peña Treviño, Jean-Marc Daveau & Philippe Roche

Authors
  1. Esther Goudet
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Fabio Sureau
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Paul Breuil
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Luis Peña Treviño
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Lirida Naviner
    View author publications

    You can also search for this author in PubMed Google Scholar

  6. Jean-Marc Daveau
    View author publications

    You can also search for this author in PubMed Google Scholar

  7. Philippe Roche
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Esther Goudet.

Ethics declarations

Conflicts of Interests

The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.

Additional information

Responsible Editor: L. M. Bolzani Pöhls

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Appendix

Appendix

1.1 Some Results on Benchmarks Circuits ISCAS85 and ISCAS89

Table 8 c2670
Full size table
Table 9 c3540
Full size table
Table 10 c5315
Full size table
Table 11 c6288
Full size table
Table 12 c7552labeltab:c7552
Full size table
Table 13 s5378
Full size table
Table 14 s9234
Full size table
Table 15 s13207
Full size table
Table 16 s15850
Full size table
Table 17 s35932
Full size table
Table 18 s38417
Full size table
Table 19 s38584
Full size table

Rights and permissions

Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Goudet, E., Sureau, F., Breuil, P. et al. Analysis of Combinational Circuit Failure Rate based on Graph Partitioning and Probabilistic Binomial Approach. J Electron Test 40, 291–313 (2024). https://doi.org/10.1007/s10836-024-06119-5

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-024-06119-5

Keywords

Search

Navigation

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy