Design of CMOS QVCO with high-Q symmetric differential inductor for wireless LAN

Abstract

Phase noise performance and current consumption of radio frequency (RF) voltage controlled oscillator (VCO) are largely dependent on the Quality (Q) factor of inductor–capacitor (LC) tank. Because the Q-factor of the LC tank is determined by an on-chip differential inductor, we designed, analyzed, and modeled the differential inductor using the high-frequency structure simulator software (HFSS), we could estimate the Q-factor and inductance of the differential symmetric inductor, to enhance the differential Q-factor, reduce current consumption and save silicon area. To verify its use in RF applications, we designed a 5 GHz differential LC-QVCO. Because accurate quadrature local oscillator (LO) signal is a key element in modern wireless transceivers, especially for direct conversion transceivers which are proliferating in a wide range of RF communication systems. Quadrature LO can be obtained by letting VCO oscillate at double the desired frequency and dividing its output. The higher oscillation frequency and frequency division circuitry, however, results in increased power consumption. Quadrature LO can also be obtained by feeding the differential outputs of the VCO oscillating at the desired frequency to a polyphase filter which is usually implemented as an RC network. This scheme results in substantial power consumption as well due to the LO buffers required to compensate for the loss of the passive filter. The third method of quadrature LO generation is QVCO where two symmetric LC-tank VCOs are coupled to each other. To obtain a smaller chip area and higher Q-factor, herein we designed a high-performance symmetric differential inductor for IEEE 802.11a and used it to design a quadrature voltage-controlled oscillator (QVCO). Using the high-frequency structure simulator software (HFSS), we could estimate the Q-factor and inductance of the differential symmetric inductor. Using a 0.13-μm CMOS process, the proposed differential inductor was designed with a width of 20 μm, the outer diameter of 244 μm, and spacing of 2 μm, with a two-turn octagonal structure. At 5 GHz, the Q-factor of the differential inductor was 14. Application of the symmetric differential inductor to Quadrature VCO improves output voltage swing and phase noise by 75% and 10 dB, respectively (for a given power consumption), while silicon chip area is reduced by 35% compared to conventional single inductor equivalents. Furthermore, a QVCO with a wide operating range (20% of 4.5–5.5 GHz) was designed. The phase noise of the QVCO was − 119.6 dBc/Hz at 1 MHz offset from 5.15 GHz. The output phase error of the proposed QVCO was less than 0.5°, and the total power consumption at 1.2 V was 5.4 mW. The QVCO proposed in this study was designed to achieve a smaller chip area and higher Q-factor, and will be available for use in IEEE 802.11a transceiver chips for 5.15–5.35 GHz Wireless-LAN in the future.