Skip to main content

Advertisement

Log in

Design of Low Power VLSI Architecture of Line Coding Schemes

  • Published:
Wireless Personal Communications Aims and scope Submit manuscript

Abstract

Line coding is used to tune the wave form based on the properties of the physical channel. The wave form is tuned in voltage or current or photon levels for the proper digital data transport. Bi-Phase Mark Coding (BMC), Bi-Phase Space Coding (BPSC) and Phase Coding (PC) are used as Line coding techniques. Most of the existing systems discuss about any one of the coding techniques among BPSC and PC. Limited number of systems discusses about BPSC and PC generation and degeneration operations together. The first objective of the proposed work is to design BMC, BPSC and PC techniques Generation and Degeneration operation in a single system. The second objective is to reduce the area and power consumption by modifying the number of MOS devices used for the system design and by adjusting the width of the MOS devices. The system is designed using Cadence® Virtuoso Schematic Editor at 180 nm technology. Simulation is done using Cadence® Virtuoso ADE and the Layout is designed using Cadence® Virtuoso Layout Suite XL. The proposed system requires 59 transistors and occupies 1632.88 µm2. Required power can be reduced up to 33% by using any one of the suitable coding among BMC, BPSC and PC based on the properties of the input data signal. If the input data is having equal possibility of high and low level signals, PC technique will be suitable for power reduction. If the high level beats the low level, BPSC technique will be suitable. If the low level beats the high level, BMC technique will be suitable.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17
Fig. 18
Fig. 19
Fig. 20
Fig. 21
Fig. 22
Fig. 23
Fig. 24
Fig. 25

Similar content being viewed by others

References

  1. Lee, Y.-H., Pan, C.-W., & Tsai, F.-H. (2015). VLSI Architecture design of FM0/Manchester codec with 100% hardware utilization rate for DSRC-based sensor nodes in ITS applications. IEEE Sensors Journal, 15(12), 6875–6889.

    Article  Google Scholar 

  2. Benabes, P., Gauthier, A., & Oksman, J. (2003). A Manchester code generator running at 1 GHz. In Proceedings of ieee, international conference on electronics, circuits and systems (Vol. 3, pp. 1156–1159).

  3. Hung, Y.-C., Kuo, M.-M., Tung, C.-K., & Shieh, S.-H. (2009). High speed CMOS chip design for Manchester and Miller encoder. In Intelligent information hiding and multimedia signal processing (pp. 538–541).

  4. Lee, Y.-H., & Pan, C.-W. (2015). Fully reused VLSI architecture of FM0/Manchester encoder using SOLS technique for DSRC applications. IEEE Transactions On Very Large Scale Integration (VLSI) Systems, 23(1), 18–29.

    Article  Google Scholar 

  5. Watkinson, J. (1994). The art of digital audio (2nd ed.). Oxford: Focal Press. ISBN 0-240-51320-7.

    Google Scholar 

  6. Data Encoding Techniques. http://web.cs.wpi.edu/~rek/Undergrad_Nets/B06/Data_Encoding.pdf. Accessed 28 Jan 2016.

  7. Forster, R. Manchester encoding. http://katzen.me.uk/Books/quintessential/chapters_1ed/manchester.htm. Accessed 28 Jan 2016.

  8. Rida, A., Yang, L., & Tentzeris, M. M. (2010). RFID-enabled sensor design and applications. Norwood: Artech House.

    Google Scholar 

  9. Fairhurst, G. Manchester encoding. http://www.erg.abdn.ac.uk/users/gorry/course/phy-pages/man.html. Accessed 28 Jan 2016.

  10. Lakshmi, N. V., & Rajaram, M. (2013). An octo coding technique to reduce energy transition in low power VLSI circuits. International Journal of Research in Engineering and Technology, 02(11), 674–679.

    Article  Google Scholar 

  11. Mishra, S. S., Agrawal, A. K., & Nagaria, R. K. (2010). A comparative performance analysis of various CMOS design techniques for XOR and XNOR circuits. International Journal on Emerging Technologies, 1(1), 1–10.

    Google Scholar 

  12. Marković, C., Nikolić, B., & Oklobdžijac, V. G. (2000). A general method in synthesis of pass-transistor circuits. Microelectronics Journal, 31, 991–998.

    Article  Google Scholar 

  13. Heo, S., Krashinsky, R., & Asanovic, K. (2007). Activity–sensitive flip-flop and latch selections for reduced energy. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 15(9), 1060–1064.

    Article  Google Scholar 

  14. Signal Encoding. http://www.aast-compeng.info/images/encodingtech.pdf. Accessed 28 Jan 2016.

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to A. Andrew Roobert.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Rajakumar, G., Andrew Roobert, A. Design of Low Power VLSI Architecture of Line Coding Schemes. Wireless Pers Commun 99, 1455–1473 (2018). https://doi.org/10.1007/s11277-018-5286-4

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11277-018-5286-4

Keywords

Navigation

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy