Abstract
A novel read circuit for low power dual bit-line SRAM is proposed. The local sensing circuit uses differential cell current and regenerative feedback to turn into latch. This allows lower of two bit-line currents to flow into the global sensing stage which converts to suitable CMOS voltage level. The proposed local sensing circuit uses cascode amplifier and substrate bias for reduced delay of latch formation. Simulation is done using TSMC 32 nm and compared with some prevalent sensing schemes. The proposed circuit consumes average power only 30% of other prominent latch-type scheme having bit-line and data-line capacitance between100 to 200fF representing various SRAM macro structures. Leakage current of proposed circuit shows 18% improvement over the other latch-type schemes. The proposed circuit offers improved current sensitivity, improved delay by 56% compared to earlier suggested schemes and latching operation at 0.2 V supply, ensuring small memory cell size with reduced leakage with improved stability and reliability. Rigorous simulations were done for inter-die process variation, latching and overall sensing delay and clock frequency ranging from 200 MHz up to 1 GHz. The proposed scheme exhibits reduced latching and sensing delay, leakage etc. over wide temperature range and varying memory sizes. This enables its effective deployment in wireless sensor nodes.















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Bhatnagar, V., Pandey, M.K. & Pandey, S. A Variation Tolerant Nanoscale SRAM for Low Power Wireless Sensor Nodes. Wireless Pers Commun 124, 3235–3251 (2022). https://doi.org/10.1007/s11277-022-09510-7
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DOI: https://doi.org/10.1007/s11277-022-09510-7