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A Variation Tolerant Nanoscale SRAM for Low Power Wireless Sensor Nodes

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Abstract

A novel read circuit for low power dual bit-line SRAM is proposed. The local sensing circuit uses differential cell current and regenerative feedback to turn into latch. This allows lower of two bit-line currents to flow into the global sensing stage which converts to suitable CMOS voltage level. The proposed local sensing circuit uses cascode amplifier and substrate bias for reduced delay of latch formation. Simulation is done using TSMC 32 nm and compared with some prevalent sensing schemes. The proposed circuit consumes average power only 30% of other prominent latch-type scheme having bit-line and data-line capacitance between100 to 200fF representing various SRAM macro structures. Leakage current of proposed circuit shows 18% improvement over the other latch-type schemes. The proposed circuit offers improved current sensitivity, improved delay by 56% compared to earlier suggested schemes and latching operation at 0.2 V supply, ensuring small memory cell size with reduced leakage with improved stability and reliability. Rigorous simulations were done for inter-die process variation, latching and overall sensing delay and clock frequency ranging from 200 MHz up to 1 GHz. The proposed scheme exhibits reduced latching and sensing delay, leakage etc. over wide temperature range and varying memory sizes. This enables its effective deployment in wireless sensor nodes.

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Data Availability

The data used to support the findings of this study are available from the corresponding author upon request.

References

  1. Sachdeva, A., & Tomar, V. K. (2021). A Multi-bit error upset immune 12T SRAM cell for 5G satellite communications. Wireless Personal Communications, 120, 2201–2225.

    Article  Google Scholar 

  2. K.-S. Yeo, W.-L. Goh, Z.-H. Kong, Q-X. Zhang and W.-G. Yeo, (2002) High-performance low-power current sense amplifier using a cross-coupled current-mirror Configuration, IEEE Proceedings - Circuits, Devices and System 149(516): 308–314.

  3. Seng, Y. K. (1998). New current conveyor for high-speed low-power current sensing. IEEE Proceedings of Devices and Systems, 145(2), 85.

    Article  Google Scholar 

  4. Witch, B., Nirschil, T., & Landsiedel, D. S. (2000). (2000) Yield and speed optimization of a latch-type voltage sense amplifier. IEEE Journal of Solid-State Circuit, 39(7), 1148–1158.

    Google Scholar 

  5. Singh, R., & Baht, N. (2004). An offset compensation technique for latch type sense amplifiers in high-speed low-power SRAMs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12(6), 652–657.

    Article  Google Scholar 

  6. Do, A.-T., Kong, Z. H., Yeo, K. S., & Low, J. Y. S. (2011). Design and sensitivity analysis of a new current-mode sense amplifier for low-power SRAM. IEEE Transactions on Very Large Scale Integration Systems, 19(2), 196–204.

    Article  Google Scholar 

  7. Attarzadeh, H., & Sharifkhani, M. (2014). An auto calibrated, dual mode SRAM macro using a hybrid offset cancelled sense amplifier. Microelectronics Journal, 45(6), 781–792.

    Article  Google Scholar 

  8. Lorenzo, R., & Chaudhury, S. (2017). A novel SRAM design with a body-bias controller circuit for low leakage, high-speed and improved stability. Wireless Personal Communications, 94(4), 3513–3529.

    Article  Google Scholar 

  9. Reniwal, B., & Vishvakarma, S. K. (2013). A reliable, process-sensitive-tolerant hybrid sense amplifier for ultra low power SRAM. International Journal of Electronics and Electrical Engineering, 1(1), 34–38.

    Article  Google Scholar 

  10. AK Singh, MM Seong, CMR Prabhu (2013) A proposed eleven-transistor (11-T) CMOS SRAM cell for improved read stability and reduced read power consumption, Journal of Circuits, Systems, and Computers 12(7) 1350062–1–1350062–12.

  11. Gavaskar, K., Ragupathy, U. S., & Malini, V. (2019). Proposed design of 1 KB memory array structure for cache memories. Wireless Personal Communications, 109(2), 823–847.

    Article  Google Scholar 

  12. Singh, M. K., & Akashe, S. (2018). Design and enactment of diverse low power techniques based schmitt trigger. Wireless Personal Communications, 101, 2105–2125.

    Article  Google Scholar 

  13. MA Turi, JG Delgado-Frias (2020) Effective low leakage 6T and 8T FinFET SRAMs: Using cells with reverse-biased FinFETs, near-threshold operation, and power gating. IEEE Transactions on Circuits and Systems II: Express Briefs 67(4): 8736268, pp. 765–769.

  14. Lorenzo, R., & Pailly, R. (2020). Single bit-line 11T SRAM cell for low power and improved stability. IET Computers and Digital Techniques, 14(3), 114–121.

    Article  Google Scholar 

  15. Bhatnagar, V., Kumar, P., & Pandey, S. (2018). A dual Vt disturb-free subthreshold SRAM with write-assist and read isolation (wari) and write-back for half-selected cells. Journal of Semiconductors, 39(2), 025001.

    Article  Google Scholar 

  16. Lai, Y.-C., & Huang, S. Y. (2008). A resilient and power-efficient automatic-power-down sense amplifier for SRAM design. IEEE Transactions on Circuits and Systems—II: Express briefs, 55(10), 1031.

    Article  Google Scholar 

  17. Fan, M. L., Hu, V.P.-H., Chen, Y. N., Su, P., & Chuang, C.-T. (2012). Variability analysis of sense amplifier for FinFET subthreshold SRAM applications”. IEEE Transactions on Circuits and Systems—II: Express Briefs, 59(12), 878–882.

    Article  Google Scholar 

  18. Pal, S., Bose, S., & Islam, A. (2020). A low power SRAM cell design for wireless sensor network applications”. Microsystem Technologies, 26(7), 2325–2335.

    Article  Google Scholar 

  19. K Monga, N Chaturved, S Gurunarayanan (2020) Design of a novel CMOS/MTJ-based multibit SRAM cell with low store energy for IoT applications. International Journal of Electronics 107(6): 899–14.

  20. Bhatnagar, V., Kumar, P., Pandey, N., & Pandey, S. (2018). A boosted negative bit-line SRAM with write assisted cell in 45nm CMOS technology. Journal of Semiconductors (IOP Science), 39(2), 025002.

    Article  Google Scholar 

  21. I Ullah, JS Yang, J Chung (2020) ER-TCAM: A soft-error-resilient SRAM-based ternary content-addressable memory for FPGAs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28(4): 1084–1088.

  22. Kumar, H., & Tomar, V. K. (2021). A review on performance evaluation of different low power SRAM cells in nano-scale era. Wireless Personal Communications, 117, 1959–1984.

    Article  Google Scholar 

  23. F Tachibana, O Hirabayashi, Y Takeyama, M Shizuno, A Kawasumi, K Kushida, A Suzuki, Y Niki, S Sasaki, T Yabe, Y Unekawa (2014) A 27% active and 85% standby power reduction in dual power supply SRAM using BL power calculator and digitally controllably retention circuit. IEEE Journal of Solid-State Circuits 49(1): 118–126.

  24. MSM Siddiqui, ZC Lee, TTH Kim (2021). A 16-kb 9T ultralow-voltage SRAM with column-based split cell-VSS, data-aware write-assist, and enhanced read sensing margin in 28-nm FDSOI. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 29(10): 1707–1719.

  25. MH Sheu, CM Tsai, MY Tsai, SC Hsia, SM Morsalin, JF Lin (2021) A 0.3 V PNN based 10T SRAM with pulse control based read-assist and write data-aware schemes for low power applications. Sensors 21(19):6591.

  26. Kaur, H., Sarin, R. K., Anand, S., et al. (2021). 6-T and 7-T SRAM cell design using doping-less charge plasma TFET. SILICON, 13, 4091–4100.

    Article  Google Scholar 

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Correspondence to Sujata Pandey.

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Bhatnagar, V., Pandey, M.K. & Pandey, S. A Variation Tolerant Nanoscale SRAM for Low Power Wireless Sensor Nodes. Wireless Pers Commun 124, 3235–3251 (2022). https://doi.org/10.1007/s11277-022-09510-7

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