Abstract
Translation validation was invented in the 90’s by Pnueli et al. as a technique to formally verify the correctness of code generators. Rather than certifying the code generator or exhaustively qualifying it, translation validators attempt to verify that program transformations preserve semantics. In this work, we adopt this approach to formally verify that the clock semantics and data dependence are preserved during the compilation of the Signal compiler. Translation validation is implemented for every compilation phase from the initial phase until the latest phase where the executable code is generated, by proving the transformation in each phase of the compiler preserves the semantics. We represent the clock semantics, the data dependence of a program and its transformed counterpart as first-order formulas which are called clock models and synchronous dependence graphs (SDGs), respectively. We then introduce clock refinement and dependence refinement relations which express the preservations of clock semantics and dependence, as a relation on clock models and SDGs, respectively. Our validator does not require any instrumentation or modification of the compiler, nor any rewriting of the source program.
Similar content being viewed by others
References
Berry G. The foundations of Esterel. In: Proof, Language, and Interaction. 2000, 425–454
Halbwachs N. A synchronous language at work: the story of lustre. In: Proceedings of the 3rd ACM and IEEE International Conference on Formal Methods and Models for Co-Design. 2005, 3–11
Gamati A. Designing embedded systems with the Signal programming language: synchronous, reactive specification. Springer Publishing Company, Incorporated, 2009
Inria. The coq proof assitant. http://coq.inria.fr
Do-178c. http://rtca.org
Pnueli A, Siegel M, Singerman E. Translation validation. Tools and Algorithms for the Construction and Analysis of Systems, Springer, 1998-151-166
Pnueli A, Shtrichman O, Siegel M. Translation validation: from Signal to C. Lecture Notes in Computer Science, 1999,1710: 231–255
Inria. The compcert project. http://compcert.inria.fr
Necula G C. Translation validation for an optimizing compiler. ACM SIGPLAN Notices, 2000, 35(5): 83–94
Tristan J B, Govereau P, Morrisett G. Evaluating value-graph translation validation for LLVM. ACM Sigplan Notices, 2011, 295–305
Dutertre B, Moura de L. Yices Sat-solver. http://yices.csl.ri.com
Espresso, Polychrony toolset. http://www.irisa.fr/espresso/Polychrony
Benveniste A, Le Guernic P. Hybrid dynamical systems theory and the signal language. IEEE Transactions on Automatic Control, 1990, 35(5): 535–546
Gautier T, Le Guernic P, Besnard L. Signal: a declarative language for synchronous programming of real-time systems. Lecture Notes in Computer Science, 1987, 274: 257–277
Abramsky S, Jung A. Domain theory. Abramsky S, Gabbay D M, Maibaum T S E, ed(s). Handbook of Logic in Computer Science: Volume 3: Semantic Structures. Oxford: Clarendon Press, 1994, 1–168
Kahn G. The semantics of a simple language for parallel programming. IFIP Congress, 1974, 471–475
Besnard L, Gautier T, Le Guernic P, Talpin J P. Compilation of polychromous data flow equations. Synthesis of Embedded Software, Springer, 2010, 1–40
Ackermann W. Solvable Cases of the Decision Problem. Vol. 12. North-Holland Pub. Co., 1954
Le Guernic P, Gautier T. Data-flow to von neumann: the signal approach. Rapports de recherche-INRIA
Gamatié A, Gonnord L. Static analysis of synchronous programs in signal for effcient design of multi-clocked embedded systems. ACM Sigplan Notices, 2011, 46(5): 71–80
Allen F E. Control flow analysis. ACM SIGPLAN Notices, 1970, 1–19
Biere A, Heule M, Maaren v H, Walsh T. Handbook of Satisfiability. Frontiers in Artificial Intelligence and Applications, vol. 185, 2009
Ma-eïs O, Le Guernic P. Combining dependability with architectural adaptability by means of the signal language. Lecture Notes in Computer Science, 1993(724): 99–110
Barrett C, Ranise S, Stump A, Tinelli C. The satisfiability modulo theories library (SMT-LIB). http://www.SMT-LIB.org, 2008
Bryant R E. Graph-based algorithms for boolean function manipulation. IEEE Transactions on Computers, 1986, 100(8): 677–691
Leroy X. Formal certification of a compiler back-end or: programming a compiler with a proof assistant. ACM SIGPLAN Notices, 2006, 41(1): 42–54
Tristan J B, Leroy X. A simple, verified validator for software pipelining. ACM SIGPLAN Notices, 2010, 45(1):83–92
Biernacki D, Colaço J L, Hamon G, Pouzet M. Clock-directed modular code generation for synchronous data-flow languages. ACM SIGPLAN Notices, 2008, 43(7): 121–130
Ngo V C, Talpin J P, Gautier T, Le Guernic P, Besnard L. Formal verification of compiler transformations on polychronous equations. Lecture Notes in Computer Science, 2012, 7321:113–127
Author information
Authors and Affiliations
Corresponding author
Additional information
Van Chan Ngo is a PhD student at INRIA. His main research interests are design, development, and formal verification of embedded real-time systems, and compiler theory. He finished the engineer degree with excellent ranking in Computer Engineering at the Talent Training Center, Hanoi University of Technology in 2005, and the graduate degree in Applied Mathematics and Computer Science within the French government scholarship program at Verimag Laboratory, Université de Grenoble 1, Grenoble, France in 2008.
Jean-Pierre Talpin is a senior researcher with INRIA and leads the project team who develops the open-source Polychrony environment. He received his PhD from Université Paris VI Pierre et Marie Curie in 1993. He then was a research associate with the European Computer-Industry Research Centre in Munich before to join INRIA in 1995. Jean-Pierre edited two books with Elsevier and Springer, guestedited more than ten special issues of ACM and IEEE scientific journals, and authored more than 20 journal articles and book chapters and 60 conference papers. He received the 2004 ACM Award for the most influential POPL paper, for his 2nd conference paper with Mads Tofte, and the 2012 LICS Test of Time Award, for his 1st conference paper with Pierre Jouvelot.
Thierry Gautier is a researcher with INRIA. He received the graduate degree from the Institut National des Sciences Appliquées, Rennes, France, in 1980, and the PhD degree in computer science from University of Rennes 1 in 1984. He is one of the designers of the Signal language, the polychronous model of computation and the Polychrony toolset. His main research interests lie in the safe design of complex embedded systems, including formal modeling, formal validation, and transformations of models to target architectures.
Paul Le Guernic graduated from Institut National des Sciences Appliquées de Rennes in 1974. He performed his Thèse de troisième cycle in Computer Science in 1976. From 1978 to 1984 he had a research position at INRIA. He is Directeur de Recherche in this institute since 1985. He has been head of the “Programming Environment for Realtime Applications” group, which has defined and developed the Signal language. His main current interests include the development of theories, tools, and methods, for the design of real-time embedded heterogeneous systems. He is one the architects of the Polychrony toool set.
Loïc Besnard is currently a senior engineer at CNRS, France. He received his PhD degree in computer science from University of Rennes, France (1992). His research interests include the software reliability for the design of embedded systems: modeling, temporal analysis, formal verification, simulation, and synthesis of embedded systems. He is involved in the development of the Polychony toolset based on the synchronous language Signal.
Rights and permissions
About this article
Cite this article
Ngo, V.C., Talpin, JP., Gautier, T. et al. Formal verification of synchronous data-flow program transformations toward certified compilers. Front. Comput. Sci. 7, 598–616 (2013). https://doi.org/10.1007/s11704-013-3910-8
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s11704-013-3910-8