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FPGA implementation novel lightweight MBRISI cipher

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Abstract

The advancement Internet of things has led to an increasing exchange of information. Privacy and security has become a major concern. In this emerging ubiquitous computing world, Lightweight cryptographic algorithms are tailor made to secure the information in low resource devices for the Internet of Things (IoT) applications. In this paper an area efficient, high performance lightweight cipher, MBRISI cipher is proposed. The cipher is a combination of BRIGHT family of ciphers comprises of Addition-Modulo, Rotation and EX-OR (ARX) operations and the modification of SIMON cipher and also a novel lightweight key generation algorithm is used. The proposed cipher is better than the state of art existing lightweight ciphers and can be extended to support different block sizes and key sizes for the low resource environments like the IoT. The proposed MBRISI cipher encrypts a 32-bit plaintext employing a 64-bit key is implemented and then analyzed. The cipher is implemented in MATLAB tool (for software implementation) and is analyzed for correlation coefficient, entropy and histogram, avalanche criterion and Key-sensitivity. The Verilog code is written and simulated using Xilinx-Vivado tool and synthesized using FPGA’s Artix-7 and Basys-3.

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Acknowledgements

The authors would like to thank the Department of Electronics and Communication and Engineering, AJ Institute of Engineering, Department of Computer Science and Engineering NMAMIT Nitte and Visvesvaraya Technological University, Belagavi for the support for carrying out the research work.

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Authors and Affiliations

  1. Department of Computer Science and Engineering, N M A M Institute of Technology, Karkala, Karnataka, India

    Asmita Poojary

  2. Department of E & C Engineering, A J Institute of Engineering and Technology, Kottara, Mangaluru, Karnataka, India

    V. G. Kiran Kumar

  3. Department of Information Science and Engineering, A J Institute of Engineering and Technology, Kottara, Mangaluru, Karnataka, India

    H. R. Nagesh

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  1. Asmita Poojary
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  3. H. R. Nagesh
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Correspondence to V. G. Kiran Kumar.

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Both Asmita Poojary and Dr. V.G. Kiran Kumar are first authors while Dr. H.R. Nagesh is second author.

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Poojary, A., Kiran Kumar, V.G. & Nagesh, H.R. FPGA implementation novel lightweight MBRISI cipher. J Ambient Intell Human Comput 14, 11625–11637 (2023). https://doi.org/10.1007/s12652-022-03726-y

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