Abstract
In this work we investigate the problem of detection and location ofsingle and unlinked multiple k-coupling faults in n × 1 random-access memories (RAMs). This fault model covers allcrosstalks between any k cells in n × 1 RAMs. The problem of memory testing has been reduced to the problem of the generationof (n,k-1)-exhaustive backgrounds. We have obtained practical test lengths, for a memory size around 1 M, for detecting up to6-couplings by exhaustive tests and up to 9-couplings bynear-exhaustive tests. The best known test algorithms up to nowprovide for the detection of 5-couplings only in a 1 M memory, usingexhaustive tests. Beyond these parameters, test lengths wereimpractical. Furthermore, our method for generation of(n,k-1)-exhaustive backgrounds yields short test lengths givingrise to considerably shorter testing times than the present mostefficient tests for large n and for k greater than 3. Our test lengths are 50% shorter than other methods for the case of detectingup to 5-couplings in a 1 Mbit RAM. The systematic nature of both ourtests enables us to use a built-in self-test (BIST) scheme, for RAMs, with low hardware overhead. For a 1Mbit memory, the BIST areaoverhead for the detection of 5-couplings is less than 1% for SRAMand 6.8% for a DRAM. For the detection of 9-couplings with 99% or higher probability, the BIST area overhead is less than 0.2% forSRAM and 1.5% for DRAM.
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References
A.J. van de Goor, Testing Semiconductor Memories, Theory and Practice,John Wiley and Sons, Chichester, UK, 1991.
J.P. Hayes, “Detection of Pattern-Sensitive Faults in Random-Access Memories,” IEEE Transactions on Computers,Vol. c-24, pp. 150–157, 1975.
R. Nair, S.M. Thatte, and J.A. Abraham, “Efficient Algorithms for Testing Semiconductor Random-Access Memories,” Dig. of Papers, 7th Intl. Conf. on Fault-Tolerant Computing, Los Angels, CA, 1977, pp. 81–87.
D.S. Suk and S.M. Reddy, “Test Procedures for a Class of Pattern-Sensitive Faults in Semiconductor Random-Access Memories,” IEEE Transactions on Computers, Vol. c-29, pp. 419–429, 1980.
B.F. Cockburn, “Deterministic Tests for Detecting Single V-Coupling Faults in RAMs,” J. Electronic Testing: Theory and Applications, Vol. 5, No.1, pp. 91–113, 1994.
M.G. Karpovsky, V.N. Yarmolik, and A.J van de Goor, “Pseudoexhaustive Word-Oriented DRAM Testing,” Proc. European Design and Test Conference, 1995, pp. 24–38.
B.F. Cockburn, “A 20 MHz Test Vector Generator for Producing Tests that Detect Single 4-and 5-Coupling Faults in RAMs,” Records of the IEEE Int. Workshop on Memory Testing, San Jose, CA, 1993, pp. 10–14.
J. Savir, W.H. McAnney, and S.R. Vecchio, “Testing for Coupled Cells in Random Access Memories,” IEEE Trans. on Computers, Vol. c-40, No.10, pp. 1177–1180, 1991.
R. David, A. Fuentes, and B. Courtois, “Random Pattern Testing versus Deterministic Testing of RAMs,” IEEE Transaction on Computers, Vol. c-38, pp. 637–650, 1989.
R. David, J.A. Brzozowski, and H. Jurgensen, “Random Test Lengths for Bounded Faults in RAMs,” Proc. of the Third European Test Conference, Rotterdam, 1993, pp. 149–158.
M.G. Karpovsky and V.N. Yarmolik, “Transparent Memory Testing for Pattern Sensitive Faults,” Proc. International Test Conference, 1994, pp. 862–867.
D.T. Tang and C.L. Chen, “Iterative Exhaustive Pattern Generation for Logic Testing,” IBM J. of Res. Develop., Vol. 28, No.2, pp. 212–219, 1984.
L.B. Levitin and M.G. Karpovsky, “Traveling Salesman Problem in the Space of Binary Vectors,” Proc. of International Symp. on Information Theory, Norway, 1994, p. 316.
N.J.A. Sloane, “Covering Arrays and Intersecting Codes,” J. Combinatorial Design, Vol. 1, No.1, pp. 51–64, 1993.
D.T. Tang and L.S. Woo, “Exhaustive Test Pattern Generation with Constant Weight Vectors,” IEEE Transaction on Comp., Vol. c-32, No.12, pp. 1145–1150, 1983.
L.B. Levitin and M.G. Karpovsky, “Efficient Exhaustive Test Based on MDS Codes,” Proc. of IEEE International Symposium on Information Theory, Ann Arbor, 1986, p. 64.
L.B. Levitin and M.G. Karpovsky, “Exhaustive Testing of Almost all Devices with Outputs Depending on Limited Number of Inputs,” Open Systems and Information Dynamics, Vol. 2, No.3, pp. 1–16, 1994.
F.J. MacWilliams and N.J.A. Sloane, The Theory of Error-Correcting Codes, North Holland Publishing Company, Amsterdam, 1977.
M. Franklin and K.K. Saluja, “Built-In Self-Testing of Random-Access Memory,” IEEE Transaction on Computers, Vol. 23, pp. 45–55, 1990.
A.K. Chandra, L.T. Kou, G. Markowsky, and S. Zaks, “On Sets of Boolean n-Vectors with all k-Projections Surjective,” Acta Informatica, Vol. 20, pp. 103–111, 1983.
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Das, D., Karpovsky, M. Exhaustive and Near-Exhaustive Memory Testing Techniques and their BIST Implementations. Journal of Electronic Testing 10, 215–229 (1997). https://doi.org/10.1023/A:1008215624768
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DOI: https://doi.org/10.1023/A:1008215624768