diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 0000000..9d42b5b --- /dev/null +++ b/.gitmodules @@ -0,0 +1,6 @@ +[submodule "vivado_design_space_explorer_template"] + path = vivado_design_space_explorer_template + url = https://github.com/pConst/vivado_design_space_explorer_template.git +[submodule "quartus_design_space_explorer_template"] + path = quartus_design_space_explorer_template + url = https://github.com/pConst/quartus_design_space_explorer_template.git diff --git a/ActionBurst.v b/ActionBurst.v deleted file mode 100644 index 0980d7c..0000000 --- a/ActionBurst.v +++ /dev/null @@ -1,84 +0,0 @@ -//-------------------------------------------------------------------------------- -// ActionBurst.v -// Konstantin Pavlov, pavlovconst@gmail.com -//-------------------------------------------------------------------------------- - -// INFO -------------------------------------------------------------------------------- -// Module is designed to generate one-shot trigger pulses on multiple channels (default is 8) -// Every output channel is triggered only once -// Channels get triggered in sequense from out[0] to out[8] -// That is useful when you need to start some tasks in exact order, but there are no convinient signals to line them up. -// Instance of ActionBurst() is started by high level on start input and the only way to stop generation before all channels get triggered is to reset the instance - - -/* --- INSTANTIATION TEMPLATE BEGIN --- - -ActionBurst AB1 ( - .clk( ), - .nrst( 1'b1 ), - .step_wdth( ), - .start( ), - .busy( ), - .out( ) - ); -defparam AB1.WIDTH = 8; - ---- INSTANTIATION TEMPLATE END ---*/ - - -module ActionBurst(clk,nrst,step_wdth,start,busy,out); - -parameter WIDTH = 8; - -input wire clk; -input wire nrst; -input wire [31:0] step_wdth; // Module buffers step_wdth in PG instance on the SECOND cycle ater start applyed! -input wire start; -output reg busy = 0; -output wire [(WIDTH-1):0] out; - -wire PgOut; -reg [31:0] state = 0; -//reg [31:0] step_wdth_buf = 0; // buffering is done in PG - -PulseGen PG( - .clk( clk ), - .nrst( start || busy ), - .low_wdth( step_wdth[31:0] ), - .high_wdth( 32'b1 ), - .rpt( 1'b1 ), - .start( busy ), - .busy( ), - .out( PgOut ) - ); - -always @ (posedge clk) begin - if (~nrst) begin - state[31:0] <= 0; - end else begin - if (~busy) begin - if (start) begin // buffering input values - state[31:0] <= 0; - //step_wdth_buf[31:0] <= step_wdth[31:0]; // buffering is done in PG - busy <= 1; - end // start - end else begin - if (PgOut) begin - if (state != (WIDTH-1)) begin - state[31:0] <= state[31:0] + 1'b1; - end else begin - busy <= 0; - end // state - end // PgOut - end // busy - end // nrst -end - -genvar i; -generate - for (i=0; i -All the code is highly reusable across typical FPGA projects and mainstream FPGA vendors.
-Please feel free to contact me in case you found any code issues.
-Also, give me a pleasure, tell me if the code has got succesfully implemented in your hobby, scientific or industrial projects!
+Hi! This is a collection of Verilog SystemVerilog synthesizable modules. -Konstantin Pavlov, pavlovconst@gmail.com +All the code is highly reusable across typical FPGA projects and mainstream FPGA vendors. -The code is licensed under CC BY-SA 4_0.
-You can remix, transform, and build upon the material for any purpose, even commercially
-You must provide the name of the creator and distribute your contributions under the same license as the original
+Please feel free to make pull requests or contact me in case you spot any code issues. -Directories description: ------------------------ - -| DIRECTORY | DESCRIPTION | -|-----------|-------------| -| Advanced Synthesis Cookbook/ | useful code from Altera's cookbook | -| KCPSM6_Release9_30Sept14/ | Xilinx's Picoblaze soft processo | -| pacoblaze-2.2/ | version of Picoblaze adapted for Altera devices | -| example_projects/ | FPGA project examples | -| benchmark_projects/ | compilation time benchmarks for a dosen of FPGA types | -| scripts/ | useful TCL scripts | - -Scripts description: --------------------- - -| SCRIPT | DESCRIPTION | -|--------|-------------| -| scripts/allow_undefined_ports.tcl | allows generation of test projects with undefined pins for Vivado IDE | -| scripts/compile_quartus.tcl | boilerplate script for commandline project compilation in Quartus IDE | -| scripts/convert_sof_to_jam.bat | Altera/Intel FPGA configuration file converter | -| scripts/convert_sof_to_rbf.bat | another Altera/Intel FPGA configuration file converter | -| scripts/iverilog_compile.tcl | complete script to compile Verilog sources with iverilog tool and run simulation in gtkwave tool | -| scripts/modelsim_compile.tcl | Modelsim no-project-mode compilation script | -| scripts/post_flow_quartus.tcl | custom reporting or report analisys for Intel Quartus IDE | -| scripts/post_flow_vivado.tcl | custom reporting or report analisys for Xilinx Vivado IDE | -| scripts/program_all.bat | command line programmer example for Altera/Intel FPGAs | -| scripts/project_version_auto_increment.tcl | project version autoincrement script for Quartus IDE | -| scripts/quartus_system_console_init.tcl | initialization script for reading/writing Avalon-MM through JTAG-to-Avalon-MM bridge IP | -| scripts/set_project_directory.tcl | changes current directory to match project directory in Vivado IDE | -| scripts/write_avalon_mm_from_file.tcl | writing bulk binary data from binary file to Avalon-MM through JTAG-to-Avalon-MM bridge IP | - -Modules description: +Also, give me a pleasure, tell me if the code has got succesfully implemented in your hobby, scientific or industrial projects! + +Licensing +--------- +The code is licensed under CC BY-SA 4_0 +That means, that you can remix, transform, and build upon the material for any purpose, even commercially. +However, YOU MUST provide the name of the creator and distribute your contributions under the same license as the original. + +Contents description -------------------- - -| MODULE | DESCRIPTION | -|--------|-------------| -| ActionBurst.v | multichannel one-shot triggering module | -| ActionBurst2.v | multichannel one-shot triggering with variable steps | -| adder_tree.sv | adding multiple values together in parallel | -| bin2gray.sv | combinational Gray code to binary converter | -| bin2pos.sv | converts binary coded value to positional (one-hot) code | -| clk_divider.sv | wide reference clock divider | -| debounce.v | two-cycle debounce for input buttons | -| delay.sv | useful module to make static delays or to synchronize across clock domains | -| dynamic_delay.sv | dynamic delay for arbitrary input signal | -| edge_detect.sv | combinational edge detector, gives one-tick pulses on every signal edge | -| encoder.v | digital encoder input logic module | -| fifo_single_clock_reg_*.sv | single-clock FIFO buffer (queue) implementation | -| gray2bin.sv | combinational binary to Gray code converter | -| leave_one_hot.sv | combinational module that leaves only lowest hot bit | -| lifo.sv | single-clock LIFO buffer (stack) implementation | -| main_tb.sv | basic testbench template | -| NDivide.v | primitive integer divider | -| pos2bin.sv | converts positional (one-hot) value to binary representation | -| pos2bin.sv | converts positional (one-hot) value to binary representation | -| prbs_gen_chk.sv | PRBS pattern generator or checker | -| pulse_gen.sv | generates pulses with given width and delay | -| pulse_stretch.sv | configurable pulse stretcher/extender module | -| reset_set.sv | SR trigger variant w/o metastable state, set dominates here | -| reverse_bytes.sv | reverses bytes order within multi-byte array | -| reverse_vector.sv | reverses signal order within multi-bit bus | -| set_reset.sv | SR trigger variant w/o metastable state, reset dominates here | -| spi_master.sv | universal spi master module | -| UartRx.v | straightforward yet simple UART receiver | -| UartTx.v | straightforward yet simple UART transmitter | -| uart_rx_shifter.sv | UART-like receiver shifter for simple synchronous messaging inside the FPGA or between FPGAs | -| uart_rx_shifter.sv | UART-like receiver shifter for simple synchronous messaging inside the FPGA or between FPGAs | -| UartRxExtreme.v | extreme minimal UART receiver implementation | -| UartTxExtreme.v | extreme minimal UART transmitter implementation | - -Also added testbenches for selected modules +For your convinience I`ve tagged some sources by their "difficulty": +:green_circle: - for the most basic tasks +:red_circle: - for advanced or special purpose routines + +If you are a beginner in HW design - you may want to start exploring :green_circle: code first. +Almost every source file in the repository contains detailed description and instantiation template! + +| | DIRECTORY | DESCRIPTION | +|---------------|--------------|-------------| +| | Advanced Synthesis Cookbook/ | useful code from Altera's cookbook | +| | KCPSM6_Release9_30Sept14/ | Xilinx's Picoblaze soft processor sources | +| :red_circle: | XilinxBoardStore_with_Alveo_cards_support | board definitions for Xilinx Alveo accelerator cards | +| | pacoblaze-2.2/ | version of Picoblaze adapted for Altera devices | +| | avalon_mm_master_templates/ | Avalon-MM component templates from Altera | +| | axi_master_slave_templates/ | AXI componet templates generated by Vivado | +| | benchmark_projects/ | benchmarking various IDEs to compile exact same Verilog project | +| | dual_port_ram_templates/ | Block RAM templates | +| | example_projects/ | FPGA project boilerplates and examples | +| | gitignores/ | gitignore files for FPGA projects | +| | scripts/ | useful TCL, batch and shell scripts | +| :red_circle: | scripts_for_intel_hls/ | useful scripts for compiling for Intel HLS | +| :red_circle: | scripts_for_xilinx_hls/ | useful scripts for compiling for Xilinx HLS | +| | xpm | Xilinx parametrizable macros sources | + +| | FILE | DESCRIPTION | +|----------------|-------------------- |-------------| +| | adder_tree.sv | adding multiple values together in parallel | +| | axi4l_logger.sv | sniffs all AXI transactions and stores address and data to fifo | +| :green_circle: | bin2gray.sv | combinational Gray code to binary converter | +| | bin2pos.sv | converts binary coded value to positional (one-hot) code | +| | cdc_data.sv | standard two-stage data synchronizer | +| | cdc_strobe.sv | clock crossing synchronizer for one-cycle strobes | +| :green_circle: | clk_divider.sv | wide reference clock divider | +| | clogb2.svh | calculates counter/address width based on specified vector/RAM depth | +| :green_circle: | debounce.v | two-cycle debounce for input buttons | +| :green_circle: | delay.sv | useful module to make static delays or to synchronize across clock domains | +| | delayed_event.sv | generates delayed pulse one clock width | +| | dynamic_delay.sv | dynamic delay for arbitrary input signal | +| :green_circle: | edge_detect.sv | combinational edge detector, gives one-tick pulses on every signal edge | +| | encoder.v | digital encoder input logic module | +| :red_circle: | fast_counter.sv | synthetic counter | +| | fifo_combiner.sv | accumulates data words from multiple FIFOs to a single output FIFO | +| | fifo_operator.sv | performs custom operation on data words from multiple FIFOs and stores result to a single output FIFO | +| :red_circle: | fifo_single_clock_ram_*.sv | single-clock FIFO buffer (queue) implementation | +| :red_circle: | fifo_single_clock_reg_*.sv | single-clock FIFO buffer (queue) implementation | +| :green_circle: | gray2bin.sv | combinational binary to Gray code converter | +| :red_circle: | gray_functions.vh | Gray code parametrizable converter functions | +| :green_circle: | hex2ascii.sv | converts 4-bit binary nibble to 8-bit human-readable ASCII char | +| | leave_one_hot.sv | combinational module that leaves only lowest hot bit | +| | lifo.sv | single-clock LIFO buffer (stack) implementation | +| | main_tb.sv | basic testbench template | +| | moving_average.sv | Simple moving average implementation | +| | pack_unpack_array.v | macros for packing and unpacking 2D and 3D vectors in Verilog-2001 | +| | pattern_detect.sv | detects data pattern specified | +| | pdm_modulator.sv | pulse density modulation generator module | +| | pos2bin.sv | converts positional (one-hot) value to binary representation | +| | prbs_gen_chk.sv | PRBS pattern generator or checker | +| | preview_fifo.sv | FIFO with an ability to be read 0, 1 or 2 words at once | +| | priority_enc.sv | combinational priority_encoder | +| | pulse_gen.sv | generates pulses with given width and delay | +| | pulse_stretch.sv | configurable pulse stretcher/extender module | +| | pwm_modulator.sv | pulse width modulation generator | +| :red_circle: | read_ahead_buf.sv | substitutes fifo read port and performs fifo data update at the same clock cycle | +| | reset_set.sv | SR trigger variant w/o metastable state, set dominates here | +| | reset_set_comb.sv | synchronous SR trigger, but has a combinational output | +| | reverse_bytes.sv | reverses bytes order within multi-byte array | +| | reverse_dimensions.sv | reverses dimension order in SystemVerilog 2D vector | +| | reverse_vector.sv | reverses signal order within multi-bit bus | +| | round_robin_enc.sv | round robin combinational encoder | +| | round_robin_performance_enc.sv | performance improved round robin encoder | +| | set_reset.sv | SR trigger variant w/o metastable state, reset dominates here | +| | set_reset_comb.sv | synchronous SR trigger, but has a combinational output | +| | sim_clk_gen.sv | testbench clock generator | +| :red_circle: | soft_latch.sv | combinational data hold circuit | +| | spi_master.sv | universal spi master module | +| :red_circle: | true_dual_port_write_first_2_clock_ram.sv | double port RAM/ROM module | +| :red_circle: | true_single_port_write_first_ram.sv | single port RAM/ROM module | +| | uart_debug_printer.sv | debug data printer to UART terminal | +| :green_circle: | uart_rx.sv | straightforward yet simple UART receiver | +| | uart_rx_shifter.sv | UART-like receiver shifter for simple synchronous messaging inside the FPGA or between FPGAs | +| :green_circle: | uart_tx.sv | straightforward yet simple UART transmitter | +| | uart_tx_shifter.sv | UART-like transmitter shifter for simple synchronous messaging inside the FPGA or between FPGAs | + +Also added testbenches for selected modules. + \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/README.md b/XilinxBoardStore_with_Alveo_cards_support/README.md new file mode 100644 index 0000000..2857990 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/README.md @@ -0,0 +1,6 @@ + +This is a checkout from original Xilinx repo +https://github.com/Xilinx/XilinxBoardStore commit 78a40f2 + +This version of board store supports creating Vivado projects for Alveo U200, U250 and U280 accelerators. Future revisions of board store dropped support for Alveo cards for some reason + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Avnet/minized/1.2/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Avnet/minized/1.2/board.xml new file mode 100644 index 0000000..047e844 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Avnet/minized/1.2/board.xml @@ -0,0 +1,80 @@ + + + + + MiniZed Board File Image + + + + 1.0 + +1.2 +MiniZed + + + + + 1 DIP switch + + + + + + + + + + + + + Red LED + + + + + + + + + + + + + Green LED + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Avnet/minized/1.2/minized.jpg b/XilinxBoardStore_with_Alveo_cards_support/boards/Avnet/minized/1.2/minized.jpg new file mode 100644 index 0000000..2bd49f5 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Avnet/minized/1.2/minized.jpg differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Avnet/minized/1.2/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Avnet/minized/1.2/part0_pins.xml new file mode 100644 index 0000000..bda51eb --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Avnet/minized/1.2/part0_pins.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Avnet/minized/1.2/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Avnet/minized/1.2/preset.xml new file mode 100644 index 0000000..dedb05c --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Avnet/minized/1.2/preset.xml @@ -0,0 +1,707 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Avnet/minized/1.2/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Avnet/minized/1.2/xitem.json new file mode 100644 index 0000000..a1e3f49 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Avnet/minized/1.2/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "minized", + "display": "MiniZed", + "revision": "1.2", + "description": "MiniZed", + "company": "em.avnet.com", + "company_display": "Avnet", + "author": "zedhed", + "contributors": [ + { + "group": "Avnet", + "url": "avnet.com" + } + ], + "category": "Single Part", + "website": "http://www.minized.org", + "search-keywords": [ + "minized", + "em.avnet.com", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Avnet/picozed_7010_fmc2/1.2/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Avnet/picozed_7010_fmc2/1.2/board.xml new file mode 100644 index 0000000..d365e3d --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Avnet/picozed_7010_fmc2/1.2/board.xml @@ -0,0 +1,64 @@ + + + + + PicoZed FMC Carrier Card V2 File Image + + + + e + +1.2 +PicoZed 7010 SOM + FMC Carrier V2 + + + + + 1 push button + + + + + + + + + + + + + 1 LED + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Avnet/picozed_7010_fmc2/1.2/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Avnet/picozed_7010_fmc2/1.2/part0_pins.xml new file mode 100644 index 0000000..7df3806 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Avnet/picozed_7010_fmc2/1.2/part0_pins.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Avnet/picozed_7010_fmc2/1.2/picozed_fmc2_carrier_card.jpg b/XilinxBoardStore_with_Alveo_cards_support/boards/Avnet/picozed_7010_fmc2/1.2/picozed_fmc2_carrier_card.jpg new file mode 100644 index 0000000..d3b088f Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Avnet/picozed_7010_fmc2/1.2/picozed_fmc2_carrier_card.jpg differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Avnet/picozed_7010_fmc2/1.2/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Avnet/picozed_7010_fmc2/1.2/preset.xml new file mode 100644 index 0000000..62c6678 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Avnet/picozed_7010_fmc2/1.2/preset.xml @@ -0,0 +1,363 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ "description": "PicoZed 7010 SOM + FMC Carrier V2", + "company": "em.avnet.com", + "company_display": "Avnet", + "author": "Avnet", + "contributors": [ + { + "group": "Avnet", + "url": "www.avnet.com" + } + ], + "category": "Single Part", + "website": "http://www.picozed.org", + "search-keywords": [ + "picozed_7010_fmc2", + "em.avnet.com", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Avnet/ultra96/1.2/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Avnet/ultra96/1.2/board.xml new file mode 100644 index 0000000..9732d07 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Avnet/ultra96/1.2/board.xml @@ -0,0 +1,46 @@ + + + + + Ultra96 Board File Image + + + + Rev 1 + + 1.2 + Ultra96 Evaluation Platform + + + + + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Avnet/ultra96/1.2/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Avnet/ultra96/1.2/part0_pins.xml new file mode 100644 index 0000000..2aad475 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Avnet/ultra96/1.2/part0_pins.xml @@ -0,0 +1,175 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Avnet/ultra96/1.2/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Avnet/ultra96/1.2/preset.xml new file mode 100644 index 0000000..d234235 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Avnet/ultra96/1.2/preset.xml @@ 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"digilentinc.com", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/arty-a7-35/E.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/arty-a7-35/E.0/board.xml new file mode 100644 index 0000000..12eb9ac --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/arty-a7-35/E.0/board.xml @@ -0,0 +1,1287 @@ + + + + E.0 + +1.0 +Arty A7-35 + + + + + DDR3 board interface, it can use MIG IP for connection. + + + + + + 4-position user DIP Switches + + + + + + + + + + + + + + + + Secondary interface to communicate with ethernet phy. + + + + + + + + + + + + + + + + + + + + + + + + + Primary interface to communicate with ethernet phy in MII mode. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Shield I2C + + + + + + + + + + + + + + + + + + + + + + + + + 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a/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/arty-a7-35/E.0/mig.prj b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/arty-a7-35/E.0/mig.prj new file mode 100644 index 0000000..9b31d7b --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/arty-a7-35/E.0/mig.prj @@ -0,0 +1,134 @@ + + + + design_1_mig_7series_0_0 + 1 + 1 + OFF + 1024 + ON + Enabled + xc7a35ti-csg324/-1L + 2.3 + No Buffer + No Buffer + ACTIVE LOW + FALSE + 1 + 50 Ohms + 0 + + DDR3_SDRAM/Components/MT41K128M16XX-15E + 3000 + 1.8V + 4:1 + 166.666 + 0 + 666 + 1.000 + 1 + 1 + 1 + 1 + 16 + 1 + 1 + Disabled + Normal + FALSE + + 14 + 10 + 3 + 1.35V + 268435456 + BANK_ROW_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 5 + Normal + No + Slow Exit + Enable + RZQ/6 + Disable + Enable + RZQ/6 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 5 + Enabled + Normal + Dynamic ODT off + AXI + + RD_PRI_REG + 28 + 128 + 4 + 0 + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/arty-a7-35/E.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/arty-a7-35/E.0/part0_pins.xml new file mode 100644 index 0000000..ffe0dd4 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/arty-a7-35/E.0/part0_pins.xml @@ -0,0 +1,133 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/arty-a7-35/E.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/arty-a7-35/E.0/preset.xml new file mode 100644 index 0000000..df58104 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/arty-a7-35/E.0/preset.xml @@ -0,0 +1,385 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/arty-a7-35/E.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/arty-a7-35/E.0/xitem.json new file mode 100644 index 0000000..7909dfb --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/arty-a7-35/E.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "arty-a7-35", + "display": "Arty A7-35", + "revision": "1.0", + "description": "Arty A7-35", + "company": "digilentinc.com", + "company_display": "Digilent Inc", + "author": "ArtVVB", + "contributors": [ + { + "group": "Digilent Inc", + "url": "digilentinc.com" + } + ], + "category": "Single Part", + "website": "www.digilentinc.com/Arty-A7-35", + "search-keywords": [ + "arty-a7-35", + "digilentinc.com", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/arty-s7-25/E.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/arty-s7-25/E.0/board.xml new file mode 100644 index 0000000..cdfc612 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/arty-s7-25/E.0/board.xml @@ -0,0 +1,1113 @@ + + + + E.0 + +1.0 +Arty S7-25 + + + + + DDR3 board interface, it can use MIG IP for connection. + + + + + + 4-position user DIP Switches + + + + + + + + + + + + + + + + Shield I2C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 4 LEDs + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 4 Push Buttons + + + + + + + + + + + + + + + + Quad SPI Flash + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Onboard Reset Button + + + + + + + + + + + + + + + + 2 RGB LEDs + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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USB-to-UART Bridge, which allows a connection to a host computer with a USB port + + + + + + Pmod Connector JA + + + Pmod Connector JB + + + Pmod Connector JC + + + Pmod Connector JD + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/arty-s7-25/E.0/mig.prj b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/arty-s7-25/E.0/mig.prj new file mode 100644 index 0000000..ac6b4d6 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/arty-s7-25/E.0/mig.prj @@ -0,0 +1,138 @@ + + + + system_mig_7series_0_2 + 1 + 1 + OFF + 1024 + ON + Disabled + xc7s25-csga324/-1 + 4.0 + Single-Ended + No Buffer + ACTIVE LOW + FALSE + 1 + 50 Ohms + 0 + + DDR3_SDRAM/Components/MT41K128M16XX-15E + 3077 + 1.8V + 4:1 + 99.997 + 1 + 649 + 3.250 + 1 + 1 + 1 + 1 + 16 + 1 + 1 + Disabled + Normal + 4 + FALSE + + 14 + 10 + 3 + 1.35V + 268435456 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a/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/arty-s7-25/E.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/arty-s7-25/E.0/preset.xml new file mode 100644 index 0000000..f5447f3 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/arty-s7-25/E.0/preset.xml @@ -0,0 +1,394 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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"board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/arty-s7-50/B.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/arty-s7-50/B.0/board.xml new file mode 100644 index 0000000..377ae4f --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/arty-s7-50/B.0/board.xml @@ -0,0 +1,1113 @@ + + + + B.0 + +1.0 +Arty S7-50 + + + + + DDR3 board interface, it can use MIG IP for connection. + + + + + + 4-position user DIP Switches + + + + + + + + + + + + + + + + Shield I2C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 4 LEDs + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 4 Push Buttons + + + + + + + + + + + + + + + + Quad SPI Flash + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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through A11 for digital use + + + Shield SPI + + + 1.35V Single-Ended 100MHz oscillator used as DDR clock on the board + + + 3.3V Single-Ended 12MHz oscillator used as system clock on the board + + + USB-to-UART Bridge, which allows a connection to a host computer with a USB port + + + + + + Pmod Connector JA + + + Pmod Connector JB + + + Pmod Connector JC + + + Pmod Connector JD + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/arty-s7-50/B.0/mig.prj b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/arty-s7-50/B.0/mig.prj new file mode 100644 index 0000000..e4f4a69 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/arty-s7-50/B.0/mig.prj @@ -0,0 +1,138 @@ + + + + system_mig_7series_0_2 + 1 + 1 + OFF + 1024 + ON + Disabled + xc7s50-csga324/-1 + 4.0 + Single-Ended + No Buffer + ACTIVE LOW + FALSE + 1 + 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b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/arty/C.0/mig.prj new file mode 100644 index 0000000..9b31d7b --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/arty/C.0/mig.prj @@ -0,0 +1,134 @@ + + + + design_1_mig_7series_0_0 + 1 + 1 + OFF + 1024 + ON + Enabled + xc7a35ti-csg324/-1L + 2.3 + No Buffer + No Buffer + ACTIVE LOW + FALSE + 1 + 50 Ohms + 0 + + DDR3_SDRAM/Components/MT41K128M16XX-15E + 3000 + 1.8V + 4:1 + 166.666 + 0 + 666 + 1.000 + 1 + 1 + 1 + 1 + 16 + 1 + 1 + Disabled + Normal + FALSE + + 14 + 10 + 3 + 1.35V + 268435456 + BANK_ROW_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 5 + Normal + No + Slow Exit + Enable + RZQ/6 + Disable + Enable + RZQ/6 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 5 + Enabled + Normal + Dynamic ODT off + AXI + + RD_PRI_REG + 28 + 128 + 4 + 0 + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/arty/C.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/arty/C.0/part0_pins.xml new file mode 100644 index 0000000..ffe0dd4 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/arty/C.0/part0_pins.xml @@ -0,0 +1,133 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/arty/C.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/arty/C.0/preset.xml new file mode 100644 index 0000000..df58104 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/arty/C.0/preset.xml @@ -0,0 +1,385 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/arty/C.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "arty", + "display": "Arty", + "revision": "1.1", + "description": "Arty", + "company": "digilentinc.com", + "company_display": "Digilent Inc", + "author": "ArtVVB", + "contributors": [ + { + "group": "Digilent Inc", + "url": "digilentinc.com" + } + ], + "category": "Single Part", + "website": "www.digilentinc.com/Arty", + "search-keywords": [ + "arty", + "digilentinc.com", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/basys3/C.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/basys3/C.0/board.xml new file mode 100644 index 0000000..8b81b13 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/basys3/C.0/board.xml @@ -0,0 +1,844 @@ + + + + C.0 + +1.1 +Basys3 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a/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/basys3/C.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/basys3/C.0/part0_pins.xml new file mode 100644 index 0000000..3ef61d5 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/basys3/C.0/part0_pins.xml @@ -0,0 +1,94 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/basys3/C.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/basys3/C.0/preset.xml new file mode 100644 index 0000000..139a22f --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/basys3/C.0/preset.xml @@ -0,0 +1,313 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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"company_display": "Digilent Inc", + "author": "ArtVVB", + "contributors": [ + { + "group": "Digilent Inc", + "url": "digilentinc.com" + } + ], + "category": "Single Part", + "website": "www.digilentinc.com/basys3", + "search-keywords": [ + "basys3", + "digilentinc.com", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/cmod-s7-25/B.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/cmod-s7-25/B.0/board.xml new file mode 100644 index 0000000..c5a8966 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/cmod-s7-25/B.0/board.xml @@ -0,0 +1,426 @@ + + + + B.0 + + 1.0 + Cmod S7-25 + + + + + 12 MHz Single-Ended System Clock + + + + + + + + + + + + + BTN0 used as Active High System Reset + + + + + + + + + + + + + 4 LEDs + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RGB LED + + + + + + + + + + + + + + + + + + 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--git a/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/cmod-s7-25/B.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/cmod-s7-25/B.0/part0_pins.xml new file mode 100644 index 0000000..ec30415 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/cmod-s7-25/B.0/part0_pins.xml @@ -0,0 +1,37 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/cmod-s7-25/B.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/cmod-s7-25/B.0/preset.xml new file mode 100644 index 0000000..48d2ff0 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/cmod-s7-25/B.0/preset.xml @@ -0,0 +1,307 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ { + "group": "Digilent Inc", + "url": "digilentinc.com" + } + ], + "category": "Single Part", + "website": "https://reference.digilentinc.com/programmable-logic/cmod-s7/start", + "search-keywords": [ + "cmod-s7-25", + "digilentinc.com", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/cmod_a7-15t/B.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/cmod_a7-15t/B.0/board.xml new file mode 100644 index 0000000..dda21c7 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/cmod_a7-15t/B.0/board.xml @@ -0,0 +1,481 @@ + + + + B.0 + +1.1 +Cmod A7-15t + + + + + 512KB SRAM + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RGB LED + + + + + + + + + + + + + + + + + + + + + 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"ArtVVB", + "contributors": [ + { + "group": "Digilent Inc", + "url": "digilentinc.com" + } + ], + "category": "Single Part", + "website": "https://reference.digilentinc.com/cmod_a7", + "search-keywords": [ + "cmod_a7-15t", + "digilentinc.com", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/cmod_a7-35t/B.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/cmod_a7-35t/B.0/board.xml new file mode 100644 index 0000000..075e897 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/cmod_a7-35t/B.0/board.xml @@ -0,0 +1,481 @@ + + + + B.0 + +1.1 +Cmod A7-35t + + + + + 512KB SRAM + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RGB LED + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/cmod_a7-35t/B.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/cmod_a7-35t/B.0/part0_pins.xml new file mode 100644 index 0000000..e4a2fea --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/cmod_a7-35t/B.0/part0_pins.xml @@ -0,0 +1,58 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/cmod_a7-35t/B.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/cmod_a7-35t/B.0/preset.xml new file mode 100644 index 0000000..bb869c5 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/cmod_a7-35t/B.0/preset.xml @@ -0,0 +1,270 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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"ArtVVB", + "contributors": [ + { + "group": "Digilent Inc", + "url": "digilentinc.com" + } + ], + "category": "Single Part", + "website": "https://reference.digilentinc.com/cmod_a7", + "search-keywords": [ + "cmod_a7-35t", + "digilentinc.com", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/cora-z7-07s/B.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/cora-z7-07s/B.0/board.xml new file mode 100644 index 0000000..325875e --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/cora-z7-07s/B.0/board.xml @@ -0,0 +1,688 @@ + + + + B.0 + + 1.0 + Cora Z7-07S + + + + + + + + + + + + + + + + + + + 2 Push Buttons + + + + + + + + + + + + + + 2 RGB LEDs + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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--git a/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/cora-z7-07s/B.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/cora-z7-07s/B.0/preset.xml new file mode 100644 index 0000000..88b7edf --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/cora-z7-07s/B.0/preset.xml @@ -0,0 +1,590 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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Z7-07S", + "revision": "1.0", + "description": "Cora Z7-07S", + "company": "digilentinc.com", + "company_display": "Digilent Inc", + "author": "ArtVVB", + "contributors": [ + { + "group": "Digilent Inc", + "url": "digilentinc.com" + } + ], + "category": "Single Part", + "website": "http://www.digilentinc.com", + "search-keywords": [ + "cora-z7-07s", + "digilentinc.com", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/cora-z7-10/B.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/cora-z7-10/B.0/board.xml new file mode 100644 index 0000000..0c1c3a9 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/cora-z7-10/B.0/board.xml @@ -0,0 +1,688 @@ + + + + B.0 + + 1.0 + Cora Z7-10 + + + + + + + + + + + + + + + + + + + 2 Push Buttons + + + + + + + + + + + + + + 2 RGB LEDs + + + + + + + + + + + + + + + + + + + + + + + + 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a/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/nexys4_ddr/C.1/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/nexys4_ddr/C.1/xitem.json new file mode 100644 index 0000000..4c49f70 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Digilent/nexys4_ddr/C.1/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "nexys4_ddr", + "display": "Nexys4 DDR", + "revision": "1.1", + "description": "Nexys4 DDR", + "company": "digilentinc.com", + "company_display": "Digilent Inc", + "author": "ArtVVB", + "contributors": [ + { + "group": "Digilent Inc", + "url": "digilentinc.com" + } + ], + "category": "Single Part", + "website": "www.digilentinc.com/nexys4", + "search-keywords": [ + "nexys4_ddr", + "digilentinc.com", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git 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Supported PCB Revisions: REV02, REV01.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0712-info", + "search-keywords": [ + "te0712_200_2i", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0712_35_2I/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0712_35_2I/1.0/board.xml new file mode 100644 index 0000000..4a47a0c --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0712_35_2I/1.0/board.xml @@ -0,0 +1,1516 @@ + + + + + + + + + + + + TE0712 Board File Image + + + + + + + + 0.2 + + + + + 1.0 + + + Artix-7 TE0712_35_2I Board (form factor 4x5cm) with 1GB DDR3, 100MBit Ethernet, speed grade -2 and industrial temperature grade. Supported PCB Revisions: REV02. + + + + + + + FPGA part on the board + + + + DDR3 board interface, it can use MIG IP for connection. + + + + + + + Primary interface to communicate with ethernet phy in MII mode. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Secondary interface to communicate with ethernet phy when mode is selected as MII,GMII,1000BaseX. + + + + + + + + + + + + + + + + + + + Secondary interface to communicate with ethernet phy when mode is selected as SGMII. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + All Module B2B as single ASIO GPIO Port + + + + DDR3 memory + + + + + + + + Active High + + + + USB-to-UART Bridge, which allows a connection to a host computer with a USB port + + + + 32 MByte storage that can be used for configuration or data storage + + + + differential 50 MHz oscillator used as system differential clock on the board + + + + + + + MGT clock 0 + + + + + + + I2C + + + + RMII + + + + MDIO_IO + + + + MDIO_MDC + + + + PHY RESET OUT + + + + system led und normal led + + + + LED + + + + system LED + + + + p0 (8 bits) in J1 + + + + p0 (6 bits) in J1 + + + + p1a (22 bits) in J1 + + + + p1b (26 bits) in J1 + + + + p2a (20 bits) in J2 + + + + p2b (30 bits) in J2 + + + + p2c (18 bits) in J2 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0712_35_2I/1.0/mig.prj b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0712_35_2I/1.0/mig.prj new file mode 100644 index 0000000..9e7e430 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0712_35_2I/1.0/mig.prj @@ -0,0 +1,159 @@ + + + + design_1_mig_7series_0_0 + 1 + 1 + OFF + 1024 + ON + Enabled + xc7a35t-fgg484/-2 + 2.1 + Differential + No Buffer + ACTIVE HIGH + FALSE + 0 + 50 Ohms + 0 + + DDR3_SDRAM/Components/MT41J256m16XX-125 + 2500 + 1.8V + 4:1 + 50 + 1 + 4.000 + 8 + 16 + 1 + 1 + 32 + 1 + 1 + Disabled + Normal + FALSE + + 15 + 10 + 3 + 1.5V + 1073741824 + BANK_ROW_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 6 + Normal + No + Slow Exit + Enable + RZQ/7 + Disable + Enable + RZQ/4 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 5 + Enabled + Normal + Dynamic ODT off + AXI + + RD_PRI_REG + 30 + 32 + 1 + 0 + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0712_35_2I/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0712_35_2I/1.0/part0_pins.xml new file mode 100644 index 0000000..aa5337c --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0712_35_2I/1.0/part0_pins.xml @@ -0,0 +1,212 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0712_35_2I/1.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0712_35_2I/1.0/preset.xml new file mode 100644 index 0000000..e104b0d --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0712_35_2I/1.0/preset.xml @@ -0,0 +1,55 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0712_35_2I/1.0/te0712_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0712_35_2I/1.0/te0712_board.png new file mode 100644 index 0000000..d21908a Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0712_35_2I/1.0/te0712_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0712_35_2I/1.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0712_35_2I/1.0/xitem.json new file mode 100644 index 0000000..82e0b4c --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0712_35_2I/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0712_35_2i", + "display": "Artix-7 TE0712_35_2I. SPRT PCB: REV02", + "revision": "1.0", + "description": "Artix-7 TE0712_35_2I Board (form factor 4x5cm) with 1GB DDR3, 100MBit Ethernet, speed grade -2 and industrial temperature grade. Supported PCB Revisions: REV02.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0712-info", + "search-keywords": [ + "te0712_35_2i", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_14S/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_14S/1.0/board.xml new file mode 100644 index 0000000..06618b9 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_14S/1.0/board.xml @@ -0,0 +1,723 @@ + + + + + + + + + + + + ZYNQ-7 TE0720 Board File Image + + + + + + + + 0.3 + 0.2 + + + + + 1.0 + + + ZYNQ-7 TE0720_14S Board (form factor 4x5 cm) with 1GByte DDR3L, 1GBit Ethernet, Speed Grade -1 and commercial temperature grade. Supported PCB Revisions: REV02, REV03. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + p1a (22 bits ) in JM1 odd pins from/to FPGA-Bank 35 + + + + p1b (26 bits) in JM1 even pins from/to FPGA-Bank 35 + + + + p2a (20 bits) in JM2 odd pins from/to FPGA-Bank 13 + + + + p2b (30 bits) in JM2 even pins from/to FPGA-Bank 13 + + + + p2c (18 bits) in JM2 even and odd pins from/to FPGA-Bank 33 + + + + p3a (16 bits) in JM3 odd pins from/to FPGA-Bank 34 + + + + p3b (20 bits) in JM3 even pins from/to FPGA-Bank 34 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_14S/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_14S/1.0/part0_pins.xml new file mode 100644 index 0000000..72d466d --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_14S/1.0/part0_pins.xml @@ -0,0 +1,163 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_14S/1.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_14S/1.0/preset.xml new file mode 100644 index 0000000..01c131f --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_14S/1.0/preset.xml @@ -0,0 +1,134 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_14S/1.0/te0720_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_14S/1.0/te0720_board.png new file mode 100644 index 0000000..06061e9 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_14S/1.0/te0720_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_14S/1.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_14S/1.0/xitem.json new file mode 100644 index 0000000..7313be2 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_14S/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0720_14s", + "display": "ZYNQ-7 TE0720_14S. SPRT PCB: REV02, REV03", + "revision": "1.0", + "description": "ZYNQ-7 TE0720_14S Board (form factor 4x5 cm) with 1GByte DDR3L, 1GBit Ethernet, Speed Grade -1 and commercial temperature grade. Supported PCB Revisions: REV02, REV03.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0720-info", + "search-keywords": [ + "te0720_14s", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1C/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1C/1.0/board.xml new file mode 100644 index 0000000..78bd0c8 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1C/1.0/board.xml @@ -0,0 +1,723 @@ + + + + + + + + + + + + ZYNQ-7 TE0720 Board File Image + + + + + + + + 0.3 + 0.2 + + + + + 1.0 + + + ZYNQ-7 TE0720_1CF(_, A) Board (form factor 4x5 cm) with 1GB DDR, 1GBit Ethernet, Speed Grade -1 and commercial temperature grade. Supported PCB Revisions: REV02, REV03. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + p1a (22 bits ) in JM1 odd pins from/to FPGA-Bank 35 + + + + p1b (26 bits) in JM1 even pins from/to FPGA-Bank 35 + + + + p2a (20 bits) in JM2 odd pins from/to FPGA-Bank 13 + + + + p2b (30 bits) in JM2 even pins from/to FPGA-Bank 13 + + + + p2c (18 bits) in JM2 even and odd pins from/to FPGA-Bank 33 + + + + p3a (16 bits) in JM3 odd pins from/to FPGA-Bank 34 + + + + p3b (20 bits) in JM3 even pins from/to FPGA-Bank 34 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1C/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1C/1.0/part0_pins.xml new file mode 100644 index 0000000..5535c8f --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1C/1.0/part0_pins.xml @@ -0,0 +1,163 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1C/1.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1C/1.0/preset.xml new file mode 100644 index 0000000..a842ba5 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1C/1.0/preset.xml @@ -0,0 +1,135 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1C/1.0/te0720_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1C/1.0/te0720_board.png new file mode 100644 index 0000000..06061e9 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1C/1.0/te0720_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1C/1.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1C/1.0/xitem.json new file mode 100644 index 0000000..c946b4c --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1C/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0720_1c", + "display": "ZYNQ-7 TE0720_1CF(_, A). SPRT PCB: REV02, REV03", + "revision": "1.0", + "description": "ZYNQ-7 TE0720_1CF(_, A) Board (form factor 4x5 cm) with 1GB DDR, 1GBit Ethernet, Speed Grade -1 and commercial temperature grade. Supported PCB Revisions: REV02, REV03.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0720-info", + "search-keywords": [ + "te0720_1c", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1C/2.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1C/2.0/board.xml new file mode 100644 index 0000000..54bb6f3 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1C/2.0/board.xml @@ -0,0 +1,723 @@ + + + + + + + + + + + + ZYNQ-7 TE0720 Board File Image + + + + + + + + 0.3 + 0.2 + + + + + 2.0 + + + ZYNQ-7 TE0720_1CR Board (form factor 4x5 cm) with 256MB DDR, 1GBit Ethernet, Speed Grade -1 and commercial temperature grade. Supported PCB Revisions: REV02, REV03. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + p1a (22 bits ) in JM1 odd pins from/to FPGA-Bank 35 + + + + p1b (26 bits) in JM1 even pins from/to FPGA-Bank 35 + + + + p2a (20 bits) in JM2 odd pins from/to FPGA-Bank 13 + + + + p2b (30 bits) in JM2 even pins from/to FPGA-Bank 13 + + + + p2c (18 bits) in JM2 even and odd pins from/to FPGA-Bank 33 + + + + p3a (16 bits) in JM3 odd pins from/to FPGA-Bank 34 + + + + p3b (20 bits) in JM3 even pins from/to FPGA-Bank 34 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1C/2.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1C/2.0/part0_pins.xml new file mode 100644 index 0000000..1f73a06 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1C/2.0/part0_pins.xml @@ -0,0 +1,163 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1C/2.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1C/2.0/preset.xml new file mode 100644 index 0000000..7d49ca6 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1C/2.0/preset.xml @@ -0,0 +1,134 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1C/2.0/te0720_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1C/2.0/te0720_board.png new file mode 100644 index 0000000..06061e9 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1C/2.0/te0720_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1C/2.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1C/2.0/xitem.json new file mode 100644 index 0000000..0f8a7df --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1C/2.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0720_1c", + "display": "ZYNQ-7 TE0720_1CR. SPRT PCB: REV02, REV03", + "revision": "2.0", + "description": "ZYNQ-7 TE0720_1CR Board (form factor 4x5 cm) with 256MB DDR, 1GBit Ethernet, Speed Grade -1 and commercial temperature grade. Supported PCB Revisions: REV02, REV03.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0720-info", + "search-keywords": [ + "te0720_1c", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1IL/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1IL/1.0/board.xml new file mode 100644 index 0000000..b2b2ddc --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1IL/1.0/board.xml @@ -0,0 +1,723 @@ + + + + + + + + + + + + ZYNQ-7 TE0720 Board File Image + + + + + + + + 0.3 + 0.2 + + + + + 1.0 + + + ZYNQ-7 TE0720_L1IF Board (form factor 4x5 cm) with 512MB DDR3L, 1GBit Ethernet, Speed Grade -1 and industrial temperature grade. Supported PCB Revisions: REV02, REV03. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + p1a (22 bits ) in JM1 odd pins from/to FPGA-Bank 35 + + + + p1b (26 bits) in JM1 even pins from/to FPGA-Bank 35 + + + + p2a (20 bits) in JM2 odd pins from/to FPGA-Bank 13 + + + + p2b (30 bits) in JM2 even pins from/to FPGA-Bank 13 + + + + p2c (18 bits) in JM2 even and odd pins from/to FPGA-Bank 33 + + + + p3a (16 bits) in JM3 odd pins from/to FPGA-Bank 34 + + + + p3b (20 bits) in JM3 even pins from/to FPGA-Bank 34 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1IL/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1IL/1.0/part0_pins.xml new file mode 100644 index 0000000..bef08b2 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1IL/1.0/part0_pins.xml @@ -0,0 +1,163 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1IL/1.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1IL/1.0/preset.xml new file mode 100644 index 0000000..9fb62cd --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1IL/1.0/preset.xml @@ -0,0 +1,135 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1IL/1.0/te0720_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1IL/1.0/te0720_board.png new file mode 100644 index 0000000..06061e9 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1IL/1.0/te0720_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1IL/1.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1IL/1.0/xitem.json new file mode 100644 index 0000000..3b1f65f --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1IL/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0720_1il", + "display": "ZYNQ-7 TE0720_L1IF. SPRT PCB: REV02, REV03", + "revision": "1.0", + "description": "ZYNQ-7 TE0720_L1IF Board (form factor 4x5 cm) with 512MB DDR3L, 1GBit Ethernet, Speed Grade -1 and industrial temperature grade. Supported PCB Revisions: REV02, REV03.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0720-info", + "search-keywords": [ + "te0720_1il", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1Q/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1Q/1.0/board.xml new file mode 100644 index 0000000..90cc6e3 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1Q/1.0/board.xml @@ -0,0 +1,723 @@ + + + + + + + + + + + + ZYNQ-7 TE0720 Board File Image + + + + + + + + 0.3 + 0.2 + + + + + 1.0 + + + ZYNQ-7 TE0720_1QF(_, A) Board (form factor 4x5 cm) with 1GB DDR, 1GBit Ethernet, Speed Grade -1 and expanded temperature grade (automotive). Supported PCB Revisions: REV02, REV03. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + p1a (22 bits ) in JM1 odd pins from/to FPGA-Bank 35 + + + + p1b (26 bits) in JM1 even pins from/to FPGA-Bank 35 + + + + p2a (20 bits) in JM2 odd pins from/to FPGA-Bank 13 + + + + p2b (30 bits) in JM2 even pins from/to FPGA-Bank 13 + + + + p2c (18 bits) in JM2 even and odd pins from/to FPGA-Bank 33 + + + + p3a (16 bits) in JM3 odd pins from/to FPGA-Bank 34 + + + + p3b (20 bits) in JM3 even pins from/to FPGA-Bank 34 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1Q/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1Q/1.0/part0_pins.xml new file mode 100644 index 0000000..5fa1a1b --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1Q/1.0/part0_pins.xml @@ -0,0 +1,163 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1Q/1.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1Q/1.0/preset.xml new file mode 100644 index 0000000..01c131f --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1Q/1.0/preset.xml @@ -0,0 +1,134 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1Q/1.0/te0720_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1Q/1.0/te0720_board.png new file mode 100644 index 0000000..06061e9 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1Q/1.0/te0720_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1Q/1.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1Q/1.0/xitem.json new file mode 100644 index 0000000..d2c76b7 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_1Q/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0720_1q", + "display": "ZYNQ-7 TE0720_1QF (_, A). SPRT PCB: REV02, REV03", + "revision": "1.0", + "description": "ZYNQ-7 TE0720_1QF(_, A) Board (form factor 4x5 cm) with 1GB DDR, 1GBit Ethernet, Speed Grade -1 and expanded temperature grade (automotive). Supported PCB Revisions: REV02, REV03.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0720-info", + "search-keywords": [ + "te0720_1q", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_2E/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_2E/1.0/board.xml new file mode 100644 index 0000000..c93df25 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_2E/1.0/board.xml @@ -0,0 +1,723 @@ + + + + + + + + + + + + ZYNQ-7 TE0720 Board File Image + + + + + + + + 0.3 + 0.2 + + + + + 1.0 + + + ZYNQ-7 TE0720_2EF Board (form factor 4x5 cm) with 1GB DDR, 1GBit Ethernet, Speed Grade -2 and extended temperature grade. Supported PCB Revisions: REV02, REV03. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + p1a (22 bits ) in JM1 odd pins from/to FPGA-Bank 35 + + + + p1b (26 bits) in JM1 even pins from/to FPGA-Bank 35 + + + + p2a (20 bits) in JM2 odd pins from/to FPGA-Bank 13 + + + + p2b (30 bits) in JM2 even pins from/to FPGA-Bank 13 + + + + p2c (18 bits) in JM2 even and odd pins from/to FPGA-Bank 33 + + + + p3a (16 bits) in JM3 odd pins from/to FPGA-Bank 34 + + + + p3b (20 bits) in JM3 even pins from/to FPGA-Bank 34 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_2E/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_2E/1.0/part0_pins.xml new file mode 100644 index 0000000..35696ab --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_2E/1.0/part0_pins.xml @@ -0,0 +1,163 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_2E/1.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_2E/1.0/preset.xml new file mode 100644 index 0000000..01c131f --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_2E/1.0/preset.xml @@ -0,0 +1,134 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_2E/1.0/te0720_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_2E/1.0/te0720_board.png new file mode 100644 index 0000000..06061e9 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_2E/1.0/te0720_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_2E/1.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_2E/1.0/xitem.json new file mode 100644 index 0000000..59ab662 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_2E/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0720_2e", + "display": "ZYNQ-7 TE0720_2EF. SPRT PCB: REV02, REV03", + "revision": "1.0", + "description": "ZYNQ-7 TE0720_2EF Board (form factor 4x5 cm) with 1GB DDR, 1GBit Ethernet, Speed Grade -2 and extended temperature grade. Supported PCB Revisions: REV02, REV03.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0720-info", + "search-keywords": [ + "te0720_2e", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_2I/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_2I/1.0/board.xml new file mode 100644 index 0000000..263ed66 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_2I/1.0/board.xml @@ -0,0 +1,722 @@ + + + + + + + + + + + + ZYNQ-7 TE0720 Board File Image + + + + + + + 0.3 + 0.2 + + + + + 1.0 + + + ZYNQ-7 TE0720_2IF(_, C3, C8, A) Board (form factor 4x5 cm) with 1GB DDR, 1GBit Ethernet, Speed Grade -2 and industrial temperature grade. Supported PCB Revisions: REV02, REV03. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + p1a (22 bits ) in JM1 odd pins from/to FPGA-Bank 35 + + + + p1b (26 bits) in JM1 even pins from/to FPGA-Bank 35 + + + + p2a (20 bits) in JM2 odd pins from/to FPGA-Bank 13 + + + + p2b (30 bits) in JM2 even pins from/to FPGA-Bank 13 + + + + p2c (18 bits) in JM2 even and odd pins from/to FPGA-Bank 33 + + + + p3a (16 bits) in JM3 odd pins from/to FPGA-Bank 34 + + + + p3b (20 bits) in JM3 even pins from/to FPGA-Bank 34 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_2I/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_2I/1.0/part0_pins.xml new file mode 100644 index 0000000..35696ab --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_2I/1.0/part0_pins.xml @@ -0,0 +1,163 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_2I/1.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_2I/1.0/preset.xml new file mode 100644 index 0000000..01c131f --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_2I/1.0/preset.xml @@ -0,0 +1,134 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_2I/1.0/te0720_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_2I/1.0/te0720_board.png new file mode 100644 index 0000000..06061e9 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_2I/1.0/te0720_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_2I/1.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_2I/1.0/xitem.json new file mode 100644 index 0000000..04790ac --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0720_2I/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0720_2i", + "display": "ZYNQ-7 TE0720_2IF (_, C3, C8, A). SPRT PCB: REV02, REV03", + "revision": "1.0", + "description": "ZYNQ-7 TE0720_2IF(_, C3, C8, A) Board (form factor 4x5 cm) with 1GB DDR, 1GBit Ethernet, Speed Grade -2 and industrial temperature grade. Supported PCB Revisions: REV02, REV03.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0720-info", + "search-keywords": [ + "te0720_2i", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722/1.0/board.xml new file mode 100644 index 0000000..84f9254 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722/1.0/board.xml @@ -0,0 +1,389 @@ + + + + + + + + + + + + + ZYNQ-7 TE0722 Board File Image + + + + + + + 0.2 + 0.1 + + + + + 1.0 + + + ZYNQ-7 TE0722 Board (form factor 1.8 x 5.1 cm) without DDR, speed grade -1 and commercial temperature range. Supported PCB Revisions: REV01,REV2. Note: Primary boot device is QSPI, SD can be used as secondary boot device only. DDR less Zynq need a modified FSBL! + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LEDs on the module, one red, one green and one blue + + + + 32-Bit GPIO pin header on the module P(31 downto 0) + + + + 30-Bit GPIO pin header without uart pins on the module P(29 downto 0) + + + + UART to DIP-Pin header (TxD:P30, RxD:P31) + + + + UART to J2-Pin header (XMOD-JTAG) (TxD:7, RxD:3) + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722/1.0/part0_pins.xml new file mode 100644 index 0000000..da12bec --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722/1.0/part0_pins.xml @@ -0,0 +1,52 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722/1.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722/1.0/preset.xml new file mode 100644 index 0000000..543b458 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722/1.0/preset.xml @@ -0,0 +1,47 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722/1.0/te0722_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722/1.0/te0722_board.png new file mode 100644 index 0000000..9ff11d6 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722/1.0/te0722_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722/1.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722/1.0/xitem.json new file mode 100644 index 0000000..35791cb --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0722", + "display": "ZYNQ-7 TE0722. SPRT PCB: REV01, REV02", + "revision": "1.0", + "description": "ZYNQ-7 TE0722 Board (form factor 1.8 x 5.1 cm) without DDR, speed grade -1 and commercial temperature range. Supported PCB Revisions: REV01,REV2. Note: Primary boot device is QSPI, SD can be used as secondary boot device only. DDR less Zynq need a modified FSBL!", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0722-info", + "search-keywords": [ + "te0722", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722_7S/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722_7S/1.0/board.xml new file mode 100644 index 0000000..485d48d --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722_7S/1.0/board.xml @@ -0,0 +1,389 @@ + + + + + + + + + + + + + ZYNQ-7 TE0722 Board File Image + + + + + + + 0.2 + 0.1 + + + + + 1.0 + + + ZYNQ-7S TE0722-07S Board (form factor 1.8 x 5.1 cm) with single ARM Cortex-A9, without DDR, speed grade -1 and commercial temperature range. Supported PCB Revisions: REV01,REV2. Note: Primary boot device is QSPI, SD can be used as secondary boot device only. DDR less Zynq need a modified FSBL! + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LEDs on the module, one red, one green and one blue + + + + 32-Bit GPIO pin header on the module P(31 downto 0) + + + + 30-Bit GPIO pin header without uart pins on the module P(29 downto 0) + + + + UART to DIP-Pin header (TxD:P30, RxD:P31) + + + + UART to J2-Pin header (XMOD-JTAG) (TxD:7, RxD:3) + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722_7S/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722_7S/1.0/part0_pins.xml new file mode 100644 index 0000000..2d4b795 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722_7S/1.0/part0_pins.xml @@ -0,0 +1,52 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722_7S/1.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722_7S/1.0/preset.xml new file mode 100644 index 0000000..543b458 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722_7S/1.0/preset.xml @@ -0,0 +1,47 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722_7S/1.0/te0722_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722_7S/1.0/te0722_board.png new file mode 100644 index 0000000..9ff11d6 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722_7S/1.0/te0722_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722_7S/1.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722_7S/1.0/xitem.json new file mode 100644 index 0000000..da24af2 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722_7S/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0722_7s", + "display": "ZYNQ-7S TE0722_07S. SPRT PCB: REV01, REV02", + "revision": "1.0", + "description": "ZYNQ-7S TE0722-07S Board (form factor 1.8 x 5.1 cm) with single ARM Cortex-A9, without DDR, speed grade -1 and commercial temperature range. Supported PCB Revisions: REV01,REV2. Note: Primary boot device is QSPI, SD can be used as secondary boot device only. DDR less Zynq need a modified FSBL!", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0722-info", + "search-keywords": [ + "te0722_7s", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722_I/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722_I/1.0/board.xml new file mode 100644 index 0000000..9c7befe --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722_I/1.0/board.xml @@ -0,0 +1,389 @@ + + + + + + + + + + + + + ZYNQ-7 TE0722 Board File Image + + + + + + + 0.2 + 0.1 + + + + + 1.0 + + + ZYNQ-7 TE0722_I Board (form factor 1.8 x 5.1 cm) without DDR, speed grade -1 and industrial temperature range. Supported PCB Revisions: REV01,REV2. Note: Primary boot device is QSPI, SD can be used as secondary boot device only. DDR less Zynq need a modified FSBL! + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LEDs on the module, one red, one green and one blue + + + + 32-Bit GPIO pin header on the module P(31 downto 0) + + + + 30-Bit GPIO pin header without uart pins on the module P(29 downto 0) + + + + UART to DIP-Pin header (TxD:P30, RxD:P31) + + + + UART to J2-Pin header (XMOD-JTAG) (TxD:7, RxD:3) + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722_I/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722_I/1.0/part0_pins.xml new file mode 100644 index 0000000..da12bec --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722_I/1.0/part0_pins.xml @@ -0,0 +1,52 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722_I/1.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722_I/1.0/preset.xml new file mode 100644 index 0000000..543b458 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722_I/1.0/preset.xml @@ -0,0 +1,47 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722_I/1.0/te0722_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722_I/1.0/te0722_board.png new file mode 100644 index 0000000..9ff11d6 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722_I/1.0/te0722_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722_I/1.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722_I/1.0/xitem.json new file mode 100644 index 0000000..98a58f1 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0722_I/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0722_i", + "display": "ZYNQ-7 TE0722_I. SPRT PCB: REV01, REV02", + "revision": "1.0", + "description": "ZYNQ-7 TE0722_I Board (form factor 1.8 x 5.1 cm) without DDR, speed grade -1 and industrial temperature range. Supported PCB Revisions: REV01,REV2. Note: Primary boot device is QSPI, SD can be used as secondary boot device only. DDR less Zynq need a modified FSBL!", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0722-info", + "search-keywords": [ + "te0722_i", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0724_10_1I/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0724_10_1I/1.0/board.xml new file mode 100644 index 0000000..b946c7d --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0724_10_1I/1.0/board.xml @@ -0,0 +1,69 @@ + + + + + + + + + + + + PCB Series Name Board File Image + + + + + + + + 0.2 + + + + + 1.0 + + + ZYNQ-7 TE0724_10_1I Board (form factor 4x6cm) with 1GB DDR3L, 1GBit Ethernet, speed grade -1 and industrial temperature grade. Supported PCB Revisions: REV02. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0724_10_1I/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0724_10_1I/1.0/part0_pins.xml new file mode 100644 index 0000000..d6821e3 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0724_10_1I/1.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0724_10_1I/1.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0724_10_1I/1.0/preset.xml new file mode 100644 index 0000000..9b97037 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0724_10_1I/1.0/preset.xml @@ -0,0 +1,54 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0724_10_1I/1.0/te0724_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0724_10_1I/1.0/te0724_board.png new file mode 100644 index 0000000..8599824 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0724_10_1I/1.0/te0724_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0724_10_1I/1.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0724_10_1I/1.0/xitem.json new file mode 100644 index 0000000..b8779a3 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0724_10_1I/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0724_10_1i", + "display": "ZYNQ-7 TE0724_10_1I( : 1GB DDR3L). SPRT PCB: REV02", + "revision": "1.0", + "description": "ZYNQ-7 TE0724_10_1I Board (form factor 4x6cm) with 1GB DDR3L, 1GBit Ethernet, speed grade -1 and industrial temperature grade. Supported PCB Revisions: REV02.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0724-info", + "search-keywords": [ + "te0724_10_1i", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0724_20_1I/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0724_20_1I/1.0/board.xml new file mode 100644 index 0000000..550a581 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0724_20_1I/1.0/board.xml @@ -0,0 +1,69 @@ + + + + + + + + + + + + PCB Series Name Board File Image + + + + + + + + 0.2 + + + + + 1.0 + + + ZYNQ-7 TE0724_20_1I Board (form factor 4x6cm) with 1GB DDR3L, 1GBit Ethernet, speed grade -1 and industrial temperature grade. Supported PCB Revisions: REV02. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0724_20_1I/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0724_20_1I/1.0/part0_pins.xml new file mode 100644 index 0000000..6f3c0ca --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0724_20_1I/1.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0724_20_1I/1.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0724_20_1I/1.0/preset.xml new file mode 100644 index 0000000..9b97037 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0724_20_1I/1.0/preset.xml @@ -0,0 +1,54 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0724_20_1I/1.0/te0724_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0724_20_1I/1.0/te0724_board.png new file mode 100644 index 0000000..8599824 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0724_20_1I/1.0/te0724_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0724_20_1I/1.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0724_20_1I/1.0/xitem.json new file mode 100644 index 0000000..94430a0 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0724_20_1I/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0724_20_1i", + "display": "ZYNQ-7 TE0724_20_1I( : 1GB DDR3L). SPRT PCB: REV02", + "revision": "1.0", + "description": "ZYNQ-7 TE0724_20_1I Board (form factor 4x6cm) with 1GB DDR3L, 1GBit Ethernet, speed grade -1 and industrial temperature grade. Supported PCB Revisions: REV02.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0724-info", + "search-keywords": [ + "te0724_20_1i", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725LP/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725LP/1.0/board.xml new file mode 100644 index 0000000..d3600bc --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725LP/1.0/board.xml @@ -0,0 +1,943 @@ + + + + + + + + + + + + TE0725LP Image + + + + + + + + 0.1 + + + + + 1.0 + + + TE0725LP_100_2(C, D, L) Board (form factor 3.5x7.3 cm) with optional HyperRAM and commercial temperature grade. Supported PCB Revisions: REV01. Important Note: C, D, L assembly option use different external power supply! + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + All Module B2B as single ASIO GPIO Port + + + + Active High + + + + I2C + + + + USB-to-UART Bridge, which allows a connection to a host computer with a USB port + + + + 256 MB of nonvolatile storage that can be used for configuration or data storage + + + + 100 MHz clock from SiT8008 + + + + + + + system led und normal led + + + + p1a (21 bits) in J1 + + + + p1b (21 bits) in J1 + + + + p2a (21 bits) in J2 + + + + p2b (21 bits) in J2 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725LP/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725LP/1.0/part0_pins.xml new file mode 100644 index 0000000..79f0f39 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725LP/1.0/part0_pins.xml @@ -0,0 +1,139 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725LP/1.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725LP/1.0/preset.xml new file mode 100644 index 0000000..0d40662 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725LP/1.0/preset.xml @@ -0,0 +1,20 @@ + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725LP/1.0/te0725lp_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725LP/1.0/te0725lp_board.png new file mode 100644 index 0000000..58c27d3 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725LP/1.0/te0725lp_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725LP/1.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725LP/1.0/xitem.json new file mode 100644 index 0000000..7a4fdd9 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725LP/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0725lp_100", + "display": "Artix-7 TE0725LP_100_2(C, D, L). SPRT PCB: REV01", + "revision": "1.0", + "description": "TE0725LP_100_2(C, D, L) Board (form factor 3.5x7.3 cm) with optional HyperRAM and commercial temperature grade. Supported PCB Revisions: REV01. Important Note: C, D, L assembly option use different external power supply!", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0725LP-info", + "search-keywords": [ + "te0725lp_100", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_100_2C/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_100_2C/1.0/board.xml new file mode 100644 index 0000000..bb7dd6d --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_100_2C/1.0/board.xml @@ -0,0 +1,945 @@ + + + + + + + + + + + + TE0725 Board File Image + + + + + + + + 0.3 + 0.2 + 0.1 + + + + + 1.0 + + + Artix-7 TE0725_100_2C(_, F) Board (form factor 3.5x7.3 cm) with 8MB HyperRAM and commercial temperature range. PFO only on ...F assembly variant. Supported PCB Revisions: REV01 REV02, REV03. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + All Module B2B as single ASIO GPIO Port + + + + Active High + + + + I2C + + + + USB-to-UART Bridge, which allows a connection to a host computer with a USB port + + + + 256 MB of nonvolatile storage that can be used for configuration or data storage + + + + 100 MHz clock from SiT8008 + + + + + + + system led und normal led + + + + p1a (21 bits) in J1 + + + + p1b (21 bits) in J1 + + + + p2a (21 bits) in J2 + + + + p2b (21 bits) in J2 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_100_2C/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_100_2C/1.0/part0_pins.xml new file mode 100644 index 0000000..9815586 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_100_2C/1.0/part0_pins.xml @@ -0,0 +1,139 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_100_2C/1.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_100_2C/1.0/preset.xml new file mode 100644 index 0000000..81f3c10 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_100_2C/1.0/preset.xml @@ -0,0 +1,20 @@ + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_100_2C/1.0/te0725_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_100_2C/1.0/te0725_board.png new file mode 100644 index 0000000..22169ac Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_100_2C/1.0/te0725_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_100_2C/1.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_100_2C/1.0/xitem.json new file mode 100644 index 0000000..a991b07 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_100_2C/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0725_100_2c", + "display": "Artix-7 TE0725_100_2C(_, F). SPRT PCB: REV01, REV02, REV03", + "revision": "1.0", + "description": "Artix-7 TE0725_100_2C(_, F) Board (form factor 3.5x7.3 cm) with 8MB HyperRAM and commercial temperature range. PFO only on ...F assembly variant. Supported PCB Revisions: REV01 REV02, REV03.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0725-info", + "search-keywords": [ + "te0725_100_2c", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_100_2I/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_100_2I/1.0/board.xml new file mode 100644 index 0000000..b6c19c1 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_100_2I/1.0/board.xml @@ -0,0 +1,945 @@ + + + + + + + + + + + + TE0725 Board File Image + + + + + + + + 0.3 + 0.2 + 0.1 + + + + + 1.0 + + + Artix-7 TE0725_100_2I9 Board (form factor 3.5x7.3 cm) with 8MB HyperRAM and industrial temperature range. Supported PCB Revisions: REV01 REV02, REV03. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + All Module B2B as single ASIO GPIO Port + + + + Active High + + + + I2C + + + + USB-to-UART Bridge, which allows a connection to a host computer with a USB port + + + + 256 MB of nonvolatile storage that can be used for configuration or data storage + + + + 100 MHz clock from SiT8008 + + + + + + + system led und normal led + + + + p1a (21 bits) in J1 + + + + p1b (21 bits) in J1 + + + + p2a (21 bits) in J2 + + + + p2b (21 bits) in J2 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_100_2I/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_100_2I/1.0/part0_pins.xml new file mode 100644 index 0000000..9815586 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_100_2I/1.0/part0_pins.xml @@ -0,0 +1,139 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_100_2I/1.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_100_2I/1.0/preset.xml new file mode 100644 index 0000000..81f3c10 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_100_2I/1.0/preset.xml @@ -0,0 +1,20 @@ + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_100_2I/1.0/te0725_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_100_2I/1.0/te0725_board.png new file mode 100644 index 0000000..22169ac Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_100_2I/1.0/te0725_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_100_2I/1.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_100_2I/1.0/xitem.json new file mode 100644 index 0000000..b860fad --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_100_2I/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0725_100_2i", + "display": "Artix-7 TE0725_100_2I9. SPRT PCB: REV01, REV02, REV03", + "revision": "1.0", + "description": "Artix-7 TE0725_100_2I9 Board (form factor 3.5x7.3 cm) with 8MB HyperRAM and industrial temperature range. Supported PCB Revisions: REV01 REV02, REV03.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0725-info", + "search-keywords": [ + "te0725_100_2i", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_15_1C/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_15_1C/1.0/board.xml new file mode 100644 index 0000000..98a9f1d --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_15_1C/1.0/board.xml @@ -0,0 +1,945 @@ + + + + + + + + + + + + TE0725 Board File Image + + + + + + + + 0.3 + 0.2 + 0.1 + + + + + 1.0 + + + Artix-7 TE0725_15_1C Board (form factor 3.5x7.3 cm) with 8MB HyperRAM and commercial temperature range. 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SPRT PCB: REV01, REV02, REV03", + "revision": "1.0", + "description": "Artix-7 TE0725_15_1C Board (form factor 3.5x7.3 cm) with 8MB HyperRAM and commercial temperature range. Supported PCB Revisions: REV01 REV02, REV03.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0725-info", + "search-keywords": [ + "te0725_15_1c", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_35_2C/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_35_2C/1.0/board.xml new file mode 100644 index 0000000..9d66f5f --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_35_2C/1.0/board.xml @@ -0,0 +1,945 @@ + + + + + + + + + + + + TE0725 Board File Image + + + + + + + + 0.3 + 0.2 + 0.1 + + + + + 1.0 + + + Artix-7 TE0725_35_2C Board (form factor 3.5x7.3 cm) with 8MB HyperRAM and commercial temperature range. Supported PCB Revisions: REV01 REV02, REV03. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + All Module B2B as single ASIO GPIO Port + + + + Active High + + + + I2C + + + + USB-to-UART Bridge, which allows a connection to a host computer with a USB port + + + + 256 MB of nonvolatile storage that can be used for configuration or data storage + + + + 100 MHz clock from SiT8008 + + + + + + + system led und normal led + + + + p1a (21 bits) in J1 + + + + p1b (21 bits) in J1 + + + + p2a (21 bits) in J2 + + + + p2b (21 bits) in J2 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_35_2C/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_35_2C/1.0/part0_pins.xml new file mode 100644 index 0000000..5774cd2 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_35_2C/1.0/part0_pins.xml @@ -0,0 +1,139 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_35_2C/1.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_35_2C/1.0/preset.xml new file mode 100644 index 0000000..81f3c10 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_35_2C/1.0/preset.xml @@ -0,0 +1,20 @@ + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_35_2C/1.0/te0725_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_35_2C/1.0/te0725_board.png new file mode 100644 index 0000000..22169ac Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_35_2C/1.0/te0725_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_35_2C/1.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_35_2C/1.0/xitem.json new file mode 100644 index 0000000..3dc16b1 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0725_35_2C/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0725_35_2c", + "display": "Artix-7 TE0725_35_2C. SPRT PCB: REV01, REV02, REV03", + "revision": "1.0", + "description": "Artix-7 TE0725_35_2C Board (form factor 3.5x7.3 cm) with 8MB HyperRAM and commercial temperature range. Supported PCB Revisions: REV01 REV02, REV03.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0725-info", + "search-keywords": [ + "te0725_35_2c", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/1.0/board.xml new file mode 100644 index 0000000..62b36bc --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/1.0/board.xml @@ -0,0 +1,69 @@ + + + + + + + + + + + + ZYNQ-7 TE0726_01 Board File Image + + + + + + + 0.1 + + + + + 1.0 + + + ZYNQ-7 TE0726-01 ZynqBerry Board (form factor like RPI2) with 64MB Memory and 100MBit Ethernet, speed grade -1 and commercial temperature range. Supported PCB Revisions: REV01. Note: primary boot device is QSPI, SD can be used as secondary boot device only. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/1.0/part0_pins.xml new file mode 100644 index 0000000..f7ce2ba --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/1.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/1.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/1.0/preset.xml new file mode 100644 index 0000000..2b42c97 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/1.0/preset.xml @@ -0,0 +1,58 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/1.0/te0726_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/1.0/te0726_board.png new file mode 100644 index 0000000..5d4cd38 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/1.0/te0726_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/1.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/1.0/xitem.json new file mode 100644 index 0000000..f32b5d5 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0726_01", + "display": "ZYNQ-7 TE0726_01 (64MB DDR). SPRT PCB: REV01.", + "revision": "1.0", + "description": "ZYNQ-7 TE0726-01 ZynqBerry Board (form factor like RPI2) with 64MB Memory and 100MBit Ethernet, speed grade -1 and commercial temperature range. Supported PCB Revisions: REV01. Note: primary boot device is QSPI, SD can be used as secondary boot device only.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0726-info", + "search-keywords": [ + "te0726_01", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/2.1/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/2.1/board.xml new file mode 100644 index 0000000..57f29e6 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/2.1/board.xml @@ -0,0 +1,70 @@ + + + + + + + + + + + + ZYNQ-7 TE0726_R Board File Image + + + + + + + 0.3 + 0.2 + + + + + 2.1 + + + ZYNQ-7 TE0726-R ZynqBerry Board (form factor like RPI2) with 128MB Memory and 100MBit Ethernet, speed grade -1 and commercial temperature range. Supported PCB Revisions: REV03 and REV02. Note: primary boot device is QSPI, SD can be used as secondary boot device only. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/2.1/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/2.1/part0_pins.xml new file mode 100644 index 0000000..1d0deec --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/2.1/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/2.1/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/2.1/preset.xml new file mode 100644 index 0000000..cb46085 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/2.1/preset.xml @@ -0,0 +1,47 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/2.1/te0726_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/2.1/te0726_board.png new file mode 100644 index 0000000..5d4cd38 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/2.1/te0726_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/2.1/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/2.1/xitem.json new file mode 100644 index 0000000..28a0a92 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/2.1/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0726_r", + "display": "ZYNQ-7 TE0726_R (128MB DDR). SPRT PCB: REV03R, REV02.", + "revision": "2.1", + "description": "ZYNQ-7 TE0726-R ZynqBerry Board (form factor like RPI2) with 128MB Memory and 100MBit Ethernet, speed grade -1 and commercial temperature range. Supported PCB Revisions: REV03 and REV02. Note: primary boot device is QSPI, SD can be used as secondary boot device only.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0726-info", + "search-keywords": [ + "te0726_r", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/3.1/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/3.1/board.xml new file mode 100644 index 0000000..bcbeb19 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/3.1/board.xml @@ -0,0 +1,70 @@ + + + + + + + + + + + + ZYNQ-7 TE0726_M Board File Image + + + + + + + 0.3 + 0.2 + + + + + 3.1 + + + ZYNQ-7 TE0726-M ZynqBerry Board (form factor like RPI2) with 512MB Memory and 100MBit Ethernet, speed grade -1 and commercial temperature range. Supported PCB Revisions: REV03 and REV02. Note: primary boot device is QSPI, SD can be used as secondary boot device only. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/3.1/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/3.1/part0_pins.xml new file mode 100644 index 0000000..2c43aef --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/3.1/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/3.1/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/3.1/preset.xml new file mode 100644 index 0000000..da9e4f8 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/3.1/preset.xml @@ -0,0 +1,48 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/3.1/te0726_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/3.1/te0726_board.png new file mode 100644 index 0000000..5d4cd38 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/3.1/te0726_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/3.1/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/3.1/xitem.json new file mode 100644 index 0000000..00d6dc5 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726/3.1/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0726_m", + "display": "ZYNQ-7 TE0726_M (512MB DDR). SPRT PCB: REV03, REV02.", + "revision": "3.1", + "description": "ZYNQ-7 TE0726-M ZynqBerry Board (form factor like RPI2) with 512MB Memory and 100MBit Ethernet, speed grade -1 and commercial temperature range. Supported PCB Revisions: REV03 and REV02. Note: primary boot device is QSPI, SD can be used as secondary boot device only.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0726-info", + "search-keywords": [ + "te0726_m", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726_7S/3.1/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726_7S/3.1/board.xml new file mode 100644 index 0000000..bce0423 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726_7S/3.1/board.xml @@ -0,0 +1,70 @@ + + + + + + + + + + + + ZYNQ-7 TE0726_M Board File Image + + + + + + + 0.3 + 0.2 + + + + + 3.1 + + + ZYNQ-7S TE0726-07S ZynqBerry Board (form factor like RPI2) with single ARM Cortex-A9, 512MB Memory, 100MBit Ethernet, speed grade -1 and commercial temperature range. Supported PCB Revisions: REV03 and REV02. Note: primary boot device is QSPI, SD can be used as secondary boot device only. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726_7S/3.1/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726_7S/3.1/part0_pins.xml new file mode 100644 index 0000000..0449cdd --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726_7S/3.1/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726_7S/3.1/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726_7S/3.1/preset.xml new file mode 100644 index 0000000..da9e4f8 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726_7S/3.1/preset.xml @@ -0,0 +1,48 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726_7S/3.1/te0726_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726_7S/3.1/te0726_board.png new file mode 100644 index 0000000..5d4cd38 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726_7S/3.1/te0726_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726_7S/3.1/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726_7S/3.1/xitem.json new file mode 100644 index 0000000..2afdbf6 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0726_7S/3.1/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0726_7s", + "display": "ZYNQ-7S TE0726_07S (512MB DDR). SPRT PCB: REV03, REV02.", + "revision": "3.1", + "description": "ZYNQ-7S TE0726-07S ZynqBerry Board (form factor like RPI2) with single ARM Cortex-A9, 512MB Memory, 100MBit Ethernet, speed grade -1 and commercial temperature range. Supported PCB Revisions: REV03 and REV02. Note: primary boot device is QSPI, SD can be used as secondary boot device only.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0726-info", + "search-keywords": [ + "te0726_7s", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0729_20_2I/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0729_20_2I/1.0/board.xml new file mode 100644 index 0000000..790d572 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0729_20_2I/1.0/board.xml @@ -0,0 +1,943 @@ + + + + + + + + + + + + TE0729 Board File Image + + + + + + + + 0.2 + 0.1 + + + + + 1.0 + + + ZYNQ-7 TE0729_20_2I(F) Board (form factor 5 x 7 cm) with 512MB DDR3, 2 x 100MBit Ethernet, 1 x 1GBit Ethernet, speed grade -2 and industrial temperature range.Supported PCB Revisions: REV02, REV01. + + + + + + + FPGA part on the board + + + + + + + + + + Primary interface to communicate with ethernet phy in MII mode. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Secondary interface to communicate with ethernet phy when mode is selected as MII,GMII,1000BaseX. + + + + + + + + + + + + + + + + + + + Secondary interface to communicate with ethernet phy when mode is selected as SGMII. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Primary interface to communicate with ethernet phy in MII mode. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Secondary interface to communicate with ethernet phy when mode is selected as MII,GMII,1000BaseX. + + + + + + + + + + + + + + + + + + + Secondary interface to communicate with ethernet phy when mode is selected as SGMII. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + P1a (24 bits) in J1 + + + + P1b (24 bits) in J1 + + + + P1c (24 bits) in J1 + + + + P1d (24 bits) in J1 + + + + P2a (10 bits) in J2 + + + + P2b (30 bits) in J2 + + + + PHY on the board + + + MII0 + + + + + + + + + + + + + + + PHY on the board + + + + MII1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0729_20_2I/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0729_20_2I/1.0/part0_pins.xml new file mode 100644 index 0000000..6d8a68b --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0729_20_2I/1.0/part0_pins.xml @@ -0,0 +1,189 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0729_20_2I/1.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0729_20_2I/1.0/preset.xml new file mode 100644 index 0000000..40df06c --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0729_20_2I/1.0/preset.xml @@ -0,0 +1,62 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0729_20_2I/1.0/te0729_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0729_20_2I/1.0/te0729_board.png new file mode 100644 index 0000000..21a3a49 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0729_20_2I/1.0/te0729_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0729_20_2I/1.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0729_20_2I/1.0/xitem.json new file mode 100644 index 0000000..47c4db6 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0729_20_2I/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0729_20_2i", + "display": "ZYNQ-7 TE0729_20_2I(F). SPRT PCB: REV02, REV01", + "revision": "1.0", + "description": "ZYNQ-7 TE0729_20_2I(F) Board (form factor 5 x 7 cm) with 512MB DDR3, 2 x 100MBit Ethernet, 1 x 1GBit Ethernet, speed grade -2 and industrial temperature range.Supported PCB Revisions: REV02, REV01.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0729-info", + "search-keywords": [ + "te0729_20_2i", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0729_20_2I/2.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0729_20_2I/2.0/board.xml new file mode 100644 index 0000000..d526920 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0729_20_2I/2.0/board.xml @@ -0,0 +1,943 @@ + + + + + + + + + + + + TE0729 Board File Image + + + + + + + + 0.2 + 0.1 + + + + + 2.0 + + + ZYNQ-7 TE0729_20_2I(R,RA) Board (form factor 5 x 7 cm) with 512MB DDR3, 1 x 1GBit Ethernet, speed grade -2 and industrial temperature range.Supported PCB Revisions: REV02, REV01. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0729_20_2I/2.0/te0729_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0729_20_2I/2.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0729_20_2I/2.0/xitem.json new file mode 100644 index 0000000..badc40b --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0729_20_2I/2.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0729_20_2i", + "display": "ZYNQ-7 TE0729_20_2I(R,RA). SPRT PCB: REV02, REV01", + "revision": "2.0", + "description": "ZYNQ-7 TE0729_20_2I(R,RA) Board (form factor 5 x 7 cm) with 512MB DDR3, 1 x 1GBit Ethernet, speed grade -2 and industrial temperature range.Supported PCB Revisions: REV02, REV01.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0729-info", + "search-keywords": [ + "te0729_20_2i", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2CG_1E/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2CG_1E/1.0/board.xml new file mode 100644 index 0000000..96cb97b --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2CG_1E/1.0/board.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0803 Board File Image + + + + + + + + 0.1 + + + + + 1.0 + + + Zynq UltraScale+ TE0803-2CG-1E(_, A: 2GB DDR) Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV01. Board Part is only with minimum PS-Setup. Use for own carrier or simple SDK debugging. User must configure B2B MIOs manually, depending on his carrier board connection. Without user PS configuration only JTAG and QSPI boot is possible with this board part file. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2CG_1E/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2CG_1E/1.0/part0_pins.xml new file mode 100644 index 0000000..b69f352 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2CG_1E/1.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2CG_1E/1.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2CG_1E/1.0/preset.xml new file mode 100644 index 0000000..abadafc --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2CG_1E/1.0/preset.xml @@ -0,0 +1,38 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2CG_1E/1.0/te0803_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2CG_1E/1.0/te0803_board.png new file mode 100644 index 0000000..da41ca0 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2CG_1E/1.0/te0803_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2CG_1E/1.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2CG_1E/1.0/xitem.json new file mode 100644 index 0000000..b750033 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2CG_1E/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0803_2cg_1e", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0803-2CG-1E(_, A: 2GB DDR). SPRT PCB: REV01", + "revision": "1.0", + "description": "Zynq UltraScale+ TE0803-2CG-1E(_, A: 2GB DDR) Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV01. Board Part is only with minimum PS-Setup. Use for own carrier or simple SDK debugging. User must configure B2B MIOs manually, depending on his carrier board connection. Without user PS configuration only JTAG and QSPI boot is possible with this board part file.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0803-info", + "search-keywords": [ + "te0803_2cg_1e", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2CG_1E/2.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2CG_1E/2.0/board.xml new file mode 100644 index 0000000..68295d3 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2CG_1E/2.0/board.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0803 Board File Image + + + + + + + + 0.1 + + + + + 2.0 + + + Zynq UltraScale+ TE0803-2CG-1E(_, A: 2GB DDR) Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV01. Board Part is for usage with carrier-board TEBF0808. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2CG_1E/2.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2CG_1E/2.0/part0_pins.xml new file mode 100644 index 0000000..b69f352 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2CG_1E/2.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2CG_1E/2.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2CG_1E/2.0/preset.xml new file mode 100644 index 0000000..059f7f7 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2CG_1E/2.0/preset.xml @@ -0,0 +1,119 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2CG_1E/2.0/te0803_starterkit.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2CG_1E/2.0/te0803_starterkit.png new file mode 100644 index 0000000..8066350 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2CG_1E/2.0/te0803_starterkit.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2CG_1E/2.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2CG_1E/2.0/xitem.json new file mode 100644 index 0000000..da7a120 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2CG_1E/2.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0803_2cg_1e_tebf0808", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0803-2CG-1E(_, A: 2GB DDR) with TEBF0808. SPRT PCB: REV01", + "revision": "2.0", + "description": "Zynq UltraScale+ TE0803-2CG-1E(_, A: 2GB DDR) Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV01. Board Part is for usage with carrier-board TEBF0808.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0803-info", + "search-keywords": [ + "te0803_2cg_1e_tebf0808", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2EG_1E/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2EG_1E/1.0/board.xml new file mode 100644 index 0000000..3f9f439 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2EG_1E/1.0/board.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0803 Board File Image + + + + + + + + 0.1 + + + + + 1.0 + + + Zynq UltraScale+ TE0803-2EG-1E(_, A: 2GB DDR) Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV01. Board Part is only with minimum PS-Setup. Use for own carrier or simple SDK debugging. User must configure B2B MIOs manually, depending on his carrier board connection. Without user PS configuration only JTAG and QSPI boot is possible with this board part file. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2EG_1E/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2EG_1E/1.0/part0_pins.xml new file mode 100644 index 0000000..2266f7a --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2EG_1E/1.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2EG_1E/1.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2EG_1E/1.0/preset.xml new file mode 100644 index 0000000..abadafc --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2EG_1E/1.0/preset.xml @@ -0,0 +1,38 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2EG_1E/1.0/te0803_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2EG_1E/1.0/te0803_board.png new file mode 100644 index 0000000..da41ca0 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2EG_1E/1.0/te0803_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2EG_1E/1.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2EG_1E/1.0/xitem.json new file mode 100644 index 0000000..adb5191 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2EG_1E/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0803_2eg_1e", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0803-2EG-1E(_, A: 2GB DDR). SPRT PCB: REV01", + "revision": "1.0", + "description": "Zynq UltraScale+ TE0803-2EG-1E(_, A: 2GB DDR) Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV01. Board Part is only with minimum PS-Setup. Use for own carrier or simple SDK debugging. User must configure B2B MIOs manually, depending on his carrier board connection. Without user PS configuration only JTAG and QSPI boot is possible with this board part file.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0803-info", + "search-keywords": [ + "te0803_2eg_1e", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2EG_1E/2.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2EG_1E/2.0/board.xml new file mode 100644 index 0000000..2ac55a1 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2EG_1E/2.0/board.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0803 Board File Image + + + + + + + + 0.1 + + + + + 2.0 + + + Zynq UltraScale+ TE0803-2EG-1E(_, A: 2GB DDR) Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV01. Board Part is for usage with carrier-board TEBF0808. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2EG_1E/2.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2EG_1E/2.0/part0_pins.xml new file mode 100644 index 0000000..2266f7a --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2EG_1E/2.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2EG_1E/2.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2EG_1E/2.0/preset.xml new file mode 100644 index 0000000..059f7f7 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2EG_1E/2.0/preset.xml @@ -0,0 +1,119 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2EG_1E/2.0/te0803_starterkit.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2EG_1E/2.0/te0803_starterkit.png new file mode 100644 index 0000000..8066350 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2EG_1E/2.0/te0803_starterkit.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2EG_1E/2.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2EG_1E/2.0/xitem.json new file mode 100644 index 0000000..fcb724e --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_2EG_1E/2.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0803_2eg_1e_tebf0808", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0803-2EG-1E(_, A: 2GB DDR) with TEBF0808. SPRT PCB: REV01", + "revision": "2.0", + "description": "Zynq UltraScale+ TE0803-2EG-1E(_, A: 2GB DDR) Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV01. Board Part is for usage with carrier-board TEBF0808.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0803-info", + "search-keywords": [ + "te0803_2eg_1e_tebf0808", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3CG_1E/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3CG_1E/1.0/board.xml new file mode 100644 index 0000000..040342b --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3CG_1E/1.0/board.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0803 Board File Image + + + + + + + + 0.1 + + + + + 1.0 + + + Zynq UltraScale+ TE0803-3CG-1E(_, A: 2GB DDR) Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV01. Board Part is only with minimum PS-Setup. Use for own carrier or simple SDK debugging. User must configure B2B MIOs manually, depending on his carrier board connection. Without user PS configuration only JTAG and QSPI boot is possible with this board part file. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3CG_1E/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3CG_1E/1.0/part0_pins.xml new file mode 100644 index 0000000..8e257cb --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3CG_1E/1.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3CG_1E/1.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3CG_1E/1.0/preset.xml new file mode 100644 index 0000000..abadafc --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3CG_1E/1.0/preset.xml @@ -0,0 +1,38 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3CG_1E/1.0/te0803_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3CG_1E/1.0/te0803_board.png new file mode 100644 index 0000000..da41ca0 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3CG_1E/1.0/te0803_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3CG_1E/1.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3CG_1E/1.0/xitem.json new file mode 100644 index 0000000..c06b121 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3CG_1E/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0803_3cg_1e", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0803-3CG-1E(_, A: 2GB DDR). SPRT PCB: REV01", + "revision": "1.0", + "description": "Zynq UltraScale+ TE0803-3CG-1E(_, A: 2GB DDR) Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV01. Board Part is only with minimum PS-Setup. Use for own carrier or simple SDK debugging. User must configure B2B MIOs manually, depending on his carrier board connection. Without user PS configuration only JTAG and QSPI boot is possible with this board part file.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0803-info", + "search-keywords": [ + "te0803_3cg_1e", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3CG_1E/2.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3CG_1E/2.0/board.xml new file mode 100644 index 0000000..3a1e331 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3CG_1E/2.0/board.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0803 Board File Image + + + + + + + + 0.1 + + + + + 2.0 + + + Zynq UltraScale+ TE0803-3CG-1E(_, A: 2GB DDR) Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV01. Board Part is for usage with carrier-board TEBF0808. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3CG_1E/2.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3CG_1E/2.0/part0_pins.xml new file mode 100644 index 0000000..8e257cb --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3CG_1E/2.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3CG_1E/2.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3CG_1E/2.0/preset.xml new file mode 100644 index 0000000..059f7f7 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3CG_1E/2.0/preset.xml @@ -0,0 +1,119 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3CG_1E/2.0/te0803_starterkit.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3CG_1E/2.0/te0803_starterkit.png new file mode 100644 index 0000000..8066350 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3CG_1E/2.0/te0803_starterkit.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3CG_1E/2.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3CG_1E/2.0/xitem.json new file mode 100644 index 0000000..89f4136 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3CG_1E/2.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0803_3cg_1e_tebf0808", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0803-3CG-1E(_, A: 2GB DDR) with TEBF0808. SPRT PCB: REV01", + "revision": "2.0", + "description": "Zynq UltraScale+ TE0803-3CG-1E(_, A: 2GB DDR) Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV01. Board Part is for usage with carrier-board TEBF0808.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0803-info", + "search-keywords": [ + "te0803_3cg_1e_tebf0808", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/1.0/board.xml new file mode 100644 index 0000000..3dcef5a --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/1.0/board.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0803 Board File Image + + + + + + + + 0.1 + + + + + 1.0 + + + Zynq UltraScale+ TE0803-3EG-1E(_, A: 2GB DDR) Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV01. Board Part is only with minimum PS-Setup. Use for own carrier or simple SDK debugging. User must configure B2B MIOs manually, depending on his carrier board connection. Without user PS configuration only JTAG and QSPI boot is possible with this board part file. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/1.0/part0_pins.xml new file mode 100644 index 0000000..79ef328 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/1.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/1.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/1.0/preset.xml new file mode 100644 index 0000000..abadafc --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/1.0/preset.xml @@ -0,0 +1,38 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/1.0/te0803_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/1.0/te0803_board.png new file mode 100644 index 0000000..da41ca0 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/1.0/te0803_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/1.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/1.0/xitem.json new file mode 100644 index 0000000..ff7bd74 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0803_3eg_1e", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0803-3EG-1E(_, A: 2GB DDR). SPRT PCB: REV01", + "revision": "1.0", + "description": "Zynq UltraScale+ TE0803-3EG-1E(_, A: 2GB DDR) Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV01. Board Part is only with minimum PS-Setup. Use for own carrier or simple SDK debugging. User must configure B2B MIOs manually, depending on his carrier board connection. Without user PS configuration only JTAG and QSPI boot is possible with this board part file.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0803-info", + "search-keywords": [ + "te0803_3eg_1e", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/2.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/2.0/board.xml new file mode 100644 index 0000000..2875a22 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/2.0/board.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0803 Board File Image + + + + + + + + 0.1 + + + + + 2.0 + + + Zynq UltraScale+ TE0803-3EG-1E(_, A: 2GB DDR) Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV01. Board Part is for usage with carrier-board TEBF0808. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/2.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/2.0/part0_pins.xml new file mode 100644 index 0000000..79ef328 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/2.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/2.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/2.0/preset.xml new file mode 100644 index 0000000..059f7f7 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/2.0/preset.xml @@ -0,0 +1,119 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/2.0/te0803_starterkit.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/2.0/te0803_starterkit.png new file mode 100644 index 0000000..8066350 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/2.0/te0803_starterkit.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/2.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/2.0/xitem.json new file mode 100644 index 0000000..49128c1 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/2.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0803_3eg_1e_tebf0808", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0803-3EG-1E(_, A: 2GB DDR) with TEBF0808. SPRT PCB: REV01", + "revision": "2.0", + "description": "Zynq UltraScale+ TE0803-3EG-1E(_, A: 2GB DDR) Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV01. Board Part is for usage with carrier-board TEBF0808.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0803-info", + "search-keywords": [ + "te0803_3eg_1e_tebf0808", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/3.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/3.0/board.xml new file mode 100644 index 0000000..cf7a1ef --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/3.0/board.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0803 Board File Image + + + + + + + + 0.1 + + + + + 3.0 + + + Zynq UltraScale+ TE0803-3EG-1E(B: 4GB DDR) Board (form factor 5.2x7.6 cm) with 4x 1 GByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV01. Board Part is only with minimum PS-Setup. Use for own carrier or simple SDK debugging. User must configure B2B MIOs manually, depending on his carrier board connection. Without user PS configuration only JTAG and QSPI boot is possible with this board part file. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/3.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/3.0/part0_pins.xml new file mode 100644 index 0000000..79ef328 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/3.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/3.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/3.0/preset.xml new file mode 100644 index 0000000..6823684 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/3.0/preset.xml @@ -0,0 +1,44 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/3.0/te0803_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/3.0/te0803_board.png new file mode 100644 index 0000000..da41ca0 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/3.0/te0803_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/3.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/3.0/xitem.json new file mode 100644 index 0000000..be684c3 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/3.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0803_3eg_1e", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0803-3EG-1E(B: 4GB DDR). SPRT PCB: REV01", + "revision": "3.0", + "description": "Zynq UltraScale+ TE0803-3EG-1E(B: 4GB DDR) Board (form factor 5.2x7.6 cm) with 4x 1 GByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV01. Board Part is only with minimum PS-Setup. Use for own carrier or simple SDK debugging. User must configure B2B MIOs manually, depending on his carrier board connection. Without user PS configuration only JTAG and QSPI boot is possible with this board part file.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0803-info", + "search-keywords": [ + "te0803_3eg_1e", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/4.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/4.0/board.xml new file mode 100644 index 0000000..3601a07 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/4.0/board.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0803 Board File Image + + + + + + + + 0.1 + + + + + 4.0 + + + Zynq UltraScale+ TE0803-3EG-1E(B: 4GB DDR) Board (form factor 5.2x7.6 cm) with 4x 1 GByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV01. Board Part is for usage with carrier-board TEBF0808. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/4.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/4.0/part0_pins.xml new file mode 100644 index 0000000..79ef328 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/4.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/4.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/4.0/preset.xml new file mode 100644 index 0000000..66ede85 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/4.0/preset.xml @@ -0,0 +1,125 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/4.0/te0803_starterkit.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/4.0/te0803_starterkit.png new file mode 100644 index 0000000..8066350 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/4.0/te0803_starterkit.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/4.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/4.0/xitem.json new file mode 100644 index 0000000..da87bd0 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_3EG_1E/4.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0803_3eg_1e_tebf0808", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0803-3EG-1E(B: 4GB DDR) with TEBF0808. SPRT PCB: REV01", + "revision": "4.0", + "description": "Zynq UltraScale+ TE0803-3EG-1E(B: 4GB DDR) Board (form factor 5.2x7.6 cm) with 4x 1 GByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV01. Board Part is for usage with carrier-board TEBF0808.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0803-info", + "search-keywords": [ + "te0803_3eg_1e_tebf0808", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4CG_1E/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4CG_1E/1.0/board.xml new file mode 100644 index 0000000..71e55c6 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4CG_1E/1.0/board.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0803 Board File Image + + + + + + + + 0.1 + + + + + 1.0 + + + Zynq UltraScale+ TE0803-4CG-1E(A: 2GB DDR) Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV01. Board Part is only with minimum PS-Setup. Use for own carrier or simple SDK debugging. User must configure B2B MIOs manually, depending on his carrier board connection. Without user PS configuration only JTAG and QSPI boot is possible with this board part file. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4CG_1E/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4CG_1E/1.0/part0_pins.xml new file mode 100644 index 0000000..4175677 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4CG_1E/1.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4CG_1E/1.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4CG_1E/1.0/preset.xml new file mode 100644 index 0000000..abadafc --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4CG_1E/1.0/preset.xml @@ -0,0 +1,38 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4CG_1E/1.0/te0803_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4CG_1E/1.0/te0803_board.png new file mode 100644 index 0000000..da41ca0 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4CG_1E/1.0/te0803_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4CG_1E/1.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4CG_1E/1.0/xitem.json new file mode 100644 index 0000000..a223ae6 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4CG_1E/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0803_4cg_1e", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0803-4CG-1E(A: 2GB DDR). SPRT PCB: REV01", + "revision": "1.0", + "description": "Zynq UltraScale+ TE0803-4CG-1E(A: 2GB DDR) Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV01. Board Part is only with minimum PS-Setup. Use for own carrier or simple SDK debugging. User must configure B2B MIOs manually, depending on his carrier board connection. Without user PS configuration only JTAG and QSPI boot is possible with this board part file.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0803-info", + "search-keywords": [ + "te0803_4cg_1e", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4CG_1E/2.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4CG_1E/2.0/board.xml new file mode 100644 index 0000000..89852d7 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4CG_1E/2.0/board.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0803 Board File Image + + + + + + + + 0.1 + + + + + 2.0 + + + Zynq UltraScale+ TE0803-4CG-1E(A: 2GB DDR) Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV01. Board Part is for usage with carrier-board TEBF0808. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4CG_1E/2.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4CG_1E/2.0/part0_pins.xml new file mode 100644 index 0000000..4175677 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4CG_1E/2.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4CG_1E/2.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4CG_1E/2.0/preset.xml new file mode 100644 index 0000000..059f7f7 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4CG_1E/2.0/preset.xml @@ -0,0 +1,119 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4CG_1E/2.0/te0803_starterkit.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4CG_1E/2.0/te0803_starterkit.png new file mode 100644 index 0000000..8066350 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4CG_1E/2.0/te0803_starterkit.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4CG_1E/2.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4CG_1E/2.0/xitem.json new file mode 100644 index 0000000..ff74d15 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4CG_1E/2.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0803_4cg_1e_tebf0808", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0803-4CG-1E(A: 2GB DDR) with TEBF0808. SPRT PCB: REV01", + "revision": "2.0", + "description": "Zynq UltraScale+ TE0803-4CG-1E(A: 2GB DDR) Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV01. Board Part is for usage with carrier-board TEBF0808.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0803-info", + "search-keywords": [ + "te0803_4cg_1e_tebf0808", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1E/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1E/1.0/board.xml new file mode 100644 index 0000000..ec72f8f --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1E/1.0/board.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0803 Board File Image + + + + + + + + 0.1 + + + + + 1.0 + + + Zynq UltraScale+ TE0803-4EG-1E(A: 2GB DDR) Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV01. Board Part is only with minimum PS-Setup. Use for own carrier or simple SDK debugging. User must configure B2B MIOs manually, depending on his carrier board connection. Without user PS configuration only JTAG and QSPI boot is possible with this board part file. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1E/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1E/1.0/part0_pins.xml new file mode 100644 index 0000000..9f99879 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1E/1.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1E/1.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1E/1.0/preset.xml new file mode 100644 index 0000000..abadafc --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1E/1.0/preset.xml @@ -0,0 +1,38 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1E/1.0/te0803_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1E/1.0/te0803_board.png new file mode 100644 index 0000000..da41ca0 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1E/1.0/te0803_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1E/1.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1E/1.0/xitem.json new file mode 100644 index 0000000..3369837 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1E/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0803_4eg_1e", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0803-4EG-1E(A: 2GB DDR). SPRT PCB: REV01", + "revision": "1.0", + "description": "Zynq UltraScale+ TE0803-4EG-1E(A: 2GB DDR) Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV01. Board Part is only with minimum PS-Setup. Use for own carrier or simple SDK debugging. User must configure B2B MIOs manually, depending on his carrier board connection. Without user PS configuration only JTAG and QSPI boot is possible with this board part file.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0803-info", + "search-keywords": [ + "te0803_4eg_1e", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1E/2.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1E/2.0/board.xml new file mode 100644 index 0000000..f5cd351 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1E/2.0/board.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0803 Board File Image + + + + + + + + 0.1 + + + + + 2.0 + + + Zynq UltraScale+ TE0803-4EG-1E(A: 2GB DDR) Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV01. Board Part is for usage with carrier-board TEBF0808. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1E/2.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1E/2.0/part0_pins.xml new file mode 100644 index 0000000..9f99879 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1E/2.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1E/2.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1E/2.0/preset.xml new file mode 100644 index 0000000..059f7f7 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1E/2.0/preset.xml @@ -0,0 +1,119 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1E/2.0/te0803_starterkit.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1E/2.0/te0803_starterkit.png new file mode 100644 index 0000000..8066350 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1E/2.0/te0803_starterkit.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1E/2.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1E/2.0/xitem.json new file mode 100644 index 0000000..7f12fae --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1E/2.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0803_4eg_1e_tebf0808", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0803-4EG-1E(A: 2GB DDR) with TEBF0808. SPRT PCB: REV01", + "revision": "2.0", + "description": "Zynq UltraScale+ TE0803-4EG-1E(A: 2GB DDR) Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV01. Board Part is for usage with carrier-board TEBF0808.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0803-info", + "search-keywords": [ + "te0803_4eg_1e_tebf0808", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1I/5.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1I/5.0/board.xml new file mode 100644 index 0000000..0de26ad --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1I/5.0/board.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0803 Board File Image + + + + + + + + 0.2 + + + + + 5.0 + + + Zynq UltraScale+ TE0803-4EG-1I(C: 8GB DDR) Board (form factor 5.2x7.6 cm) with 4x 2 GigaByte DDR4, speed grade -1 and industrial temperature range. Supported PCB Revisions: REV02. Board Part is only with minimum PS-Setup. Use for own carrier or simple SDK debugging. User must configure B2B MIOs manually, depending on his carrier board connection. Without user PS configuration only JTAG and QSPI boot is possible with this board part file. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1I/5.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1I/5.0/part0_pins.xml new file mode 100644 index 0000000..97cae3d --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1I/5.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1I/5.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1I/5.0/preset.xml new file mode 100644 index 0000000..abadafc --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1I/5.0/preset.xml @@ -0,0 +1,38 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1I/5.0/te0803_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1I/5.0/te0803_board.png new file mode 100644 index 0000000..da41ca0 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1I/5.0/te0803_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1I/5.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1I/5.0/xitem.json new file mode 100644 index 0000000..ac318d5 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1I/5.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0803_4eg_1i", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0803-4EG-1I(C: 8GB DDR). SPRT PCB: REV02", + "revision": "5.0", + "description": "Zynq UltraScale+ TE0803-4EG-1I(C: 8GB DDR) Board (form factor 5.2x7.6 cm) with 4x 2 GigaByte DDR4, speed grade -1 and industrial temperature range. Supported PCB Revisions: REV02. Board Part is only with minimum PS-Setup. Use for own carrier or simple SDK debugging. User must configure B2B MIOs manually, depending on his carrier board connection. Without user PS configuration only JTAG and QSPI boot is possible with this board part file.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0803-info", + "search-keywords": [ + "te0803_4eg_1i", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1I/6.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1I/6.0/board.xml new file mode 100644 index 0000000..a07fd8c --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1I/6.0/board.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0803 Board File Image + + + + + + + + 0.2 + + + + + 6.0 + + + Zynq UltraScale+ TE0803-4EG-1I(C: 8GB DDR) Board (form factor 5.2x7.6 cm) with 4x 2 GigaByte DDR4, speed grade -1 and industrial temperature range. Supported PCB Revisions: REV02. Board Part is for usage with carrier-board TEBF0808. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1I/6.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1I/6.0/part0_pins.xml new file mode 100644 index 0000000..97cae3d --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1I/6.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1I/6.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1I/6.0/preset.xml new file mode 100644 index 0000000..db40c8e --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1I/6.0/preset.xml @@ -0,0 +1,125 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1I/6.0/te0803_starterkit.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1I/6.0/te0803_starterkit.png new file mode 100644 index 0000000..8066350 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1I/6.0/te0803_starterkit.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1I/6.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1I/6.0/xitem.json new file mode 100644 index 0000000..086c9cb --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EG_1I/6.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0803_4eg_1i_tebf0808", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0803-4EG-1I(C: 8GB DDR) with TEBF0808. SPRT PCB: REV02", + "revision": "6.0", + "description": "Zynq UltraScale+ TE0803-4EG-1I(C: 8GB DDR) Board (form factor 5.2x7.6 cm) with 4x 2 GigaByte DDR4, speed grade -1 and industrial temperature range. Supported PCB Revisions: REV02. Board Part is for usage with carrier-board TEBF0808.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0803-info", + "search-keywords": [ + "te0803_4eg_1i_tebf0808", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EV_1E/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EV_1E/1.0/board.xml new file mode 100644 index 0000000..9207bd4 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EV_1E/1.0/board.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0803 Board File Image + + + + + + + + 0.1 + + + + + 1.0 + + + Zynq UltraScale+ TE0803-4EV-1E(A, 3: 2GB DDR) Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV01. Board Part is only with minimum PS-Setup. Use for own carrier or simple SDK debugging. User must configure B2B MIOs manually, depending on his carrier board connection. Without user PS configuration only JTAG and QSPI boot is possible with this board part file. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EV_1E/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EV_1E/1.0/part0_pins.xml new file mode 100644 index 0000000..d5b5bfa --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EV_1E/1.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EV_1E/1.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EV_1E/1.0/preset.xml new file mode 100644 index 0000000..abadafc --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EV_1E/1.0/preset.xml @@ -0,0 +1,38 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EV_1E/1.0/te0803_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EV_1E/1.0/te0803_board.png new file mode 100644 index 0000000..da41ca0 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EV_1E/1.0/te0803_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EV_1E/1.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EV_1E/1.0/xitem.json new file mode 100644 index 0000000..2a2d7b6 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EV_1E/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0803_4ev_1e", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0803-4EV-1E(A, 3: 2GB DDR). SPRT PCB: REV01", + "revision": "1.0", + "description": "Zynq UltraScale+ TE0803-4EV-1E(A, 3: 2GB DDR) Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV01. Board Part is only with minimum PS-Setup. Use for own carrier or simple SDK debugging. User must configure B2B MIOs manually, depending on his carrier board connection. Without user PS configuration only JTAG and QSPI boot is possible with this board part file.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0803-info", + "search-keywords": [ + "te0803_4ev_1e", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EV_1E/2.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EV_1E/2.0/board.xml new file mode 100644 index 0000000..5a5cae2 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EV_1E/2.0/board.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0803 Board File Image + + + + + + + + 0.1 + + + + + 2.0 + + + Zynq UltraScale+ TE0803-4EV-1E(A, 3: 2GB DDR) Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV01. Board Part is for usage with carrier-board TEBF0808. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EV_1E/2.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EV_1E/2.0/part0_pins.xml new file mode 100644 index 0000000..d5b5bfa --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EV_1E/2.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EV_1E/2.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EV_1E/2.0/preset.xml new file mode 100644 index 0000000..059f7f7 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EV_1E/2.0/preset.xml @@ -0,0 +1,119 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EV_1E/2.0/te0803_starterkit.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EV_1E/2.0/te0803_starterkit.png new file mode 100644 index 0000000..8066350 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EV_1E/2.0/te0803_starterkit.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EV_1E/2.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EV_1E/2.0/xitem.json new file mode 100644 index 0000000..aea5137 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_4EV_1E/2.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0803_4ev_1e_tebf0808", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0803-4EV-1E(A, 3: 2GB DDR) with TEBF0808. SPRT PCB: REV01", + "revision": "2.0", + "description": "Zynq UltraScale+ TE0803-4EV-1E(A, 3: 2GB DDR) Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV01. Board Part is for usage with carrier-board TEBF0808.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0803-info", + "search-keywords": [ + "te0803_4ev_1e_tebf0808", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1E/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1E/1.0/board.xml new file mode 100644 index 0000000..58ffc50 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1E/1.0/board.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0803 Board File Image + + + + + + + + 0.1 + + + + + 1.0 + + + Zynq UltraScale+ TE0803-5EV-1E(A: 2GB DDR) Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV01. Board Part is only with minimum PS-Setup. Use for own carrier or simple SDK debugging. User must configure B2B MIOs manually, depending on his carrier board connection. Without user PS configuration only JTAG and QSPI boot is possible with this board part file. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1E/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1E/1.0/part0_pins.xml new file mode 100644 index 0000000..0e45bf2 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1E/1.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1E/1.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1E/1.0/preset.xml new file mode 100644 index 0000000..abadafc --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1E/1.0/preset.xml @@ -0,0 +1,38 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1E/1.0/te0803_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1E/1.0/te0803_board.png new file mode 100644 index 0000000..da41ca0 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1E/1.0/te0803_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1E/1.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1E/1.0/xitem.json new file mode 100644 index 0000000..a1e7739 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1E/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0803_5ev_1e", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0803-5EV-1E(A: 2GB DDR). SPRT PCB: REV01", + "revision": "1.0", + "description": "Zynq UltraScale+ TE0803-5EV-1E(A: 2GB DDR) Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV01. Board Part is only with minimum PS-Setup. Use for own carrier or simple SDK debugging. User must configure B2B MIOs manually, depending on his carrier board connection. Without user PS configuration only JTAG and QSPI boot is possible with this board part file.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0803-info", + "search-keywords": [ + "te0803_5ev_1e", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1E/2.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1E/2.0/board.xml new file mode 100644 index 0000000..a81c707 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1E/2.0/board.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0803 Board File Image + + + + + + + + 0.1 + + + + + 2.0 + + + Zynq UltraScale+ TE0803-5EV-1E(A: 2GB DDR) Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV01. Board Part is for usage with carrier-board TEBF0808. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1E/2.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1E/2.0/part0_pins.xml new file mode 100644 index 0000000..0e45bf2 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1E/2.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1E/2.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1E/2.0/preset.xml new file mode 100644 index 0000000..059f7f7 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1E/2.0/preset.xml @@ -0,0 +1,119 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1E/2.0/te0803_starterkit.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1E/2.0/te0803_starterkit.png new file mode 100644 index 0000000..8066350 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1E/2.0/te0803_starterkit.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1E/2.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1E/2.0/xitem.json new file mode 100644 index 0000000..6049f09 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1E/2.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0803_5ev_1e_tebf0808", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0803-5EV-1E(A: 2GB DDR) with TEBF0808. SPRT PCB: REV01", + "revision": "2.0", + "description": "Zynq UltraScale+ TE0803-5EV-1E(A: 2GB DDR) Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV01. Board Part is for usage with carrier-board TEBF0808.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0803-info", + "search-keywords": [ + "te0803_5ev_1e_tebf0808", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1I/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1I/1.0/board.xml new file mode 100644 index 0000000..4a17703 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1I/1.0/board.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0803 Board File Image + + + + + + + + 0.1 + + + + + 1.0 + + + Zynq UltraScale+ TE0803-5EV-1I(A: 2GB DDR) Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, speed grade -1 and industrial temperature range. Supported PCB Revisions: REV01. Board Part is only with minimum PS-Setup. Use for own carrier or simple SDK debugging. User must configure B2B MIOs manually, depending on his carrier board connection. Without user PS configuration only JTAG and QSPI boot is possible with this board part file. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1I/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1I/1.0/part0_pins.xml new file mode 100644 index 0000000..b3cb7b7 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1I/1.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1I/1.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1I/1.0/preset.xml new file mode 100644 index 0000000..abadafc --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1I/1.0/preset.xml @@ -0,0 +1,38 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1I/1.0/te0803_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1I/1.0/te0803_board.png new file mode 100644 index 0000000..da41ca0 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1I/1.0/te0803_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1I/1.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1I/1.0/xitem.json new file mode 100644 index 0000000..868b32d --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1I/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0803_5ev_1i", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0803-5EV-1I(A: 2GB DDR). SPRT PCB: REV01", + "revision": "1.0", + "description": "Zynq UltraScale+ TE0803-5EV-1I(A: 2GB DDR) Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, speed grade -1 and industrial temperature range. Supported PCB Revisions: REV01. Board Part is only with minimum PS-Setup. Use for own carrier or simple SDK debugging. User must configure B2B MIOs manually, depending on his carrier board connection. Without user PS configuration only JTAG and QSPI boot is possible with this board part file.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0803-info", + "search-keywords": [ + "te0803_5ev_1i", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1I/2.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1I/2.0/board.xml new file mode 100644 index 0000000..5cbd369 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1I/2.0/board.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0803 Board File Image + + + + + + + + 0.1 + + + + + 2.0 + + + Zynq UltraScale+ TE0803-5EV-1I(A: 2GB DDR) Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, speed grade -1 and industrial temperature range. Supported PCB Revisions: REV01. Board Part is for usage with carrier-board TEBF0808. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1I/2.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1I/2.0/part0_pins.xml new file mode 100644 index 0000000..b3cb7b7 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1I/2.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1I/2.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1I/2.0/preset.xml new file mode 100644 index 0000000..059f7f7 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1I/2.0/preset.xml @@ -0,0 +1,119 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1I/2.0/te0803_starterkit.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1I/2.0/te0803_starterkit.png new file mode 100644 index 0000000..8066350 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1I/2.0/te0803_starterkit.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1I/2.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1I/2.0/xitem.json new file mode 100644 index 0000000..e1ca58f --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0803_5EV_1I/2.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0803_5ev_1i_tebf0808", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0803-5EV-1I(A: 2GB DDR) with TEBF0808. SPRT PCB: REV01", + "revision": "2.0", + "description": "Zynq UltraScale+ TE0803-5EV-1I(A: 2GB DDR) Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, speed grade -1 and industrial temperature range. Supported PCB Revisions: REV01. Board Part is for usage with carrier-board TEBF0808.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0803-info", + "search-keywords": [ + "te0803_5ev_1i_tebf0808", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0807_ES2/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0807_ES2/1.0/board.xml new file mode 100644 index 0000000..5f0efd6 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0807_ES2/1.0/board.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + PCB Series Name Board File Image + + + + + + + + 0.1 + + + + + 1.0 + + + UltraSOM (ZYNQ-UltraScale+) TE0807-07EV-1E-ES2 Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, Speed Grade -1 and extended temperature range. Supported PCB Revisions: REV01. Board Part is only with minimum PS-Setup. Use for own carrier or simple SDK debugging. User must configure B2B MIOs manually, depending on his carrier board connection. Without user PS configuration only JTAG and QSPI boot is possible with this board part file. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0807_ES2/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0807_ES2/1.0/part0_pins.xml new file mode 100644 index 0000000..f81f338 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0807_ES2/1.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0807_ES2/1.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0807_ES2/1.0/preset.xml new file mode 100644 index 0000000..18dd4f7 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0807_ES2/1.0/preset.xml @@ -0,0 +1,43 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0807_ES2/1.0/te0807_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0807_ES2/1.0/te0807_board.png new file mode 100644 index 0000000..f2bb958 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0807_ES2/1.0/te0807_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0807_ES2/1.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0807_ES2/1.0/xitem.json new file mode 100644 index 0000000..ec20441 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0807_ES2/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0807_es2", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0807-07EV-1E-ES2. SPRT PCB: REV01.", + "revision": "1.0", + "description": "UltraSOM (ZYNQ-UltraScale+) TE0807-07EV-1E-ES2 Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, Speed Grade -1 and extended temperature range. Supported PCB Revisions: REV01. Board Part is only with minimum PS-Setup. Use for own carrier or simple SDK debugging. User must configure B2B MIOs manually, depending on his carrier board connection. Without user PS configuration only JTAG and QSPI boot is possible with this board part file.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0807-info", + "search-keywords": [ + "te0807_es2", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0807_ES2/2.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0807_ES2/2.0/board.xml new file mode 100644 index 0000000..b86aa44 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0807_ES2/2.0/board.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + PCB Series Name Board File Image + + + + + + + + 0.1 + + + + + 2.0 + + + UltraSOM (ZYNQ-UltraScale+) TE0807-07EV-1E-ES2 Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, Speed Grade -1 and extended temperature range. Supported PCB Revisions: REV01. Board Part is for usage with carrier-board TEBF0808. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0807_ES2/2.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0807_ES2/2.0/part0_pins.xml new file mode 100644 index 0000000..f81f338 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0807_ES2/2.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0807_ES2/2.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0807_ES2/2.0/preset.xml new file mode 100644 index 0000000..0faddc1 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0807_ES2/2.0/preset.xml @@ -0,0 +1,123 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0807_ES2/2.0/te0807_starterkit.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0807_ES2/2.0/te0807_starterkit.png new file mode 100644 index 0000000..2410feb Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0807_ES2/2.0/te0807_starterkit.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0807_ES2/2.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0807_ES2/2.0/xitem.json new file mode 100644 index 0000000..9faaa29 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0807_ES2/2.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0807_es2_tebf0808", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0807-07EV-1E-ES2 with TEBF0808. SPRT PCB: REV01.", + "revision": "2.0", + "description": "UltraSOM (ZYNQ-UltraScale+) TE0807-07EV-1E-ES2 Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, Speed Grade -1 and extended temperature range. Supported PCB Revisions: REV01. Board Part is for usage with carrier-board TEBF0808.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0807-info", + "search-keywords": [ + "te0807_es2_tebf0808", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_15EG_1E/3.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_15EG_1E/3.0/board.xml new file mode 100644 index 0000000..8bafd28 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_15EG_1E/3.0/board.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0808 Board File Image + + + + + + + + 0.4 + + + + + 3.0 + + + Zynq UltraScale+ TE0808-15EG-1E(B,E: 4GB DDR) Board (form factor 5.2x7.6 cm) with 4x 1 GByte DDR4, speed grade -1 and extended temperature range. Board Part is only with minimum PS-Setup. Use for own carrier or simple SDK debugging. User must configure B2B MIOs manually, depending on his carrier board connection. Without user PS configuration only JTAG and QSPI boot is possible with this board part file. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_15EG_1E/3.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_15EG_1E/3.0/part0_pins.xml new file mode 100644 index 0000000..c2cce2f --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_15EG_1E/3.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_15EG_1E/3.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_15EG_1E/3.0/preset.xml new file mode 100644 index 0000000..112f956 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_15EG_1E/3.0/preset.xml @@ -0,0 +1,44 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_15EG_1E/3.0/te0808_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_15EG_1E/3.0/te0808_board.png new file mode 100644 index 0000000..7b8e3c6 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_15EG_1E/3.0/te0808_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_15EG_1E/3.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_15EG_1E/3.0/xitem.json new file mode 100644 index 0000000..78fdaa2 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_15EG_1E/3.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0808_15eg_1e", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0808-15EG-1E(B,E: 4GB DDR). SPRT PCB: REV04.", + "revision": "3.0", + "description": "Zynq UltraScale+ TE0808-15EG-1E(B,E: 4GB DDR) Board (form factor 5.2x7.6 cm) with 4x 1 GByte DDR4, speed grade -1 and extended temperature range. Board Part is only with minimum PS-Setup. Use for own carrier or simple SDK debugging. User must configure B2B MIOs manually, depending on his carrier board connection. Without user PS configuration only JTAG and QSPI boot is possible with this board part file.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0808-info", + "search-keywords": [ + "te0808_15eg_1e", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_15EG_1E/4.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_15EG_1E/4.0/board.xml new file mode 100644 index 0000000..4e76021 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_15EG_1E/4.0/board.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0808 Board File Image + + + + + + + + 0.4 + + + + + 4.0 + + + Zynq UltraScale+ TE0808-15EG-1E(B,E: 4GB DDR) Board (form factor 5.2x7.6 cm) with 4x 1 GByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV04. Board Part is for usage with carrier-board TEBF0808. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_15EG_1E/4.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_15EG_1E/4.0/part0_pins.xml new file mode 100644 index 0000000..c2cce2f --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_15EG_1E/4.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_15EG_1E/4.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_15EG_1E/4.0/preset.xml new file mode 100644 index 0000000..3a973c6 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_15EG_1E/4.0/preset.xml @@ -0,0 +1,124 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_15EG_1E/4.0/te0808_starterkit.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_15EG_1E/4.0/te0808_starterkit.png new file mode 100644 index 0000000..5c51e7d Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_15EG_1E/4.0/te0808_starterkit.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_15EG_1E/4.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_15EG_1E/4.0/xitem.json new file mode 100644 index 0000000..69bb24d --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_15EG_1E/4.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0808_15eg_1e_tebf0808", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0808-15EG-1E(B,E: 4GB DDR) with TEBF0808. SPRT Module PCB: REV04.", + "revision": "4.0", + "description": "Zynq UltraScale+ TE0808-15EG-1E(B,E: 4GB DDR) Board (form factor 5.2x7.6 cm) with 4x 1 GByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV04. Board Part is for usage with carrier-board TEBF0808.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0808-info", + "search-keywords": [ + "te0808_15eg_1e_tebf0808", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_2ES2/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_2ES2/1.0/board.xml new file mode 100644 index 0000000..6fb2d18 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_2ES2/1.0/board.xml @@ -0,0 +1,69 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0808 Board File Image + + + + + + + + 0.4 + 0.3 + + + + + 1.0 + + + Zynq UltraScale+ TE0808-2ES2 Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, Speed Grade -2 and industrial temperature range. Supported PCB Revisions: REV03, REV04. Board Part is only with minimum PS-Setup. Use for own carrier or simple SDK debugging. User must configure B2B MIOs manually, depending on his carrier board connection. Without user PS configuration only JTAG and QSPI boot is possible with this board part file. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_2ES2/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_2ES2/1.0/part0_pins.xml new file mode 100644 index 0000000..486fc35 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_2ES2/1.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_2ES2/1.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_2ES2/1.0/preset.xml new file mode 100644 index 0000000..fcea57d --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_2ES2/1.0/preset.xml @@ -0,0 +1,44 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_2ES2/1.0/te0808_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_2ES2/1.0/te0808_board.png new file mode 100644 index 0000000..7b8e3c6 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_2ES2/1.0/te0808_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_2ES2/1.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_2ES2/1.0/xitem.json new file mode 100644 index 0000000..871da90 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_2ES2/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0808_2es2", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0808-2ES2. SPRT PCB: REV03,REV04.", + "revision": "1.0", + "description": "Zynq UltraScale+ TE0808-2ES2 Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, Speed Grade -2 and industrial temperature range. Supported PCB Revisions: REV03, REV04. Board Part is only with minimum PS-Setup. Use for own carrier or simple SDK debugging. User must configure B2B MIOs manually, depending on his carrier board connection. Without user PS configuration only JTAG and QSPI boot is possible with this board part file.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0808-info", + "search-keywords": [ + "te0808_2es2", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_2ES2/2.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_2ES2/2.0/board.xml new file mode 100644 index 0000000..8df18e1 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_2ES2/2.0/board.xml @@ -0,0 +1,69 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0808 Board File Image + + + + + + + + 0.4 + 0.3 + + + + + 2.0 + + + Zynq UltraScale+ TE0808-2ES2 Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, Speed Grade -2 and industrial temperature range. Supported PCB Revisions: REV03, REV04. Board Part is for usage with carrier-board TEBF0808. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_2ES2/2.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_2ES2/2.0/part0_pins.xml new file mode 100644 index 0000000..486fc35 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_2ES2/2.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_2ES2/2.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_2ES2/2.0/preset.xml new file mode 100644 index 0000000..7f6b7dc --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_2ES2/2.0/preset.xml @@ -0,0 +1,124 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_2ES2/2.0/te0808_starterkit.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_2ES2/2.0/te0808_starterkit.png new file mode 100644 index 0000000..5c51e7d Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_2ES2/2.0/te0808_starterkit.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_2ES2/2.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_2ES2/2.0/xitem.json new file mode 100644 index 0000000..ad34678 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_2ES2/2.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0808_2es2_tebf0808", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0808-2ES2 with TEBF0808. SPRT Module PCB: REV03,REV04.", + "revision": "2.0", + "description": "Zynq UltraScale+ TE0808-2ES2 Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, Speed Grade -2 and industrial temperature range. Supported PCB Revisions: REV03, REV04. Board Part is for usage with carrier-board TEBF0808.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0808-info", + "search-keywords": [ + "te0808_2es2_tebf0808", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_6EG_1E/3.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_6EG_1E/3.0/board.xml new file mode 100644 index 0000000..8081b9b --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_6EG_1E/3.0/board.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0808 Board File Image + + + + + + + + 0.4 + + + + + 3.0 + + + Zynq UltraScale+ TE0808-6EG-1E(E,3: 4GB DDR) Board (form factor 5.2x7.6 cm) with 4x 1 GByte DDR4, speed grade -1 and extended temperature range. Board Part is only with minimum PS-Setup. Use for own carrier or simple SDK debugging. User must configure B2B MIOs manually, depending on his carrier board connection. Without user PS configuration only JTAG and QSPI boot is possible with this board part file. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_6EG_1E/3.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_6EG_1E/3.0/part0_pins.xml new file mode 100644 index 0000000..e05196a --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_6EG_1E/3.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_6EG_1E/3.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_6EG_1E/3.0/preset.xml new file mode 100644 index 0000000..112f956 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_6EG_1E/3.0/preset.xml @@ -0,0 +1,44 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_6EG_1E/3.0/te0808_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_6EG_1E/3.0/te0808_board.png new file mode 100644 index 0000000..7b8e3c6 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_6EG_1E/3.0/te0808_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_6EG_1E/3.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_6EG_1E/3.0/xitem.json new file mode 100644 index 0000000..b44bff7 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_6EG_1E/3.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0808_6eg_1e", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0808-6EG-1E(E,3: 4GB DDR). SPRT PCB: REV04.", + "revision": "3.0", + "description": "Zynq UltraScale+ TE0808-6EG-1E(E,3: 4GB DDR) Board (form factor 5.2x7.6 cm) with 4x 1 GByte DDR4, speed grade -1 and extended temperature range. Board Part is only with minimum PS-Setup. Use for own carrier or simple SDK debugging. User must configure B2B MIOs manually, depending on his carrier board connection. Without user PS configuration only JTAG and QSPI boot is possible with this board part file.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0808-info", + "search-keywords": [ + "te0808_6eg_1e", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_6EG_1E/4.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_6EG_1E/4.0/board.xml new file mode 100644 index 0000000..4d4defd --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_6EG_1E/4.0/board.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0808 Board File Image + + + + + + + + 0.4 + + + + + 4.0 + + + Zynq UltraScale+ TE0808-6EG-1E(E,3: 4GB DDR) Board (form factor 5.2x7.6 cm) with 4x 1 GByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV04. Board Part is for usage with carrier-board TEBF0808. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_6EG_1E/4.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_6EG_1E/4.0/part0_pins.xml new file mode 100644 index 0000000..7fceac3 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_6EG_1E/4.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_6EG_1E/4.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_6EG_1E/4.0/preset.xml new file mode 100644 index 0000000..3a973c6 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_6EG_1E/4.0/preset.xml @@ -0,0 +1,124 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_6EG_1E/4.0/te0808_starterkit.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_6EG_1E/4.0/te0808_starterkit.png new file mode 100644 index 0000000..5c51e7d Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_6EG_1E/4.0/te0808_starterkit.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_6EG_1E/4.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_6EG_1E/4.0/xitem.json new file mode 100644 index 0000000..015dadb --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_6EG_1E/4.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0808_6eg_1e_tebf0808", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0808-6EG-1E(E,3: 4GB DDR) with TEBF0808. SPRT Module PCB: REV04.", + "revision": "4.0", + "description": "Zynq UltraScale+ TE0808-6EG-1E(E,3: 4GB DDR) Board (form factor 5.2x7.6 cm) with 4x 1 GByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV04. Board Part is for usage with carrier-board TEBF0808.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0808-info", + "search-keywords": [ + "te0808_6eg_1e_tebf0808", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/1.0/board.xml new file mode 100644 index 0000000..66edf94 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/1.0/board.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0808 Board File Image + + + + + + + + 0.4 + + + + + 1.0 + + + Zynq UltraScale+ TE0808-9EG-1E(A: 2GB DDR) Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, speed grade -1 and extended temperature range. Board Part is only with minimum PS-Setup. Use for own carrier or simple SDK debugging. User must configure B2B MIOs manually, depending on his carrier board connection. Without user PS configuration only JTAG and QSPI boot is possible with this board part file. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/1.0/part0_pins.xml new file mode 100644 index 0000000..3ba4801 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/1.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/1.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/1.0/preset.xml new file mode 100644 index 0000000..6e7da01 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/1.0/preset.xml @@ -0,0 +1,38 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/1.0/te0808_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/1.0/te0808_board.png new file mode 100644 index 0000000..7b8e3c6 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/1.0/te0808_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/1.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/1.0/xitem.json new file mode 100644 index 0000000..78fa77e --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0808_9eg_1e", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0808-9EG-1E(A: 2GB DDR). SPRT PCB: REV04.", + "revision": "1.0", + "description": "Zynq UltraScale+ TE0808-9EG-1E(A: 2GB DDR) Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, speed grade -1 and extended temperature range. Board Part is only with minimum PS-Setup. Use for own carrier or simple SDK debugging. User must configure B2B MIOs manually, depending on his carrier board connection. Without user PS configuration only JTAG and QSPI boot is possible with this board part file.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0808-info", + "search-keywords": [ + "te0808_9eg_1e", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/2.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/2.0/board.xml new file mode 100644 index 0000000..95aef60 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/2.0/board.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0808 Board File Image + + + + + + + + 0.4 + + + + + 2.0 + + + Zynq UltraScale+ TE0808-9EG-1E(A: 2GB DDR) Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV04. Board Part is for usage with carrier-board TEBF0808. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/2.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/2.0/part0_pins.xml new file mode 100644 index 0000000..3ba4801 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/2.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/2.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/2.0/preset.xml new file mode 100644 index 0000000..3158864 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/2.0/preset.xml @@ -0,0 +1,118 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/2.0/te0808_starterkit.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/2.0/te0808_starterkit.png new file mode 100644 index 0000000..5c51e7d Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/2.0/te0808_starterkit.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/2.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/2.0/xitem.json new file mode 100644 index 0000000..e32cd20 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/2.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0808_9eg_1e_tebf0808", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0808-9EG-1E(A: 2GB DDR) with TEBF0808. SPRT Module PCB: REV04.", + "revision": "2.0", + "description": "Zynq UltraScale+ TE0808-9EG-1E(A: 2GB DDR) Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV04. Board Part is for usage with carrier-board TEBF0808.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0808-info", + "search-keywords": [ + "te0808_9eg_1e_tebf0808", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/3.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/3.0/board.xml new file mode 100644 index 0000000..a4fed4b --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/3.0/board.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0808 Board File Image + + + + + + + + 0.4 + + + + + 3.0 + + + Zynq UltraScale+ TE0808-9EG-1E(B,D,E,L: 4GB DDR) Board (form factor 5.2x7.6 cm) with 4x 1 GByte DDR4, speed grade -1 and extended temperature range. Board Part is only with minimum PS-Setup. Use for own carrier or simple SDK debugging. User must configure B2B MIOs manually, depending on his carrier board connection. Without user PS configuration only JTAG and QSPI boot is possible with this board part file. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/3.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/3.0/part0_pins.xml new file mode 100644 index 0000000..3ba4801 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/3.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/3.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/3.0/preset.xml new file mode 100644 index 0000000..112f956 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/3.0/preset.xml @@ -0,0 +1,44 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/3.0/te0808_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/3.0/te0808_board.png new file mode 100644 index 0000000..7b8e3c6 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/3.0/te0808_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/3.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/3.0/xitem.json new file mode 100644 index 0000000..d6620a5 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/3.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0808_9eg_1e", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0808-9EG-1E(B,D,E,L: 4GB DDR). SPRT PCB: REV04.", + "revision": "3.0", + "description": "Zynq UltraScale+ TE0808-9EG-1E(B,D,E,L: 4GB DDR) Board (form factor 5.2x7.6 cm) with 4x 1 GByte DDR4, speed grade -1 and extended temperature range. Board Part is only with minimum PS-Setup. Use for own carrier or simple SDK debugging. User must configure B2B MIOs manually, depending on his carrier board connection. Without user PS configuration only JTAG and QSPI boot is possible with this board part file.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0808-info", + "search-keywords": [ + "te0808_9eg_1e", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/4.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/4.0/board.xml new file mode 100644 index 0000000..5b75a2d --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/4.0/board.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0808 Board File Image + + + + + + + + 0.4 + + + + + 4.0 + + + Zynq UltraScale+ TE0808-9EG-1E(B,D,E,L: 4GB DDR) Board (form factor 5.2x7.6 cm) with 4x 1 GByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV04. Board Part is for usage with carrier-board TEBF0808. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/4.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/4.0/part0_pins.xml new file mode 100644 index 0000000..3ba4801 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/4.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/4.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/4.0/preset.xml new file mode 100644 index 0000000..3a973c6 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/4.0/preset.xml @@ -0,0 +1,124 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/4.0/te0808_starterkit.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/4.0/te0808_starterkit.png new file mode 100644 index 0000000..5c51e7d Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/4.0/te0808_starterkit.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/4.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/4.0/xitem.json new file mode 100644 index 0000000..9ea0840 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_1E/4.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0808_9eg_1e_tebf0808", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0808-9EG-1E(B,D,E,L: 4GB DDR) with TEBF0808. SPRT Module PCB: REV04.", + "revision": "4.0", + "description": "Zynq UltraScale+ TE0808-9EG-1E(B,D,E,L: 4GB DDR) Board (form factor 5.2x7.6 cm) with 4x 1 GByte DDR4, speed grade -1 and extended temperature range. Supported PCB Revisions: REV04. Board Part is for usage with carrier-board TEBF0808.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0808-info", + "search-keywords": [ + "te0808_9eg_1e_tebf0808", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_2I/3.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_2I/3.0/board.xml new file mode 100644 index 0000000..12fff9a --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_2I/3.0/board.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0808 Board File Image + + + + + + + + 0.4 + + + + + 3.0 + + + Zynq UltraScale+ TE0808-9EG-2I(B,E: 4GB DDR) Board (form factor 5.2x7.6 cm) with 4x 1 GByte DDR4, speed grade -1 and industrial temperature range. Supported PCB Revisions: REV04. Board Part is only with minimum PS-Setup. Use for own carrier or simple SDK debugging. User must configure B2B MIOs manually, depending on his carrier board connection. Without user PS configuration only JTAG and QSPI boot is possible with this board part file. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_2I/3.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_2I/3.0/part0_pins.xml new file mode 100644 index 0000000..20ebf69 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_2I/3.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_2I/3.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_2I/3.0/preset.xml new file mode 100644 index 0000000..112f956 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_2I/3.0/preset.xml @@ -0,0 +1,44 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_2I/3.0/te0808_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_2I/3.0/te0808_board.png new file mode 100644 index 0000000..7b8e3c6 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_2I/3.0/te0808_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_2I/3.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_2I/3.0/xitem.json new file mode 100644 index 0000000..4d6e0c7 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_2I/3.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0808_9eg_2i", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0808-9EG-2I(B,E: 4GB DDR). SPRT PCB: REV04.", + "revision": "3.0", + "description": "Zynq UltraScale+ TE0808-9EG-2I(B,E: 4GB DDR) Board (form factor 5.2x7.6 cm) with 4x 1 GByte DDR4, speed grade -1 and industrial temperature range. Supported PCB Revisions: REV04. Board Part is only with minimum PS-Setup. Use for own carrier or simple SDK debugging. User must configure B2B MIOs manually, depending on his carrier board connection. Without user PS configuration only JTAG and QSPI boot is possible with this board part file.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0808-info", + "search-keywords": [ + "te0808_9eg_2i", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_2I/4.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_2I/4.0/board.xml new file mode 100644 index 0000000..68c0a0d --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_2I/4.0/board.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0808 Board File Image + + + + + + + + 0.4 + + + + + 4.0 + + + Zynq UltraScale+ TE0808-9EG-2I(B,D,E,L: 4GB DDR) Board (form factor 5.2x7.6 cm) with 4x 1 GByte DDR4, speed grade -1 and industrial temperature range. Supported PCB Revisions: REV04. Board Part is for usage with carrier-board TEBF0808. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_2I/4.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_2I/4.0/part0_pins.xml new file mode 100644 index 0000000..20ebf69 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_2I/4.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_2I/4.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_2I/4.0/preset.xml new file mode 100644 index 0000000..3a973c6 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_2I/4.0/preset.xml @@ -0,0 +1,124 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_2I/4.0/te0808_starterkit.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_2I/4.0/te0808_starterkit.png new file mode 100644 index 0000000..5c51e7d Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_2I/4.0/te0808_starterkit.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_2I/4.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_2I/4.0/xitem.json new file mode 100644 index 0000000..fb96a1a --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_9EG_2I/4.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0808_9eg_2i_tebf0808", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0808-9EG-2I(B,E: 4GB DDR) with TEBF0808. SPRT Module PCB: REV04.", + "revision": "4.0", + "description": "Zynq UltraScale+ TE0808-9EG-2I(B,D,E,L: 4GB DDR) Board (form factor 5.2x7.6 cm) with 4x 1 GByte DDR4, speed grade -1 and industrial temperature range. Supported PCB Revisions: REV04. Board Part is for usage with carrier-board TEBF0808.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0808-info", + "search-keywords": [ + "te0808_9eg_2i_tebf0808", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_ES2/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_ES2/1.0/board.xml new file mode 100644 index 0000000..8f9833e --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_ES2/1.0/board.xml @@ -0,0 +1,69 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0808 Board File Image + + + + + + + + 0.4 + 0.3 + + + + + 1.0 + + + Zynq UltraScale+ TE0808-ES2 Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4 and industrial temperature range. Supported PCB Revisions: REV03, REV04. Board Part is only with minimum PS-Setup. Use for own carrier or simple SDK debugging. User must configure B2B MIOs manually, depending on his carrier board connection. Without user PS configuration only JTAG and QSPI boot is possible with this board part file. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_ES2/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_ES2/1.0/part0_pins.xml new file mode 100644 index 0000000..d72cabc --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_ES2/1.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_ES2/1.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_ES2/1.0/preset.xml new file mode 100644 index 0000000..fcea57d --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_ES2/1.0/preset.xml @@ -0,0 +1,44 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_ES2/1.0/te0808_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_ES2/1.0/te0808_board.png new file mode 100644 index 0000000..7b8e3c6 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_ES2/1.0/te0808_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_ES2/1.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_ES2/1.0/xitem.json new file mode 100644 index 0000000..13a178f --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_ES2/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0808_es2", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0808-ES2. SPRT PCB: REV03,REV04.", + "revision": "1.0", + "description": "Zynq UltraScale+ TE0808-ES2 Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4 and industrial temperature range. Supported PCB Revisions: REV03, REV04. Board Part is only with minimum PS-Setup. Use for own carrier or simple SDK debugging. User must configure B2B MIOs manually, depending on his carrier board connection. Without user PS configuration only JTAG and QSPI boot is possible with this board part file.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0808-info", + "search-keywords": [ + "te0808_es2", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_ES2/2.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_ES2/2.0/board.xml new file mode 100644 index 0000000..87c81b4 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_ES2/2.0/board.xml @@ -0,0 +1,69 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0808 Board File Image + + + + + + + + 0.4 + 0.3 + + + + + 2.0 + + + Zynq UltraScale+ TE0808-ES2 Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4 and industrial temperature range. Supported PCB Revisions: REV03, REV04. Board Part is for usage with carrier-board TEBF0808. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_ES2/2.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_ES2/2.0/part0_pins.xml new file mode 100644 index 0000000..d72cabc --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_ES2/2.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_ES2/2.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_ES2/2.0/preset.xml new file mode 100644 index 0000000..7f6b7dc --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_ES2/2.0/preset.xml @@ -0,0 +1,124 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_ES2/2.0/te0808_starterkit.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_ES2/2.0/te0808_starterkit.png new file mode 100644 index 0000000..5c51e7d Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_ES2/2.0/te0808_starterkit.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_ES2/2.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_ES2/2.0/xitem.json new file mode 100644 index 0000000..ffce087 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0808_ES2/2.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0808_es2_tebf0808", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0808-ES2 with TEBF0808. SPRT Module PCB: REV03,REV04.", + "revision": "2.0", + "description": "Zynq UltraScale+ TE0808-ES2 Board (form factor 5.2x7.6 cm) with 4x 512 MByte DDR4 and industrial temperature range. Supported PCB Revisions: REV03, REV04. Board Part is for usage with carrier-board TEBF0808.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0808-info", + "search-keywords": [ + "te0808_es2_tebf0808", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2CG_1E/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2CG_1E/1.0/board.xml new file mode 100644 index 0000000..cb592bb --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2CG_1E/1.0/board.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0820 Board File Image + + + + + + + + 0.2 + + + + + 1.0 + + + Zynq UltraScale+ TE0820-2CG-1E(_, A) Board (form factor 4x5 cm) with 2x 512MByte DDR4, 2x 32MByte Flash, speed grade -1 and extended temperature range. Supported PCB Revisions: REV02. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2CG_1E/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2CG_1E/1.0/part0_pins.xml new file mode 100644 index 0000000..a1e4a9f --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2CG_1E/1.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2CG_1E/1.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2CG_1E/1.0/preset.xml new file mode 100644 index 0000000..07a9206 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2CG_1E/1.0/preset.xml @@ -0,0 +1,69 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2CG_1E/1.0/te0820_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2CG_1E/1.0/te0820_board.png new file mode 100644 index 0000000..69db035 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2CG_1E/1.0/te0820_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2CG_1E/1.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2CG_1E/1.0/xitem.json new file mode 100644 index 0000000..522f6cd --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2CG_1E/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0820_2cg_1e", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0820-2CG-1E(_, A : 1 GB DDR). SPRT PCB: REV02", + "revision": "1.0", + "description": "Zynq UltraScale+ TE0820-2CG-1E(_, A) Board (form factor 4x5 cm) with 2x 512MByte DDR4, 2x 32MByte Flash, speed grade -1 and extended temperature range. Supported PCB Revisions: REV02.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0820-info", + "search-keywords": [ + "te0820_2cg_1e", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2EG_1E/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2EG_1E/1.0/board.xml new file mode 100644 index 0000000..3f76dd3 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2EG_1E/1.0/board.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0820 Board File Image + + + + + + + + 0.2 + + + + + 1.0 + + + Zynq UltraScale+ TE0820-2EG-1E(_, 3, A, L) Board (form factor 4x5 cm) with 2x 512MByte DDR4, 2x 32MByte Flash, speed grade -1 and extended temperature range. Supported PCB Revisions: REV02. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2EG_1E/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2EG_1E/1.0/part0_pins.xml new file mode 100644 index 0000000..19da5d9 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2EG_1E/1.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2EG_1E/1.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2EG_1E/1.0/preset.xml new file mode 100644 index 0000000..07a9206 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2EG_1E/1.0/preset.xml @@ -0,0 +1,69 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2EG_1E/1.0/te0820_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2EG_1E/1.0/te0820_board.png new file mode 100644 index 0000000..69db035 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2EG_1E/1.0/te0820_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2EG_1E/1.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2EG_1E/1.0/xitem.json new file mode 100644 index 0000000..4fcf5a9 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2EG_1E/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0820_2eg_1e", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0820-2EG-1E(_, 3, A, L : 1 GB DDR). SPRT PCB: REV02", + "revision": "1.0", + "description": "Zynq UltraScale+ TE0820-2EG-1E(_, 3, A, L) Board (form factor 4x5 cm) with 2x 512MByte DDR4, 2x 32MByte Flash, speed grade -1 and extended temperature range. Supported PCB Revisions: REV02.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0820-info", + "search-keywords": [ + "te0820_2eg_1e", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2EG_1E/2.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2EG_1E/2.0/board.xml new file mode 100644 index 0000000..e56e8a9 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2EG_1E/2.0/board.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0820 Board File Image + + + + + + + + 0.2 + + + + + 2.0 + + + Zynq UltraScale+ TE0820-2EG-1E(E : 2 GB DDR) Board (form factor 4x5 cm) with 2x 1GB DDR4, 2x 32MByte Flash, speed grade -1 and extended temperature range. Supported PCB Revisions: REV02. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2EG_1E/2.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2EG_1E/2.0/part0_pins.xml new file mode 100644 index 0000000..19da5d9 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2EG_1E/2.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2EG_1E/2.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2EG_1E/2.0/preset.xml new file mode 100644 index 0000000..9659d99 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2EG_1E/2.0/preset.xml @@ -0,0 +1,67 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2EG_1E/2.0/te0820_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2EG_1E/2.0/te0820_board.png new file mode 100644 index 0000000..69db035 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2EG_1E/2.0/te0820_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2EG_1E/2.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2EG_1E/2.0/xitem.json new file mode 100644 index 0000000..ccc8400 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_2EG_1E/2.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0820_2eg_1e", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0820-2EG-1E(E : 2 GB DDR). SPRT PCB: REV02", + "revision": "2.0", + "description": "Zynq UltraScale+ TE0820-2EG-1E(E : 2 GB DDR) Board (form factor 4x5 cm) with 2x 1GB DDR4, 2x 32MByte Flash, speed grade -1 and extended temperature range. Supported PCB Revisions: REV02.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0820-info", + "search-keywords": [ + "te0820_2eg_1e", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_3CG_1E/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_3CG_1E/1.0/board.xml new file mode 100644 index 0000000..d035ce0 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_3CG_1E/1.0/board.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0820 Board File Image + + + + + + + + 0.2 + + + + + 1.0 + + + Zynq UltraScale+ TE0820-3CG-1E(_, A) Board (form factor 4x5 cm) with 2x 512MByte DDR4, 2x 32MByte Flash, speed grade -1 and extended temperature range. Supported PCB Revisions: REV02. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_3CG_1E/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_3CG_1E/1.0/part0_pins.xml new file mode 100644 index 0000000..59493fa --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_3CG_1E/1.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_3CG_1E/1.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_3CG_1E/1.0/preset.xml new file mode 100644 index 0000000..07a9206 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_3CG_1E/1.0/preset.xml @@ -0,0 +1,69 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_3CG_1E/1.0/te0820_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_3CG_1E/1.0/te0820_board.png new file mode 100644 index 0000000..69db035 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_3CG_1E/1.0/te0820_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_3CG_1E/1.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_3CG_1E/1.0/xitem.json new file mode 100644 index 0000000..da7cbb3 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_3CG_1E/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0820_3cg_1e", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0820-3CG-1E(_, A : 1 GB DDR). SPRT PCB: REV02", + "revision": "1.0", + "description": "Zynq UltraScale+ TE0820-3CG-1E(_, A) Board (form factor 4x5 cm) with 2x 512MByte DDR4, 2x 32MByte Flash, speed grade -1 and extended temperature range. Supported PCB Revisions: REV02.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0820-info", + "search-keywords": [ + "te0820_3cg_1e", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_3EG_1E/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_3EG_1E/1.0/board.xml new file mode 100644 index 0000000..89c81de --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_3EG_1E/1.0/board.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0820 Board File Image + + + + + + + + 0.2 + + + + + 1.0 + + + Zynq UltraScale+ TE0820-3EG-1E(_, 3, A, L) Board (form factor 4x5 cm) with 2x 512MByte DDR4, 2x 32MByte Flash, speed grade -1 and extended temperature range. Supported PCB Revisions: REV02. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_3EG_1E/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_3EG_1E/1.0/part0_pins.xml new file mode 100644 index 0000000..44869ae --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_3EG_1E/1.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_3EG_1E/1.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_3EG_1E/1.0/preset.xml new file mode 100644 index 0000000..07a9206 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_3EG_1E/1.0/preset.xml @@ -0,0 +1,69 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_3EG_1E/1.0/te0820_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_3EG_1E/1.0/te0820_board.png new file mode 100644 index 0000000..69db035 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_3EG_1E/1.0/te0820_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_3EG_1E/1.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_3EG_1E/1.0/xitem.json new file mode 100644 index 0000000..2270420 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_3EG_1E/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0820_3eg_1e", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0820-3EG-1E(_, 3, A, L : 1 GB DDR). SPRT PCB: REV02", + "revision": "1.0", + "description": "Zynq UltraScale+ TE0820-3EG-1E(_, 3, A, L) Board (form factor 4x5 cm) with 2x 512MByte DDR4, 2x 32MByte Flash, speed grade -1 and extended temperature range. Supported PCB Revisions: REV02.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0820-info", + "search-keywords": [ + "te0820_3eg_1e", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_4CG_1E/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_4CG_1E/1.0/board.xml new file mode 100644 index 0000000..7d4d7f0 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_4CG_1E/1.0/board.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0820 Board File Image + + + + + + + + 0.2 + + + + + 1.0 + + + Zynq UltraScale+ TE0820-4CG-1E(A) Board (form factor 4x5 cm) with 2x 512MByte DDR4, 2x 32MByte Flash, speed grade -1 and extended temperature range. Supported PCB Revisions: REV02. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_4CG_1E/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_4CG_1E/1.0/part0_pins.xml new file mode 100644 index 0000000..36dc685 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_4CG_1E/1.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_4CG_1E/1.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_4CG_1E/1.0/preset.xml new file mode 100644 index 0000000..07a9206 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_4CG_1E/1.0/preset.xml @@ -0,0 +1,69 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_4CG_1E/1.0/te0820_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_4CG_1E/1.0/te0820_board.png new file mode 100644 index 0000000..69db035 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_4CG_1E/1.0/te0820_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_4CG_1E/1.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_4CG_1E/1.0/xitem.json new file mode 100644 index 0000000..89c8650 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_4CG_1E/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0820_4cg_1e", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0820-4CG-1E(A : 1 GB DDR). SPRT PCB: REV02", + "revision": "1.0", + "description": "Zynq UltraScale+ TE0820-4CG-1E(A) Board (form factor 4x5 cm) with 2x 512MByte DDR4, 2x 32MByte Flash, speed grade -1 and extended temperature range. Supported PCB Revisions: REV02.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0820-info", + "search-keywords": [ + "te0820_4cg_1e", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_4EV_1E/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_4EV_1E/1.0/board.xml new file mode 100644 index 0000000..c52e9cc --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_4EV_1E/1.0/board.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + ZYNQ-UltraScale+ TE0820 Board File Image + + + + + + + + 0.3 + + + + + 1.0 + + + Zynq UltraScale+ TE0820-4EV-1E(A) Board (form factor 4x5 cm) with 2x 1GByte DDR4, 2x 32MByte Flash, speed grade -1 and extended temperature range. Supported PCB Revisions: REV03. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_4EV_1E/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_4EV_1E/1.0/part0_pins.xml new file mode 100644 index 0000000..7fcad81 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_4EV_1E/1.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_4EV_1E/1.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_4EV_1E/1.0/preset.xml new file mode 100644 index 0000000..9659d99 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_4EV_1E/1.0/preset.xml @@ -0,0 +1,67 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_4EV_1E/1.0/te0820_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_4EV_1E/1.0/te0820_board.png new file mode 100644 index 0000000..69db035 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_4EV_1E/1.0/te0820_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_4EV_1E/1.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_4EV_1E/1.0/xitem.json new file mode 100644 index 0000000..fc26a89 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TE0820_4EV_1E/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "te0820_4ev_1e", + "display": "UltraSOM (ZYNQ-UltraScale+) TE0820-4EV-1E(A : 2 GB DDR). SPRT PCB: REV03", + "revision": "1.0", + "description": "Zynq UltraScale+ TE0820-4EV-1E(A) Board (form factor 4x5 cm) with 2x 1GByte DDR4, 2x 32MByte Flash, speed grade -1 and extended temperature range. Supported PCB Revisions: REV03.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/te0820-info", + "search-keywords": [ + "te0820_4ev_1e", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TEB0911_9EG_1E/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TEB0911_9EG_1E/1.0/board.xml new file mode 100644 index 0000000..f0600f6 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TEB0911_9EG_1E/1.0/board.xml @@ -0,0 +1,69 @@ + + + + + + + + + + + + PCB Series Name Board File Image + + + + + + + + 0.3 + 0.2 + + + + + 1.0 + + + ZYNQ-UltraScale+ TEB0911-09EG-1E Board (form factor 40.6 x 23.1 cm) with six FMC-Connectors, DDR SODIMM (for 8GB DDR4-2400 CT8G4SFS824A), speed grade -1 and extended temperature range. Supported PCB Revisions:REV03, REV02. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TEB0911_9EG_1E/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TEB0911_9EG_1E/1.0/part0_pins.xml new file mode 100644 index 0000000..8d6c185 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TEB0911_9EG_1E/1.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TEB0911_9EG_1E/1.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TEB0911_9EG_1E/1.0/preset.xml new file mode 100644 index 0000000..023386e --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TEB0911_9EG_1E/1.0/preset.xml @@ -0,0 +1,110 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TEB0911_9EG_1E/1.0/teb0911_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TEB0911_9EG_1E/1.0/teb0911_board.png new file mode 100644 index 0000000..d4a24d6 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TEB0911_9EG_1E/1.0/teb0911_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TEB0911_9EG_1E/1.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TEB0911_9EG_1E/1.0/xitem.json new file mode 100644 index 0000000..e3b4e63 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TEB0911_9EG_1E/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "teb0911_9eg_1e", + "display": "ZYNQ-UltraScale+ TEB0911-09EG-1E. SPRT PCB: REV03,REV02.", + "revision": "1.0", + "description": "ZYNQ-UltraScale+ TEB0911-09EG-1E Board (form factor 40.6 x 23.1 cm) with six FMC-Connectors, DDR SODIMM (for 8GB DDR4-2400 CT8G4SFS824A), speed grade -1 and extended temperature range. Supported PCB Revisions:REV03, REV02.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/teb0911-info", + "search-keywords": [ + "teb0911_9eg_1e", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TEC0850_15EG_1E/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TEC0850_15EG_1E/1.0/board.xml new file mode 100644 index 0000000..df5289c --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TEC0850_15EG_1E/1.0/board.xml @@ -0,0 +1,69 @@ + + + + + + + + + + + + TEC0850 + + + + + + + + 0.2 + + + + + 1.0 + + + UltraScale+ Zynq TEC0850-15EG-1E. Board (form factor 10.0 x 16.2 cm) with DDR with SODIMM (configured for KVR24S17S8/8), 1GBit Ethernet, speed grade -1 and extended temperature grade. Supported PCB Revisions: REV02. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TEC0850_15EG_1E/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TEC0850_15EG_1E/1.0/part0_pins.xml new file mode 100644 index 0000000..7a7198a --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TEC0850_15EG_1E/1.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TEC0850_15EG_1E/1.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TEC0850_15EG_1E/1.0/preset.xml new file mode 100644 index 0000000..f760cd0 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TEC0850_15EG_1E/1.0/preset.xml @@ -0,0 +1,75 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TEC0850_15EG_1E/1.0/tec0850_board.png b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TEC0850_15EG_1E/1.0/tec0850_board.png new file mode 100644 index 0000000..8c3c522 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TEC0850_15EG_1E/1.0/tec0850_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TEC0850_15EG_1E/1.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TEC0850_15EG_1E/1.0/xitem.json new file mode 100644 index 0000000..f63df91 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Trenz_Electronic/TEC0850_15EG_1E/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "tec0850_15eg_1e", + "display": "UltraScale+ Zynq TEC0850-15EG-1E. SPRT PCB: REV02", + "revision": "1.0", + "description": "UltraScale+ Zynq TEC0850-15EG-1E. Board (form factor 10.0 x 16.2 cm) with DDR with SODIMM (configured for KVR24S17S8/8), 1GBit Ethernet, speed grade -1 and extended temperature grade. Supported PCB Revisions: REV02.", + "company": "trenz.biz", + "company_display": "Trenz Electronic GmbH", + "author": "trenz.biz", + "contributors": [ + { + "group": "Trenz Electronic GmbH", + "url": "https://www.trenz-electronic.de/" + } + ], + "category": "Single Part", + "website": "trenz.org/tec0850-info", + "search-keywords": [ + "tec0850_15eg_1e", + "trenz.biz", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/ac701/1.4/ac701_board.jpg b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/ac701/1.4/ac701_board.jpg new file mode 100644 index 0000000..bcc6bab Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/ac701/1.4/ac701_board.jpg differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/ac701/1.4/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/ac701/1.4/board.xml new file mode 100644 index 0000000..a6556d0 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/ac701/1.4/board.xml @@ -0,0 +1,1111 @@ + + + + + AC701 Board File Image + + + + 1.1 + + 1.4 + Artix-7 AC701 Evaluation Platform + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + FPGA part on the board + + + DDR3 board interface, it can use MIG IP for connection. + + + + + + 4-position user DIP Switch + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Secondary interface to communicate with ethernet phy when mode is selected as MII,GMII,1000BaseX. + + + + + + + + + + + + + + + + + + Secondary interface to communicate with ethernet phy when mode is selected as SGMII. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Primary interface to communicate with ethernet phy in RGMII mode. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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can be used for configuration or data storage + + + 2.5V LVDS differential 200 MHz oscillator used as system differential clock on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/ac701/1.4/changelog.txt b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/ac701/1.4/changelog.txt new file mode 100644 index 0000000..1319a41 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/ac701/1.4/changelog.txt @@ -0,0 +1,5 @@ +######### AC701 Change log ############## + +1.4 +Added FMC support + diff --git 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"config": { + "items": [ + { + "infra": { + "name": "au280", + "display": "Alveo U280 Data Center Accelerator Card", + "revision": "1.0", + "description": "Alveo U280 Data Center Accelerator Card", + "company": "xilinx.com", + "company_display": "Xilinx", + "author": "Vanitha", + "contributors": [ + { + "group": "Xilinx", + "url": "www.xilinx.com" + } + ], + "category": "Single Part", + "website": "http://www.xilinx.com/u280", + "search-keywords": [ + "au280", + "xilinx.com", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/kc705/1.6/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/kc705/1.6/board.xml new file mode 100644 index 0000000..f11f527 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/kc705/1.6/board.xml @@ -0,0 +1,2028 @@ + + + + + KC705 Board File Image + + + + 1.1 + + 1.6 + Kintex-7 KC705 Evaluation Platform + + + + + + + Impacts connection between flash_qspi and flash_bpi.If value=true, flash_qspi will be enabled + + + Impacts connection between flash_qspi and flash_bpi.If value=true, flash_bpi will be enabled + + + value=true will configure component phy to work in MII or GMII mode or RGMII mode based on J30 and J64 + + + value=true will configure component phy to work in SGMII mode. + + + value=true will configure component phy to work in MII or GMII mode. + + + value=true will configure component phy to work in SGMII mode. + + + value=true will configure component phy either to work RGMII mode. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + FPGA part on the board + + + DDR3 board interface, it can use MIG IP for connection. + + + + + + Primary interface to communicate with ethernet phy in GMII mode. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + true + false + true + false + false + + + + + Primary interface to communicate with ethernet phy in MII mode. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + true + false + true + false + false + + + + + Primary interface to communicate with ethernet phy in RGMII mode. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + true + false + false + false + true + + + + + + + + Primary interface to communicate with ethernet phy in SGMII mode. + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + true + false + true + false + + + + + Secondary interface to communicate with ethernet phy when mode is selected as MII,GMII,1000BaseX. + + + + + + + + + + + + + + + + + + Secondary interface to communicate with ethernet phy when mode is selected as SGMII. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 4-position user DIP Switch + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + true + false + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + true + false + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 GB DDR3 memory SODIMM + + + + + + + PHY on the board + + + To enable this mode jumpers need to be {J29_P1_P2 true} {J30_P1_P2 true} {J64 false} + + + + + + + + + + + To enable this mode jumpers need to be {J29_P1_P2 true} {J30_P1_P2 true} {J64 false} + + + + + + + + + + + To enable this mode jumpers need to be {J29_P2_P3 true} {J30_P2_P3 true} {J64 false} + + + + + + + + + + + + To enable this mode jumpers need to be {J29_P1_P2 true} {J30_P1_P2 false} {J30_P2_P3 false} {J64 true} + + + + + + + + + + + + + DIP Switches 3 to 0 + + + Edge Drive Jog Encoder Rotary Switch, INCB, PUSH, INCA, Active High + + + 2.5V LVDS differential 200 MHz oscillator used as system differential clock on the board + + + + + + Ethernet 125 MHz SGMII GTX Clock + + + + + + PHY outside the board connected through sfp + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + PHY outside the board connected through sma + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + PHY outside the board connected through sma in lvds mode + + + + + + + + + + + + + SMA MGT CLOCK + + + + + + 128 MB of nonvolatile storage that can be used for configuration or software storage + + + To enable this mode jumpers need to be {SW13_M0 false} {SW13_M1 true} + + + + + + + + + + + 128 MB of nonvolatile storage that can be used for configuration or data storage + + + To enable this mode jumpers need to be {SW13_M0 true} {SW13_M1 false} + + + + + + + + + + + LEDs, 7 to 0, Active High + + + A 2-line by 16-character display + + + USB-to-UART Bridge, which allows a connection to a host computer with a USB port + + + + + + + I2C + + + CPU Reset Push Button, Active High + + + Push Buttons, C W E S N, Active High + + + Clock input from PCI Express edge connector + + + + + + + PCI Express + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/kc705/1.6/changelog.txt @@ -0,0 +1,7 @@ +######### KC705 Change log ############## +1.6 +Updated mig.prj to fix mrCasLatency and mr2CasLatency + +1.5 +Added FMC support + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/kc705/1.6/kc705_board.jpeg b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/kc705/1.6/kc705_board.jpeg new file mode 100644 index 0000000..ce15e5d Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/kc705/1.6/kc705_board.jpeg differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/kc705/1.6/mig.prj b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/kc705/1.6/mig.prj new file mode 100644 index 0000000..49d6b02 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/kc705/1.6/mig.prj @@ -0,0 +1,222 @@ + + + + design_1_mig_7series_0_0 + + 1 + + 1 + + OFF + + 1024 + + ON + + Enabled + + xc7k325t-ffg900/-2 + + 4.2 + + Differential + + Use System Clock + + ACTIVE HIGH + + FALSE + + 0 + + 50 Ohms + + 1 + + + DDR3_SDRAM/SODIMMs/MT8JTF12864HZ-1G6 + 1250 + 1.8V + 4:1 + 200 + 1 + 800 + 8.000 + 1 + 1 + 1 + 1 + 64 + 1 + 1 + Disabled + Normal + 4 + FALSE + + 14 + 10 + 3 + 1.5V + 1073741824 + BANK_ROW_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 11 + Normal + No + Slow Exit + Enable + RZQ/7 + Disable + Enable + RZQ/6 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 8 + Enabled + Normal + Dynamic ODT off + AXI + + RD_PRI_REG + 32 + 512 + 1 + 1 + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/kc705/1.6/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/kc705/1.6/part0_pins.xml new file mode 100644 index 0000000..077b6e2 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/kc705/1.6/part0_pins.xml @@ -0,0 +1,431 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/kc705/1.6/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/kc705/1.6/preset.xml new file mode 100644 index 0000000..742022e --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/kc705/1.6/preset.xml @@ -0,0 +1,531 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/kc705/1.6/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/kc705/1.6/xitem.json new file mode 100644 index 0000000..2c08b7a --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/kc705/1.6/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "kc705", + "display": "Kintex-7 KC705 Evaluation Platform", + "revision": "1.6", + "description": "Kintex-7 KC705 Evaluation Platform", + "company": "xilinx.com", + "company_display": "Xilinx", + "author": "Vanitha", + "contributors": [ + { + "group": "Xilinx", + "url": "www.xilinx.com" + } + ], + "category": "Single Part", + "website": "http://www.xilinx.com/kc705", + "search-keywords": [ + "kc705", + "xilinx.com", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/kcu105/1.6/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/kcu105/1.6/board.xml new file mode 100644 index 0000000..2e0fc68 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/kcu105/1.6/board.xml @@ -0,0 +1,2037 @@ + + + + + KCU105 Board File Image + + + + 1.0 + + 1.6 + Kintex-UltraScale KCU105 Evaluation Platform + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Kintex-UltraScale FPGA part on the board + + + DDR4 board interface, it can use MIG IP for connection. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 4-position user DIP Switch + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + > + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Primary interface to communicate with ethernet phy in SGMII mode. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Secondary interface to communicate with ethernet phy when mode is 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b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/kcu105/1.6/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "kcu105", + "display": "Kintex-UltraScale KCU105 Evaluation Platform", + "revision": "1.6", + "description": "Kintex-UltraScale KCU105 Evaluation Platform", + "company": "xilinx.com", + "company_display": "Xilinx", + "author": "Vanitha", + "contributors": [ + { + "group": "Xilinx", + "url": "www.xilinx.com" + } + ], + "category": "Single Part", + "website": "www.xilinx.com/kcu105", + "search-keywords": [ + "kcu105", + "xilinx.com", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/kcu116/1.4/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/kcu116/1.4/board.xml new file mode 100644 index 0000000..d3a39ed --- /dev/null +++ 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+ +1.2 +Avoiding upper case attributes + +1.1 +Enabled SGMII over LVDS support + +1.0 +KCU116 production board support + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/kcu116/1.4/kcu116_board.jpeg b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/kcu116/1.4/kcu116_board.jpeg new file mode 100644 index 0000000..1ee8f64 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/kcu116/1.4/kcu116_board.jpeg differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/kcu116/1.4/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/kcu116/1.4/part0_pins.xml new file mode 100644 index 0000000..cbb7e75 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/kcu116/1.4/part0_pins.xml @@ -0,0 +1,296 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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"xilinx.com", + "company_display": "Xilinx", + "author": "Vanitha", + "contributors": [ + { + "group": "Xilinx", + "url": "www.xilinx.com" + } + ], + "category": "Single Part", + "website": "www.xilinx.com/kcu116", + "search-keywords": [ + "kcu116", + "xilinx.com", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/kcu1500/1.2/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/kcu1500/1.2/board.xml new file mode 100644 index 0000000..03c2a42 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/kcu1500/1.2/board.xml @@ -0,0 +1,1649 @@ + + + + + Xilinx Developer Board for Acceleration with Kintex UltraScale KU115 + + + + + 1.0 + + + 1.2 + + Kintex UltraScale KCU1500 Acceleration Development Board + + + + + + + + + + + + Kintex UltraScale KU115 FPGA + + + + + DDR4 board interface, it can use DDR4 IP for connection. + + + + + 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index 0000000..1d70059 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/kcu1500/1.2/kcu1500_board.png differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/kcu1500/1.2/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/kcu1500/1.2/part0_pins.xml new file mode 100644 index 0000000..bc5955e --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/kcu1500/1.2/part0_pins.xml @@ -0,0 +1,591 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/kcu1500/1.2/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "KCU1500", + "display": "Kintex UltraScale KCU1500 Acceleration Development Board", + "revision": "1.2", + "description": "Kintex UltraScale KCU1500 Acceleration Development Board", + "company": "xilinx.com", + "company_display": "Xilinx", + "author": "Vanitha", + "contributors": [ + { + "group": "Xilinx", + "url": "www.xilinx.com" + } + ], + "category": "Single Part", + "website": "https://www.xilinx.com/products/boards-and-kits/dk-u1-kcu1500-g.html", + "search-keywords": [ + "KCU1500", + "xilinx.com", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/sp701/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/sp701/1.0/board.xml new file mode 100644 index 0000000..6ae608c --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/sp701/1.0/board.xml @@ -0,0 +1,625 @@ + + + + + SP701 Board File Image + + + + 1.0 + + 1.0 + Spartan-7 SP701 Evaluation Platform + + + + + FPGA part on the board + + + + DDR3 board interface, it can use MIG IP for connection. + + + + + + + + 16-position user DIP Switch + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Secondary interface to communicate with ethernet phy when mode is selected as SGMII. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Secondary interface to communicate with ethernet phy when mode is selected as SGMII. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Primary interface to communicate with ethernet phy in RGMII mode. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/sp701/1.0/xitem.json new file mode 100644 index 0000000..83ba1b5 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/sp701/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "SP701", + "display": "Spartan-7 SP701 Evaluation Platform", + "revision": "1.0", + "description": "Spartan-7 SP701 Evaluation Platform", + "company": "xilinx.com", + "company_display": "Xilinx", + "author": "Vanitha", + "contributors": [ + { + "group": "Xilinx", + "url": "www.xilinx.com" + } + ], + "category": "Single Part", + "website": "http://www.xilinx.com/sp701", + "search-keywords": [ + "SP701", + "xilinx.com", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/v350/es/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/v350/es/1.0/board.xml new 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a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/v350/es/1.0/changelog.txt b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/v350/es/1.0/changelog.txt new file mode 100644 index 0000000..aaf7446 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/v350/es/1.0/changelog.txt @@ -0,0 +1,8 @@ +######### V350 Initial change log ############## +1.0 + +V350_es Initial board support. + +Features: +CIPS block automation +AXI_NOC X4 Interleaved Memory Controllers \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/v350/es/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/v350/es/1.0/part0_pins.xml new file mode 100644 index 0000000..521210b --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/v350/es/1.0/part0_pins.xml @@ -0,0 +1,664 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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clock inputs of a GTX transceiver + + + LEDs, 3 to 0, Active High + + + + CPU Reset Push Button, Active High + + + PHY outside the board connected through sfp + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + PHY outside the board connected through sma + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + SMA MGT Clock, 125 MHz + + + 2.5V LVDS differential 200 MHz oscillator used as system differential clock on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zc706/1.4/changelog.txt b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zc706/1.4/changelog.txt new file mode 100644 index 0000000..bb346a1 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zc706/1.4/changelog.txt @@ -0,0 +1,5 @@ +######### ZC706 Change log ############## + +1.4 +Added FMC support + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zc706/1.4/mig.prj b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zc706/1.4/mig.prj new file mode 100644 index 0000000..d98eee7 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zc706/1.4/mig.prj @@ -0,0 +1,203 @@ + + + + design_1_mig_7series_1_0 + 1 + 1 + OFF + 1024 + ON + Enabled + xc7z045-ffg900/-2 + 1.9 + Differential + Use System Clock + ACTIVE HIGH + FALSE + 0 + 50 Ohms + 1 + + DDR3_SDRAM/SODIMMs/MT8JTF12864HZ-1G6 + 1250 + 1.8V + 4:1 + 200 + 1 + 8.000 + 1 + 1 + 1 + 1 + 64 + 1 + 1 + Disabled + Normal + FALSE + + 14 + 10 + 3 + 1.5V + BANK_ROW_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 6 + Normal + No + Slow Exit + Enable + RZQ/7 + Disable + Enable + RZQ/6 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 5 + Enabled + Normal + Dynamic ODT off + AXI + + RD_PRI_REG + 32 + 512 + 2 + 0 + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zc706/1.4/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zc706/1.4/part0_pins.xml new file mode 100644 index 0000000..e78f5fa --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zc706/1.4/part0_pins.xml @@ -0,0 +1,216 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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"search-keywords": [ + "zc706", + "xilinx.com", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zc706/1.4/zc706_board.jpg b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zc706/1.4/zc706_board.jpg new file mode 100644 index 0000000..69bb54e Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zc706/1.4/zc706_board.jpg differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu102/3.3/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu102/3.3/board.xml new file mode 100644 index 0000000..a961e04 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu102/3.3/board.xml @@ -0,0 +1,903 @@ + + + + + ZCU102 Board File Image + + + + 1.0 + 1.1 + + 3.3 + Zynq UltraScale+ ZCU102 Evaluation Board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + DDR4 board interface, it can use DDR4 controller IP for connection. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8-position user DIP Switch + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + SI570 based User programmable differential 300 MHz Clock. Can be used for DDR4 input system clock + + + + + + PL UART + + + + + + + PL I2C0 + + + PL I2C1 + + + 2GB DDR4 SDRAM memory SODIMM + + + + + + + CPU Reset Push Button, Active High + + + DIP Switches 7 to 0 + + + + LEDs, 7 to 0, Active High + + + + Push Buttons, C W E S N, Active High + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu102/3.3/changelog.txt b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu102/3.3/changelog.txt new file mode 100644 index 0000000..1b306db --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu102/3.3/changelog.txt @@ -0,0 +1,21 @@ +3.3 +Added PSU_DYNAMIC_DDR_CONFIG_EN to MPSoC preset +Added 1.1 as compatible board rev + +3.2 +Updated DDR4 CLK IOSTANDARDs + +3.1 +Updated PS_REF_CLK frequency to match ZCU102 board UG +Added FMC support + +3.0 +production device support +Revised MPSOC clock settings for Display port +APU frequency chnaged from 1100M to 1200Mhz + + +2.1 +GT configuration revised from DP-DP-USB-SATA to PCIe-DP-USB-SATA +PMU GPI is disbaled + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu102/3.3/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu102/3.3/part0_pins.xml new file mode 100644 index 0000000..887280c --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu102/3.3/part0_pins.xml @@ -0,0 +1,331 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu102/3.3/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu102/3.3/preset.xml new file mode 100644 index 0000000..b8b7049 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu102/3.3/preset.xml @@ -0,0 +1,438 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu102/3.3/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu102/3.3/xitem.json new file mode 100644 index 0000000..0a33f45 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu102/3.3/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "zcu102", + "display": "Zynq UltraScale+ ZCU102 Evaluation Board", + "revision": "3.3", + "description": "Zynq UltraScale+ ZCU102 Evaluation Board", + "company": "xilinx.com", + "company_display": "Xilinx", + "author": "Vanitha", + "contributors": [ + { + "group": "Xilinx", + "url": "www.xilinx.com" + } + ], + "category": "Single Part", + "website": "www.xilinx.com/zcu102", + "search-keywords": [ + "zcu102", + "xilinx.com", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu102/3.3/zcu102_board.jpeg b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu102/3.3/zcu102_board.jpeg new file mode 100644 index 0000000..4679f7a Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu102/3.3/zcu102_board.jpeg differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu104/1.1/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu104/1.1/board.xml new file mode 100644 index 0000000..3d39ca7 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu104/1.1/board.xml @@ -0,0 +1,657 @@ + + + + + + ZCU104 Board File Image + + + + + RevA + RevB + RevC + + + 1.1 + + Zynq UltraScale+ ZCU104 Evaluation Board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + DDR4 board interface, it can use DDR4 controller IP for connection. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 4-Position User DIP Switch + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + SI570 based User programmable differential 300 MHz Clock. Can be used for DDR4 input system clock + + + + + + + PL UART + + + + + + + + PL I2C + + + + + 2GB DDR4 SDRAM memory SODIMM + + + + + + + + CPU Reset Push Button, Active High + + + + DIP Switches 3 to 0 + + + + LEDs, 3 to 0, Active High + + + + Push Buttons, 3 to 0, Active High + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu104/1.1/changelog.txt b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu104/1.1/changelog.txt new file mode 100644 index 0000000..0ab8571 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu104/1.1/changelog.txt @@ -0,0 +1,12 @@ +**********ZCU104 changelog ************** + +1.1 +Removed MIG IO attributes + +----Dec 13(2018.1) --------- +Enabled PLDDR4 and FMC + +Int_1.0 +Internal support for ZCU104 with MPSoC, a PL clock, CPU reset interfaces + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu104/1.1/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu104/1.1/part0_pins.xml new file mode 100644 index 0000000..106f5f3 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu104/1.1/part0_pins.xml @@ -0,0 +1,228 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git 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"xilinx.com", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu104/1.1/zcu104_board.jpeg b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu104/1.1/zcu104_board.jpeg new file mode 100644 index 0000000..ba6436a Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu104/1.1/zcu104_board.jpeg differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu106/2.4/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu106/2.4/board.xml new file mode 100644 index 0000000..cc4f627 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu106/2.4/board.xml @@ -0,0 +1,1177 @@ + + + + + ZCU106 Board File Image + + + + 1.1 + + 2.4 + Zynq UltraScale+ ZCU106 Evaluation Platform + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu106/2.4/changelog.txt b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu106/2.4/changelog.txt new file mode 100644 index 0000000..61e78b4 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu106/2.4/changelog.txt @@ -0,0 +1,33 @@ +######### ZCU106 changelog ############ +2.4 +Enabled support for pcie4_uscale_plus IP +Added PSU_DYNAMIC_DDR_CONFIG_EN to MPSoC preset + +2.3 +Added GT Quad locations for XDMA + +2.2 +Swapped PL UART pins and updated DIP switch IO-Standards + +2.1 +Removed MIG IO attributes + +2.0 +Production Silicon Support + +1.2(June 23 2017) +Enabled FMC Support + +1.1(June 23 2017) +2017.2_web release +PSS_REF_CLK__FREQMHZ changed from 33.333 to 33.330 to match with board UG + + +1.0(April 28 2017) +2017.1_web release +Updated DP and other clocking parameters to match with ZCU102 board +Moved LED3 location from AP8 to AE15 and increased PL DDR4 frequency from 1066Mhz to 1200Mhz + +1.0 +ZCU106 es2 board support + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu106/2.4/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu106/2.4/part0_pins.xml new file mode 100644 index 0000000..d1a2252 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu106/2.4/part0_pins.xml @@ -0,0 +1,346 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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Platform", + "revision": "2.4", + "description": "Zynq UltraScale+ ZCU106 Evaluation Platform", + "company": "xilinx.com", + "company_display": "Xilinx", + "author": "Vanitha", + "contributors": [ + { + "group": "Xilinx", + "url": "www.xilinx.com" + } + ], + "category": "Single Part", + "website": "www.xilinx.com/zcu106", + "search-keywords": [ + "zcu106", + "xilinx.com", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu106/2.4/zcu106_board.jpeg b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu106/2.4/zcu106_board.jpeg new file mode 100644 index 0000000..844ac62 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu106/2.4/zcu106_board.jpeg differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu106/2.5/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu106/2.5/board.xml new file mode 100644 index 0000000..30620c0 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu106/2.5/board.xml @@ -0,0 +1,1311 @@ + + + + + ZCU106 Board File Image + + + + 1.1 + + 2.5 + Zynq UltraScale+ ZCU106 Evaluation Platform + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu106/2.5/changelog.txt b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu106/2.5/changelog.txt new file mode 100644 index 0000000..95bf226 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu106/2.5/changelog.txt @@ -0,0 +1,36 @@ +######### ZCU106 changelog ############ +2.5 +Added support for xxv_ethernet IP + +2.4 +Enabled support for pcie4_uscale_plus IP +Added PSU_DYNAMIC_DDR_CONFIG_EN to MPSoC preset + +2.3 +Added GT Quad locations for XDMA + +2.2 +Swapped PL UART pins and updated DIP switch IO-Standards + +2.1 +Removed MIG IO attributes + +2.0 +Production Silicon Support + +1.2(June 23 2017) +Enabled FMC Support + +1.1(June 23 2017) +2017.2_web release +PSS_REF_CLK__FREQMHZ changed from 33.333 to 33.330 to match with board UG + + +1.0(April 28 2017) +2017.1_web release +Updated DP and other clocking parameters to match with ZCU102 board +Moved LED3 location from AP8 to AE15 and increased PL DDR4 frequency from 1066Mhz to 1200Mhz + +1.0 +ZCU106 es2 board support + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu106/2.5/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu106/2.5/part0_pins.xml new file mode 100644 index 0000000..133345e --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu106/2.5/part0_pins.xml @@ -0,0 +1,357 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu106/2.5/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu106/2.5/preset.xml new file mode 100644 index 0000000..fd4a627 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu106/2.5/preset.xml @@ -0,0 +1,590 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu106/2.5/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu106/2.5/xitem.json new file mode 100644 index 0000000..9040364 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu106/2.5/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "zcu106", + "display": "Zynq UltraScale+ ZCU106 Evaluation Platform", + "revision": "2.4", + "description": "Zynq UltraScale+ ZCU106 Evaluation Platform", + "company": "xilinx.com", + "company_display": "Xilinx", + "author": "Vanitha", + "contributors": [ + { + "group": "Xilinx", + "url": "www.xilinx.com" + } + ], + "category": "Single Part", + "website": "www.xilinx.com/zcu106", + "search-keywords": [ + "zcu106", + "xilinx.com", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu106/2.5/zcu106_board.jpeg b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu106/2.5/zcu106_board.jpeg new file mode 100644 index 0000000..844ac62 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu106/2.5/zcu106_board.jpeg differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu111/1.2/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu111/1.2/board.xml new file mode 100644 index 0000000..b7db73e --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu111/1.2/board.xml @@ -0,0 +1,638 @@ + + + + + ZCU111 Board File Image + + + + Rev A + Rev B + Rev 1.0 + + 1.2 + Zynq UltraScale+ ZCU111 Evaluation Platform + + + + + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + DDR4 board interface, it can use DDR4 controller IP for connection. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8-position user DIP Switch + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + SI570 based User programmable differential 300 MHz Clock. Can be used for DDR4 input system clock + + + + + + + + PL HP Bank GC input with external termination + + + + + + + PL HP Bank GC input with external termination + + + + + + + + + + + PL UART + + + + + + + + PL I2C0 + + + + PL I2C1 + + + + 8Gb DDR4 SDRAM memory SODIMM + + + + + + + + + + + + + + + + + + CPU Reset Push Button, Active High + + + + DIP Switches 7 to 0 + + + + LEDs, 7 to 0, Active High + + + + Push Buttons, C W E S N, Active High + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu111/1.2/changelog.txt b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu111/1.2/changelog.txt new file mode 100644 index 0000000..01c8275 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu111/1.2/changelog.txt @@ -0,0 +1,10 @@ +######### ZCU111 change log ############ +1.2 +Increaed DDDR4 frequency from 1200 to 1333Mhz + +1.1 +Viavdo Board Support for Rev 1.0, Production Silicon + +1.0 +ZCU111 initial board support for Rev B, Pre production Silicon + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu111/1.2/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu111/1.2/part0_pins.xml new file mode 100644 index 0000000..e8538b4 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu111/1.2/part0_pins.xml @@ -0,0 +1,176 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu111/1.2/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu111/1.2/preset.xml new file mode 100644 index 0000000..f4b8d38 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu111/1.2/preset.xml @@ -0,0 +1,430 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu111/1.2/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu111/1.2/xitem.json new file mode 100644 index 0000000..898b5a4 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu111/1.2/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "zcu111", + "display": "Zynq UltraScale+ ZCU111 Evaluation Platform", + "revision": "1.2", + "description": "Zynq UltraScale+ ZCU111 Evaluation Platform", + "company": "xilinx.com", + "company_display": "Xilinx", + "author": "Vanitha", + "contributors": [ + { + "group": "Xilinx", + "url": "www.xilinx.com" + } + ], + "category": "Single Part", + "website": "www.xilinx.com/zcu111", + "search-keywords": [ + "zcu111", + "xilinx.com", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu111/1.2/zcu111_board.jpeg b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu111/1.2/zcu111_board.jpeg new file mode 100644 index 0000000..1058a14 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu111/1.2/zcu111_board.jpeg differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1275/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1275/1.0/board.xml new file mode 100644 index 0000000..81b5886 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1275/1.0/board.xml @@ -0,0 +1,214 @@ + + + + + ZCU1275 Board Image + + + + 2.0 + + 1.0 + Xilinx Zynq UltraScale+ RFSoC ZCU1275 Characterization Kit + + + + + + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + User Switches(8-position) + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + PL UART + + + + + + + + + + DIP Switches 7 to 0 + + + + LEDs, 7 downto 0, Active High + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1275/1.0/changelog.txt b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1275/1.0/changelog.txt new file mode 100644 index 0000000..067318f --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1275/1.0/changelog.txt @@ -0,0 +1,4 @@ +######### ZCU1275 change log ############ +1.0 +ZCU1275 board support + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1275/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1275/1.0/part0_pins.xml new file mode 100644 index 0000000..c750225 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1275/1.0/part0_pins.xml @@ -0,0 +1,38 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1275/1.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1275/1.0/preset.xml new file mode 100644 index 0000000..2bd0967 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1275/1.0/preset.xml @@ -0,0 +1,403 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1275/1.0/readme.txt b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1275/1.0/readme.txt new file mode 100644 index 0000000..adfaedd --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1275/1.0/readme.txt @@ -0,0 +1,14 @@ + +1)Validate that the xczu29dr-ffvf1760-2-e is available in your Vivado installation. Please see details in the board lounge or in user guide UG973: Vivado Release Notes, Installation, and Licensing. + +2) Copy the contents from the zip for into local Vivado install. +Vivado\201X.x\data\boards\board_files\zcu1275\ + +Alternative to step 2) +Copy the contents from the zip into a local directory . +Set the following parameter either in your Vivado_init.tcl or on the Vivado TCL console before project creation. +>> set_param board.repoPaths + +For more information please refer to user guide UG895: Vivado System-Level Design Guide, Appendix A. + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1275/1.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1275/1.0/xitem.json new file mode 100644 index 0000000..c8f69a6 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1275/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "zcu1275", + "display": "Xilinx Zynq UltraScale+ RFSoC ZCU1275 Characterization Kit", + "revision": "1.0", + "description": "Xilinx Zynq UltraScale+ RFSoC ZCU1275 Characterization Kit", + "company": "xilinx.com", + "company_display": "Xilinx", + "author": "Vanitha", + "contributors": [ + { + "group": "Xilinx", + "url": "www.xilinx.com" + } + ], + "category": "Single Part", + "website": "www.xilinx.com/zcu1254", + "search-keywords": [ + "zcu1275", + "xilinx.com", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1275/1.0/zcu1275_board.jpeg b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1275/1.0/zcu1275_board.jpeg new file mode 100644 index 0000000..a9ffdc7 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1275/1.0/zcu1275_board.jpeg differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1285/1.0/board.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1285/1.0/board.xml new file mode 100644 index 0000000..57bafc4 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1285/1.0/board.xml @@ -0,0 +1,214 @@ + + + + + ZCU1285 Board Image + + + + 2.0 + + 1.0 + Xilinx Zynq UltraScale+ RFSoC ZCU1285 Characterization Kit + + + + + + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + User Switches(8-position) + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + PL UART + + + + + + + + + + DIP Switches 7 to 0 + + + + LEDs, 7 downto 0, Active High + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1285/1.0/changelog.txt b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1285/1.0/changelog.txt new file mode 100644 index 0000000..73eb33e --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1285/1.0/changelog.txt @@ -0,0 +1,4 @@ +######### ZCU1285 change log ############ +1.0 +ZCU1285 board support + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1285/1.0/part0_pins.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1285/1.0/part0_pins.xml new file mode 100644 index 0000000..86c5db7 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1285/1.0/part0_pins.xml @@ -0,0 +1,38 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1285/1.0/preset.xml b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1285/1.0/preset.xml new file mode 100644 index 0000000..5d7b1f6 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1285/1.0/preset.xml @@ -0,0 +1,402 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1285/1.0/readme.txt b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1285/1.0/readme.txt new file mode 100644 index 0000000..d3fc9f4 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1285/1.0/readme.txt @@ -0,0 +1,14 @@ + +1)Validate that the xczu39dr-ffvf1760-2-i is available in your Vivado installation. Please see details in the board lounge or in user guide UG973: Vivado Release Notes, Installation, and Licensing. + +2) Copy the contents from the zip for into local Vivado install. +Vivado\201X.x\data\boards\board_files\zcu1285\ + +Alternative to step 2) +Copy the contents from the zip into a local directory . +Set the following parameter either in your Vivado_init.tcl or on the Vivado TCL console before project creation. +>> set_param board.repoPaths + +For more information please refer to user guide UG895: Vivado System-Level Design Guide, Appendix A. + + diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1285/1.0/xitem.json b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1285/1.0/xitem.json new file mode 100644 index 0000000..1f17f15 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1285/1.0/xitem.json @@ -0,0 +1,33 @@ +{ + "config": { + "items": [ + { + "infra": { + "name": "zcu1285", + "display": "Xilinx Zynq UltraScale+ RFSoC ZCU1285 Characterization Kit", + "revision": "1.0", + "description": "Xilinx Zynq UltraScale+ RFSoC ZCU1285 Characterization Kit", + "company": "xilinx.com", + "company_display": "Xilinx", + "author": "Vanitha", + "contributors": [ + { + "group": "Xilinx", + "url": "www.xilinx.com" + } + ], + "category": "Single Part", + "website": "www.xilinx.com/zcu1285", + "search-keywords": [ + "zcu1285", + "xilinx.com", + "board", + "Single Part" + ] + } + } + ] + }, + "_major": 1, + "_minor": 0 +} \ No newline at end of file diff --git a/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1285/1.0/zcu1285_board.jpeg b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1285/1.0/zcu1285_board.jpeg new file mode 100644 index 0000000..a9ffdc7 Binary files /dev/null and b/XilinxBoardStore_with_Alveo_cards_support/boards/Xilinx/zcu1285/1.0/zcu1285_board.jpeg differ diff --git a/XilinxBoardStore_with_Alveo_cards_support/catalog/vivado_2019.2.json b/XilinxBoardStore_with_Alveo_cards_support/catalog/vivado_2019.2.json new file mode 100644 index 0000000..d0878b3 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/catalog/vivado_2019.2.json @@ -0,0 +1,2524 @@ +{ + "catalog": { + "items": [ + { + "name": "Ultra96", + "display": "Ultra96 Evaluation Platform", + "latest_revision": "1.2", + "commit_id": "db82df60ac9023136a25d6694bf7fc90e3a8d797", + "revisions": [ + { + "revision": "1.2", + "commit_id": "db82df60ac9023136a25d6694bf7fc90e3a8d797", + "date": "21-08-2018:19:15:03", + "history": "Adding Ultra96 1.2 to the XilinxBoardStore" + } + ], + "config": { + "root": "boards/Avnet/ultra96/1.2", + "metadata_file": "xitem.json" + }, + "company": "em.avnet.com" + }, + { + "name": "picozed_7010_fmc2", + "display": "PicoZed 7010 SOM + FMC Carrier V2", + "latest_revision": "1.2", + "commit_id": "db82df60ac9023136a25d6694bf7fc90e3a8d797", + "revisions": [ + { + "revision": "1.2", + "commit_id": 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"11-09-2018:16:24:04", + "history": "Added arty-a7-100 to the XilinxBoardStore" + } + ], + "config": { + "root": "boards/Digilent/arty-a7-100/E.0", + "metadata_file": "xitem.json" + }, + "company": "digilentinc.com" + }, + { + "name": "arty-a7-35", + "display": "Arty A7-35", + "latest_revision": "1.0", + "commit_id": "db82df60ac9023136a25d6694bf7fc90e3a8d797", + "revisions": [ + { + "revision": "1.0", + "commit_id": "db82df60ac9023136a25d6694bf7fc90e3a8d797", + "date": "11-09-2018:16:24:04", + "history": "Added arty-a7-35 to the XilinxBoardStore" + } + ], + "config": { + "root": "boards/Digilent/arty-a7-35/E.0", + "metadata_file": "xitem.json" + }, + "company": "digilentinc.com" + }, + { + "name": "arty-s7-25", + "display": "Arty S7-25", + "latest_revision": "1.0", + "commit_id": "db82df60ac9023136a25d6694bf7fc90e3a8d797", + "revisions": [ + { + "revision": "1.0", + "commit_id": "db82df60ac9023136a25d6694bf7fc90e3a8d797", + "date": "11-09-2018:16:24:04", + "history": "Added arty-s7-25 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"xitem.json" + }, + "company": "digilentinc.com" + }, + { + "name": "cmod-s7-25", + "display": "Cmod S7-25", + "latest_revision": "1.0", + "commit_id": "db82df60ac9023136a25d6694bf7fc90e3a8d797", + "revisions": [ + { + "revision": "1.0", + "commit_id": "db82df60ac9023136a25d6694bf7fc90e3a8d797", + "date": "11-09-2018:16:24:05", + "history": "Added cmod-s7-25 to the XilinxBoardStore" + } + ], + "config": { + "root": "boards/Digilent/cmod-s7-25/B.0", + "metadata_file": "xitem.json" + }, + "company": "digilentinc.com" + }, + { + "name": "cmod_a7-15t", + "display": "Cmod A7-15t", + "latest_revision": "1.1", + "commit_id": "db82df60ac9023136a25d6694bf7fc90e3a8d797", + "revisions": [ + { + "revision": "1.1", + "commit_id": "db82df60ac9023136a25d6694bf7fc90e3a8d797", + "date": "11-09-2018:16:24:05", + "history": "Added cmod_a7-15t to the XilinxBoardStore" + } + ], + "config": { + "root": "boards/Digilent/cmod_a7-15t/B.0", + "metadata_file": "xitem.json" + }, + "company": "digilentinc.com" + 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"boards/Avnet/minized/1.2", + "metadata_file": "xitem.json" + }, + "company": "em.avnet.com" + }, + { + "name": "te0712_100_1i", + "display": "Artix-7 TE0712_100_1I. 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"metadata_file": "xitem.json" + }, + "company": "xilinx.com" + }, + { + "name": "zcu111", + "display": "Zynq UltraScale+ ZCU111 Evaluation Platform", + "latest_revision": "1.2", + "commit_id": "c0944700b73787b72133d87b7519934741cda4ee", + "revisions": [ + { + "revision": "1.2", + "commit_id": "c0944700b73787b72133d87b7519934741cda4ee", + "date": "28-05-2019:11:04:52", + "history": "Migrating 7 series latest board files from perforce to git" + } + ], + "config": { + "root": "boards/Xilinx/zcu111/1.2", + "metadata_file": "xitem.json" + }, + "company": "xilinx.com" + }, + { + "name": "zcu1275", + "display": "Xilinx Zynq UltraScale+ RFSoC ZCU1275 Characterization Kit", + "latest_revision": "1.0", + "commit_id": "c0944700b73787b72133d87b7519934741cda4ee", + "revisions": [ + { + "revision": "1.0", + "commit_id": "c0944700b73787b72133d87b7519934741cda4ee", + "date": "28-05-2019:11:05:07", + "history": "Migrating 7 series latest board files from perforce to git" + } + ], + "config": { + "root": "boards/Xilinx/zcu1275/1.0", + "metadata_file": "xitem.json" + }, + "company": "xilinx.com" + }, + { + "name": "zcu1285", + "display": "Xilinx Zynq UltraScale+ RFSoC ZCU1285 Characterization Kit", + "latest_revision": "1.0", + "commit_id": "c0944700b73787b72133d87b7519934741cda4ee", + "revisions": [ + { + "revision": "1.0", + "commit_id": "c0944700b73787b72133d87b7519934741cda4ee", + "date": "28-05-2019:11:05:16", + "history": "Migrating 7 series latest board files from perforce to git" + } + ], + "config": { + "root": "boards/Xilinx/zcu1285/1.0", + "metadata_file": "xitem.json" + }, + "company": "xilinx.com" + }, + { + "name": "au280_es1", + "display": "Alveo U280-ES1 Data Center Accelerator Card", + "latest_revision": "1.1", + "commit_id": "ff158172d435d82c4beefc0289e6831353144573", + "revisions": [ + { + "revision": "1.0", + "commit_id": "ff158172d435d82c4beefc0289e6831353144573", + "date": "28-05-2019:11:08:19", + "history": "Migrating Alveo latest board files from perforce/2019.1 to git" + } + ], + "config": { + "root": "boards/Xilinx/au280/es1/1.0", + "metadata_file": "xitem.json" + }, + "company": "xilinx.com" + }, + { + "name": "au280_es1", + "display": "Alveo U280-ES1 Data Center Accelerator Card", + "latest_revision": "1.1", + "commit_id": "ff158172d435d82c4beefc0289e6831353144573", + "revisions": [ + { + "revision": "1.1", + "commit_id": "ff158172d435d82c4beefc0289e6831353144573", + "date": "28-05-2019:11:08:19", + "history": "Migrating Alveo latest board files from perforce/2019.1 to git" + } + ], + "config": { + "root": "boards/Xilinx/au280/es1/1.1", + "metadata_file": "xitem.json" + }, + "company": "xilinx.com" + }, + { + "name": "au200", + "display": "Alveo U200 Data Center Accelerator Card", + "latest_revision": "1.2", + "commit_id": "78da943ed1848454aa4c8a176264366f572a947b", + "revisions": [ + { + "revision": "1.2", + "commit_id": "78da943ed1848454aa4c8a176264366f572a947b", + "date": "28-05-2019:11:12:54", + "history": "Migrating Alveo latest board files from perforce/2019.1 to git" + } + ], + "config": { + "root": "boards/Xilinx/au200/1.2", + "metadata_file": "xitem.json" + }, + "company": "xilinx.com" + }, + { + "name": "v350_es", + "display": "V350 ES0 Data Center Accelerator Card", + "latest_revision": "1.0", + "commit_id": "676be16ce37967f77b51e33fb84ae29b957e4b95", + "revisions": [ + { + "revision": "1.0", + "commit_id": "676be16ce37967f77b51e33fb84ae29b957e4b95", + "date": "13-07-2019:20:07:54", + "history": "Adding v350 board support" + } + ], + "config": { + "root": "boards/Xilinx/v350/es/1.0", + "metadata_file": "xitem.json" + }, + "company": "xilinx.com" + }, + { + "name": "au250", + "display": "Alveo U250 Data Center Accelerator Card", + "latest_revision": "1.2", + "commit_id": "ff158172d435d82c4beefc0289e6831353144573", + "revisions": [ + { + "revision": "1.2", + "commit_id": "ff158172d435d82c4beefc0289e6831353144573", + "date": "28-05-2019:11:13:39", + "history": "Migrating Alveo latest board files from perforce/2019.1 to git" + } + ], + "config": { + "root": "boards/Xilinx/au250/1.2", + "metadata_file": "xitem.json" + }, + "company": "xilinx.com" + } + ], + "categories": [ + { + "name": "single_part", + "display_name": "Single Part", + "description": "This category represents all the boards which have single part", + "parent": "" + }, + { + "name": "multi_part", + "display_name": "Multi Part", + "description": "This category represents all the boards which have multi part", + "parent": "" + }, + { + "name": "daughter_card", + "display_name": "Daughter Card", + "description": "This category represents all the boards which are daughter cards", + "parent": "" + }, + { + "name": "misc", + "display_name": "Misc", + "description": "This category represents miscellaneous variety of boards", + "default": true, + "parent": "" + } + ] + }, + "_major": 1, + "_minor": 0 +} diff --git a/XilinxBoardStore_with_Alveo_cards_support/catalog/xstore.json b/XilinxBoardStore_with_Alveo_cards_support/catalog/xstore.json new file mode 100644 index 0000000..9669c78 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/catalog/xstore.json @@ -0,0 +1,39 @@ +{ + "catalog": { + "current_branch": "master", + "supported_products": [ + { + "product_name": "vivado", + "supported_releases": [ + { + "version": "2018.1", + "xitem_catalogue_file": "catalog/vivado_2018.1.json", + "remote_repo_branch_to_sync": "2018.1" + }, + { + "version": "2018.2", + "xitem_catalogue_file": "catalog/vivado_2018.2.json", + "remote_repo_branch_to_sync": "2018.2" + }, + { + "version": "2018.3", + "xitem_catalogue_file": "catalog/vivado_2018.3.json", + "remote_repo_branch_to_sync": "2018.3" + }, + { + "version": "2019.1", + "xitem_catalogue_file": "catalog/vivado_2019.1.json", + "remote_repo_branch_to_sync": "2019.1" + }, + { + "version": "2019.2", + "xitem_catalogue_file": "catalog/vivado_2019.2.json", + "remote_repo_branch_to_sync": "master" + } + ] + } + ] + }, + "_major": 1, + "_minor": 0 +} diff --git a/XilinxBoardStore_with_Alveo_cards_support/utility/add_xitem_entry.py b/XilinxBoardStore_with_Alveo_cards_support/utility/add_xitem_entry.py new file mode 100644 index 0000000..2065e6f --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/utility/add_xitem_entry.py @@ -0,0 +1,201 @@ +import sys +import argparse +import json +import os +from collections import OrderedDict +from time import gmtime, strftime + +def loadStoreJson(args): + store_dir = args.store_dir + if store_dir.endswith('/'): + store_dir = store_dir[:-1] + + current_product = args.product + current_product = args.product.lower() + current_version = args.version + store_dir_path1 = store_dir + "/" + args.product + "/" + args.version + if not os.path.exists(store_dir_path1): + store_dir_path1 = store_dir + + catalog_file = store_dir_path1 + "/" + "catalog/xstore.json" + try : + infile= open(catalog_file,"r") + except IOError: + print ('cannot open', catalog_file) + exit() + else: + infile.close() + + is_product_supported = False + + with open(catalog_file, 'r') as json_file: + data = json.load(json_file,object_pairs_hook=OrderedDict) + catalog = data['catalog'] + + if data['_major'] != 1: + print ("store Major version is not supported") + exit() + + if data['_minor'] != 0: + print ("store Minor version is not supported") + exit() + + supported_products = catalog['supported_products'] + for supported_product in supported_products: + if (current_product == supported_product['product_name']): + supported_versions = supported_product['supported_releases'] + for supported_version in supported_versions: + if supported_version['version'] == current_version: + is_product_supported = True + item_catalog_file = supported_version['xitem_catalogue_file'] + + if is_product_supported == False: + print ("The store is not supported") + exit() + json_file.close() + catalog_file = store_dir_path1 + "/" + item_catalog_file + addXitemEntry(args,catalog_file) + +def extractItemRoot(args,item_revision): + store_dir = args.store_dir + item_json = args.xitem_file + abs_store_dir = os.path.abspath(store_dir) + abs_item_json_path = os.path.abspath(item_json) + item_root = abs_item_json_path + + item_root = abs_item_json_path.replace(abs_store_dir,'') + prefix_dir = "/" + args.product + "/" + args.version + "/" + if item_root.startswith(prefix_dir) : + item_root = item_root.replace(prefix_dir,'') + suffix_dir = "/xitem.json" + if item_root.endswith(suffix_dir): + item_root = item_root.replace(suffix_dir,'') + elif item_root.endswith('xitem.json'): + item_root= item_root.replace('xitem.json','') + item_root = item_root.replace('\\','/') + if item_root.startswith('/'): + item_root = item_root[1:] + if item_root.endswith('/'): + item_root = item_root[:-1] + return item_root + +def addXitemEntry(args,item_catalog_file): + store_dir = args.store_dir + try : + infile= open(item_catalog_file,"r") + except IOError: + print ('cannot open', item_catalog_file) + exit() + else: + infile.close() + + with open(item_catalog_file, 'r') as json_file: + data = json.load(json_file,object_pairs_hook=OrderedDict) + catalog = data['catalog'] + items = catalog['items'] + + loadXitemJson(args.xitem_file,items,args) + json_file.close() + + with open(item_catalog_file, 'w') as json_file: + json.dump(data,json_file,indent =2) + json_file.close() + +def loadXitemJson(xitem_json_file,xitems,args): + try : + infile= open(xitem_json_file,"r") + except IOError: + print ('cannot open', xitem_json_file) + exit() + else: + infile.close() + + with open(xitem_json_file, 'r') as xitem_json_file: + xitem_data = json.load(xitem_json_file,object_pairs_hook=OrderedDict) + xitem_config = xitem_data['config'] + xitem_items = xitem_config['items'] + if len(xitem_items) < 1: + print ("Not get xitems , xitem file is not valid") + exit() + xitem_infra = xitem_items[0]['infra'] + new_item = OrderedDict() + new_item['name'] = xitem_infra['name'] + new_item['display'] = xitem_infra['display'] + new_item['latest_revision'] = xitem_infra['revision'] + new_item['commit_id'] = args.commit_id + + current_revision = OrderedDict() + current_revision['revision'] = xitem_infra['revision'] + current_revision['commit_id'] = args.commit_id + showtime = strftime("%d-%m-%Y:%H:%M:%S", gmtime()) + current_revision['date'] = showtime + current_revision['history'] = args.description + revisions = [current_revision] + + item_root = "" + item_root = extractItemRoot(args,xitem_infra['revision']) + item_config = OrderedDict() + item_config['root'] = item_root + item_config['metadata_file'] = "xitem.json" + new_item['revisions'] = revisions + new_item['config'] = item_config + new_item['company'] = xitem_infra['company'] + + item_already_found = False + item_revision_found = False + + for xitem in xitems: + if xitem['name']== new_item['name']: + existed_xitem = xitem + item_already_found = True + break + + if item_already_found: + existed_revisions = existed_xitem['revisions'] + for existed_revision in existed_revisions: + if existed_revision['revision'] == xitem_infra['revision']: + item_revision_found = True + if existed_xitem["commit_id"] != args.commit_id: + if args.commit_id!="": + existed_xitem['commit_id'] = args.commit_id + existed_revision['commit_id'] = args.commit_id + print ("Updated commit-id of the xitem.") + break + if item_already_found: + if item_revision_found: + print ("Not added xitem as it is already present") + return + else: + existed_revisions = existed_xitem['revisions'] + existed_revisions.append(current_revision) + if args.mark_latest: + existed_xitem['latest_revision'] = xitem_infra['revision'] + + else: + xitems.append(new_item) + message = "Added the item" + new_item['name'] + ":" + xitem_infra['revision'] + " in to item catalog file." + print (message) + + +def parse_cmdline(): + + parser = argparse.ArgumentParser(description='Utility python script', + epilog="Utility script to add xitem entry in store catalog file .") +# parser.add_argument('--catalog_file', help="Path of the store catalog file", required = False) + parser.add_argument('--store_dir', help="Store Root Directory which has all the boards, catalog files", required = True) + # parser.add_argument('--output_file', help="Path of the board.xml file", required = False) + parser.add_argument('--xitem_file', help="Path of the xitem json file", required = True) + # parser.add_argument('--item_root', help="Path of the xitem relative to store root", required = True) + parser.add_argument('--commit_id', help="Path of the xitem json file", required = False,default = "") + parser.add_argument('--description', help="Decsription of the xitem ", required = True) + parser.add_argument('--product', help="Decsription of the xitem ", required = False,default = "Vivado") + parser.add_argument('--version', help="Decsription of the xitem ", required = False,default = "2018.1") + parser.add_argument('--mark_latest', type=bool, help="To mark this xitem revision as latest revision (in case of multiple revisions of items are present)", required = False, default = True) + return parser + +def main(): + parser = parse_cmdline() + args = parser.parse_args() + loadStoreJson(args) + +if __name__ == '__main__': main() diff --git a/XilinxBoardStore_with_Alveo_cards_support/utility/generate_xitem_json.py b/XilinxBoardStore_with_Alveo_cards_support/utility/generate_xitem_json.py new file mode 100644 index 0000000..c4d3777 --- /dev/null +++ b/XilinxBoardStore_with_Alveo_cards_support/utility/generate_xitem_json.py @@ -0,0 +1,125 @@ +import sys +import json +import argparse +from xml.dom import minidom +from collections import OrderedDict + +def createXitemJson(xmldoc,args) : + itemlist = xmldoc.getElementsByTagName('board') + length = len(itemlist) + + if length > 0: + name = itemlist[0].attributes['name'].value + dsname = itemlist[0].attributes['display_name'].value + vendor = itemlist[0].attributes['vendor'].value + url = itemlist[0].attributes['url'].value + schema_version = itemlist[0].attributes['schema_version'].value + #if (schema_version < "2.0"): + # print ("The utility script does work for schema 2.0 only") + # exit() + else: + print ("Did not find board Specific data in file , cannot Create xitem json file") + exit() + + subtype = "board" + imagelist = xmldoc.getElementsByTagName('image') + + imlength = len(imagelist) + deslist = xmldoc.getElementsByTagName("description") + deslen = len(deslist) + if deslen > 0 : + des = deslist[imlength].firstChild + if des: + descr = des.nodeValue.strip() + filever = xmldoc.getElementsByTagName("file_version") + + for filev in filever: + child = (filev.firstChild) + if child: + ver = child.nodeValue.strip() + else : + print ("Did not finf file_version in the board file") + exit() + + complist = xmldoc.getElementsByTagName("component") + fpgacount = 0 + category = "Single Part" + for compnode in complist: + comp_type = compnode.attributes['type'].value + if comp_type == "fpga": + fpgacount+=1 + + if fpgacount > 1 : + category = "Multi part" + + data = OrderedDict() + config = OrderedDict() + search_keywords = [name,vendor,subtype,category] + + orderItem = OrderedDict() + company_name = vendor + if (args.company_display_name !=""): + vendor = args.company_display_name + + orderItem["name"] = name + orderItem["display"] = dsname + orderItem["revision"] = ver + orderItem["description"] = descr + orderItem["company"] = company_name + orderItem["company_display"] = vendor + orderItem["author"] = args.author + + contributor = OrderedDict() + + contributor['group'] = vendor + contributor["url"] = args.company_url + contributors = [contributor] + + orderItem["contributors"] = contributors + orderItem["category"] = category + orderItem["website"] = url + orderItem["search-keywords"] = search_keywords + + item = OrderedDict() + item["infra"] = orderItem + + orderItems = [item] + config['items'] = orderItems + + data['config'] = config + data["_major"] = 1 + data["_minor"] = 0 + + try: + outfile = open(args.output_file,'w') + except IOError: + print ('cannot open', args.output_file) + else: + json.dump(data, outfile,indent = 2) + outfile.close() + +def parse_cmdline(): + + parser = argparse.ArgumentParser(description='Utility python script', + epilog="Utility script to create xitem.json from board.xml .") + parser.add_argument('--board_file', help="Path of the board.xml file", required = True) + parser.add_argument('--author', help="Author of the board ", required = True) + parser.add_argument('--category', help="category the board belongs to.(Single part/ Multi part,...) ", required = False) + parser.add_argument('--company_display_name', help="Comapny of the board", required = True, default = "") + parser.add_argument('--company_url', help="Comapny URL ", required = True,default = "") + parser.add_argument('--output_file', help="Refers to the outputfile, default: xitem.json ", required = False, default = "xitem.json") + return parser + +def main(): + parser = parse_cmdline() + args = parser.parse_args() + try : + infile= open(args.board_file,"r") + except IOError: + print ('cannot open', args.board_file) + else: + infile.close() + xmldoc = minidom.parse(args.board_file) + createXitemJson(xmldoc,args) + +if __name__ == '__main__': main() diff --git a/ascii2hex.sv b/ascii2hex.sv new file mode 100644 index 0000000..6ab3768 --- /dev/null +++ b/ascii2hex.sv @@ -0,0 +1,52 @@ +//------------------------------------------------------------------------------ +// hex2ascii.sv +// published as part of https://github.com/pConst/basic_verilog +// Konstantin Pavlov, pavlovconst@gmail.com +//------------------------------------------------------------------------------ + +// INFO ------------------------------------------------------------------------ +// Converts 8-bit human-readable ASCII char to 4-bit binary nibble +// For example, "F" char becomes 4'b1111, "4" char becomes 4'b0100 +// + + +/* --- INSTANTIATION TEMPLATE BEGIN --- + +ascii2hex AH ( + .ascii( ), + .hex( ) +); + +--- INSTANTIATION TEMPLATE END ---*/ + + +module ascii2hex ( + input [7:0] ascii, + output [3:0] hex +); + + always_comb begin + case( ascii[7:0] ) + 8'd48 : hex[3:0] = 4'h0; + 8'd49 : hex[3:0] = 4'h1; + 8'd50 : hex[3:0] = 4'h2; + 8'd51 : hex[3:0] = 4'h3; + 8'd52 : hex[3:0] = 4'h4; + 8'd53 : hex[3:0] = 4'h5; + 8'd54 : hex[3:0] = 4'h6; + 8'd55 : hex[3:0] = 4'h7; + 8'd56 : hex[3:0] = 4'h8; + 8'd57 : hex[3:0] = 4'h9; + + 8'd65, 8'd97 : hex[3:0] = 4'hA; // lowercase and capital letters + 8'd66, 8'd98 : hex[3:0] = 4'hB; + 8'd67, 8'd99 : hex[3:0] = 4'hC; + 8'd68, 8'd100: hex[3:0] = 4'hD; + 8'd69, 8'd101: hex[3:0] = 4'hE; + 8'd70, 8'd102: hex[3:0] = 4'hF; + + default : hex[3:0] = 4'h0; + endcase + +endmodule + diff --git a/barrel_shifter.sv b/barrel_shifter.sv new file mode 100644 index 0000000..ea2f598 --- /dev/null +++ b/barrel_shifter.sv @@ -0,0 +1,59 @@ +//------------------------------------------------------------------------------ +// barrel_shifter.sv +// Konstantin Pavlov, pavlovconst@gmail.com +//------------------------------------------------------------------------------ + +// INFO ------------------------------------------------------------------------- +// Barrel shifter written in System Verilog +// + +/* --- INSTANTIATION TEMPLATE BEGIN --- + +barrel_shifter #( + .DATA_W( 32 ) +) bs_inst ( + .clk( clk ), + .nrst( nrst,), + .ena( 1'b1 ), + .l_nr( 1'b1 ), + .dst( ), + + .id( id[31:0] ), + .od( od[31:0] ) +); + +--- INSTANTIATION TEMPLATE END ---*/ + + +module barrel_shifter #( parameter + DATA_W = 32, + DIST_W = $clog2(DATA_W) +)( + input clk, // clock + input nrst, // negative reset + input ena, // enable + input l_nr, // shift left or right + input [DIST_W-1:0] dst, // shift distance in bits + + input [DATA_W-1:0] id, // input data vector + output logic [DATA_W-1:0] od = '0 // shifted data vector +); + + always_ff @(posedge clk) begin + if( ~nrst ) begin + od[DATA_W-1:0] <= '0; + end else begin + if( ena ) begin + + if( l_nr ) begin + od[DATA_W-1:0] <= ({2{id[DATA_W-1:0]}} << dst[DIST_W-1:0]) >> DATA_W; + end else begin + od[DATA_W-1:0] <= {2{id[DATA_W-1:0]}} >> dst[DIST_W-1:0]; + end // if l_nr + + end // if ena + end // nrst + end + +endmodule + diff --git a/benchmark_projects/benchmark_results.txt b/benchmark_projects/benchmark_results.txt index 9a91ccd..83e4ec3 100644 --- a/benchmark_projects/benchmark_results.txt +++ b/benchmark_projects/benchmark_results.txt @@ -1,10 +1,11 @@ +// published as part of https://github.com/pConst/basic_verilog +// Konstantin Pavlov, pavlovconst@gmail.com Compilation time results for reference benchmark projects ========================================================= - Xeon E5-2630 v4, RAM 32GB, Windows 7 ------------------------------------ quartus_benchmark - 4m 58s ( Quartus Lite 17 ) @@ -13,7 +14,6 @@ gowin_benchmark - 4m 15s ( Gowin_V1.9.6Beta ) ise_benchmark - 9m 10s ( ISE 12.4 ) - Xeon E5-2630 v4, RAM 32GB, Windows 7, project files on RamDisk ------------------------------------- @@ -21,10 +21,38 @@ quartus_benchmark - 4m 57s ( Quartus Lite 17 ) vivado_benchmark - 5m 56s ( Vivado 2019.2 ) - Xeon E5-2630 v4, RAM 32GB, Windows 7, project files on RamDisk, HyperThreading OFF ------------------------------------- quartus_benchmark - 4m 50s ( Quartus Lite 17 ) vivado_benchmark - 5m 43s ( Vivado 2019.2 ) + + +AMD Ryzen 7 5700G, RAM 64GB, Xubuntu 22.04.1 +HyperThreading OFF +------------------------------------ +quartus_benchmark - 1m 58s ( Quartus Lite 20.1.1 ) +vivado_benchmark - 4m 07s ( Vivado 2021.2 ) +vivado_benchmark - 4m 05s ( Vivado 2022.1 ) + + +Intel i7 13700K, RAM 128GB, Windows 10 +------------------------------------ +quartus_benchmark - 2m 34s ( Quartus Lite 20.1.1 ) +vivado_benchmark - 3m 47s ( Vivado 2022.1 ) + + +AMD Ryzen 9 7900X, DDR5 2x32GB 5200 МГц, MB B650, NMVe (1000 ГБ SSD M.2 Samsung 970 EVO Plus) +------------------------------------ +vivado_benchmark - 1m 39s ( Vivado 2023.1.2 ) - by dxp from electronix.ru forum + +Intel Xeon W-2145, DDR4 32GB, Platform: LENOVO ThinStation P520 +------------------------------------ +vivado_benchmark - 6m 38s ( Vivado 2021.1 ) - by dtmf73 from electronix.ru forum + +Laptop Core i7-8750H CPU @ 2.20GHz, 32GB RAM, SSD Samsung 990, Windows 10 +------------------------------------ +quartus_benchmark - 4m 01s ( Quartus Lite 20.1.0 ) +vivado_benchmark - 5m 18s ( Vivado 2023.2 ) +gowin_benchmark - 3m 01s ( Gowin_V1.9.9 ) diff --git a/bin2gray.sv b/bin2gray.sv index f17e671..0b42790 100644 --- a/bin2gray.sv +++ b/bin2gray.sv @@ -1,5 +1,6 @@ //------------------------------------------------------------------------------ // bin2gray.sv +// published as part of https://github.com/pConst/basic_verilog // Konstantin Pavlov, pavlovconst@gmail.com //------------------------------------------------------------------------------ @@ -26,9 +27,9 @@ module bin2gray #( parameter output logic[WIDTH-1:0] gray_out ); -always_comb begin - gray_out[WIDTH-1:0] = bin_in[WIDTH-1:0]^(bin_in[WIDTH-1:0]>>1); -end + always_comb begin + gray_out[WIDTH-1:0] = bin_in[WIDTH-1:0] ^ ( bin_in[WIDTH-1:0] >> 1 ); + end endmodule diff --git a/clogb2.svh b/clogb2.svh index 5c7336e..df7303a 100755 --- a/clogb2.svh +++ b/clogb2.svh @@ -5,7 +5,42 @@ //------------------------------------------------------------------------------ // INFO ------------------------------------------------------------------------ -// Calculates counter/address width based on specified vector/RAM depth +// Calculates counter width based on specified vector/RAM depth +// see also: http://www.sunburst-design.com/papers/CummingsHDLCON2001_Verilog2001.pdf +// +// WARNING: +// ======== +// - clogb2() usage is a quite obsolete technique, left from Verilog-2001 era +// when system function $clog2() was not supported or was implemented falcely +// +// - don`t use clogb2() for new designs! Instead: +// +// - use $clog2(DEPTH) when declaring wr_addr[] pointer, which can refer any +// RAM element from 0 to DEPTH-1 +// +// - use $clog2(DEPTH+1) to declare counters, which should hold any walue from +// 0 up to the DEPTH (inclusive) +// +// +// Compared with system function $clog2(): +// ======================================= +// $clog2(0) = 0; clogb2(0) = 0; +// $clog2(1) = 0; clogb2(1) = 1; +// $clog2(2) = 1; clogb2(2) = 2; +// $clog2(3) = 2; clogb2(3) = 2; +// $clog2(4) = 2; clogb2(4) = 3; +// $clog2(5) = 3; clogb2(5) = 3; +// $clog2(6) = 3; clogb2(6) = 3; +// $clog2(7) = 3; clogb2(7) = 3; +// $clog2(8) = 3; clogb2(8) = 4; +// $clog2(9) = 4; clogb2(9) = 4; +// $clog2(10)= 4; clogb2(10)= 4; +// $clog2(11)= 4; clogb2(11)= 4; +// $clog2(12)= 4; clogb2(12)= 4; +// $clog2(13)= 4; clogb2(13)= 4; +// $clog2(14)= 4; clogb2(14)= 4; +// $clog2(15)= 4; clogb2(15)= 4; +// $clog2(16)= 4; clogb2(16)= 5; // // Function should be instantiated inside a module // But you are free to call it from anywhere by its hierarchical name @@ -15,10 +50,11 @@ // function integer clogb2; - input integer depth; + input [31:0] depth; for( clogb2=0; depth>0; clogb2=clogb2+1 ) begin depth = depth >> 1; end + endfunction diff --git a/comb_repeater.sv b/comb_repeater.sv new file mode 100644 index 0000000..385c3d5 --- /dev/null +++ b/comb_repeater.sv @@ -0,0 +1,64 @@ +//------------------------------------------------------------------------------ +// comb_repeater.sv +// Konstantin Pavlov, pavlovconst@gmail.com +//------------------------------------------------------------------------------ + +// INFO ------------------------------------------------------------------------ +// Combinational signal repeater +// +// Every stage consists of two sequential inverters +// Configurable number of stages +// +// Adapted for AMD/Xilinx devices +// + + +/* --- INSTANTIATION TEMPLATE BEGIN --- + +comb_repeater #( + .LENGTH( 2 ), + .WIDTH( 1 ) +) R1 ( + .in( ), + .out( ) +); + +--- INSTANTIATION TEMPLATE END ---*/ + + +module comb_repeater #( parameter + LENGTH = 1, // repeater chain length + WIDTH = 1 // repeater bus width +)( + input [WIDTH-1:0] in, + output logic [WIDTH-1:0] out +); + + + (* DONT_TOUCH = "TRUE" *) logic [LENGTH-1:0][WIDTH-1:0] s1; // first inverter outputs + (* DONT_TOUCH = "TRUE" *) logic [LENGTH-1:0][WIDTH-1:0] s2; // second inverter outputs + + genvar i; + generate + for( i=0; i0; i=i-1 ) begin + data[i+1][WIDTH-1:0] <= data[i][WIDTH-1:0]; + end + data[1][WIDTH-1:0] <= in[WIDTH-1:0]; + end + end + + assign out[WIDTH-1:0] = data[LENGTH][WIDTH-1:0]; + +endmodule + diff --git a/delayed_event.sv b/delayed_event.sv index ce7c15e..f174316 100644 --- a/delayed_event.sv +++ b/delayed_event.sv @@ -1,14 +1,19 @@ //------------------------------------------------------------------------------ // delayed_event.sv +// published as part of https://github.com/pConst/basic_verilog // Konstantin Pavlov, pavlovconst@gmail.com //------------------------------------------------------------------------------ // INFO ------------------------------------------------------------------------ // Module generates delayed pulse one clock width -// Could be useful for initialization or sequencing some tasks -// Could be easily daisy-chained by connecting "after_event" outputs -// to the subsequent "ena" inputs // +// - Could be useful for initialization or sequencing some tasks +// - Could be easily daisy-chained by connecting "after_event" outputs +// to the subsequent "ena" inputs +// - Only one event can be triggered after every reset +// - Delay operation could be suspended by setting ena to 0 at any time + + // | // |___,___, ,___,___,___,___,___,___,___,___,___,___,___, // | , |___| , , , , , , , , , , , nrst @@ -43,8 +48,7 @@ delayed_event #( --- INSTANTIATION TEMPLATE END ---*/ module delayed_event #( parameter - DELAY = 32, - CNTR_WIDTH = $clog2(DELAY) + DELAY = 32 )( input clk, // system clock input nrst, // negative reset @@ -56,31 +60,87 @@ module delayed_event #( parameter ); -logic [CNTR_WIDTH-1:0] seq_cntr = CNTR_WIDTH'(DELAY); - -logic seq_cntr_is_0; -assign seq_cntr_is_0 = (seq_cntr[CNTR_WIDTH-1:0]=='0); + localparam CNTR_W = $clog2(DELAY+1); + + generate + //========================================================================== + if ( DELAY == 0 ) begin + + logic ena_rise; + edge_detect event_edge ( + .clk( clk ), + .anrst( nrst ), + .in( ena ), + .rising( ena_rise ) + ); + + assign on_event = ena_rise; + assign before_event = 1'b0; + assign after_event = 1'b1; + + //========================================================================== + end else if ( DELAY == 1 ) begin + + logic ena_d1 = 1'b0; + always_ff @(posedge clk) begin + if( ~nrst ) begin + ena_d1 <= 1'b0; + end else begin + ena_d1 <= ena; + end + end + + logic ena_rise; + edge_detect event_edge ( + .clk( clk ), + .anrst( nrst ), + .in( ena_d1 ), + .rising( ena_rise ) + ); + + logic got_ena = 1'b0; + always_ff @(posedge clk) begin + if( ~nrst ) begin + got_ena <= 1'b0; + end if( on_event ) begin + got_ena <= 1'b1; + end + end + + assign on_event = ena_rise; + assign before_event = !got_ena && !ena_rise; + assign after_event = got_ena || ena_rise; + + //========================================================================== + end else begin + + logic [CNTR_W-1:0] seq_cntr = CNTR_W'(DELAY); + + logic seq_cntr_is_0; + assign seq_cntr_is_0 = (seq_cntr[CNTR_W-1:0]=='0); + + always_ff @(posedge clk) begin + if( ~nrst) begin + seq_cntr[CNTR_W-1:0] <= CNTR_W'(DELAY); + end else begin + if( ena && ~seq_cntr_is_0 ) begin + seq_cntr[CNTR_W-1:0] <= seq_cntr[CNTR_W-1:0] - 1'b1; + end + end // nrst + end + + edge_detect event_edge ( + .clk( clk ), + .anrst( 1'b1 ), + .in( seq_cntr_is_0 ), + .rising( on_event ) + ); + + assign before_event = ~seq_cntr_is_0; + assign after_event = seq_cntr_is_0; -always_ff @(posedge clk) begin - if( ~nrst) begin - seq_cntr[CNTR_WIDTH-1:0] <= DELAY; - end else begin - if( ena && ~seq_cntr_is_0 ) begin - seq_cntr[CNTR_WIDTH-1:0] <= seq_cntr[CNTR_WIDTH-1:0] - 1'b1; end - end // nrst -end - -edge_detect cntr_edge ( - .clk( clk ), - .nrst( 1'b1 ), - .in( seq_cntr_is_0 ), - .rising( on_event ) -); - -assign before_event = ~seq_cntr_is_0; -assign after_event = seq_cntr_is_0; - + endgenerate endmodule diff --git a/delayed_event_tb.sv b/delayed_event_tb.sv new file mode 100644 index 0000000..310725a --- /dev/null +++ b/delayed_event_tb.sv @@ -0,0 +1,187 @@ +//------------------------------------------------------------------------------ +// delayed_event_tb.sv +// published as part of https://github.com/pConst/basic_verilog +// Konstantin Pavlov, pavlovconst@gmail.com +//------------------------------------------------------------------------------ + +// INFO ------------------------------------------------------------------------ +// Testbench for delayed_event.sv + +// use this define to make some things differently in simulation +`define SIMULATION yes + +`timescale 1ns / 1ps + +module delayed_event_tb(); + +initial begin + // Print out time markers in nanoseconds + // Example: $display("[T=%0t] start=%d", $realtime, start); + $timeformat(-9, 3, " ns"); + + // seed value setting is intentionally manual to achieve repeatability between sim runs + $urandom( 1 ); // SEED value +end + +logic clk200; +sim_clk_gen #( + .FREQ( 200_000_000 ), // in Hz + .PHASE( 0 ), // in degrees + .DUTY( 50 ), // in percentage + .DISTORT( 10 ) // in picoseconds +) clk200_gen ( + .ena( 1'b1 ), + .clk( clk200 ), + .clkd( ) +); + +logic nrst_once; + +logic [31:0] clk200_div; +clk_divider #( + .WIDTH( 32 ) +) cd1 ( + .clk( clk200 ), + .nrst( nrst_once ), + .ena( 1'b1 ), + .out( clk200_div[31:0] ) +); + +logic [31:0] clk200_div_rise; +edge_detect ed1[31:0] ( + .clk( {32{clk200}} ), + .anrst( {32{nrst_once}} ), + .in( clk200_div[31:0] ), + .rising( clk200_div_rise[31:0] ), + .falling( ), + .both( ) +); + +// external device "asynchronous" clock +logic clk33; +logic clk33d; +sim_clk_gen #( + .FREQ( 200_000_000 ), // in Hz + .PHASE( 0 ), // in degrees + .DUTY( 50 ), // in percentage + .DISTORT( 1000 ) // in picoseconds +) clk33_gen ( + .ena( 1'b1 ), + .clk( clk33 ), + .clkd( clk33d ) +); + + +logic rst; +initial begin + rst = 1'b0; // initialization + repeat( 1 ) @(posedge clk200); + + forever begin + repeat( 1 ) @(posedge clk200); // synchronous rise + rst = 1'b1; + //$urandom( 1 ); // uncomment to get the same random pattern EVERY nrst + + repeat( 2 ) @(posedge clk200); // synchronous fall, controls rst pulse width + rst = 1'b0; + + repeat( 100 ) @(posedge clk200); // controls test body width + end +end +logic nrst; +assign nrst = ~rst; + + +logic rst_once; +initial begin + rst_once = 1'b0; // initialization + repeat( 1 ) @(posedge clk200); + + repeat( 1 ) @(posedge clk200); // synchronous rise + rst_once = 1'b1; + + repeat( 2 ) @(posedge clk200); // synchronous fall, controls rst_once pulse width + rst_once = 1'b0; +end +//logic nrst_once; // declared before +assign nrst_once = ~rst_once; + + +// random pattern generation +logic [31:0] rnd_data; +always_ff @(posedge clk200) begin + rnd_data[31:0] <= $urandom; + end + +initial forever begin + @(posedge nrst); + $display("[T=%0t] rnd_data[]=%h", $realtime, rnd_data[31:0]); +end + + +// helper start strobe appears unpredictable up to 20 clocks after nrst +logic start; +initial forever begin + start = 1'b0; // initialization + + @(posedge nrst); // synchronous rise after EVERY nrst + repeat( $urandom_range(0, 20) ) @(posedge clk200); + start = 1'b1; + + @(posedge clk200); // synchronous fall exactly 1 clock after rise + start = 1'b0; +end + + +initial begin +// #10000 $stop; +// #10000 $finish; +end + +// sweeping pulses +logic sp = 1'b1; +logic [4:0] sp_duty_cycle = 8'd0; +initial forever begin + if( sp_duty_cycle[4:0] == 0 ) begin + sp = 1'b1; + repeat( 10 ) @(posedge clk200); + end + sp = 1'b0; + repeat( 1 ) @(posedge clk200); + sp = 1'b1; + repeat( 1 ) @(posedge clk200); + sp = 1'b0; + repeat( sp_duty_cycle ) @(posedge clk200); + sp_duty_cycle[4:0] = sp_duty_cycle[4:0] + 1'b1; // overflow is expected here +end + + +// Module under test =========================================================== + +logic sp_d1; +always_ff @(posedge clk200) begin + if( sp ) begin + sp_d1 <= 1'b0; + end else begin + sp_d1 <= 1'b1; + end +end + + +for(genvar i=0; i<16; i++) begin + + delayed_event #( + .DELAY( i ) + ) de ( + .clk( clk200 ), + .nrst( ~sp ), //|rnd_data[2:0] ), + .ena( 1'b1 ), //sp_d1 ), + + .on_event( ), + .before_event( ), + .after_event( ) + ); +end + +endmodule + diff --git a/dual_port_ram_templates/byte_enabled_true_dual_port_ram.v b/dual_port_ram_templates/byte_enabled_true_dual_port_ram.v deleted file mode 100755 index f5a5fc5..0000000 --- a/dual_port_ram_templates/byte_enabled_true_dual_port_ram.v +++ /dev/null @@ -1,65 +0,0 @@ -// Quartus Prime SystemVerilog Template -// -// True Dual-Port RAM with different read/write addresses and single read/write clock -// and with a control for writing single bytes into the memory word; byte enable - -// Read during write produces old data on ports A and B and old data on mixed ports -// For device families that do not support this mode (e.g. Stratix V) the ram is not inferred - -module byte_enabled_true_dual_port_ram - #( - parameter int - BYTE_WIDTH = 8, - ADDRESS_WIDTH = 6, - BYTES = 4, - DATA_WIDTH_R = BYTE_WIDTH * BYTES -) -( - input [ADDRESS_WIDTH-1:0] addr1, - input [ADDRESS_WIDTH-1:0] addr2, - input [BYTES-1:0] be1, - input [BYTES-1:0] be2, - input [BYTE_WIDTH-1:0] data_in1, - input [BYTE_WIDTH-1:0] data_in2, - input we1, we2, clk, - output [DATA_WIDTH_R-1:0] data_out1, - output [DATA_WIDTH_R-1:0] data_out2); - localparam RAM_DEPTH = 1 << ADDRESS_WIDTH; - - // model the RAM with two dimensional packed array - logic [BYTES-1:0][BYTE_WIDTH-1:0] ram[0:RAM_DEPTH-1]; - - reg [DATA_WIDTH_R-1:0] data_reg1; - reg [DATA_WIDTH_R-1:0] data_reg2; - - // port A - always@(posedge clk) - begin - if(we1) begin - // edit this code if using other than four bytes per word - if(be1[0]) ram[addr1][0] <= data_in1; - if(be1[1]) ram[addr1][1] <= data_in1; - if(be1[2]) ram[addr1][2] <= data_in1; - if(be1[3]) ram[addr1][3] <= data_in1; - end - data_reg1 <= ram[addr1]; - end - - assign data_out1 = data_reg1; - - // port B - always@(posedge clk) - begin - if(we2) begin - // edit this code if using other than four bytes per word - if(be2[0]) ram[addr2][0] <= data_in2; - if(be2[1]) ram[addr2][1] <= data_in2; - if(be2[2]) ram[addr2][2] <= data_in2; - if(be2[3]) ram[addr2][3] <= data_in2; - end - data_reg2 <= ram[addr2]; - end - - assign data_out2 = data_reg2; - -endmodule : byte_enabled_true_dual_port_ram diff --git a/dual_port_ram_templates/true_dual_port_ram_dual_clock.v b/dual_port_ram_templates/true_dual_port_ram_dual_clock.v deleted file mode 100755 index 3e62d50..0000000 --- a/dual_port_ram_templates/true_dual_port_ram_dual_clock.v +++ /dev/null @@ -1,44 +0,0 @@ -// Quartus Prime Verilog Template -// True Dual Port RAM with dual clocks - -module true_dual_port_ram_dual_clock -#(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=6) -( - input [(DATA_WIDTH-1):0] data_a, data_b, - input [(ADDR_WIDTH-1):0] addr_a, addr_b, - input we_a, we_b, clk_a, clk_b, - output reg [(DATA_WIDTH-1):0] q_a, q_b -); - - // Declare the RAM variable - reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0]; - - always @ (posedge clk_a) - begin - // Port A - if (we_a) - begin - ram[addr_a] <= data_a; - q_a <= data_a; - end - else - begin - q_a <= ram[addr_a]; - end - end - - always @ (posedge clk_b) - begin - // Port B - if (we_b) - begin - ram[addr_b] <= data_b; - q_b <= data_b; - end - else - begin - q_b <= ram[addr_b]; - end - end - -endmodule \ No newline at end of file diff --git a/dual_port_single_port_ram_templates/SystemVerilog/byte_enabled_simple_dual_port_ram.sv b/dual_port_single_port_ram_templates/SystemVerilog/byte_enabled_simple_dual_port_ram.sv new file mode 100644 index 0000000..a1d22ec --- /dev/null +++ b/dual_port_single_port_ram_templates/SystemVerilog/byte_enabled_simple_dual_port_ram.sv @@ -0,0 +1,37 @@ +// Quartus Prime SystemVerilog Template +// +// Simple Dual-Port RAM with different read/write addresses and single read/write clock +// and with a control for writing single bytes into the memory word; byte enable + +module byte_enabled_simple_dual_port_ram + #(parameter int + ADDR_WIDTH = 6, + BYTE_WIDTH = 8, + BYTES = 4, + WIDTH = BYTES * BYTE_WIDTH +) +( + input [ADDR_WIDTH-1:0] waddr, + input [ADDR_WIDTH-1:0] raddr, + input [BYTES-1:0] be, + input [BYTE_WIDTH-1:0] wdata, + input we, clk, + output reg [WIDTH - 1:0] q +); + localparam int WORDS = 1 << ADDR_WIDTH ; + + // use a multi-dimensional packed array to model individual bytes within the word + logic [BYTES-1:0][BYTE_WIDTH-1:0] ram[0:WORDS-1]; + + always_ff@(posedge clk) + begin + if(we) begin + // edit this code if using other than four bytes per word + if(be[0]) ram[waddr][0] <= wdata; + if(be[1]) ram[waddr][1] <= wdata; + if(be[2]) ram[waddr][2] <= wdata; + if(be[3]) ram[waddr][3] <= wdata; + end + q <= ram[raddr]; + end +endmodule : byte_enabled_simple_dual_port_ram diff --git a/dual_port_single_port_ram_templates/SystemVerilog/byte_enabled_true_dual_port_ram.sv b/dual_port_single_port_ram_templates/SystemVerilog/byte_enabled_true_dual_port_ram.sv new file mode 100644 index 0000000..338b2de --- /dev/null +++ b/dual_port_single_port_ram_templates/SystemVerilog/byte_enabled_true_dual_port_ram.sv @@ -0,0 +1,65 @@ +// Quartus Prime SystemVerilog Template +// +// True Dual-Port RAM with different read/write addresses and single read/write clock +// and with a control for writing single bytes into the memory word; byte enable + +// Read during write produces old data on ports A and B and old data on mixed ports +// For device families that do not support this mode (e.g. Stratix V) the ram is not inferred + +module byte_enabled_true_dual_port_ram + #( + parameter int + BYTE_WIDTH = 8, + ADDRESS_WIDTH = 6, + BYTES = 4, + DATA_WIDTH_R = BYTE_WIDTH * BYTES +) +( + input [ADDRESS_WIDTH-1:0] addr1, + input [ADDRESS_WIDTH-1:0] addr2, + input [BYTES-1:0] be1, + input [BYTES-1:0] be2, + input [BYTE_WIDTH-1:0] data_in1, + input [BYTE_WIDTH-1:0] data_in2, + input we1, we2, clk, + output [DATA_WIDTH_R-1:0] data_out1, + output [DATA_WIDTH_R-1:0] data_out2); + localparam RAM_DEPTH = 1 << ADDRESS_WIDTH; + + // model the RAM with two dimensional packed array + logic [BYTES-1:0][BYTE_WIDTH-1:0] ram[0:RAM_DEPTH-1]; + + reg [DATA_WIDTH_R-1:0] data_reg1; + reg [DATA_WIDTH_R-1:0] data_reg2; + + // port A + always@(posedge clk) + begin + if(we1) begin + // edit this code if using other than four bytes per word + if(be1[0]) ram[addr1][0] <= data_in1; + if(be1[1]) ram[addr1][1] <= data_in1; + if(be1[2]) ram[addr1][2] <= data_in1; + if(be1[3]) ram[addr1][3] <= data_in1; + end + data_reg1 <= ram[addr1]; + end + + assign data_out1 = data_reg1; + + // port B + always@(posedge clk) + begin + if(we2) begin + // edit this code if using other than four bytes per word + if(be2[0]) ram[addr2][0] <= data_in2; + if(be2[1]) ram[addr2][1] <= data_in2; + if(be2[2]) ram[addr2][2] <= data_in2; + if(be2[3]) ram[addr2][3] <= data_in2; + end + data_reg2 <= ram[addr2]; + end + + assign data_out2 = data_reg2; + +endmodule : byte_enabled_true_dual_port_ram diff --git a/dual_port_single_port_ram_templates/SystemVerilog/mixed_width_ram.sv b/dual_port_single_port_ram_templates/SystemVerilog/mixed_width_ram.sv new file mode 100644 index 0000000..3d08f9b --- /dev/null +++ b/dual_port_single_port_ram_templates/SystemVerilog/mixed_width_ram.sv @@ -0,0 +1,47 @@ +// Quartus Prime SystemVerilog Template +// +// Mixed-width RAM with separate read and write addresses and data widths +// that are controlled by the parameters RW and WW. RW and WW must specify a +// read/write ratio supported by the memory blocks in your target device. +// Otherwise, Quartus Prime will not infer a RAM. + +module mixed_width_ram + #(parameter int + WORDS = 256, + RW = 8, + WW = 32) +( + input we, + input clk, + input [$clog2((RW < WW) ? WORDS : (WORDS * RW)/WW) - 1 : 0] waddr, + input [WW-1:0] wdata, + input [$clog2((RW < WW) ? (WORDS * WW)/RW : WORDS) - 1 : 0] raddr, + output logic [RW-1:0] q +); + + // Use a multi-dimensional packed array to model the different read/write + // width + localparam int R = (RW < WW) ? WW/RW : RW/WW; + localparam int B = (RW < WW) ? RW: WW; + + logic [R-1:0][B-1:0] ram[0:WORDS-1]; + + generate if(RW < WW) begin + // Smaller read? + always_ff@(posedge clk) + begin + if(we) ram[waddr] <= wdata; + q <= ram[raddr / R][raddr % R]; + end + end + else begin + // Smaller write? + always_ff@(posedge clk) + begin + if(we) ram[waddr / R][waddr % R] <= wdata; + q <= ram[raddr]; + end + end + endgenerate + +endmodule : mixed_width_ram \ No newline at end of file diff --git a/dual_port_single_port_ram_templates/SystemVerilog/mixed_width_true_dual_port_ram.sv b/dual_port_single_port_ram_templates/SystemVerilog/mixed_width_true_dual_port_ram.sv new file mode 100644 index 0000000..8fac163 --- /dev/null +++ b/dual_port_single_port_ram_templates/SystemVerilog/mixed_width_true_dual_port_ram.sv @@ -0,0 +1,57 @@ +// Quartus Prime SystemVerilog Template +// +// True Dual-Port RAM with single clock and different data width on the two ports +// +// The first datawidth and the widths of the addresses are specified +// The second data width is equal to DATA_WIDTH1 * RATIO, where RATIO = (1 << (ADDRESS_WIDTH1 - ADDRESS_WIDTH2) +// RATIO must have value that is supported by the memory blocks in your target +// device. Otherwise, no RAM will be inferred. +// +// Read-during-write behavior returns old data for all combinations of read and +// write on both ports +// +// This style of RAM cannot be used on certain devices, e.g. Stratix V; in that case use the template for Dual-Port RAM with new data on read-during write on the same port + +module mixed_width_true_dual_port_ram + #(parameter int + DATA_WIDTH1 = 8, + ADDRESS_WIDTH1 = 10, + ADDRESS_WIDTH2 = 8) +( + input [ADDRESS_WIDTH1-1:0] addr1, + input [ADDRESS_WIDTH2-1:0] addr2, + input [DATA_WIDTH1 -1:0] data_in1, + input [DATA_WIDTH1*(1<<(ADDRESS_WIDTH1 - ADDRESS_WIDTH2))-1:0] data_in2, + input we1, we2, clk, + output reg [DATA_WIDTH1-1 :0] data_out1, + output reg [DATA_WIDTH1*(1<<(ADDRESS_WIDTH1 - ADDRESS_WIDTH2))-1:0] data_out2); + + localparam RATIO = 1 << (ADDRESS_WIDTH1 - ADDRESS_WIDTH2); // valid values are 2,4,8... family dependent + localparam DATA_WIDTH2 = DATA_WIDTH1 * RATIO; + localparam RAM_DEPTH = 1 << ADDRESS_WIDTH2; + + // Use a multi-dimensional packed array to model the different read/ram width + reg [RATIO-1:0] [DATA_WIDTH1-1:0] ram[0:RAM_DEPTH-1]; + + reg [DATA_WIDTH1-1:0] data_reg1; + reg [DATA_WIDTH2-1:0] data_reg2; + + // Port A + always@(posedge clk) + begin + if(we1) + ram[addr1 / RATIO][addr1 % RATIO] <= data_in1; + data_reg1 <= ram[addr1 / RATIO][addr1 % RATIO]; + end + assign data_out1 = data_reg1; + + // port B + always@(posedge clk) + begin + if(we2) + ram[addr2] <= data_in2; + data_reg2 <= ram[addr2]; + end + + assign data_out2 = data_reg2; +endmodule : mixed_width_true_dual_port_ram \ No newline at end of file diff --git a/dual_port_single_port_ram_templates/SystemVerilog/mixed_width_true_dual_port_ram_new_rw.sv b/dual_port_single_port_ram_templates/SystemVerilog/mixed_width_true_dual_port_ram_new_rw.sv new file mode 100644 index 0000000..5ee9547 --- /dev/null +++ b/dual_port_single_port_ram_templates/SystemVerilog/mixed_width_true_dual_port_ram_new_rw.sv @@ -0,0 +1,68 @@ +// Quartus Prime SystemVerilog Template +// +// True Dual-Port RAM with single clock and different data width on the two ports and width new data on read during write on same port +// +// The first datawidth and the widths of the addresses are specified +// The second data width is equal to DATA_WIDTH1 * RATIO, where RATIO = (1 << (ADDRESS_WIDTH1 - ADDRESS_WIDTH2) +// RATIO must have value that is supported by the memory blocks in your target +// device. Otherwise, no RAM will be inferred. +// +// Read-during-write behavior returns old data for mixed ports and the new data on the same port +// +// This style of RAM can be used on certain devices, e.g. Stratix V, which do not support old data for read during write on same port + +module mixed_width_true_dual_port_ram_new_rw + #(parameter int + DATA_WIDTH1 = 8, + ADDRESS_WIDTH1 = 10, + ADDRESS_WIDTH2 = 8) +( + input [ADDRESS_WIDTH1-1:0] addr1, + input [ADDRESS_WIDTH2-1:0] addr2, + input [DATA_WIDTH1 -1:0] data_in1, + input [DATA_WIDTH1*(1<<(ADDRESS_WIDTH1 - ADDRESS_WIDTH2))-1:0] data_in2, + input we1, we2, clk, + output reg [DATA_WIDTH1-1 :0] data_out1, + output reg [DATA_WIDTH1*(1<<(ADDRESS_WIDTH1 - ADDRESS_WIDTH2))-1:0] data_out2); + + localparam RATIO = 1 << (ADDRESS_WIDTH1 - ADDRESS_WIDTH2); // valid values are 2,4,8... family dependent + localparam DATA_WIDTH2 = DATA_WIDTH1 * RATIO; + localparam RAM_DEPTH = 1 << ADDRESS_WIDTH2; + + // Use a multi-dimensional packed array to model the different read/ram width + reg [RATIO-1:0] [DATA_WIDTH1-1:0] ram[0:RAM_DEPTH-1]; + + reg [DATA_WIDTH1-1:0] data_reg1; + reg [DATA_WIDTH2-1:0] data_reg2; + + // Port A + always@(posedge clk) + begin + if(we1) + begin + ram[addr1 / RATIO][addr1 % RATIO] <= data_in1; + data_reg1 <= data_in1; + end + else + begin + data_reg1 <= ram[addr1 / RATIO][addr1 % RATIO]; + end + end + assign data_out1 = data_reg1; + + // port B + always@(posedge clk) + begin + if(we2) + begin + ram[addr2] <= data_in2; + data_reg2 <= data_in2; + end + else + begin + data_reg2 <= ram[addr2]; + end + end + + assign data_out2 = data_reg2; +endmodule : mixed_width_true_dual_port_ram_new_rw diff --git a/dual_port_single_port_ram_templates/Verilog/dual_port_rom.v b/dual_port_single_port_ram_templates/Verilog/dual_port_rom.v new file mode 100644 index 0000000..cc8287c --- /dev/null +++ b/dual_port_single_port_ram_templates/Verilog/dual_port_rom.v @@ -0,0 +1,32 @@ +// Quartus Prime Verilog Template +// Dual Port ROM + +module dual_port_rom +#(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=8) +( + input [(ADDR_WIDTH-1):0] addr_a, addr_b, + input clk, + output reg [(DATA_WIDTH-1):0] q_a, q_b +); + + // Declare the ROM variable + reg [DATA_WIDTH-1:0] rom[2**ADDR_WIDTH-1:0]; + + // Initialize the ROM with $readmemb. Put the memory contents + // in the file dual_port_rom_init.txt. Without this file, + // this design will not compile. + // See Verilog LRM 1364-2001 Section 17.2.8 for details on the + // format of this file. + + initial + begin + $readmemb("dual_port_rom_init.txt", rom); + end + + always @ (posedge clk) + begin + q_a <= rom[addr_a]; + q_b <= rom[addr_b]; + end + +endmodule diff --git a/dual_port_single_port_ram_templates/Verilog/simple_dual_port_ram_dual_clock.v b/dual_port_single_port_ram_templates/Verilog/simple_dual_port_ram_dual_clock.v new file mode 100644 index 0000000..e1671bf --- /dev/null +++ b/dual_port_single_port_ram_templates/Verilog/simple_dual_port_ram_dual_clock.v @@ -0,0 +1,30 @@ +// Quartus Prime Verilog Template +// Simple Dual Port RAM with separate read/write addresses and +// separate read/write clocks + +module simple_dual_port_ram_dual_clock +#(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=6) +( + input [(DATA_WIDTH-1):0] data, + input [(ADDR_WIDTH-1):0] read_addr, write_addr, + input we, read_clock, write_clock, + output reg [(DATA_WIDTH-1):0] q +); + + // Declare the RAM variable + reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0]; + + always @ (posedge write_clock) + begin + // Write + if (we) + ram[write_addr] <= data; + end + + always @ (posedge read_clock) + begin + // Read + q <= ram[read_addr]; + end + +endmodule diff --git a/dual_port_single_port_ram_templates/Verilog/simple_dual_port_ram_single_clock.v b/dual_port_single_port_ram_templates/Verilog/simple_dual_port_ram_single_clock.v new file mode 100644 index 0000000..530b09a --- /dev/null +++ b/dual_port_single_port_ram_templates/Verilog/simple_dual_port_ram_single_clock.v @@ -0,0 +1,30 @@ +// Quartus Prime Verilog Template +// Simple Dual Port RAM with separate read/write addresses and +// single read/write clock + +module simple_dual_port_ram_single_clock +#(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=6) +( + input [(DATA_WIDTH-1):0] data, + input [(ADDR_WIDTH-1):0] read_addr, write_addr, + input we, clk, + output reg [(DATA_WIDTH-1):0] q +); + + // Declare the RAM variable + reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0]; + + always @ (posedge clk) + begin + // Write + if (we) + ram[write_addr] <= data; + + // Read (if read_addr == write_addr, return OLD data). To return + // NEW data, use = (blocking write) rather than <= (non-blocking write) + // in the write assignment. NOTE: NEW data may require extra bypass + // logic around the RAM. + q <= ram[read_addr]; + end + +endmodule diff --git a/dual_port_single_port_ram_templates/Verilog/single_port_ram.v b/dual_port_single_port_ram_templates/Verilog/single_port_ram.v new file mode 100644 index 0000000..918fdb4 --- /dev/null +++ b/dual_port_single_port_ram_templates/Verilog/single_port_ram.v @@ -0,0 +1,33 @@ +// Quartus Prime Verilog Template +// Single port RAM with single read/write address + +module single_port_ram +#(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=6) +( + input [(DATA_WIDTH-1):0] data, + input [(ADDR_WIDTH-1):0] addr, + input we, clk, + output [(DATA_WIDTH-1):0] q +); + + // Declare the RAM variable + reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0]; + + // Variable to hold the registered read address + reg [ADDR_WIDTH-1:0] addr_reg; + + always @ (posedge clk) + begin + // Write + if (we) + ram[addr] <= data; + + addr_reg <= addr; + end + + // Continuous assignment implies read returns NEW data. + // This is the natural behavior of the TriMatrix memory + // blocks in Single Port mode. + assign q = ram[addr_reg]; + +endmodule diff --git a/dual_port_single_port_ram_templates/Verilog/single_port_ram_with_init.v b/dual_port_single_port_ram_templates/Verilog/single_port_ram_with_init.v new file mode 100644 index 0000000..1b68f45 --- /dev/null +++ b/dual_port_single_port_ram_templates/Verilog/single_port_ram_with_init.v @@ -0,0 +1,44 @@ +// Quartus Prime Verilog Template +// Single port RAM with single read/write address and initial contents +// specified with an initial block + +module single_port_ram_with_init +#(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=6) +( + input [(DATA_WIDTH-1):0] data, + input [(ADDR_WIDTH-1):0] addr, + input we, clk, + output [(DATA_WIDTH-1):0] q +); + + // Declare the RAM variable + reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0]; + + // Variable to hold the registered read address + reg [ADDR_WIDTH-1:0] addr_reg; + + // Specify the initial contents. You can also use the $readmemb + // system task to initialize the RAM variable from a text file. + // See the $readmemb template page for details. + initial + begin : INIT + integer i; + for(i = 0; i < 2**ADDR_WIDTH; i = i + 1) + ram[i] = {DATA_WIDTH{1'b1}}; + end + + always @ (posedge clk) + begin + // Write + if (we) + ram[addr] <= data; + + addr_reg <= addr; + end + + // Continuous assignment implies read returns NEW data. + // This is the natural behavior of the TriMatrix memory + // blocks in Single Port mode. + assign q = ram[addr_reg]; + +endmodule diff --git a/dual_port_single_port_ram_templates/Verilog/single_port_rom.v b/dual_port_single_port_ram_templates/Verilog/single_port_rom.v new file mode 100644 index 0000000..3d15de1 --- /dev/null +++ b/dual_port_single_port_ram_templates/Verilog/single_port_rom.v @@ -0,0 +1,33 @@ +// Quartus Prime Verilog Template +// Single Port ROM + +module single_port_rom +#(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=8) +( + input [(ADDR_WIDTH-1):0] addr, + input clk, + output reg [(DATA_WIDTH-1):0] q +); + + // Declare the ROM variable + reg [DATA_WIDTH-1:0] rom[2**ADDR_WIDTH-1:0]; + + // Initialize the ROM with $readmemb. Put the memory contents + // in the file single_port_rom_init.txt. Without this file, + // this design will not compile. + + // See Verilog LRM 1364-2001 Section 17.2.8 for details on the + // format of this file, or see the "Using $readmemb and $readmemh" + // template later in this section. + + initial + begin + $readmemb("single_port_rom_init.txt", rom); + end + + always @ (posedge clk) + begin + q <= rom[addr]; + end + +endmodule diff --git a/dual_port_single_port_ram_templates/Verilog/true_dual_port_ram_dual_clock.v b/dual_port_single_port_ram_templates/Verilog/true_dual_port_ram_dual_clock.v new file mode 100644 index 0000000..654d2d8 --- /dev/null +++ b/dual_port_single_port_ram_templates/Verilog/true_dual_port_ram_dual_clock.v @@ -0,0 +1,44 @@ +// Quartus Prime Verilog Template +// True Dual Port RAM with dual clocks + +module true_dual_port_ram_dual_clock +#(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=6) +( + input [(DATA_WIDTH-1):0] data_a, data_b, + input [(ADDR_WIDTH-1):0] addr_a, addr_b, + input we_a, we_b, clk_a, clk_b, + output reg [(DATA_WIDTH-1):0] q_a, q_b +); + + // Declare the RAM variable + reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0]; + + always @ (posedge clk_a) + begin + // Port A + if (we_a) + begin + ram[addr_a] <= data_a; + q_a <= data_a; + end + else + begin + q_a <= ram[addr_a]; + end + end + + always @ (posedge clk_b) + begin + // Port B + if (we_b) + begin + ram[addr_b] <= data_b; + q_b <= data_b; + end + else + begin + q_b <= ram[addr_b]; + end + end + +endmodule diff --git a/dual_port_single_port_ram_templates/Verilog/true_dual_port_ram_single_clock.v b/dual_port_single_port_ram_templates/Verilog/true_dual_port_ram_single_clock.v new file mode 100644 index 0000000..aabfe96 --- /dev/null +++ b/dual_port_single_port_ram_templates/Verilog/true_dual_port_ram_single_clock.v @@ -0,0 +1,44 @@ +// Quartus Prime Verilog Template +// True Dual Port RAM with single clock + +module true_dual_port_ram_single_clock +#(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=6) +( + input [(DATA_WIDTH-1):0] data_a, data_b, + input [(ADDR_WIDTH-1):0] addr_a, addr_b, + input we_a, we_b, clk, + output reg [(DATA_WIDTH-1):0] q_a, q_b +); + + // Declare the RAM variable + reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0]; + + // Port A + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + q_a <= data_a; + end + else + begin + q_a <= ram[addr_a]; + end + end + + // Port B + always @ (posedge clk) + begin + if (we_b) + begin + ram[addr_b] <= data_b; + q_b <= data_b; + end + else + begin + q_b <= ram[addr_b]; + end + end + +endmodule diff --git a/dual_port_ram_templates/xilinx_true_dual_port_read_first_2_clock_ram.v b/dual_port_single_port_ram_templates/xilinx_true_dual_port_read_first_2_clock_ram.v old mode 100755 new mode 100644 similarity index 100% rename from dual_port_ram_templates/xilinx_true_dual_port_read_first_2_clock_ram.v rename to dual_port_single_port_ram_templates/xilinx_true_dual_port_read_first_2_clock_ram.v diff --git a/edge_detect.v b/edge_detect.v new file mode 100644 index 0000000..a409893 --- /dev/null +++ b/edge_detect.v @@ -0,0 +1,62 @@ +//------------------------------------------------------------------------------ +// edge_detect.v +// published as part of https://github.com/pConst/basic_verilog +// Konstantin Pavlov, pavlovconst@gmail.com +//------------------------------------------------------------------------------ + +// INFO ------------------------------------------------------------------------ +// Edge detector, ver.4 +// (simplified Verilog version, see ./edge_detect.sv for advanced features) +// +// In case when "in" port has toggle rate 100% (changes every clock period) +// "rising" and "falling" outputs will completely replicate input +// "both" output will be always active in this case +// + +/* --- INSTANTIATION TEMPLATE BEGIN --- + +edge_detect #( + .WIDTH( 32 ) +) ED1 ( + .clk( clk ), + .anrst( 1'b1 ), + .in( in[31:0] ), + .rising( in_rise[31:0] ), + .falling( ), + .both( ) +); + +--- INSTANTIATION TEMPLATE END ---*/ + + +module edge_detect #( parameter + bit [7:0] WIDTH = 1 +)( + input clk, + input anrst, + + input [WIDTH-1:0] in, + + output [WIDTH-1:0] rising, + output [WIDTH-1:0] falling, + output [WIDTH-1:0] both +); + + // data delay line + reg [WIDTH-1:0] in_d = '0; + always_ff @(posedge clk or negedge anrst) begin + if ( ~anrst ) begin + in_d[WIDTH-1:0] <= '0; + end else begin + in_d[WIDTH-1:0] <= in[WIDTH-1:0]; + end + end + + always @(*) begin + rising[WIDTH-1:0] = {WIDTH{anrst}} & (in[WIDTH-1:0] & ~in_d[WIDTH-1:0]); + falling[WIDTH-1:0] = {WIDTH{anrst}} & (~in[WIDTH-1:0] & in_d[WIDTH-1:0]); + + both[WIDTH-1:0] = rising[WIDTH-1:0] | falling[WIDTH-1:0]; + end + +endmodule diff --git a/encdec_8b10b.v b/encdec_8b10b.v new file mode 100644 index 0000000..ce39dab --- /dev/null +++ b/encdec_8b10b.v @@ -0,0 +1,274 @@ +// Chuck Benz, Hollis, NH Copyright (c)2002 +// +// The information and description contained herein is the +// property of Chuck Benz. +// +// Permission is granted for any reuse of this information +// and description as long as this copyright notice is +// preserved. Modifications may be made as long as this +// notice is preserved. + +// per Widmer and Franaszek + + +module decode_8b10b (datain, dispin, dataout, dispout, code_err, disp_err); + input [9:0] datain; + input dispin; + output [8:0] dataout; + output dispout; + output code_err; + output disp_err; + + wire ai = datain[0]; + wire bi = datain[1]; + wire ci = datain[2]; + wire di = datain[3]; + wire ei = datain[4]; + wire ii = datain[5]; + wire fi = datain[6]; + wire gi = datain[7]; + wire hi = datain[8]; + wire ji = datain[9]; + + wire aeqb = (ai & bi) | (!ai & !bi); + wire ceqd = (ci & di) | (!ci & !di); + wire p22 = (ai & bi & !ci & !di) | + (ci & di & !ai & !bi) | + ( !aeqb & !ceqd); + wire p13 = ( !aeqb & !ci & !di) | + ( !ceqd & !ai & !bi); + wire p31 = ( !aeqb & ci & di) | + ( !ceqd & ai & bi); + + wire p40 = ai & bi & ci & di; + wire p04 = !ai & !bi & !ci & !di; + + wire disp6a = p31 | (p22 & dispin); // pos disp if p22 and was pos, or p31. + wire disp6a2 = p31 & dispin; // disp is ++ after 4 bits + wire disp6a0 = p13 & ! dispin; // -- disp after 4 bits + + wire disp6b = (((ei & ii & ! disp6a0) | (disp6a & (ei | ii)) | disp6a2 | + (ei & ii & di)) & (ei | ii | di)); + + // The 5B/6B decoding special cases where ABCDE != abcde + + wire p22bceeqi = p22 & bi & ci & (ei == ii); + wire p22bncneeqi = p22 & !bi & !ci & (ei == ii); + wire p13in = p13 & !ii; + wire p31i = p31 & ii; + wire p13dei = p13 & di & ei & ii; + wire p22aceeqi = p22 & ai & ci & (ei == ii); + wire p22ancneeqi = p22 & !ai & !ci & (ei == ii); + wire p13en = p13 & !ei; + wire anbnenin = !ai & !bi & !ei & !ii; + wire abei = ai & bi & ei & ii; + wire cdei = ci & di & ei & ii; + wire cndnenin = !ci & !di & !ei & !ii; + + // non-zero disparity cases: + wire p22enin = p22 & !ei & !ii; + wire p22ei = p22 & ei & ii; + //wire p13in = p12 & !ii; + //wire p31i = p31 & ii; + wire p31dnenin = p31 & !di & !ei & !ii; + //wire p13dei = p13 & di & ei & ii; + wire p31e = p31 & ei; + + wire compa = p22bncneeqi | p31i | p13dei | p22ancneeqi | + p13en | abei | cndnenin; + wire compb = p22bceeqi | p31i | p13dei | p22aceeqi | + p13en | abei | cndnenin; + wire compc = p22bceeqi | p31i | p13dei | p22ancneeqi | + p13en | anbnenin | cndnenin; + wire compd = p22bncneeqi | p31i | p13dei | p22aceeqi | + p13en | abei | cndnenin; + wire compe = p22bncneeqi | p13in | p13dei | p22ancneeqi | + p13en | anbnenin | cndnenin; + + wire ao = ai ^ compa; + wire bo = bi ^ compb; + wire co = ci ^ compc; + wire do_ = di ^ compd; + wire eo = ei ^ compe; + + wire feqg = (fi & gi) | (!fi & !gi); + wire heqj = (hi & ji) | (!hi & !ji); + wire fghj22 = (fi & gi & !hi & !ji) | + (!fi & !gi & hi & ji) | + ( !feqg & !heqj); + wire fghjp13 = ( !feqg & !hi & !ji) | + ( !heqj & !fi & !gi); + wire fghjp31 = ( (!feqg) & hi & ji) | + ( !heqj & fi & gi); + + wire dispout = (fghjp31 | (disp6b & fghj22) | (hi & ji)) & (hi | ji); + + wire ko = ( (ci & di & ei & ii) | ( !ci & !di & !ei & !ii) | + (p13 & !ei & ii & gi & hi & ji) | + (p31 & ei & !ii & !gi & !hi & !ji)); + + wire alt7 = (fi & !gi & !hi & // 1000 cases, where disp6b is 1 + ((dispin & ci & di & !ei & !ii) | ko | + (dispin & !ci & di & !ei & !ii))) | + (!fi & gi & hi & // 0111 cases, where disp6b is 0 + (( !dispin & !ci & !di & ei & ii) | ko | + ( !dispin & ci & !di & ei & ii))); + + wire k28 = (ci & di & ei & ii) | ! (ci | di | ei | ii); + // k28 with positive disp into fghi - .1, .2, .5, and .6 special cases + wire k28p = ! (ci | di | ei | ii); + wire fo = (ji & !fi & (hi | !gi | k28p)) | + (fi & !ji & (!hi | gi | !k28p)) | + (k28p & gi & hi) | + (!k28p & !gi & !hi); + wire go = (ji & !fi & (hi | !gi | !k28p)) | + (fi & !ji & (!hi | gi |k28p)) | + (!k28p & gi & hi) | + (k28p & !gi & !hi); + wire ho = ((ji ^ hi) & ! ((!fi & gi & !hi & ji & !k28p) | (!fi & gi & hi & !ji & k28p) | + (fi & !gi & !hi & ji & !k28p) | (fi & !gi & hi & !ji & k28p))) | + (!fi & gi & hi & ji) | (fi & !gi & !hi & !ji); + + wire disp6p = (p31 & (ei | ii)) | (p22 & ei & ii); + wire disp6n = (p13 & ! (ei & ii)) | (p22 & !ei & !ii); + wire disp4p = fghjp31; + wire disp4n = fghjp13; + + assign code_err = p40 | p04 | (fi & gi & hi & ji) | (!fi & !gi & !hi & !ji) | + (p13 & !ei & !ii) | (p31 & ei & ii) | + (ei & ii & fi & gi & hi) | (!ei & !ii & !fi & !gi & !hi) | + (ei & !ii & gi & hi & ji) | (!ei & ii & !gi & !hi & !ji) | + (!p31 & ei & !ii & !gi & !hi & !ji) | + (!p13 & !ei & ii & gi & hi & ji) | + (((ei & ii & !gi & !hi & !ji) | + (!ei & !ii & gi & hi & ji)) & + ! ((ci & di & ei) | (!ci & !di & !ei))) | + (disp6p & disp4p) | (disp6n & disp4n) | + (ai & bi & ci & !ei & !ii & ((!fi & !gi) | fghjp13)) | + (!ai & !bi & !ci & ei & ii & ((fi & gi) | fghjp31)) | + (fi & gi & !hi & !ji & disp6p) | + (!fi & !gi & hi & ji & disp6n) | + (ci & di & ei & ii & !fi & !gi & !hi) | + (!ci & !di & !ei & !ii & fi & gi & hi); + + assign dataout = {ko, ho, go, fo, eo, do_, co, bo, ao}; + + // my disp err fires for any legal codes that violate disparity, may fire for illegal codes + assign disp_err = ((dispin & disp6p) | (disp6n & !dispin) | + (dispin & !disp6n & fi & gi) | + (dispin & ai & bi & ci) | + (dispin & !disp6n & disp4p) | + (!dispin & !disp6p & !fi & !gi) | + (!dispin & !ai & !bi & !ci) | + (!dispin & !disp6p & disp4n) | + (disp6p & disp4p) | (disp6n & disp4n)); +endmodule + + +module encode_8b10b (datain, dispin, dataout, dispout); + input [8:0] datain; + input dispin; // 0 = neg disp; 1 = pos disp + output [9:0] dataout; + output dispout; + + wire ai = datain[0]; + wire bi = datain[1]; + wire ci = datain[2]; + wire di = datain[3]; + wire ei = datain[4]; + wire fi = datain[5]; + wire gi = datain[6]; + wire hi = datain[7]; + wire ki = datain[8]; + + wire aeqb = (ai & bi) | (!ai & !bi); + wire ceqd = (ci & di) | (!ci & !di); + wire l22 = (ai & bi & !ci & !di) | + (ci & di & !ai & !bi) | + ( !aeqb & !ceqd); + wire l40 = ai & bi & ci & di; + wire l04 = !ai & !bi & !ci & !di; + wire l13 = ( !aeqb & !ci & !di) | + ( !ceqd & !ai & !bi); + wire l31 = ( !aeqb & ci & di) | + ( !ceqd & ai & bi); + + // The 5B/6B encoding + + wire ao = ai; + wire bo = (bi & !l40) | l04; + wire co = l04 | ci | (ei & di & !ci & !bi & !ai); + wire do_ = di & ! (ai & bi & ci); + wire eo = (ei | l13) & ! (ei & di & !ci & !bi & !ai); + wire io = (l22 & !ei) | + (ei & !di & !ci & !(ai&bi)) | // D16, D17, D18 + (ei & l40) | + (ki & ei & di & ci & !bi & !ai) | // K.28 + (ei & !di & ci & !bi & !ai); + + // pds16 indicates cases where d-1 is assumed + to get our encoded value + wire pd1s6 = (ei & di & !ci & !bi & !ai) | (!ei & !l22 & !l31); + // nds16 indicates cases where d-1 is assumed - to get our encoded value + wire nd1s6 = ki | (ei & !l22 & !l13) | (!ei & !di & ci & bi & ai); + + // ndos6 is pds16 cases where d-1 is + yields - disp out - all of them + wire ndos6 = pd1s6; + // pdos6 is nds16 cases where d-1 is - yields + disp out - all but one + wire pdos6 = ki | (ei & !l22 & !l13); + + + // some Dx.7 and all Kx.7 cases result in run length of 5 case unless + // an alternate coding is used (referred to as Dx.A7, normal is Dx.P7) + // specifically, D11, D13, D14, D17, D18, D19. + wire alt7 = fi & gi & hi & (ki | + (dispin ? (!ei & di & l31) : (ei & !di & l13))); + + + wire fo = fi & ! alt7; + wire go = gi | (!fi & !gi & !hi); + wire ho = hi; + wire jo = (!hi & (gi ^ fi)) | alt7; + + // nd1s4 is cases where d-1 is assumed - to get our encoded value + wire nd1s4 = fi & gi; + // pd1s4 is cases where d-1 is assumed + to get our encoded value + wire pd1s4 = (!fi & !gi) | (ki & ((fi & !gi) | (!fi & gi))); + + // ndos4 is pd1s4 cases where d-1 is + yields - disp out - just some + wire ndos4 = (!fi & !gi); + // pdos4 is nd1s4 cases where d-1 is - yields + disp out + wire pdos4 = fi & gi & hi; + + // only legal K codes are K28.0->.7, K23/27/29/30.7 + // K28.0->7 is ei=di=ci=1,bi=ai=0 + // K23 is 10111 + // K27 is 11011 + // K29 is 11101 + // K30 is 11110 - so K23/27/29/30 are ei & l31 + wire illegalk = ki & + (ai | bi | !ci | !di | !ei) & // not K28.0->7 + (!fi | !gi | !hi | !ei | !l31); // not K23/27/29/30.7 + + // now determine whether to do the complementing + // complement if prev disp is - and pd1s6 is set, or + and nd1s6 is set + wire compls6 = (pd1s6 & !dispin) | (nd1s6 & dispin); + + // disparity out of 5b6b is disp in with pdso6 and ndso6 + // pds16 indicates cases where d-1 is assumed + to get our encoded value + // ndos6 is cases where d-1 is + yields - disp out + // nds16 indicates cases where d-1 is assumed - to get our encoded value + // pdos6 is cases where d-1 is - yields + disp out + // disp toggles in all ndis16 cases, and all but that 1 nds16 case + + wire disp6 = dispin ^ (ndos6 | pdos6); + + wire compls4 = (pd1s4 & !disp6) | (nd1s4 & disp6); + assign dispout = disp6 ^ (ndos4 | pdos4); + + assign dataout = {(jo ^ compls4), (ho ^ compls4), + (go ^ compls4), (fo ^ compls4), + (io ^ compls6), (eo ^ compls6), + (do_ ^ compls6), (co ^ compls6), + (bo ^ compls6), (ao ^ compls6)}; +endmodule + diff --git a/example_projects/fast_counter_iterative_test/FMAX plots_cyclonev.png b/example_projects/fast_counter_iterative_test/FMAX plots_cyclonev.png deleted file mode 100644 index 2dbb6cd..0000000 Binary files a/example_projects/fast_counter_iterative_test/FMAX plots_cyclonev.png and /dev/null differ diff --git a/example_projects/fast_counter_iterative_test/FMAX plots_cyclonev.xlsx b/example_projects/fast_counter_iterative_test/FMAX plots_cyclonev.xlsx deleted file mode 100644 index dfee830..0000000 Binary files a/example_projects/fast_counter_iterative_test/FMAX plots_cyclonev.xlsx and /dev/null differ diff --git a/example_projects/fast_counter_iterative_test/Makefile b/example_projects/fast_counter_iterative_test/Makefile deleted file mode 100644 index 93c3f45..0000000 --- a/example_projects/fast_counter_iterative_test/Makefile +++ /dev/null @@ -1,59 +0,0 @@ -#------------------------------------------------------------------------------ -# Makefile for iterative compilation for Intel / Altera Quartus -# Konstantin Pavlov, pavlovconst@gmail.com -# -# -# INFO ------------------------------------------------------------------------ -# -# - This is a top-level Makefile -# - It makes a bunch of Quartus project copies which differ only one variable -# - Then it compiles all projects in parallel and collects FMAX data -# -# - Please define var sweep range below -# - Separate quartus project will be created and compiled for every var value -# -# - This makefile is "make -j"-friendly -# - - -VAR_START = 5 -VAR_STOP = 32 -VAR = $(shell seq $(VAR_START) ${VAR_STOP}) - -JOBS = $(addprefix job,${VAR}) - - -.PHONY: all report clean - - -all: fmax - echo '$@ success' - -${JOBS}: job%: - mkdir -p ./$*; \ - cp ./base/* ./$*; \ - echo "\`define WIDTH $*" > ./$*/define.vh; \ - $(MAKE) -C ./$* stap - -fmax: ${JOBS} - echo '# FMAX summary report for iterative compilation' > ./fmax.csv; \ - for (( var = $(VAR_START); var <= $(VAR_STOP); var++ )); do \ - { echo $$var ', '; \ - cat ./$$var/OUTPUT/test.sta.rpt | \ - grep -A2 '; Fmax ; Restricted Fmax ; Clock Name ; Note ;' | \ - tail -n1 | cut -d\; -f3 | cut -d' ' -f2; echo ', '; \ - cat ./$$var/OUTPUT/test.sta.rpt | \ - grep -A3 '; Fmax ; Restricted Fmax ; Clock Name ; Note ;' | \ - tail -n1 | cut -d\; -f3 | cut -d' ' -f2; } >> ./fmax.csv; \ - done; \ - echo 'fmax.csv file done' - -report: ./fmax.csv - cat ./fmax.csv - -clean: - for (( var = $(VAR_START); var <= $(VAR_STOP); var++ )); do \ - rm -rfv ./$$var; \ - rm -rfv ./fmax.csv; \ - done - diff --git a/example_projects/fast_counter_iterative_test/base/Makefile b/example_projects/fast_counter_iterative_test/base/Makefile deleted file mode 100644 index 08147e9..0000000 --- a/example_projects/fast_counter_iterative_test/base/Makefile +++ /dev/null @@ -1,209 +0,0 @@ -#------------------------------------------------------------------------------ -# Makefile for Intel / Altera Quartus -# Konstantin Pavlov, pavlovconst@gmail.com -# -# -# INFO ------------------------------------------------------------------------ -# -# - Use this Makefile in linux terminal or on Windows under Cygwin -# -# - Default target ("make" command without any options) is intended to get fast -# compilation and timing analysis. Suitable for general project development -# and debugging -# -# - "make -j" runs timing analysis and *.sof file assembling in parallel. That -# saves you ~20 seconds every time :) -# -# - Specific targets (for example, "make sof") provide you requested results -# assuming that timing analysis is unnexessary -# -# - Check that Quartus and Modelsim directories are in your $PATH. Something like -# echo $PATH | tr : \\n | grep quartus -# export PATH = '/cygdrive/c/intelFPGA/17.0/quartus/bin64:$PATH' -# export PATH = '/cygdrive/c/intelFPGA/17.0/quartus/bin:$PATH' -# echo $PATH | tr : \\n | grep modelsim -# export PATH = '/cygdrive/c/intelFPGA/17.0/modelsim_ase/win32aloem:$PATH' - - - -PROJ_DIR = $(shell pwd) -PROJ = $(shell ls -1 *.qpf | tail -n1 | awk '{ gsub(".qpf","") } 1' ) -#SRCS = $(shell ls -R1 SOURCE/*.{v,sv,vh,sdc,tcl,hex,bin} 2>/dev/null | grep -v ':' ) -SRCS = $(shell ls -R1 SOURCE/* ) - -QPF = $(PROJ).qpf -QSF = $(PROJ).qsf -SOF = ./OUTPUT/$(PROJ).sof -POF = ./OUTPUT/$(PROJ).pof -RBF = ./OUTPUT/$(PROJ).rbf -JAM = ./OUTPUT/$(PROJ).jam - -PRE_SCRIPT = './DEBUG/pre_flow.tcl' -POST_SCRIPT = './DEBUG/post_flow.tcl' - -MAP_REPORT = ./OUTPUT/$(PROJ).map.rpt -FIT_REPORT = ./OUTPUT/$(PROJ).fit.rpt - -DSE_CONFIG = $(PROJ).dse - -TARGET_IP = 192.168.1.1 -TARGET_PORT = USB-1 -TARGET_CHIP = 1 - -QUARTUS_DIR = /cygdrive/c/intelFPGA_lite/20.1/quartus/bin64/ - - - -.PHONY: all info clean stp gui - - -all: sta sof - - -info: - echo -e \\n ' Project directory: ' $(PROJ_DIR) \ - \\n ' Project name: ' $(PROJ) \ - \\n ' Preject sources: ' $(SRCS) - -gui: - quartus $(QPF) 1>/dev/null - - -$(MAP_REPORT): $(SRCS) $(QPF) $(QSF) - $(shell if test -f $(PRE_SCRIPT); then quartus_sh -t $(PRE_SCRIPT) compile $(PROJ) $(PROJ); fi ) - $(QUARTUS_DIR)quartus_map --no_banner \ - --read_settings_files=on \ - --write_settings_files=off \ - --64bit $(PROJ) -c $(PROJ) - # dont use --effort=fast because it can dramatically increase fitting time -map: $(PROJ).map.rpt - - -$(FIT_REPORT): $(MAP_REPORT) - # $(QUARTUS_DIR)quartus_cdb --read_settings_files=on \ - # --write_settings_files=off \ - # --64bit $(PROJ) -c $(PROJ) - $(QUARTUS_DIR)quartus_fit --no_banner \ - --read_settings_files=on \ - --write_settings_files=off \ - --inner_num=1 \ - --one_fit_attempt=on \ - --pack_register=off \ - --effort=fast \ - --64bit $(PROJ) -c $(PROJ) - # using --io_smart_recompile for secondary fitter launches is tricky -fit: $(FIT_REPORT) - - -$(SOF): $(FIT_REPORT) - $(QUARTUS_DIR)quartus_asm --no_banner \ - --read_settings_files=off \ - --write_settings_files=off \ - --64bit $(PROJ) -c $(PROJ) -asm: $(SOF) - - -sta: $(FIT_REPORT) - $(QUARTUS_DIR)quartus_sta $(PROJ) -c $(PROJ) - #$(shell if test -f $(POST_SCRIPT); then quartus_sh -t $(POST_SCRIPT) compile $(PROJ) $(PROJ); fi ) - -stap: $(FIT_REPORT) - $(QUARTUS_DIR)quartus_sta --parallel --model=slow $(PROJ) -c $(PROJ) - #$(shell if test -f $(POST_SCRIPT); then quartus_sh -t $(POST_SCRIPT) compile $(PROJ) $(PROJ); fi ) - - -$(POF): $(SOF) - $(QUARTUS_DIR)quartus_cpf --no_banner \ - -c $(SOF) $(POF) -$(RBF): $(SOF) - $(QUARTUS_DIR)quartus_cpf --no_banner \ - -c $(SOF) $(RBF) -$(JAM): $(SOF) - $(QUARTUS_DIR)quartus_cpf --no_banner \ - -c $(SOF) $(JAM) -sof: $(SOF) -pof: $(POF) -rbf: $(RBF) -jam: $(JAM) - - -prog: sof - $(QUARTUS_DIR)quartus_pgm --no_banner \ - -c "USB-Blaster on $(TARGET_IP) [$(TARGET_PORT)]" -m jtag \ - -o "P;$(SOF)@$(TARGET_CHIP)" - -prog_pof: pof - $(QUARTUS_DIR)quartus_pgm --no_banner \ - -c "USB-Blaster on $(TARGET_IP) [$(TARGET_PORT)]" -m jtag \ - -o "BVP;$(POF)@$(TARGET_CHIP)" - -prog_rbf: rbf - $(QUARTUS_DIR)quartus_pgm --no_banner \ - -c "USB-Blaster on $(TARGET_IP) [$(TARGET_PORT)]" -m jtag \ - -o "BVP;$(RBF)@$(TARGET_CHIP)" - - -clean: - # clean common junk files - rm -rfv $(PROJ).qws c5_pin_model_dump.txt $(PROJ).ipregen.rpt .qsys_edit/ - # clean compilation databases - rm -rfv db/ incremental_db/ greybox_tmp/ - # clean output directory - rm -rfv OUTPUT/ - # clean hard memory controller - rm -rfv ddr3_hmc_ddr3_0_p0_0_summary.csv ddr3_hmc_ddr3_0_p0_1_summary.csv - # clean design space explorer files - rm -rfv dse/ dse1_base.qpf dse1_base.qsf $(PROJ).dse.rpt $(PROJ).archive.rpt - # clean early power estimator files - rm -rfv $(PROJ)_early_pwr.csv - # TODO: add project-specific files to remove here - - - -dse: $(DSE_CONFIG) - $(QUARTUS_DIR)quartus_dse --no_banner \ - --terminate off \ - --num-parallel-processors 10 \ - --auto-discover-files on \ - --revision $(PROJ) $(PROJ).qpf \ - --use-dse-file $(DSE_CONFIG) - - -sim: $(SRCS) - modelsim -do compile.tcl - -sim_clean: - - -gtkwave: $(SRCS) - # creating VVP file - iverilog -Wall -g2012 -o iverilog_sim.vvp -s $(SRCS) - # creating VCD file - vvp -v iverilog_sim.vvp - # creating settings file for gtkwave on-the-fly - echo fontname_waves Verdana 9 > .\gtkwaverc - echo fontname_signals Verdana 9 >> .\gtkwaverc - echo fontname_logfile Verdana 9 >> .\gtkwaverc - echo splash_disable 1 >> .\gtkwaverc - echo use_roundcaps 1 >> .\gtkwaverc - echo force_toolbars 1 >> .\gtkwaverc - echo left_justify_sigs 1 >> .\gtkwaverc - # launching gtkwave - # press CTRL+S to save vawe config. gtkwave will open it automatically next time - gtkwave -r .\gtkwaverc iverilog_sim.vcd wave.gtkw - - # // place this code into your testbench and add signals you want to dump - # // and navigate during simulation - # initial begin - # $dumpfile("iverilog_sim.vcd"); - # $dumpvars( 0, M ); - # #10000 $finish; - # end - - -stp: - $(QUARTUS_DIR)quartus_stp --no_banner \ - $(QPF) - - - diff --git a/example_projects/fast_counter_iterative_test/base/define.vh b/example_projects/fast_counter_iterative_test/base/define.vh deleted file mode 100644 index a04e330..0000000 --- a/example_projects/fast_counter_iterative_test/base/define.vh +++ /dev/null @@ -1 +0,0 @@ -`define WIDTH 5 \ No newline at end of file diff --git a/example_projects/fast_counter_iterative_test/base/fast_counter.sv b/example_projects/fast_counter_iterative_test/base/fast_counter.sv deleted file mode 100644 index 5207055..0000000 --- a/example_projects/fast_counter_iterative_test/base/fast_counter.sv +++ /dev/null @@ -1,109 +0,0 @@ -//------------------------------------------------------------------------------ -// fast_counter.sv -// Konstantin Pavlov, pavlovconst@gmail.com -//------------------------------------------------------------------------------ - -// INFO ------------------------------------------------------------------------ -// -// - This is a synthetic fast counter which appears faster than a standard one -// generated from pure Verilog code -// -// - My tests show that it is on average 30MHz faster in direct comparisons for -// counters from 5 to 32 bit widths in Cyclone V -// -// - Use this counter only when counter performance is your last and ultimate -// resort to conquer timings. Fast counter is area-unefficient thing. -// -// - fast_counter_iterative_test project in the repo shows fast counter`s advantage -// https://github.com/pConst/basic_verilog/fast_counter_iterative_test/ -// - - -/* --- INSTANTIATION TEMPLATE BEGIN --- - -fast_counter #( - .WIDTH( 14 ) -) fc ( - .clk( clk ), - - .set( ), // highest priority operation, use it like a reset also - .set_val( ), - .dec( ), - - .q( ), - .q_is_zero( ) -); - ---- INSTANTIATION TEMPLATE END ---*/ - - -module fast_counter #( parameter - WIDTH = 8 -)( - input clk, - - input set, - input [WIDTH-1:0] set_val, - - input dec, - - output [WIDTH-1:0] q, - output q_is_zero -); - - -const logic [5:0][15:0] lsb_bits_init = { 16'b0000000000000001, - 16'b1000000000000000, - 16'b1111111100000000, - 16'b1111000011110000, - 16'b1100110011001100, - 16'b1010101010101010 }; - - -logic [WIDTH-4-1:0] msb_bits = '0; -logic [5:0][15:0] lsb_bits = lsb_bits_init; - -logic [16*6-1:0] lsb_bits_flat; -assign lsb_bits_flat[16*6-1:0] = lsb_bits; - - -integer i,j; -always_ff @(posedge clk) begin - if( set ) begin - - msb_bits[WIDTH-4-1:0] <= set_val[WIDTH-1:4]; - for( i=0; i<6; i++ ) begin - for( j=0; j<16; j++ ) begin - lsb_bits[i][j] <= lsb_bits_init[i][(set_val[3:0]+j) % 16]; - end - end - - end else if( dec ) begin - - if( lsb_bits[5][0] ) begin - msb_bits[WIDTH-4-1:0] <= msb_bits[WIDTH-4-1:0] - 1'b1; - end - for( i=0; i<6; i++ ) begin - for( j=0; j<16; j++ ) begin - if( j==0 ) begin - lsb_bits[i][j] <= lsb_bits[i][15]; - end else begin - lsb_bits[i][j] <= lsb_bits[i][j-1]; - end - end - end - - end -end - - -assign q[WIDTH-1:4] = msb_bits[WIDTH-4-1:0]; -assign q[3] = lsb_bits[3][0], - q[2] = lsb_bits[2][0], - q[1] = lsb_bits[1][0], - q[0] = lsb_bits[0][0]; - -assign q_is_zero = ~|q[WIDTH-1:0]; - -endmodule - diff --git a/example_projects/fast_counter_iterative_test/base/main.sdc b/example_projects/fast_counter_iterative_test/base/main.sdc deleted file mode 100644 index 1b3de0b..0000000 --- a/example_projects/fast_counter_iterative_test/base/main.sdc +++ /dev/null @@ -1,6 +0,0 @@ - -create_clock -period 2.000 -waveform { 0.000 1.000 } [get_ports {clk1}] -create_clock -period 2.000 -waveform { 0.000 1.000 } [get_ports {clk2}] - -derive_pll_clocks -derive_clock_uncertainty diff --git a/example_projects/fast_counter_iterative_test/base/main.sv b/example_projects/fast_counter_iterative_test/base/main.sv deleted file mode 100644 index 06a6df5..0000000 --- a/example_projects/fast_counter_iterative_test/base/main.sv +++ /dev/null @@ -1,73 +0,0 @@ - -// Fast counter test project -// Konstantin Pavlov, pavlovconst@gmail.com - - -`include "define.vh" - -module main( - - input clk1, - input nrst1, - - input set1, - input [`WIDTH-1:0] set_val1, - input dec1, - - output logic q_is_zero1 = 1'b0, - - - input clk2, - input nrst2, - - input set2, - input [`WIDTH-1:0] set_val2, - input dec2, - - output logic q_is_zero2 = 1'b0 -); - - -logic [`WIDTH-1:0] std_cntr = '0; -always_ff @(posedge clk1) begin - if( set1 || nrst1 ) begin - std_cntr[`WIDTH-1:0] <= set_val1[`WIDTH-1:0]; - end else if( dec1 ) begin - std_cntr[`WIDTH-1:0] <= std_cntr[`WIDTH-1:0] - 1'b1; - end -end - -//registering all outputs -always_ff @(posedge clk1) begin - if( ~nrst1 ) begin - q_is_zero1 <= 1'b0; - end else begin - q_is_zero1 <= (std_cntr[`WIDTH-1:0] == '0); - end -end - - -logic qz; -fast_counter #( - .WIDTH( `WIDTH ) -) fc ( - .clk( clk2 ), - - .set( set2 || nrst2 ), - .set_val( set_val2 ), - .dec( dec2 ), - // no value output - .q_is_zero( qz ) -); - -//registering all outputs -always_ff @(posedge clk1) begin - if( ~nrst2 ) begin - q_is_zero2 <= 1'b0; - end else begin - q_is_zero2 <= qz; - end -end - - -endmodule diff --git a/example_projects/fast_counter_iterative_test/base/test.qpf b/example_projects/fast_counter_iterative_test/base/test.qpf deleted file mode 100644 index 88ba528..0000000 --- a/example_projects/fast_counter_iterative_test/base/test.qpf +++ /dev/null @@ -1,31 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 2017 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel MegaCore Function License Agreement, or other -# applicable license agreement, including, without limitation, -# that your use is for the sole purpose of programming logic -# devices manufactured by Intel and sold by Intel or its -# authorized distributors. Please refer to the applicable -# agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus Prime -# Version 17.0.0 Build 595 04/25/2017 SJ Standard Edition -# Date created = 11:22:30 September 26, 2018 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "17.0" -DATE = "11:22:30 September 26, 2018" - -# Revisions - -PROJECT_REVISION = "test" diff --git a/example_projects/fast_counter_iterative_test/base/test.qsf b/example_projects/fast_counter_iterative_test/base/test.qsf deleted file mode 100644 index 0db554a..0000000 --- a/example_projects/fast_counter_iterative_test/base/test.qsf +++ /dev/null @@ -1,26 +0,0 @@ - -set_global_assignment -name FAMILY "Cyclone V" -set_global_assignment -name DEVICE 5CGXFC4C7F27C8 -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.0.0 -set_global_assignment -name LAST_QUARTUS_VERSION "17.0.0 Lite Edition" - -set_global_assignment -name TOP_LEVEL_ENTITY main -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY OUTPUT -set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" - - -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - - -set_global_assignment -name SYSTEMVERILOG_FILE fast_counter.sv -set_global_assignment -name SYSTEMVERILOG_FILE define.vh -set_global_assignment -name SYSTEMVERILOG_FILE main.sv -set_global_assignment -name SDC_FILE main.sdc -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/example_projects/fast_counter_iterative_test/fmax.rpt b/example_projects/fast_counter_iterative_test/fmax.rpt deleted file mode 100644 index 24b4f81..0000000 --- a/example_projects/fast_counter_iterative_test/fmax.rpt +++ /dev/null @@ -1,85 +0,0 @@ -FMAX summary report for iterative compilation -5 -; 356.38 MHz ; 356.38 MHz ; clk1 ; ; -; 445.24 MHz ; 445.24 MHz ; clk2 ; ; -6 -; 329.71 MHz ; 329.71 MHz ; clk1 ; ; -; 376.51 MHz ; 376.51 MHz ; clk2 ; ; -7 -; 322.27 MHz ; 322.27 MHz ; clk1 ; ; -; 412.71 MHz ; 412.71 MHz ; clk2 ; ; -8 -; 330.58 MHz ; 330.58 MHz ; clk1 ; ; -; 341.88 MHz ; 341.88 MHz ; clk2 ; ; -9 -; 322.48 MHz ; 322.48 MHz ; clk1 ; ; -; 382.12 MHz ; 382.12 MHz ; clk2 ; ; -10 -; 288.68 MHz ; 288.68 MHz ; clk1 ; ; -; 353.23 MHz ; 353.23 MHz ; clk2 ; ; -11 -; 303.03 MHz ; 303.03 MHz ; clk2 ; ; -; 316.36 MHz ; 316.36 MHz ; clk1 ; ; -12 -; 300.48 MHz ; 300.48 MHz ; clk1 ; ; -; 323.62 MHz ; 323.62 MHz ; clk2 ; ; -13 -; 276.24 MHz ; 276.24 MHz ; clk1 ; ; -; 281.29 MHz ; 281.29 MHz ; clk2 ; ; -14 -; 283.53 MHz ; 283.53 MHz ; clk1 ; ; -; 301.11 MHz ; 301.11 MHz ; clk2 ; ; -15 -; 257.33 MHz ; 257.33 MHz ; clk1 ; ; -; 300.93 MHz ; 300.93 MHz ; clk2 ; ; -16 -; 268.02 MHz ; 268.02 MHz ; clk1 ; ; -; 282.81 MHz ; 282.81 MHz ; clk2 ; ; -17 -; 248.45 MHz ; 248.45 MHz ; clk1 ; ; -; 287.77 MHz ; 287.77 MHz ; clk2 ; ; -18 -; 246.97 MHz ; 246.97 MHz ; clk2 ; ; -; 268.1 MHz ; 268.1 MHz ; clk1 ; ; -19 -; 254.32 MHz ; 254.32 MHz ; clk1 ; ; -; 279.56 MHz ; 279.56 MHz ; clk2 ; ; -20 -; 254.07 MHz ; 254.07 MHz ; clk1 ; ; -; 277.55 MHz ; 277.55 MHz ; clk2 ; ; -21 -; 249.07 MHz ; 249.07 MHz ; clk2 ; ; -; 264.27 MHz ; 264.27 MHz ; clk1 ; ; -22 -; 242.13 MHz ; 242.13 MHz ; clk1 ; ; -; 260.55 MHz ; 260.55 MHz ; clk2 ; ; -23 -; 246.73 MHz ; 246.73 MHz ; clk2 ; ; -; 255.56 MHz ; 255.56 MHz ; clk1 ; ; -24 -; 219.88 MHz ; 219.88 MHz ; clk2 ; ; -; 258.33 MHz ; 258.33 MHz ; clk1 ; ; -25 -; 257.33 MHz ; 257.33 MHz ; clk1 ; ; -; 266.31 MHz ; 266.31 MHz ; clk2 ; ; -26 -; 229.57 MHz ; 229.57 MHz ; clk2 ; ; -; 258.87 MHz ; 258.87 MHz ; clk1 ; ; -27 -; 238.83 MHz ; 238.83 MHz ; clk2 ; ; -; 247.65 MHz ; 247.65 MHz ; clk1 ; ; -28 -; 236.74 MHz ; 236.74 MHz ; clk2 ; ; -; 259.27 MHz ; 259.27 MHz ; clk1 ; ; -29 -; 233.32 MHz ; 233.32 MHz ; clk2 ; ; -; 251.57 MHz ; 251.57 MHz ; clk1 ; ; -30 -; 222.62 MHz ; 222.62 MHz ; clk1 ; ; -; 238.04 MHz ; 238.04 MHz ; clk2 ; ; -31 -; 229.62 MHz ; 229.62 MHz ; clk1 ; ; -; 229.99 MHz ; 229.99 MHz ; clk2 ; ; -32 -; 190.62 MHz ; 190.62 MHz ; clk2 ; ; -; 228.83 MHz ; 228.83 MHz ; clk1 ; ; diff --git a/example_projects/fast_counter_iterative_test/redme.md b/example_projects/fast_counter_iterative_test/redme.md deleted file mode 100644 index e4f8051..0000000 --- a/example_projects/fast_counter_iterative_test/redme.md +++ /dev/null @@ -1,13 +0,0 @@ - -fast_counter_iterative_test project ------------------------------------ - -This project shows how to make iterative compilation for Intel / Altera Quartus FPGA - -We create a bunch of generated Quartus project copies which differ only one variable -All projects get compiled in parallel collecting FMAX data - -This particular test shows FMAX advantage of using 'fast_counter.sv' module - -Launch compilation using "make -j" command - diff --git a/example_projects/testbench_template_tb/clean_modelsim.sh b/example_projects/testbench_template_tb/clean_modelsim.sh new file mode 100644 index 0000000..1439dde --- /dev/null +++ b/example_projects/testbench_template_tb/clean_modelsim.sh @@ -0,0 +1,21 @@ +#! /usr/bin/env bash + +# ------------------------------------------------------------------------------ +# clean_modelsim.sh +# published as part of https://github.com/pConst/basic_verilog +# Konstantin Pavlov, pavlovconst@gmail.com +# ------------------------------------------------------------------------------ +# +# Use this file as a boilerplate for your custom clean script +# for Modelsim projects + + +rm -rf work + +rm transcript +rm wave.do +rm modelsim.ini +rm start_time.txt +rm vsim.wlf +rm vish_stacktrace.vstf + diff --git a/example_projects/testbench_template_tb/compile.sh b/example_projects/testbench_template_tb/compile.sh new file mode 100644 index 0000000..b37415d --- /dev/null +++ b/example_projects/testbench_template_tb/compile.sh @@ -0,0 +1,9 @@ +#!/bin/bash + +# questa_compile.sh +# Konstantin Pavlov, pavlovconst@gmail.com +# +# This is a support script for launching "Questasim compile script" on Linux + + +vsim -do compile.tcl diff --git a/example_projects/testbench_template_tb/compile.tcl b/example_projects/testbench_template_tb/compile.tcl index c5d5576..68454e5 100755 --- a/example_projects/testbench_template_tb/compile.tcl +++ b/example_projects/testbench_template_tb/compile.tcl @@ -4,7 +4,7 @@ #------------------------------------------------------------------------------ # INFO ------------------------------------------------------------------------ -# Modelsim compile script +# Modelsim/Questa compile script # based on "ModelSimSE general compile script version 1.1" by Doulos # launch the script by "vsim -do compile.tcl" command on linux @@ -71,7 +71,7 @@ foreach {library file_list} $library_file_list { set last_compile_time $time_now # Load the simulation -eval vsim $vsim_params $top_level +eval vsim -voptargs=+acc $vsim_params $top_level # Load saved wave patterns do wave.do diff --git a/example_projects/vitis_hls_test_prj_template_v2/.gitignore b/example_projects/vitis_hls_test_prj_template_v2/.gitignore new file mode 100644 index 0000000..d023ac5 --- /dev/null +++ b/example_projects/vitis_hls_test_prj_template_v2/.gitignore @@ -0,0 +1,14 @@ +#------------------------------------------------------------------------------ +# .gitignore for Vitis HLS projects +# published as part of https://github.com/pConst/basic_verilog +# Konstantin Pavlov, pavlovconst@gmail.com +#------------------------------------------------------------------------------ + +# INFO ------------------------------------------------------------------------ +# rename the file to ".gitignore" and place into your HLS project directory +# + +/prj + +vitis_hls.log + diff --git a/example_projects/vitis_hls_test_prj_template_v2/run_hls.tcl b/example_projects/vitis_hls_test_prj_template_v2/run_hls.tcl new file mode 100644 index 0000000..a17041d --- /dev/null +++ b/example_projects/vitis_hls_test_prj_template_v2/run_hls.tcl @@ -0,0 +1,28 @@ +#------------------------------------------------------------------------------ +# published as part of https://github.com/pConst/basic_verilog +# Konstantin Pavlov, pavlovconst@gmail.com +#------------------------------------------------------------------------------ + +# Create a project +open_project prj -reset +add_files src/hls_operator.cpp +add_files -tb src/hls_operator_tb.cpp -cflags "-Wno-unknown-pragmas" -csimflags "-Wno-unknown-pragmas" +set_top hls_operator + +# Create a solution +open_solution -reset sol1 -flow_target vitis +set_part {xcvu9p-flga2104-2-i} +create_clock -period 5 -name default + +#source "./prj/sol1/directives.tcl" + +#csim_design +csynth_design +#cosim_design +#export_design -rtl verilog -format ip_catalog -output /home/kp/tmp + +#export_design -flow syn -rtl verilog -format ip_catalog +#export_design -flow impl -rtl verilog -format ip_catalog + +exit + diff --git a/example_projects/vitis_hls_test_prj_template_v2/src/hls_operator.cpp b/example_projects/vitis_hls_test_prj_template_v2/src/hls_operator.cpp new file mode 100644 index 0000000..fd913e8 --- /dev/null +++ b/example_projects/vitis_hls_test_prj_template_v2/src/hls_operator.cpp @@ -0,0 +1,117 @@ +//------------------------------------------------------------------------------ +// published as part of https://github.com/pConst/basic_verilog +// Konstantin Pavlov, pavlovconst@gmail.com +//------------------------------------------------------------------------------ + +#include "ap_int.h" +#include "hls_stream.h" + +//#include "hls_operator.h" + + +//================================================================================================== +void stream_splitter( + hls::stream &is, + hls::stream &os1, + hls::stream &os2 +){ + +//#pragma HLS INLINE + + int data; + data = is.read(); + + os1.write( data ); + os2.write( data ); +} + +//================================================================================================== +void func_1( + hls::stream &is, + hls::stream &os +){ + +//#pragma HLS INLINE + + const int st_k = 5; + + os.write( is.read() + st_k ); +} + + +//================================================================================================== +void func_2( + hls::stream &is, + hls::stream &os +){ + +//#pragma HLS INLINE + + static int st_k; + + os.write( is.read() + st_k ); + + if( st_k < 4 ){ + st_k++; + } else { + st_k = 0; + } +} + + +//================================================================================================== +void func_3( + hls::stream &is, + hls::stream &os +){ + +//#pragma HLS INLINE + + //#pragma HLS DATAFLOW disable_start_propagation + //#pragma HLS INTERFACE mode=ap_ctrl_none port=return + + os.write( is.read() / 13 ); +} + + +//================================================================================================== +void hls_operator( + hls::stream &a, + hls::stream &b, + hls::stream &c, + hls::stream &d +){ + + #pragma HLS DATAFLOW disable_start_propagation + #pragma HLS INTERFACE mode=ap_ctrl_none port=return + + //#pragma HLS PIPELINE + + #pragma HLS INTERFACE port=a ap_fifo + #pragma HLS INTERFACE port=b ap_fifo + #pragma HLS INTERFACE port=c ap_fifo + #pragma HLS INTERFACE port=d ap_fifo + + + hls::stream a1; + hls::stream a2; + stream_splitter(a, a1, a2); + + + // first branch (short) + hls::stream fa_os; + func_1( a1, fa_os ); + + + // second branch (long) + hls::stream fb_os; + func_2( a2, fb_os ); + + hls::stream fc_os; + func_3( fb_os, fc_os ); + + + b.write( fa_os.read() + fc_os.read() ); + +} + diff --git a/example_projects/vitis_hls_test_prj_template_v2/src/hls_operator.h b/example_projects/vitis_hls_test_prj_template_v2/src/hls_operator.h new file mode 100644 index 0000000..98708d4 --- /dev/null +++ b/example_projects/vitis_hls_test_prj_template_v2/src/hls_operator.h @@ -0,0 +1,21 @@ + +void stream_splitter( + hls::stream &is, + hls::stream &os1 + hls::stream &os2 +); + +void func_1( + hls::stream &is, + hls::stream &os +); + +void func_2( + hls::stream &is, + hls::stream &os +); + +void func_3( + hls::stream &is, + hls::stream &os +); diff --git a/example_projects/vitis_hls_test_prj_template_v2/src/hls_operator_tb.cpp b/example_projects/vitis_hls_test_prj_template_v2/src/hls_operator_tb.cpp new file mode 100644 index 0000000..d6a3664 --- /dev/null +++ b/example_projects/vitis_hls_test_prj_template_v2/src/hls_operator_tb.cpp @@ -0,0 +1,28 @@ +//------------------------------------------------------------------------------ +// published as part of https://github.com/pConst/basic_verilog +// Konstantin Pavlov, pavlovconst@gmail.com +//------------------------------------------------------------------------------ + +#include "ap_int.h" + +#include "hls_operator.h" + +using namespace std; + +int main() { + + const int Ni = 3; + const int Nj = 5; + + for (int i = 0; i < Ni; ++i) { + for (int j = 1; j < Nj; j=j*2) { + + int result; + result = hls_operator( i, j ); + cout << i << " @ " << j << " = " << result << endl; + } + } + + return 0; +} + diff --git a/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_clean.sh b/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_clean.sh new file mode 100644 index 0000000..03828d8 --- /dev/null +++ b/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_clean.sh @@ -0,0 +1,13 @@ +#! /usr/bin/env bash +#------------------------------------------------------------------------------ +# published as part of https://github.com/pConst/basic_verilog +# Konstantin Pavlov, pavlovconst@gmail.com +#------------------------------------------------------------------------------ + +# Script to clean Vitis HLS project +# see ../example_projects/vitis_hls_prj_template_v1/ for complete example + +rm -rf prj + +rm vitis_hls.log + diff --git a/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_cosim.sh b/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_cosim.sh new file mode 100644 index 0000000..2594fbc --- /dev/null +++ b/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_cosim.sh @@ -0,0 +1,16 @@ +#! /usr/bin/env bash + +#------------------------------------------------------------------------------ +# published as part of https://github.com/pConst/basic_verilog +# Konstantin Pavlov, pavlovconst@gmail.com +#------------------------------------------------------------------------------ + +# Script to perform HLS component co-simulation +# see ../example_projects/vitis_hls_prj_template_v1/ for complete example + +if [ ! -d "./prj" ]; then + source vitis_hls_csynth.sh +fi + +vitis_hls -eval 'cosim_design' + diff --git a/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_csim.sh b/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_csim.sh new file mode 100644 index 0000000..8b37325 --- /dev/null +++ b/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_csim.sh @@ -0,0 +1,16 @@ +#! /usr/bin/env bash + +#------------------------------------------------------------------------------ +# published as part of https://github.com/pConst/basic_verilog +# Konstantin Pavlov, pavlovconst@gmail.com +#------------------------------------------------------------------------------ + +# Script to perform HLS component simulation +# see ../example_projects/vitis_hls_prj_template_v1/ for complete example + +if [ ! -d "./prj" ]; then + source vitis_hls_csynth.sh +fi + +vitis_hls -eval 'csim_design' + diff --git a/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_csynth.sh b/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_csynth.sh new file mode 100644 index 0000000..ef70ffa --- /dev/null +++ b/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_csynth.sh @@ -0,0 +1,24 @@ +#! /usr/bin/env bash +#------------------------------------------------------------------------------ +# published as part of https://github.com/pConst/basic_verilog +# Konstantin Pavlov, pavlovconst@gmail.com +#------------------------------------------------------------------------------ + +# Script to initialize HLS project solution and make CSYNTH compilation step +# see ../example_projects/vitis_hls_prj_template_v1/ for complete example + + + +rm -rf ./prj/sol1/syn +rm -rf ./prj/sol1/impl + +if (vitis_hls -f run_hls.tcl | grep --color -P "ERROR:|") ; then + + # open top Verilog + subl ./prj/sol1/syn/verilog/hls_operator.v + + # open main report + subl ./prj/sol1/syn/report/csynth.rpt + subl ./prj/sol1/syn/report/hls_operator_csynth.rpt +fi + diff --git a/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_export.sh b/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_export.sh new file mode 100644 index 0000000..5fc713b --- /dev/null +++ b/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_export.sh @@ -0,0 +1,16 @@ +#! /usr/bin/env bash + +#------------------------------------------------------------------------------ +# published as part of https://github.com/pConst/basic_verilog +# Konstantin Pavlov, pavlovconst@gmail.com +#------------------------------------------------------------------------------ + +# Script to export HLS component to Vivado IP catalog +# see ../example_projects/vitis_hls_prj_template_v1/ for complete example + +if [ ! -d "./prj" ]; then + source vitis_hls_csynth.sh +fi + +vitis_hls -eval 'export_design -rtl verilog -format ip_catalog' + diff --git a/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_gui.sh b/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_gui.sh new file mode 100644 index 0000000..ca0149d --- /dev/null +++ b/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_gui.sh @@ -0,0 +1,16 @@ +#! /usr/bin/env bash + +#------------------------------------------------------------------------------ +# published as part of https://github.com/pConst/basic_verilog +# Konstantin Pavlov, pavlovconst@gmail.com +#------------------------------------------------------------------------------ + +# Script to open Vitis HLS GUI +# see ../example_projects/vitis_hls_prj_template_v1/ for complete example + +if [ ! -d "./prj" ]; then + source vitis_hls_csynth.sh +fi + +nohup vitis_hls -p prj &> /dev/null & disown + diff --git a/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_impl.sh b/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_impl.sh new file mode 100644 index 0000000..72dd442 --- /dev/null +++ b/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_impl.sh @@ -0,0 +1,25 @@ +#! /usr/bin/env bash + +#------------------------------------------------------------------------------ +# published as part of https://github.com/pConst/basic_verilog +# Konstantin Pavlov, pavlovconst@gmail.com +#------------------------------------------------------------------------------ + +# Script to perform HLS IP synthesis and implementation +# see ../example_projects/vitis_hls_prj_template_v1/ for complete example + +if [ ! -d "./prj" ]; then + source vitis_hls_csynth.sh +fi + +if (vitis_hls -eval 'export_design -flow impl -rtl verilog -format ip_catalog' | grep --color -P "ERROR:|") ; then + + # open top Verilog + subl ./prj/sol1/syn/verilog/hls_operator.v + + # open main report + subl ./prj/sol1/impl/report/verilog/hls_operator_export.rpt + subl ./prj/sol1/impl/report/verilog/export_syn.rpt + subl ./prj/sol1/impl/report/verilog/export_impl.rpt +fi + diff --git a/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_killall.sh b/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_killall.sh new file mode 100644 index 0000000..fe86a29 --- /dev/null +++ b/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_killall.sh @@ -0,0 +1,12 @@ +#! /usr/bin/env bash + +#------------------------------------------------------------------------------ +# published as part of https://github.com/pConst/basic_verilog +# Konstantin Pavlov, pavlovconst@gmail.com +#------------------------------------------------------------------------------ + +# Script to open Vitis HLS GUI +# see ../example_projects/vitis_hls_prj_template_v1/ for complete example + +killall vitis_hls + diff --git a/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_syn.sh b/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_syn.sh new file mode 100644 index 0000000..8880a2c --- /dev/null +++ b/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_syn.sh @@ -0,0 +1,24 @@ +#! /usr/bin/env bash + +#------------------------------------------------------------------------------ +# published as part of https://github.com/pConst/basic_verilog +# Konstantin Pavlov, pavlovconst@gmail.com +#------------------------------------------------------------------------------ + +# Script to perform HLS IP synthesis +# see ../example_projects/vitis_hls_prj_template_v1/ for complete example + +if [ ! -d "./prj" ]; then + source vitis_hls_csynth.sh +fi + +if (vitis_hls -eval 'export_design -flow syn -rtl verilog -format ip_catalog' | grep --color -P "ERROR:|") ; then + + # open top Verilog + subl ./prj/sol1/syn/verilog/hls_operator.v + + # open main report + subl ./prj/sol1/impl/report/verilog/hls_operator_export.rpt + subl ./prj/sol1/impl/report/verilog/export_syn.rpt +fi + diff --git a/example_projects/vivado_test_prj_template_v2/.gitignore b/example_projects/vivado_test_prj_template_v2/.gitignore deleted file mode 100755 index a9cf0ea..0000000 --- a/example_projects/vivado_test_prj_template_v2/.gitignore +++ /dev/null @@ -1,11 +0,0 @@ - - -*.cache -*.hw -*.runs -*.sim -.Xil - -*.jou -*.log - diff --git a/example_projects/vivado_test_prj_template_v2/clean_vivado.bat b/example_projects/vivado_test_prj_template_v2/clean_vivado.bat deleted file mode 100644 index 929f98f..0000000 --- a/example_projects/vivado_test_prj_template_v2/clean_vivado.bat +++ /dev/null @@ -1,35 +0,0 @@ -@echo off -rem ------------------------------------------------------------------------------ -rem clean_vivado.bat -rem published as part of https://github.com/pConst/basic_verilog -rem Konstantin Pavlov, pavlovconst@gmail.com -rem ------------------------------------------------------------------------------ - -rem Use this file as a boilerplate for your custom clean script -rem for Vivado/Vitis projects - - -SET PROJ=test - -del /s /f /q .\%PROJ%.cache\* -rmdir /s /q .\%PROJ%.cache\ - -del /s /f /q .\%PROJ%.hw\* -rmdir /s /q .\%PROJ%.hw\ - -rem del /s /f /q .\%PROJ%.runs\* -rem rmdir /s /q .\%PROJ%.runs\ - -del /s /f /q .\%PROJ%.sim\* -rmdir /s /q .\%PROJ%.sim\ - -del /s /f /q .\.Xil\* -rmdir /s /q .\.Xil\ - -del /s /f /q .\*.jou -del /s /f /q .\*.log -del /s /f /q .\*.str - -pause -goto :eof - diff --git a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp b/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp deleted file mode 100755 index d74101f..0000000 Binary files a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp and /dev/null differ diff --git a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v b/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v deleted file mode 100755 index b6f0e52..0000000 --- a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v +++ /dev/null @@ -1,95 +0,0 @@ - -// file: clk_wiz_0.v -// -// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -//---------------------------------------------------------------------------- -// User entered comments -//---------------------------------------------------------------------------- -// None -// -//---------------------------------------------------------------------------- -// Output Output Phase Duty Cycle Pk-to-Pk Phase -// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) -//---------------------------------------------------------------------------- -// clk_out1__125.00000______0.000______50.0______119.348_____96.948 -// clk_out2__500.00000______0.000______50.0_______92.027_____96.948 -// -//---------------------------------------------------------------------------- -// Input Clock Freq (MHz) Input Jitter (UI) -//---------------------------------------------------------------------------- -// __primary_____________125____________0.010 - -`timescale 1ps/1ps - -(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v6_0_4_0_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=8.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) - -module clk_wiz_0 - ( - // Clock out ports - output clk_out1, - output clk_out2, - // Status and control signals - input resetn, - output locked, - // Clock in ports - input clk_in1 - ); - - clk_wiz_0_clk_wiz inst - ( - // Clock out ports - .clk_out1(clk_out1), - .clk_out2(clk_out2), - // Status and control signals - .resetn(resetn), - .locked(locked), - // Clock in ports - .clk_in1(clk_in1) - ); - -endmodule diff --git a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.veo b/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.veo deleted file mode 100755 index 253ee33..0000000 --- a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.veo +++ /dev/null @@ -1,82 +0,0 @@ - -// -// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -//---------------------------------------------------------------------------- -// User entered comments -//---------------------------------------------------------------------------- -// None -// -//---------------------------------------------------------------------------- -// Output Output Phase Duty Cycle Pk-to-Pk Phase -// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) -//---------------------------------------------------------------------------- -// clk_out1__125.00000______0.000______50.0______119.348_____96.948 -// clk_out2__500.00000______0.000______50.0_______92.027_____96.948 -// -//---------------------------------------------------------------------------- -// Input Clock Freq (MHz) Input Jitter (UI) -//---------------------------------------------------------------------------- -// __primary_____________125____________0.010 - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG - - clk_wiz_0 instance_name - ( - // Clock out ports - .clk_out1(clk_out1), // output clk_out1 - .clk_out2(clk_out2), // output clk_out2 - // Status and control signals - .resetn(resetn), // input resetn - .locked(locked), // output locked - // Clock in ports - .clk_in1(clk_in1)); // input clk_in1 -// INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc b/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc deleted file mode 100755 index 194ae53..0000000 --- a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc +++ /dev/null @@ -1,60 +0,0 @@ - -# file: clk_wiz_0.xdc -# -# (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# - -# Input clock periods. These duplicate the values entered for the -# input clocks. You can use these to time your system. If required -# commented constraints can be used in the top level xdc -#---------------------------------------------------------------- -# Connect to input port when clock capable pin is selected for input -create_clock -period 8.000 [get_ports clk_in1] -set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.08 - - -set_property PHASESHIFT_MODE WAVEFORM [get_cells -hierarchical *adv*] diff --git a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xml b/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xml deleted file mode 100755 index 539ad13..0000000 --- a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xml +++ /dev/null @@ -1,5025 +0,0 @@ - - - xilinx.com - customized_ip - clk_wiz_0 - 1.0 - - - s_axi_lite - S_AXI_LITE - - - - - - - ARADDR - - - s_axi_araddr - - - - - ARREADY - - - s_axi_arready - - - - - ARVALID - - - s_axi_arvalid - - - - - AWADDR - - - s_axi_awaddr - - - - - AWREADY - - - s_axi_awready - - - - - AWVALID - - - s_axi_awvalid - - - - - BREADY - - - s_axi_bready - - - - - BRESP - - - s_axi_bresp - - - - - BVALID - - - s_axi_bvalid - - - - - RDATA - - - s_axi_rdata - - - - - RREADY - - - s_axi_rready - - - - - RRESP - - - s_axi_rresp - - - - - RVALID - - - s_axi_rvalid - - - - - WDATA - - - s_axi_wdata - - - - - WREADY - - - s_axi_wready - - - - - WSTRB - - - s_axi_wstrb - - - - - WVALID - - - s_axi_wvalid - - - - - - DATA_WIDTH - 1 - - - none - - - - - PROTOCOL - AXI4LITE - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - ID_WIDTH - 0 - - - none - - - - - ADDR_WIDTH - 1 - - - none - - - - - AWUSER_WIDTH - 0 - - - none - - - - - ARUSER_WIDTH - 0 - - - none - - - - - WUSER_WIDTH - 0 - - - none - - - - - RUSER_WIDTH - 0 - - - none - - - - - BUSER_WIDTH - 0 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - HAS_BURST - 0 - - - none - - - - - HAS_LOCK - 0 - - - none - - - - - HAS_PROT - 0 - - - none - - - - - HAS_CACHE - 0 - - - none - - - - - HAS_QOS - 0 - - - none - - - - - HAS_REGION - 0 - - - none - - - - - HAS_WSTRB - 0 - - - none - - - - - HAS_BRESP - 0 - - - none - - - - - HAS_RRESP - 0 - - - none - - - - - SUPPORTS_NARROW_BURST - 0 - - - none - - - - - NUM_READ_OUTSTANDING - 1 - - - none - - - - - NUM_WRITE_OUTSTANDING - 1 - - - none - - - - - MAX_BURST_LENGTH - 1 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - NUM_READ_THREADS - 1 - - - none - - - - - NUM_WRITE_THREADS - 1 - - - none - - - - - RUSER_BITS_PER_BYTE - 0 - - - none - - - - - WUSER_BITS_PER_BYTE - 0 - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - s_axi_aclk - s_axi_aclk - - - - - - - CLK - - - s_axi_aclk - - - - - - ASSOCIATED_BUSIF - s_axi_lite - - - ASSOCIATED_RESET - s_axi_aresetn - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - ref_clk - ref_clk - - - - - - - CLK - - - ref_clk - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - s_axi_resetn - S_AXI_RESETN - - - - - - - RST - - - s_axi_aresetn - - - - - - ASSOCIATED_RESET - aresetn - - - POLARITY - ACTIVE_LOW - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - intr - Intr - - - - - - - INTERRUPT - - - ip2intc_irpt - - - - - - SENSITIVITY - LEVEL_HIGH - - - none - - - - - PortWidth - 1 - - - none - - - - - - - - false - - - - - - CLK_IN1_D - CLK_IN1_D - Differential Clock input - - - - - - - CLK_N - - - clk_in1_n - - - - - CLK_P - - - clk_in1_p - - - - - - BOARD.ASSOCIATED_PARAM - CLK_IN1_BOARD_INTERFACE - - - - required - - - - - - CAN_DEBUG - false - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - - - - false - - - - - - CLK_IN2_D - CLK_IN2_D - Differential Clock input - - - - - - - CLK_N - - - clk_in2_n - - - - - CLK_P - - - clk_in2_p - - - - - - BOARD.ASSOCIATED_PARAM - CLK_IN2_BOARD_INTERFACE - - - - required - - - - - - CAN_DEBUG - false - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - - - - false - - - - - - CLKFB_IN_D - CLKFB_IN_D - Differential Feedback Clock input - - - - - - - CLK_N - - - clkfb_in_n - - - - - CLK_P - - - clkfb_in_p - - - - - - CAN_DEBUG - false - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - - - - false - - - - - - CLKFB_OUT_D - CLKFB_OUT_D - Differential Feeback Clock Output - - - - - - - CLK_N - - - clkfb_out_n - - - - - CLK_P - - - clkfb_out_p - - - - - - CAN_DEBUG - false - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - - - - false - - - - - - reset - reset - - - - - - - RST - - - reset - - - - - - POLARITY - ACTIVE_HIGH - - - BOARD.ASSOCIATED_PARAM - RESET_BOARD_INTERFACE - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - resetn - resetn - - - - - - - RST - - - resetn - - - - - - POLARITY - ACTIVE_LOW - - - BOARD.ASSOCIATED_PARAM - RESET_BOARD_INTERFACE - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - true - - - - - - clock_CLK_IN1 - - - - - - - CLK_IN1 - - - clk_in1 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - BOARD.ASSOCIATED_PARAM - CLK_IN1_BOARD_INTERFACE - - - - - clock_CLK_OUT1 - - - - - - - CLK_OUT1 - - - clk_out1 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - clock_CLK_OUT2 - - - - - - - CLK_OUT2 - - - clk_out2 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - - - xilinx_elaborateports - Elaborate Ports - :vivado.xilinx.com:elaborate.ports - - - outputProductCRC - 9:85cf009a - - - - - xilinx_veriloginstantiationtemplate - Verilog Instantiation Template - verilogSource:vivado.xilinx.com:synthesis.template - verilog - clk_wiz_v6_0_4 - - xilinx_veriloginstantiationtemplate_view_fileset - - - - GENtimestamp - Tue Mar 29 16:40:48 UTC 2022 - - - outputProductCRC - 9:0e034b0f - - - - - xilinx_anylanguagesynthesis - Synthesis - :vivado.xilinx.com:synthesis - clk_wiz_v6_0_4 - - xilinx_anylanguagesynthesis_view_fileset - - - - GENtimestamp - Tue Mar 29 16:40:52 UTC 2022 - - - outputProductCRC - 9:0e034b0f - - - - - xilinx_synthesisconstraints - Synthesis Constraints - :vivado.xilinx.com:synthesis.constraints - - - outputProductCRC - 9:0e034b0f - - - - - xilinx_anylanguagesynthesiswrapper - Synthesis Wrapper - :vivado.xilinx.com:synthesis.wrapper - clk_wiz_0 - - xilinx_anylanguagesynthesiswrapper_view_fileset - - - - GENtimestamp - Tue Mar 29 16:40:52 UTC 2022 - - - outputProductCRC - 9:0e034b0f - - - - - xilinx_anylanguagebehavioralsimulation - Simulation - :vivado.xilinx.com:simulation - clk_wiz_v6_0_4 - - xilinx_anylanguagebehavioralsimulation_view_fileset - - - - GENtimestamp - Tue Mar 29 16:40:52 UTC 2022 - - - outputProductCRC - 9:e2eeadb1 - - - - - xilinx_anylanguagesimulationwrapper - Simulation Wrapper - :vivado.xilinx.com:simulation.wrapper - clk_wiz_0 - - xilinx_anylanguagesimulationwrapper_view_fileset - - - - GENtimestamp - Tue Mar 29 16:40:52 UTC 2022 - - - outputProductCRC - 9:e2eeadb1 - - - - - xilinx_implementation - Implementation - :vivado.xilinx.com:implementation - - xilinx_implementation_view_fileset - - - - GENtimestamp - Tue Mar 29 16:40:52 UTC 2022 - - - outputProductCRC - 9:0e034b0f - - - - - xilinx_versioninformation - Version Information - :vivado.xilinx.com:docs.versioninfo - - xilinx_versioninformation_view_fileset - - - - GENtimestamp - Tue Mar 29 16:40:52 UTC 2022 - - - outputProductCRC - 9:0e034b0f - - - - - xilinx_externalfiles - External Files - :vivado.xilinx.com:external.files - - xilinx_externalfiles_view_fileset - - - - GENtimestamp - Fri Apr 01 12:55:28 UTC 2022 - - - outputProductCRC - 9:0e034b0f - - - - - - - s_axi_aclk - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_aresetn - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_awaddr - - in - - 10 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_awvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_awready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - s_axi_wdata - - in - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_wstrb - - in - - 3 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_wvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_wready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - s_axi_bresp - - out - - 1 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - s_axi_bvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - s_axi_bready - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_araddr - - in - - 10 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_arvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_arready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - s_axi_rdata - - out - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - s_axi_rresp - - out - - 1 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - s_axi_rvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - s_axi_rready - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clk_in1_p - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clk_in1_n - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clk_in2_p - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clk_in2_n - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clkfb_in_p - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clkfb_in_n - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clkfb_out_p - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - clkfb_out_n - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - reset - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - resetn - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - true - - - - - - ref_clk - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clk_stop - - out - - 3 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clk_glitch - - out - - 3 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - interrupt - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clk_oor - - out - - 3 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - user_clk0 - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - user_clk1 - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - user_clk2 - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - user_clk3 - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clk_in1 - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - clk_out1 - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - clk_out2 - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - locked - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - - C_CLKOUT2_USED - 1 - - - C_USER_CLK_FREQ0 - 100.0 - - - C_AUTO_PRIMITIVE - MMCM - - - C_USER_CLK_FREQ1 - 100.0 - - - C_USER_CLK_FREQ2 - 100.0 - - - C_USER_CLK_FREQ3 - 100.0 - - - C_ENABLE_CLOCK_MONITOR - 0 - - - C_ENABLE_USER_CLOCK0 - 0 - - - C_ENABLE_USER_CLOCK1 - 0 - - - C_ENABLE_USER_CLOCK2 - 0 - - - C_ENABLE_USER_CLOCK3 - 0 - - - C_Enable_PLL0 - 0 - - - C_Enable_PLL1 - 0 - - - C_REF_CLK_FREQ - 100.0 - - - C_PRECISION - 1 - - - C_CLKOUT3_USED - 0 - - - C_CLKOUT4_USED - 0 - - - C_CLKOUT5_USED - 0 - - - C_CLKOUT6_USED - 0 - - - C_CLKOUT7_USED - 0 - - - C_USE_CLKOUT1_BAR - 0 - - - C_USE_CLKOUT2_BAR - 0 - - - C_USE_CLKOUT3_BAR - 0 - - - C_USE_CLKOUT4_BAR - 0 - - - c_component_name - clk_wiz_0 - - - C_PLATFORM - UNKNOWN - - - C_USE_FREQ_SYNTH - 1 - - - C_USE_PHASE_ALIGNMENT - 1 - - - C_PRIM_IN_JITTER - 0.010 - - - C_SECONDARY_IN_JITTER - 0.010 - - - C_JITTER_SEL - No_Jitter - - - C_USE_MIN_POWER - 0 - - - C_USE_MIN_O_JITTER - 0 - - - C_USE_MAX_I_JITTER - 0 - - - C_USE_DYN_PHASE_SHIFT - 0 - - - C_USE_INCLK_SWITCHOVER - 0 - - - C_USE_DYN_RECONFIG - 0 - - - C_USE_SPREAD_SPECTRUM - 0 - - - C_USE_FAST_SIMULATION - 0 - - - C_PRIMTYPE_SEL - AUTO - - - C_USE_CLK_VALID - 0 - - - C_PRIM_IN_FREQ - 125 - - - C_PRIM_IN_TIMEPERIOD - 10.000 - - - C_IN_FREQ_UNITS - Units_MHz - - - C_SECONDARY_IN_FREQ - 100.000 - - - C_SECONDARY_IN_TIMEPERIOD - 10.000 - - - C_FEEDBACK_SOURCE - FDBK_AUTO - - - C_PRIM_SOURCE - Single_ended_clock_capable_pin - - - C_PHASESHIFT_MODE - WAVEFORM - - - C_SECONDARY_SOURCE - Single_ended_clock_capable_pin - - - C_CLKFB_IN_SIGNALING - SINGLE - - - C_USE_RESET - 1 - - - C_RESET_LOW - 1 - - - C_USE_LOCKED - 1 - - - C_USE_INCLK_STOPPED - 0 - - - C_USE_CLKFB_STOPPED - 0 - - - C_USE_POWER_DOWN - 0 - - - C_USE_STATUS - 0 - - - C_USE_FREEZE - 0 - - - C_NUM_OUT_CLKS - 2 - - - C_CLKOUT1_DRIVES - BUFG - - - C_CLKOUT2_DRIVES - BUFG - - - C_CLKOUT3_DRIVES - BUFG - - - C_CLKOUT4_DRIVES - BUFG - - - C_CLKOUT5_DRIVES - BUFG - - - C_CLKOUT6_DRIVES - BUFG - - - C_CLKOUT7_DRIVES - BUFG - - - C_INCLK_SUM_ROW0 - Input Clock Freq (MHz) Input Jitter (UI) - - - C_INCLK_SUM_ROW1 - __primary_____________125____________0.010 - - - C_INCLK_SUM_ROW2 - no_secondary_input_clock - - - C_OUTCLK_SUM_ROW0A - C Outclk Sum Row0a - Output Output Phase Duty Cycle Pk-to-Pk Phase - - - C_OUTCLK_SUM_ROW0B - Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) - - - C_OUTCLK_SUM_ROW1 - clk_out1__125.00000______0.000______50.0______119.348_____96.948 - - - C_OUTCLK_SUM_ROW2 - clk_out2__500.00000______0.000______50.0_______92.027_____96.948 - - - C_OUTCLK_SUM_ROW3 - no_CLK_OUT3_output - - - C_OUTCLK_SUM_ROW4 - no_CLK_OUT4_output - - - C_OUTCLK_SUM_ROW5 - no_CLK_OUT5_output - - - C_OUTCLK_SUM_ROW6 - no_CLK_OUT6_output - - - C_OUTCLK_SUM_ROW7 - no_CLK_OUT7_output - - - C_CLKOUT1_REQUESTED_OUT_FREQ - 125 - - - C_CLKOUT2_REQUESTED_OUT_FREQ - 500 - - - C_CLKOUT3_REQUESTED_OUT_FREQ - 100.000 - - - C_CLKOUT4_REQUESTED_OUT_FREQ - 100.000 - - - C_CLKOUT5_REQUESTED_OUT_FREQ - 100.000 - - - C_CLKOUT6_REQUESTED_OUT_FREQ - 100.000 - - - C_CLKOUT7_REQUESTED_OUT_FREQ - 100.000 - - - C_CLKOUT1_REQUESTED_PHASE - 0.000 - - - C_CLKOUT2_REQUESTED_PHASE - 0.000 - - - C_CLKOUT3_REQUESTED_PHASE - 0.000 - - - C_CLKOUT4_REQUESTED_PHASE - 0.000 - - - C_CLKOUT5_REQUESTED_PHASE - 0.000 - - - C_CLKOUT6_REQUESTED_PHASE - 0.000 - - - C_CLKOUT7_REQUESTED_PHASE - 0.000 - - - C_CLKOUT1_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT2_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT3_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT4_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT5_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT6_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT7_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT1_OUT_FREQ - 125.00000 - - - C_CLKOUT2_OUT_FREQ - 500.00000 - - - C_CLKOUT3_OUT_FREQ - 100.000 - - - C_CLKOUT4_OUT_FREQ - 100.000 - - - C_CLKOUT5_OUT_FREQ - 100.000 - - - C_CLKOUT6_OUT_FREQ - 100.000 - - - C_CLKOUT7_OUT_FREQ - 100.000 - - - C_CLKOUT1_PHASE - 0.000 - - - C_CLKOUT2_PHASE - 0.000 - - - C_CLKOUT3_PHASE - 0.000 - - - C_CLKOUT4_PHASE - 0.000 - - - C_CLKOUT5_PHASE - 0.000 - - - C_CLKOUT6_PHASE - 0.000 - - - C_CLKOUT7_PHASE - 0.000 - - - C_CLKOUT1_DUTY_CYCLE - 50.0 - - - C_CLKOUT2_DUTY_CYCLE - 50.0 - - - C_CLKOUT3_DUTY_CYCLE - 50.000 - - - C_CLKOUT4_DUTY_CYCLE - 50.000 - - - C_CLKOUT5_DUTY_CYCLE - 50.000 - - - C_CLKOUT6_DUTY_CYCLE - 50.000 - - - C_CLKOUT7_DUTY_CYCLE - 50.000 - - - C_USE_SAFE_CLOCK_STARTUP - 0 - - - C_USE_CLOCK_SEQUENCING - 0 - - - C_CLKOUT1_SEQUENCE_NUMBER - 1 - - - C_CLKOUT2_SEQUENCE_NUMBER - 1 - - - C_CLKOUT3_SEQUENCE_NUMBER - 1 - - - C_CLKOUT4_SEQUENCE_NUMBER - 1 - - - C_CLKOUT5_SEQUENCE_NUMBER - 1 - - - C_CLKOUT6_SEQUENCE_NUMBER - 1 - - - C_CLKOUT7_SEQUENCE_NUMBER - 1 - - - C_MMCM_NOTES - None - - - C_MMCM_BANDWIDTH - OPTIMIZED - - - C_MMCM_CLKFBOUT_MULT_F - 8.000 - - - C_MMCM_CLKIN1_PERIOD - 8.000 - - - C_MMCM_CLKIN2_PERIOD - 10.000 - - - C_MMCM_CLKOUT4_CASCADE - FALSE - - - C_MMCM_CLOCK_HOLD - FALSE - - - C_MMCM_COMPENSATION - ZHOLD - - - C_MMCM_DIVCLK_DIVIDE - 1 - - - C_MMCM_REF_JITTER1 - 0.010 - - - C_MMCM_REF_JITTER2 - 0.010 - - - C_MMCM_STARTUP_WAIT - FALSE - - - C_MMCM_CLKOUT0_DIVIDE_F - 8.000 - - - C_MMCM_CLKOUT1_DIVIDE - 2 - - - C_MMCM_CLKOUT2_DIVIDE - 1 - - - C_MMCM_CLKOUT3_DIVIDE - 1 - - - C_MMCM_CLKOUT4_DIVIDE - 1 - - - C_MMCM_CLKOUT5_DIVIDE - 1 - - - C_MMCM_CLKOUT6_DIVIDE - 1 - - - C_MMCM_CLKOUT0_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT1_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT2_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT3_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT4_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT5_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT6_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKFBOUT_PHASE - 0.000 - - - C_MMCM_CLKOUT0_PHASE - 0.000 - - - C_MMCM_CLKOUT1_PHASE - 0.000 - - - C_MMCM_CLKOUT2_PHASE - 0.000 - - - C_MMCM_CLKOUT3_PHASE - 0.000 - - - C_MMCM_CLKOUT4_PHASE - 0.000 - - - C_MMCM_CLKOUT5_PHASE - 0.000 - - - C_MMCM_CLKOUT6_PHASE - 0.000 - - - C_MMCM_CLKFBOUT_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT0_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT1_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT2_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT3_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT4_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT5_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT6_USE_FINE_PS - FALSE - - - C_PLL_NOTES - No notes - - - C_PLL_BANDWIDTH - OPTIMIZED - - - C_PLL_CLK_FEEDBACK - CLKFBOUT - - - C_PLL_CLKFBOUT_MULT - 1 - - - C_PLL_CLKIN_PERIOD - 1.000 - - - C_PLL_COMPENSATION - SYSTEM_SYNCHRONOUS - - - C_PLL_DIVCLK_DIVIDE - 1 - - - C_PLL_REF_JITTER - 0.010 - - - C_PLL_CLKOUT0_DIVIDE - 1 - - - C_PLL_CLKOUT1_DIVIDE - 1 - - - C_PLL_CLKOUT2_DIVIDE - 1 - - - C_PLL_CLKOUT3_DIVIDE - 1 - - - C_PLL_CLKOUT4_DIVIDE - 1 - - - C_PLL_CLKOUT5_DIVIDE - 1 - - - C_PLL_CLKOUT0_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT1_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT2_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT3_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT4_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT5_DUTY_CYCLE - 0.500 - - - C_PLL_CLKFBOUT_PHASE - 0.000 - - - C_PLL_CLKOUT0_PHASE - 0.000 - - - C_PLL_CLKOUT1_PHASE - 0.000 - - - C_PLL_CLKOUT2_PHASE - 0.000 - - - C_PLL_CLKOUT3_PHASE - 0.000 - - - C_PLL_CLKOUT4_PHASE - 0.000 - - - C_PLL_CLKOUT5_PHASE - 0.000 - - - C_CLOCK_MGR_TYPE - NA - - - C_OVERRIDE_MMCM - 0 - - - C_OVERRIDE_PLL - 0 - - - C_PRIMARY_PORT - clk_in1 - - - C_SECONDARY_PORT - clk_in2 - - - C_CLK_OUT1_PORT - clk_out1 - - - C_CLK_OUT2_PORT - clk_out2 - - - C_CLK_OUT3_PORT - clk_out3 - - - C_CLK_OUT4_PORT - clk_out4 - - - C_CLK_OUT5_PORT - clk_out5 - - - C_CLK_OUT6_PORT - clk_out6 - - - C_CLK_OUT7_PORT - clk_out7 - - - C_RESET_PORT - resetn - - - C_LOCKED_PORT - locked - - - C_CLKFB_IN_PORT - clkfb_in - - - C_CLKFB_IN_P_PORT - clkfb_in_p - - - C_CLKFB_IN_N_PORT - clkfb_in_n - - - C_CLKFB_OUT_PORT - clkfb_out - - - C_CLKFB_OUT_P_PORT - clkfb_out_p - - - C_CLKFB_OUT_N_PORT - clkfb_out_n - - - C_POWER_DOWN_PORT - power_down - - - C_DADDR_PORT - daddr - - - C_DCLK_PORT - dclk - - - C_DRDY_PORT - drdy - - - C_DWE_PORT - dwe - - - C_DIN_PORT - din - - - C_DOUT_PORT - dout - - - C_DEN_PORT - den - - - C_PSCLK_PORT - psclk - - - C_PSEN_PORT - psen - - - C_PSINCDEC_PORT - psincdec - - - C_PSDONE_PORT - psdone - - - C_CLK_VALID_PORT - CLK_VALID - - - C_STATUS_PORT - STATUS - - - C_CLK_IN_SEL_PORT - clk_in_sel - - - C_INPUT_CLK_STOPPED_PORT - input_clk_stopped - - - C_CLKFB_STOPPED_PORT - clkfb_stopped - - - C_CLKIN1_JITTER_PS - 80.0 - - - C_CLKIN2_JITTER_PS - 100.0 - - - C_PRIMITIVE - MMCM - - - C_SS_MODE - CENTER_HIGH - - - C_SS_MOD_PERIOD - 4000 - - - C_SS_MOD_TIME - 0.004 - - - C_HAS_CDDC - 0 - - - C_CDDCDONE_PORT - cddcdone - - - C_CDDCREQ_PORT - cddcreq - - - C_CLKOUTPHY_MODE - VCO - - - C_ENABLE_CLKOUTPHY - 0 - - - C_INTERFACE_SELECTION - 0 - - - C_S_AXI_ADDR_WIDTH - C S Axi Addr Width - 11 - - - C_S_AXI_DATA_WIDTH - C S Axi Data Width - 32 - - - C_POWER_REG - 0000 - - - C_CLKOUT0_1 - 0000 - - - C_CLKOUT0_2 - 0000 - - - C_CLKOUT1_1 - 0000 - - - C_CLKOUT1_2 - 0000 - - - C_CLKOUT2_1 - 0000 - - - C_CLKOUT2_2 - 0000 - - - C_CLKOUT3_1 - 0000 - - - C_CLKOUT3_2 - 0000 - - - C_CLKOUT4_1 - 0000 - - - C_CLKOUT4_2 - 0000 - - - C_CLKOUT5_1 - 0000 - - - C_CLKOUT5_2 - 0000 - - - C_CLKOUT6_1 - 0000 - - - C_CLKOUT6_2 - 0000 - - - C_CLKFBOUT_1 - 0000 - - - C_CLKFBOUT_2 - 0000 - - - C_DIVCLK - 0000 - - - C_LOCK_1 - 0000 - - - C_LOCK_2 - 0000 - - - C_LOCK_3 - 0000 - - - C_FILTER_1 - 0000 - - - C_FILTER_2 - 0000 - - - C_DIVIDE1_AUTO - 1 - - - C_DIVIDE2_AUTO - 0.25 - - - C_DIVIDE3_AUTO - 1.25 - - - C_DIVIDE4_AUTO - 1.25 - - - C_DIVIDE5_AUTO - 1.25 - - - C_DIVIDE6_AUTO - 1.25 - - - C_DIVIDE7_AUTO - 1.25 - - - C_PLLBUFGCEDIV - false - - - C_MMCMBUFGCEDIV - false - - - C_PLLBUFGCEDIV1 - false - - - C_PLLBUFGCEDIV2 - false - - - C_PLLBUFGCEDIV3 - false - - - C_PLLBUFGCEDIV4 - false - - - C_MMCMBUFGCEDIV1 - false - - - C_MMCMBUFGCEDIV2 - false - - - C_MMCMBUFGCEDIV3 - false - - - C_MMCMBUFGCEDIV4 - false - - - C_MMCMBUFGCEDIV5 - false - - - C_MMCMBUFGCEDIV6 - false - - - C_MMCMBUFGCEDIV7 - false - - - C_CLKOUT1_MATCHED_ROUTING - false - - - C_CLKOUT2_MATCHED_ROUTING - false - - - C_CLKOUT3_MATCHED_ROUTING - false - - - C_CLKOUT4_MATCHED_ROUTING - false - - - C_CLKOUT5_MATCHED_ROUTING - false - - - C_CLKOUT6_MATCHED_ROUTING - false - - - C_CLKOUT7_MATCHED_ROUTING - false - - - C_CLKOUT0_ACTUAL_FREQ - 125.00000 - - - C_CLKOUT1_ACTUAL_FREQ - 500.00000 - - - C_CLKOUT2_ACTUAL_FREQ - 100.000 - - - C_CLKOUT3_ACTUAL_FREQ - 100.000 - - - C_CLKOUT4_ACTUAL_FREQ - 100.000 - - - C_CLKOUT5_ACTUAL_FREQ - 100.000 - - - C_CLKOUT6_ACTUAL_FREQ - 100.000 - - - C_M_MAX - 64.000 - - - C_M_MIN - 2.000 - - - C_D_MAX - 80.000 - - - C_D_MIN - 1.000 - - - C_O_MAX - 128.000 - - - C_O_MIN - 1.000 - - - C_VCO_MIN - 600.000 - - - C_VCO_MAX - 1200.000 - - - - - - choice_list_1d3de01d - WAVEFORM - LATENCY - - - choice_list_876bfc32 - UI - PS - - - choice_list_a9bdfce0 - LOW - HIGH - OPTIMIZED - - - choice_list_ac75ef1e - Custom - - - choice_list_b9d38208 - CLKFBOUT - CLKOUT0 - - - choice_list_e099fe6c - MMCM - PLL - - - choice_pairs_035ca1c3 - SYSTEM_SYNCHRONOUS - SOURCE_SYNCHRONOUS - INTERNAL - EXTERNAL - - - choice_pairs_0920eb1b - Custom - sys_diff_clock - - - choice_pairs_11d71346 - Single_ended_clock_capable_pin - Differential_clock_capable_pin - Global_buffer - No_buffer - - - choice_pairs_15c806d5 - FDBK_AUTO - FDBK_AUTO_OFFCHIP - FDBK_ONCHIP - FDBK_OFFCHIP - - - choice_pairs_340369e0 - Custom - sys_clock - sys_diff_clock - - - choice_pairs_3c2d3ec7 - SINGLE - DIFF - - - choice_pairs_502d9f23 - ZHOLD - EXTERNAL - INTERNAL - BUF_IN - - - choice_pairs_66e4c81f - BUFG - BUFH - BUFGCE - BUFHCE - No_buffer - - - choice_pairs_77d3d587 - MMCM - PLL - BUFGCE_DIV - - - choice_pairs_8b28f1f7 - Enable_AXI - Enable_DRP - - - choice_pairs_8eea9b32 - Units_MHz - Units_ns - - - choice_pairs_a4fbc00c - ACTIVE_HIGH - ACTIVE_LOW - - - choice_pairs_a8642b4c - No_Jitter - Min_O_Jitter - Max_I_Jitter - - - choice_pairs_c5ef7212 - Units_UI - Units_ps - - - choice_pairs_e1c87518 - REL_PRIMARY - REL_SECONDARY - - - choice_pairs_f4e10086 - CENTER_HIGH - CENTER_LOW - DOWN_HIGH - DOWN_LOW - - - choice_pairs_f669c2f5 - frequency - Time - - - - - xilinx_veriloginstantiationtemplate_view_fileset - - clk_wiz_0.veo - verilogTemplate - - - - xilinx_anylanguagesynthesis_view_fileset - - clk_wiz_0.xdc - xdc - - processing_order - early - - - - clk_wiz_0_ooc.xdc - xdc - USED_IN_implementation - USED_IN_out_of_context - USED_IN_synthesis - - - mmcm_pll_drp_func_7s_mmcm.vh - verilogSource - true - clk_wiz_v6_0_4 - - - mmcm_pll_drp_func_7s_pll.vh - verilogSource - true - clk_wiz_v6_0_4 - - - mmcm_pll_drp_func_us_mmcm.vh - verilogSource - true - clk_wiz_v6_0_4 - - - mmcm_pll_drp_func_us_pll.vh - verilogSource - true - clk_wiz_v6_0_4 - - - mmcm_pll_drp_func_us_plus_pll.vh - verilogSource - true - clk_wiz_v6_0_4 - - - mmcm_pll_drp_func_us_plus_mmcm.vh - verilogSource - true - clk_wiz_v6_0_4 - - - clk_wiz_0_clk_wiz.v - verilogSource - - - - xilinx_anylanguagesynthesiswrapper_view_fileset - - clk_wiz_0.v - verilogSource - - - - xilinx_anylanguagebehavioralsimulation_view_fileset - - mmcm_pll_drp_func_7s_mmcm.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_4 - - - mmcm_pll_drp_func_7s_pll.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_4 - - - mmcm_pll_drp_func_us_mmcm.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_4 - - - mmcm_pll_drp_func_us_pll.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_4 - - - mmcm_pll_drp_func_us_plus_pll.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_4 - - - mmcm_pll_drp_func_us_plus_mmcm.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_4 - - - clk_wiz_0_clk_wiz.v - verilogSource - - - - xilinx_anylanguagesimulationwrapper_view_fileset - - clk_wiz_0.v - verilogSource - - - - xilinx_implementation_view_fileset - - clk_wiz_0_board.xdc - xdc - USED_IN_board - USED_IN_implementation - USED_IN_synthesis - - - - xilinx_versioninformation_view_fileset - - doc/clk_wiz_v6_0_changelog.txt - text - - - - xilinx_externalfiles_view_fileset - - clk_wiz_0.dcp - dcp - USED_IN_implementation - USED_IN_synthesis - xil_defaultlib - - - clk_wiz_0_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - clk_wiz_0_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - clk_wiz_0_sim_netlist.v - verilogSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - clk_wiz_0_sim_netlist.vhdl - vhdlSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - - The Clocking Wizard creates an HDL file (Verilog or VHDL) that contains a clocking circuit customized to the user's clocking requirements. - - - Component_Name - clk_wiz_0 - - - USER_CLK_FREQ0 - User Frequency(MHz) - 100.0 - - - USER_CLK_FREQ1 - User Frequency(MHz) - 100.0 - - - USER_CLK_FREQ2 - User Frequency(MHz) - 100.0 - - - USER_CLK_FREQ3 - User Frequency(MHz) - 100.0 - - - ENABLE_CLOCK_MONITOR - Enable Clock Monitoring - false - - - ENABLE_USER_CLOCK0 - User Clock - false - - - ENABLE_USER_CLOCK1 - User Clock - false - - - ENABLE_USER_CLOCK2 - User Clock - false - - - ENABLE_USER_CLOCK3 - User Clock - false - - - Enable_PLL0 - User Clock - false - - - Enable_PLL1 - User Clock - false - - - REF_CLK_FREQ - Reference Frequency(MHz) - 100.0 - - - PRECISION - Tolerance(MHz) - 1 - - - PRIMITIVE - Primitive - MMCM - - - PRIMTYPE_SEL - Primtype Sel - mmcm_adv - - - CLOCK_MGR_TYPE - Clock Mgr Type - auto - - - USE_FREQ_SYNTH - true - - - USE_SPREAD_SPECTRUM - false - - - USE_PHASE_ALIGNMENT - true - - - USE_MIN_POWER - false - - - USE_DYN_PHASE_SHIFT - false - - - USE_DYN_RECONFIG - false - - - JITTER_SEL - No_Jitter - - - PRIM_IN_FREQ - 125 - - - PRIM_IN_TIMEPERIOD - 10.000 - - - IN_FREQ_UNITS - Units_MHz - - - PHASESHIFT_MODE - WAVEFORM - - - IN_JITTER_UNITS - Units_UI - - - RELATIVE_INCLK - REL_PRIMARY - - - USE_INCLK_SWITCHOVER - false - - - SECONDARY_IN_FREQ - 100.000 - - - SECONDARY_IN_TIMEPERIOD - 10.000 - - - SECONDARY_PORT - clk_in2 - - - SECONDARY_SOURCE - Single_ended_clock_capable_pin - - - JITTER_OPTIONS - UI - - - CLKIN1_UI_JITTER - 0.010 - - - CLKIN2_UI_JITTER - 0.010 - - - PRIM_IN_JITTER - 0.010 - - - SECONDARY_IN_JITTER - 0.010 - - - CLKIN1_JITTER_PS - 80.0 - - - CLKIN2_JITTER_PS - 100.0 - - - CLKOUT1_USED - true - - - CLKOUT2_USED - true - - - CLKOUT3_USED - false - - - CLKOUT4_USED - false - - - CLKOUT5_USED - false - - - CLKOUT6_USED - false - - - CLKOUT7_USED - false - - - NUM_OUT_CLKS - 2 - - - CLK_OUT1_USE_FINE_PS_GUI - false - - - CLK_OUT2_USE_FINE_PS_GUI - false - - - CLK_OUT3_USE_FINE_PS_GUI - false - - - CLK_OUT4_USE_FINE_PS_GUI - false - - - CLK_OUT5_USE_FINE_PS_GUI - false - - - CLK_OUT6_USE_FINE_PS_GUI - false - - - CLK_OUT7_USE_FINE_PS_GUI - false - - - PRIMARY_PORT - clk_in1 - - - CLK_OUT1_PORT - clk_out1 - - - CLK_OUT2_PORT - clk_out2 - - - CLK_OUT3_PORT - clk_out3 - - - CLK_OUT4_PORT - clk_out4 - - - CLK_OUT5_PORT - clk_out5 - - - CLK_OUT6_PORT - clk_out6 - - - CLK_OUT7_PORT - clk_out7 - - - DADDR_PORT - daddr - - - DCLK_PORT - dclk - - - DRDY_PORT - drdy - - - DWE_PORT - dwe - - - DIN_PORT - din - - - DOUT_PORT - dout - - - DEN_PORT - den - - - PSCLK_PORT - psclk - - - PSEN_PORT - psen - - - PSINCDEC_PORT - psincdec - - - PSDONE_PORT - psdone - - - CLKOUT1_REQUESTED_OUT_FREQ - 125 - - - CLKOUT1_REQUESTED_PHASE - 0.000 - - - CLKOUT1_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT2_REQUESTED_OUT_FREQ - 500 - - - CLKOUT2_REQUESTED_PHASE - 0.000 - - - CLKOUT2_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT3_REQUESTED_OUT_FREQ - 100.000 - - - CLKOUT3_REQUESTED_PHASE - 0.000 - - - CLKOUT3_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT4_REQUESTED_OUT_FREQ - 100.000 - - - CLKOUT4_REQUESTED_PHASE - 0.000 - - - CLKOUT4_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT5_REQUESTED_OUT_FREQ - 100.000 - - - CLKOUT5_REQUESTED_PHASE - 0.000 - - - CLKOUT5_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT6_REQUESTED_OUT_FREQ - 100.000 - - - CLKOUT6_REQUESTED_PHASE - 0.000 - - - CLKOUT6_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT7_REQUESTED_OUT_FREQ - 100.000 - - - CLKOUT7_REQUESTED_PHASE - 0.000 - - - CLKOUT7_REQUESTED_DUTY_CYCLE - 50.000 - - - USE_MAX_I_JITTER - false - - - USE_MIN_O_JITTER - false - - - CLKOUT1_MATCHED_ROUTING - false - - - CLKOUT2_MATCHED_ROUTING - false - - - CLKOUT3_MATCHED_ROUTING - false - - - CLKOUT4_MATCHED_ROUTING - false - - - CLKOUT5_MATCHED_ROUTING - false - - - CLKOUT6_MATCHED_ROUTING - false - - - CLKOUT7_MATCHED_ROUTING - false - - - PRIM_SOURCE - Single_ended_clock_capable_pin - - - CLKOUT1_DRIVES - BUFG - - - CLKOUT2_DRIVES - BUFG - - - CLKOUT3_DRIVES - BUFG - - - CLKOUT4_DRIVES - BUFG - - - CLKOUT5_DRIVES - BUFG - - - CLKOUT6_DRIVES - BUFG - - - CLKOUT7_DRIVES - BUFG - - - FEEDBACK_SOURCE - FDBK_AUTO - - - CLKFB_IN_SIGNALING - SINGLE - - - CLKFB_IN_PORT - clkfb_in - - - CLKFB_IN_P_PORT - clkfb_in_p - - - CLKFB_IN_N_PORT - clkfb_in_n - - - CLKFB_OUT_PORT - clkfb_out - - - CLKFB_OUT_P_PORT - clkfb_out_p - - - CLKFB_OUT_N_PORT - clkfb_out_n - - - PLATFORM - UNKNOWN - - - SUMMARY_STRINGS - empty - - - USE_LOCKED - true - - - CALC_DONE - empty - - - USE_RESET - true - - - USE_POWER_DOWN - false - - - USE_STATUS - false - - - USE_FREEZE - false - - - USE_CLK_VALID - false - - - USE_INCLK_STOPPED - false - - - USE_CLKFB_STOPPED - false - - - RESET_PORT - resetn - - - LOCKED_PORT - locked - - - POWER_DOWN_PORT - power_down - - - CLK_VALID_PORT - CLK_VALID - - - STATUS_PORT - STATUS - - - CLK_IN_SEL_PORT - clk_in_sel - - - INPUT_CLK_STOPPED_PORT - input_clk_stopped - - - CLKFB_STOPPED_PORT - clkfb_stopped - - - SS_MODE - CENTER_HIGH - - - SS_MOD_FREQ - 250 - - - SS_MOD_TIME - 0.004 - - - OVERRIDE_MMCM - false - - - MMCM_NOTES - None - - - MMCM_DIVCLK_DIVIDE - 1 - - - MMCM_BANDWIDTH - OPTIMIZED - - - MMCM_CLKFBOUT_MULT_F - 8.000 - - - MMCM_CLKFBOUT_PHASE - 0.000 - - - MMCM_CLKFBOUT_USE_FINE_PS - false - - - MMCM_CLKIN1_PERIOD - 8.000 - - - MMCM_CLKIN2_PERIOD - 10.000 - - - MMCM_CLKOUT4_CASCADE - false - - - MMCM_CLOCK_HOLD - false - - - MMCM_COMPENSATION - ZHOLD - - - MMCM_REF_JITTER1 - 0.010 - - - MMCM_REF_JITTER2 - 0.010 - - - MMCM_STARTUP_WAIT - false - - - MMCM_CLKOUT0_DIVIDE_F - 8.000 - - - MMCM_CLKOUT0_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT0_PHASE - 0.000 - - - MMCM_CLKOUT0_USE_FINE_PS - false - - - MMCM_CLKOUT1_DIVIDE - 2 - - - MMCM_CLKOUT1_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT1_PHASE - 0.000 - - - MMCM_CLKOUT1_USE_FINE_PS - false - - - MMCM_CLKOUT2_DIVIDE - 1 - - - MMCM_CLKOUT2_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT2_PHASE - 0.000 - - - MMCM_CLKOUT2_USE_FINE_PS - false - - - MMCM_CLKOUT3_DIVIDE - 1 - - - MMCM_CLKOUT3_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT3_PHASE - 0.000 - - - MMCM_CLKOUT3_USE_FINE_PS - false - - - MMCM_CLKOUT4_DIVIDE - 1 - - - MMCM_CLKOUT4_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT4_PHASE - 0.000 - - - MMCM_CLKOUT4_USE_FINE_PS - false - - - MMCM_CLKOUT5_DIVIDE - 1 - - - MMCM_CLKOUT5_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT5_PHASE - 0.000 - - - MMCM_CLKOUT5_USE_FINE_PS - false - - - MMCM_CLKOUT6_DIVIDE - 1 - - - MMCM_CLKOUT6_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT6_PHASE - 0.000 - - - MMCM_CLKOUT6_USE_FINE_PS - false - - - OVERRIDE_PLL - false - - - PLL_NOTES - None - - - PLL_BANDWIDTH - OPTIMIZED - - - PLL_CLKFBOUT_MULT - 4 - - - PLL_CLKFBOUT_PHASE - 0.000 - - - PLL_CLK_FEEDBACK - CLKFBOUT - - - PLL_DIVCLK_DIVIDE - 1 - - - PLL_CLKIN_PERIOD - 10.000 - - - PLL_COMPENSATION - SYSTEM_SYNCHRONOUS - - - PLL_REF_JITTER - 0.010 - - - PLL_CLKOUT0_DIVIDE - 1 - - - PLL_CLKOUT0_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT0_PHASE - 0.000 - - - PLL_CLKOUT1_DIVIDE - 1 - - - PLL_CLKOUT1_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT1_PHASE - 0.000 - - - PLL_CLKOUT2_DIVIDE - 1 - - - PLL_CLKOUT2_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT2_PHASE - 0.000 - - - PLL_CLKOUT3_DIVIDE - 1 - - - PLL_CLKOUT3_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT3_PHASE - 0.000 - - - PLL_CLKOUT4_DIVIDE - 1 - - - PLL_CLKOUT4_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT4_PHASE - 0.000 - - - PLL_CLKOUT5_DIVIDE - 1 - - - PLL_CLKOUT5_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT5_PHASE - 0.000 - - - RESET_TYPE - Reset Type - ACTIVE_LOW - - - USE_SAFE_CLOCK_STARTUP - false - - - USE_CLOCK_SEQUENCING - false - - - CLKOUT1_SEQUENCE_NUMBER - 1 - - - CLKOUT2_SEQUENCE_NUMBER - 1 - - - CLKOUT3_SEQUENCE_NUMBER - 1 - - - CLKOUT4_SEQUENCE_NUMBER - 1 - - - CLKOUT5_SEQUENCE_NUMBER - 1 - - - CLKOUT6_SEQUENCE_NUMBER - 1 - - - CLKOUT7_SEQUENCE_NUMBER - 1 - - - USE_BOARD_FLOW - Generate Board based IO Constraints - false - - - CLK_IN1_BOARD_INTERFACE - Custom - - - CLK_IN2_BOARD_INTERFACE - Custom - - - DIFF_CLK_IN1_BOARD_INTERFACE - Custom - - - DIFF_CLK_IN2_BOARD_INTERFACE - Custom - - - AUTO_PRIMITIVE - MMCM - - - RESET_BOARD_INTERFACE - Custom - - - ENABLE_CDDC - false - - - CDDCDONE_PORT - cddcdone - - - CDDCREQ_PORT - cddcreq - - - ENABLE_CLKOUTPHY - false - - - CLKOUTPHY_REQUESTED_FREQ - 600.000 - - - CLKOUT1_JITTER - Clkout1 Jitter - 119.348 - - - CLKOUT1_PHASE_ERROR - Clkout1 Phase - 96.948 - - - CLKOUT2_JITTER - Clkout2 Jitter - 92.027 - - - CLKOUT2_PHASE_ERROR - Clkout2 Phase - 96.948 - - - CLKOUT3_JITTER - Clkout3 Jitter - 0.0 - - - CLKOUT3_PHASE_ERROR - Clkout3 Phase - 0.0 - - - CLKOUT4_JITTER - Clkout4 Jitter - 0.0 - - - CLKOUT4_PHASE_ERROR - Clkout4 Phase - 0.0 - - - CLKOUT5_JITTER - Clkout5 Jitter - 0.0 - - - CLKOUT5_PHASE_ERROR - Clkout5 Phase - 0.0 - - - CLKOUT6_JITTER - Clkout6 Jitter - 0.0 - - - CLKOUT6_PHASE_ERROR - Clkout6 Phase - 0.0 - - - CLKOUT7_JITTER - Clkout7 Jitter - 0.0 - - - CLKOUT7_PHASE_ERROR - Clkout7 Phase - 0.0 - - - INPUT_MODE - frequency - - - INTERFACE_SELECTION - Enable_AXI - - - AXI_DRP - Write DRP registers - false - - - PHASE_DUTY_CONFIG - Phase Duty Cycle Config - false - - - - - Clocking Wizard - - XPM_CDC - - 4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2019.2 - - - - - - - - diff --git a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc b/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc deleted file mode 100755 index 3422a8e..0000000 --- a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc +++ /dev/null @@ -1,2 +0,0 @@ -#--------------------Physical Constraints----------------- - diff --git a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v b/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v deleted file mode 100755 index 74148a5..0000000 --- a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v +++ /dev/null @@ -1,213 +0,0 @@ - -// file: clk_wiz_0.v -// -// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -//---------------------------------------------------------------------------- -// User entered comments -//---------------------------------------------------------------------------- -// None -// -//---------------------------------------------------------------------------- -// Output Output Phase Duty Cycle Pk-to-Pk Phase -// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) -//---------------------------------------------------------------------------- -// clk_out1__125.00000______0.000______50.0______119.348_____96.948 -// clk_out2__500.00000______0.000______50.0_______92.027_____96.948 -// -//---------------------------------------------------------------------------- -// Input Clock Freq (MHz) Input Jitter (UI) -//---------------------------------------------------------------------------- -// __primary_____________125____________0.010 - -`timescale 1ps/1ps - -module clk_wiz_0_clk_wiz - - (// Clock in ports - // Clock out ports - output clk_out1, - output clk_out2, - // Status and control signals - input resetn, - output locked, - input clk_in1 - ); - // Input buffering - //------------------------------------ -wire clk_in1_clk_wiz_0; -wire clk_in2_clk_wiz_0; - IBUF clkin1_ibufg - (.O (clk_in1_clk_wiz_0), - .I (clk_in1)); - - - - - // Clocking PRIMITIVE - //------------------------------------ - - // Instantiation of the MMCM PRIMITIVE - // * Unused inputs are tied off - // * Unused outputs are labeled unused - - wire clk_out1_clk_wiz_0; - wire clk_out2_clk_wiz_0; - wire clk_out3_clk_wiz_0; - wire clk_out4_clk_wiz_0; - wire clk_out5_clk_wiz_0; - wire clk_out6_clk_wiz_0; - wire clk_out7_clk_wiz_0; - - wire [15:0] do_unused; - wire drdy_unused; - wire psdone_unused; - wire locked_int; - wire clkfbout_clk_wiz_0; - wire clkfbout_buf_clk_wiz_0; - wire clkfboutb_unused; - wire clkout0b_unused; - wire clkout1b_unused; - wire clkout2_unused; - wire clkout2b_unused; - wire clkout3_unused; - wire clkout3b_unused; - wire clkout4_unused; - wire clkout5_unused; - wire clkout6_unused; - wire clkfbstopped_unused; - wire clkinstopped_unused; - wire reset_high; - - MMCME2_ADV - #(.BANDWIDTH ("OPTIMIZED"), - .CLKOUT4_CASCADE ("FALSE"), - .COMPENSATION ("ZHOLD"), - .STARTUP_WAIT ("FALSE"), - .DIVCLK_DIVIDE (1), - .CLKFBOUT_MULT_F (8.000), - .CLKFBOUT_PHASE (0.000), - .CLKFBOUT_USE_FINE_PS ("FALSE"), - .CLKOUT0_DIVIDE_F (8.000), - .CLKOUT0_PHASE (0.000), - .CLKOUT0_DUTY_CYCLE (0.500), - .CLKOUT0_USE_FINE_PS ("FALSE"), - .CLKOUT1_DIVIDE (2), - .CLKOUT1_PHASE (0.000), - .CLKOUT1_DUTY_CYCLE (0.500), - .CLKOUT1_USE_FINE_PS ("FALSE"), - .CLKIN1_PERIOD (8.000)) - mmcm_adv_inst - // Output clocks - ( - .CLKFBOUT (clkfbout_clk_wiz_0), - .CLKFBOUTB (clkfboutb_unused), - .CLKOUT0 (clk_out1_clk_wiz_0), - .CLKOUT0B (clkout0b_unused), - .CLKOUT1 (clk_out2_clk_wiz_0), - .CLKOUT1B (clkout1b_unused), - .CLKOUT2 (clkout2_unused), - .CLKOUT2B (clkout2b_unused), - .CLKOUT3 (clkout3_unused), - .CLKOUT3B (clkout3b_unused), - .CLKOUT4 (clkout4_unused), - .CLKOUT5 (clkout5_unused), - .CLKOUT6 (clkout6_unused), - // Input clock control - .CLKFBIN (clkfbout_buf_clk_wiz_0), - .CLKIN1 (clk_in1_clk_wiz_0), - .CLKIN2 (1'b0), - // Tied to always select the primary input clock - .CLKINSEL (1'b1), - // Ports for dynamic reconfiguration - .DADDR (7'h0), - .DCLK (1'b0), - .DEN (1'b0), - .DI (16'h0), - .DO (do_unused), - .DRDY (drdy_unused), - .DWE (1'b0), - // Ports for dynamic phase shift - .PSCLK (1'b0), - .PSEN (1'b0), - .PSINCDEC (1'b0), - .PSDONE (psdone_unused), - // Other control and status signals - .LOCKED (locked_int), - .CLKINSTOPPED (clkinstopped_unused), - .CLKFBSTOPPED (clkfbstopped_unused), - .PWRDWN (1'b0), - .RST (reset_high)); - assign reset_high = ~resetn; - - assign locked = locked_int; -// Clock Monitor clock assigning -//-------------------------------------- - // Output buffering - //----------------------------------- - - BUFG clkf_buf - (.O (clkfbout_buf_clk_wiz_0), - .I (clkfbout_clk_wiz_0)); - - - - - - - BUFG clkout1_buf - (.O (clk_out1), - .I (clk_out1_clk_wiz_0)); - - - BUFG clkout2_buf - (.O (clk_out2), - .I (clk_out2_clk_wiz_0)); - - - -endmodule diff --git a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc b/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc deleted file mode 100755 index 82275e5..0000000 --- a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc +++ /dev/null @@ -1,58 +0,0 @@ - -# file: clk_wiz_0_ooc.xdc -# -# (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# - -################# -#DEFAULT CLOCK CONSTRAINTS - -############################################################ -# Clock Period Constraints # -############################################################ -#create_clock -period 8.000 [get_ports clk_in1] - diff --git a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v b/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v deleted file mode 100755 index b5325ca..0000000 --- a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v +++ /dev/null @@ -1,262 +0,0 @@ -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.2 (win64) Build 2700185 Thu Oct 24 18:46:05 MDT 2019 -// Date : Fri Apr 1 15:55:28 2022 -// Host : PAVLOV running 64-bit Service Pack 1 (build 7601) -// Command : write_verilog -force -mode funcsim -// J:/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v -// Design : clk_wiz_0 -// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified -// or synthesized. This netlist cannot be used for SDF annotated simulation. -// Device : xc7z020clg400-1 -// -------------------------------------------------------------------------------- -`timescale 1 ps / 1 ps - -(* NotValidForBitStream *) -module clk_wiz_0 - (clk_out1, - clk_out2, - resetn, - locked, - clk_in1); - output clk_out1; - output clk_out2; - input resetn; - output locked; - input clk_in1; - - (* IBUF_LOW_PWR *) wire clk_in1; - wire clk_out1; - wire clk_out2; - wire locked; - wire resetn; - - clk_wiz_0_clk_wiz_0_clk_wiz inst - (.clk_in1(clk_in1), - .clk_out1(clk_out1), - .clk_out2(clk_out2), - .locked(locked), - .resetn(resetn)); -endmodule - -(* ORIG_REF_NAME = "clk_wiz_0_clk_wiz" *) -module clk_wiz_0_clk_wiz_0_clk_wiz - (clk_out1, - clk_out2, - resetn, - locked, - clk_in1); - output clk_out1; - output clk_out2; - input resetn; - output locked; - input clk_in1; - - wire clk_in1; - wire clk_in1_clk_wiz_0; - wire clk_out1; - wire clk_out1_clk_wiz_0; - wire clk_out2; - wire clk_out2_clk_wiz_0; - wire clkfbout_buf_clk_wiz_0; - wire clkfbout_clk_wiz_0; - wire locked; - wire reset_high; - wire resetn; - wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED; - wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED; - wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED; - wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED; - wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED; - wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED; - wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED; - wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED; - wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED; - wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED; - wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED; - wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED; - wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED; - wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED; - wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED; - - (* BOX_TYPE = "PRIMITIVE" *) - BUFG clkf_buf - (.I(clkfbout_clk_wiz_0), - .O(clkfbout_buf_clk_wiz_0)); - (* BOX_TYPE = "PRIMITIVE" *) - (* CAPACITANCE = "DONT_CARE" *) - (* IBUF_DELAY_VALUE = "0" *) - (* IFD_DELAY_VALUE = "AUTO" *) - IBUF #( - .IOSTANDARD("DEFAULT")) - clkin1_ibufg - (.I(clk_in1), - .O(clk_in1_clk_wiz_0)); - (* BOX_TYPE = "PRIMITIVE" *) - BUFG clkout1_buf - (.I(clk_out1_clk_wiz_0), - .O(clk_out1)); - (* BOX_TYPE = "PRIMITIVE" *) - BUFG clkout2_buf - (.I(clk_out2_clk_wiz_0), - .O(clk_out2)); - (* BOX_TYPE = "PRIMITIVE" *) - MMCME2_ADV #( - .BANDWIDTH("OPTIMIZED"), - .CLKFBOUT_MULT_F(8.000000), - .CLKFBOUT_PHASE(0.000000), - .CLKFBOUT_USE_FINE_PS("FALSE"), - .CLKIN1_PERIOD(8.000000), - .CLKIN2_PERIOD(0.000000), - .CLKOUT0_DIVIDE_F(8.000000), - .CLKOUT0_DUTY_CYCLE(0.500000), - .CLKOUT0_PHASE(0.000000), - .CLKOUT0_USE_FINE_PS("FALSE"), - .CLKOUT1_DIVIDE(2), - .CLKOUT1_DUTY_CYCLE(0.500000), - .CLKOUT1_PHASE(0.000000), - .CLKOUT1_USE_FINE_PS("FALSE"), - .CLKOUT2_DIVIDE(1), - .CLKOUT2_DUTY_CYCLE(0.500000), - .CLKOUT2_PHASE(0.000000), - .CLKOUT2_USE_FINE_PS("FALSE"), - .CLKOUT3_DIVIDE(1), - .CLKOUT3_DUTY_CYCLE(0.500000), - .CLKOUT3_PHASE(0.000000), - .CLKOUT3_USE_FINE_PS("FALSE"), - .CLKOUT4_CASCADE("FALSE"), - .CLKOUT4_DIVIDE(1), - .CLKOUT4_DUTY_CYCLE(0.500000), - .CLKOUT4_PHASE(0.000000), - .CLKOUT4_USE_FINE_PS("FALSE"), - .CLKOUT5_DIVIDE(1), - .CLKOUT5_DUTY_CYCLE(0.500000), - .CLKOUT5_PHASE(0.000000), - .CLKOUT5_USE_FINE_PS("FALSE"), - .CLKOUT6_DIVIDE(1), - .CLKOUT6_DUTY_CYCLE(0.500000), - .CLKOUT6_PHASE(0.000000), - .CLKOUT6_USE_FINE_PS("FALSE"), - .COMPENSATION("ZHOLD"), - .DIVCLK_DIVIDE(1), - .IS_CLKINSEL_INVERTED(1'b0), - .IS_PSEN_INVERTED(1'b0), - .IS_PSINCDEC_INVERTED(1'b0), - .IS_PWRDWN_INVERTED(1'b0), - .IS_RST_INVERTED(1'b0), - .REF_JITTER1(0.010000), - .REF_JITTER2(0.010000), - .SS_EN("FALSE"), - .SS_MODE("CENTER_HIGH"), - .SS_MOD_PERIOD(10000), - .STARTUP_WAIT("FALSE")) - mmcm_adv_inst - (.CLKFBIN(clkfbout_buf_clk_wiz_0), - .CLKFBOUT(clkfbout_clk_wiz_0), - .CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED), - .CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED), - .CLKIN1(clk_in1_clk_wiz_0), - .CLKIN2(1'b0), - .CLKINSEL(1'b1), - .CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED), - .CLKOUT0(clk_out1_clk_wiz_0), - .CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED), - .CLKOUT1(clk_out2_clk_wiz_0), - .CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED), - .CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED), - .CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED), - .CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED), - .CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED), - .CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED), - .CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED), - .CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED), - .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .DCLK(1'b0), - .DEN(1'b0), - .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]), - .DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED), - .DWE(1'b0), - .LOCKED(locked), - .PSCLK(1'b0), - .PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED), - .PSEN(1'b0), - .PSINCDEC(1'b0), - .PWRDWN(1'b0), - .RST(reset_high)); - LUT1 #( - .INIT(2'h1)) - mmcm_adv_inst_i_1 - (.I0(resetn), - .O(reset_high)); -endmodule -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl b/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl deleted file mode 100755 index 78e4adf..0000000 --- a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl +++ /dev/null @@ -1,208 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.2 (win64) Build 2700185 Thu Oct 24 18:46:05 MDT 2019 --- Date : Fri Apr 1 15:55:28 2022 --- Host : PAVLOV running 64-bit Service Pack 1 (build 7601) --- Command : write_vhdl -force -mode funcsim --- J:/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl --- Design : clk_wiz_0 --- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or --- synthesized. This netlist cannot be used for SDF annotated simulation. --- Device : xc7z020clg400-1 --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity clk_wiz_0_clk_wiz_0_clk_wiz is - port ( - clk_out1 : out STD_LOGIC; - clk_out2 : out STD_LOGIC; - resetn : in STD_LOGIC; - locked : out STD_LOGIC; - clk_in1 : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of clk_wiz_0_clk_wiz_0_clk_wiz : entity is "clk_wiz_0_clk_wiz"; -end clk_wiz_0_clk_wiz_0_clk_wiz; - -architecture STRUCTURE of clk_wiz_0_clk_wiz_0_clk_wiz is - signal clk_in1_clk_wiz_0 : STD_LOGIC; - signal clk_out1_clk_wiz_0 : STD_LOGIC; - signal clk_out2_clk_wiz_0 : STD_LOGIC; - signal clkfbout_buf_clk_wiz_0 : STD_LOGIC; - signal clkfbout_clk_wiz_0 : STD_LOGIC; - signal reset_high : STD_LOGIC; - signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC; - signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC; - signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC; - signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC; - signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC; - signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC; - signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC; - signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC; - signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC; - signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC; - signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC; - signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC; - signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC; - signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC; - signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); - attribute BOX_TYPE : string; - attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE"; - attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE"; - attribute CAPACITANCE : string; - attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE"; - attribute IBUF_DELAY_VALUE : string; - attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0"; - attribute IFD_DELAY_VALUE : string; - attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO"; - attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE"; - attribute BOX_TYPE of clkout2_buf : label is "PRIMITIVE"; - attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE"; -begin -clkf_buf: unisim.vcomponents.BUFG - port map ( - I => clkfbout_clk_wiz_0, - O => clkfbout_buf_clk_wiz_0 - ); -clkin1_ibufg: unisim.vcomponents.IBUF - generic map( - IOSTANDARD => "DEFAULT" - ) - port map ( - I => clk_in1, - O => clk_in1_clk_wiz_0 - ); -clkout1_buf: unisim.vcomponents.BUFG - port map ( - I => clk_out1_clk_wiz_0, - O => clk_out1 - ); -clkout2_buf: unisim.vcomponents.BUFG - port map ( - I => clk_out2_clk_wiz_0, - O => clk_out2 - ); -mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV - generic map( - BANDWIDTH => "OPTIMIZED", - CLKFBOUT_MULT_F => 8.000000, - CLKFBOUT_PHASE => 0.000000, - CLKFBOUT_USE_FINE_PS => false, - CLKIN1_PERIOD => 8.000000, - CLKIN2_PERIOD => 0.000000, - CLKOUT0_DIVIDE_F => 8.000000, - CLKOUT0_DUTY_CYCLE => 0.500000, - CLKOUT0_PHASE => 0.000000, - CLKOUT0_USE_FINE_PS => false, - CLKOUT1_DIVIDE => 2, - CLKOUT1_DUTY_CYCLE => 0.500000, - CLKOUT1_PHASE => 0.000000, - CLKOUT1_USE_FINE_PS => false, - CLKOUT2_DIVIDE => 1, - CLKOUT2_DUTY_CYCLE => 0.500000, - CLKOUT2_PHASE => 0.000000, - CLKOUT2_USE_FINE_PS => false, - CLKOUT3_DIVIDE => 1, - CLKOUT3_DUTY_CYCLE => 0.500000, - CLKOUT3_PHASE => 0.000000, - CLKOUT3_USE_FINE_PS => false, - CLKOUT4_CASCADE => false, - CLKOUT4_DIVIDE => 1, - CLKOUT4_DUTY_CYCLE => 0.500000, - CLKOUT4_PHASE => 0.000000, - CLKOUT4_USE_FINE_PS => false, - CLKOUT5_DIVIDE => 1, - CLKOUT5_DUTY_CYCLE => 0.500000, - CLKOUT5_PHASE => 0.000000, - CLKOUT5_USE_FINE_PS => false, - CLKOUT6_DIVIDE => 1, - CLKOUT6_DUTY_CYCLE => 0.500000, - CLKOUT6_PHASE => 0.000000, - CLKOUT6_USE_FINE_PS => false, - COMPENSATION => "ZHOLD", - DIVCLK_DIVIDE => 1, - IS_CLKINSEL_INVERTED => '0', - IS_PSEN_INVERTED => '0', - IS_PSINCDEC_INVERTED => '0', - IS_PWRDWN_INVERTED => '0', - IS_RST_INVERTED => '0', - REF_JITTER1 => 0.010000, - REF_JITTER2 => 0.010000, - SS_EN => "FALSE", - SS_MODE => "CENTER_HIGH", - SS_MOD_PERIOD => 10000, - STARTUP_WAIT => false - ) - port map ( - CLKFBIN => clkfbout_buf_clk_wiz_0, - CLKFBOUT => clkfbout_clk_wiz_0, - CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED, - CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED, - CLKIN1 => clk_in1_clk_wiz_0, - CLKIN2 => '0', - CLKINSEL => '1', - CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED, - CLKOUT0 => clk_out1_clk_wiz_0, - CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED, - CLKOUT1 => clk_out2_clk_wiz_0, - CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED, - CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED, - CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED, - CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED, - CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED, - CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED, - CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED, - CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED, - DADDR(6 downto 0) => B"0000000", - DCLK => '0', - DEN => '0', - DI(15 downto 0) => B"0000000000000000", - DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0), - DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED, - DWE => '0', - LOCKED => locked, - PSCLK => '0', - PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED, - PSEN => '0', - PSINCDEC => '0', - PWRDWN => '0', - RST => reset_high - ); -mmcm_adv_inst_i_1: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => resetn, - O => reset_high - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity clk_wiz_0 is - port ( - clk_out1 : out STD_LOGIC; - clk_out2 : out STD_LOGIC; - resetn : in STD_LOGIC; - locked : out STD_LOGIC; - clk_in1 : in STD_LOGIC - ); - attribute NotValidForBitStream : boolean; - attribute NotValidForBitStream of clk_wiz_0 : entity is true; -end clk_wiz_0; - -architecture STRUCTURE of clk_wiz_0 is -begin -inst: entity work.clk_wiz_0_clk_wiz_0_clk_wiz - port map ( - clk_in1 => clk_in1, - clk_out1 => clk_out1, - clk_out2 => clk_out2, - locked => locked, - resetn => resetn - ); -end STRUCTURE; diff --git a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v b/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v deleted file mode 100755 index b417cf1..0000000 --- a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v +++ /dev/null @@ -1,23 +0,0 @@ -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.2 (win64) Build 2700185 Thu Oct 24 18:46:05 MDT 2019 -// Date : Fri Apr 1 15:55:28 2022 -// Host : PAVLOV running 64-bit Service Pack 1 (build 7601) -// Command : write_verilog -force -mode synth_stub -// J:/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v -// Design : clk_wiz_0 -// Purpose : Stub declaration of top-level module interface -// Device : xc7z020clg400-1 -// -------------------------------------------------------------------------------- - -// This empty module with port declaration file causes synthesis tools to infer a black box for IP. -// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. -// Please paste the declaration into a Verilog source file or add the file as an additional source. -module clk_wiz_0(clk_out1, clk_out2, resetn, locked, clk_in1) -/* synthesis syn_black_box black_box_pad_pin="clk_out1,clk_out2,resetn,locked,clk_in1" */; - output clk_out1; - output clk_out2; - input resetn; - output locked; - input clk_in1; -endmodule diff --git a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl b/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl deleted file mode 100755 index 87ae43b..0000000 --- a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl +++ /dev/null @@ -1,32 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.2 (win64) Build 2700185 Thu Oct 24 18:46:05 MDT 2019 --- Date : Fri Apr 1 15:55:28 2022 --- Host : PAVLOV running 64-bit Service Pack 1 (build 7601) --- Command : write_vhdl -force -mode synth_stub --- J:/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl --- Design : clk_wiz_0 --- Purpose : Stub declaration of top-level module interface --- Device : xc7z020clg400-1 --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -entity clk_wiz_0 is - Port ( - clk_out1 : out STD_LOGIC; - clk_out2 : out STD_LOGIC; - resetn : in STD_LOGIC; - locked : out STD_LOGIC; - clk_in1 : in STD_LOGIC - ); - -end clk_wiz_0; - -architecture stub of clk_wiz_0 is -attribute syn_black_box : boolean; -attribute black_box_pad_pin : string; -attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "clk_out1,clk_out2,resetn,locked,clk_in1"; -begin -end; diff --git a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/doc/clk_wiz_v6_0_changelog.txt b/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/doc/clk_wiz_v6_0_changelog.txt deleted file mode 100755 index 1a87123..0000000 --- a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/doc/clk_wiz_v6_0_changelog.txt +++ /dev/null @@ -1,211 +0,0 @@ -2019.2: - * Version 6.0 (Rev. 4) - * Bug Fix: Internal GUI fixes - * Other: CR Fixes - -2019.1.3: - * Version 6.0 (Rev. 3) - * No changes - -2019.1.2: - * Version 6.0 (Rev. 3) - * No changes - -2019.1.1: - * Version 6.0 (Rev. 3) - * No changes - -2019.1: - * Version 6.0 (Rev. 3) - * Bug Fix: Internal GUI fixes - * Other: New family support added - -2018.3.1: - * Version 6.0 (Rev. 2) - * No changes - -2018.3: - * Version 6.0 (Rev. 2) - * Bug Fix: Made input source independent for primary and secondary clock - * Other: New family support added - -2018.2: - * Version 6.0 (Rev. 1) - * Bug Fix: Removed vco freq check when Primitive is None - * Other: New family support added - -2018.1: - * Version 6.0 - * Bug Fix: Bug fixes in Dynamic Reconfiguration feature and Write DRP feature - * Bug Fix: Bug fixes for connection issue for s_axi_aresetn pin in IPI - * Feature Enhancement: The default value of USE_PHASE_ALIGMENT is updated to false for UltraScale and UltraScale+ devices. Phase Alignment feature uses extra clock routes in UltraScale and UltraScale+ designs when MMCMs are used. These routing resources are wasted when user do not understand when phase alignment is really needed. Now, implementation tools can use these extra clock routing resources for high fanout signals. - * Feature Enhancement: A column "Max. freq of buffer" is added in the Output Clock table which shows the maximum frequency that the selected output buffer can support - * Other: DRCs added for invalid input values in Override mode - -2017.4: - * Version 5.4 (Rev. 3) - * Bug Fix: Internal GUI issues are fixed for COMPENSATION mode as INTERNAL - * Bug Fix: Fixed issue in dynamic reconfiguration of fractional values of M in MMCME3, MMCME4 - -2017.3: - * Version 5.4 (Rev. 2) - * General: Internal GUI changes. No effect on the customer design. Added support for aspartan7 devices - -2017.2: - * Version 5.4 (Rev. 1) - * General: Internal GUI changes. No effect on the customer design. - -2017.1: - * Version 5.4 - * Port Change: Minor version upgrade. CLR pins are added to the pin list when selected buffer is BUFGCEDIV for ultrascale and ultrascale plus devices. - * Other: Added support for new zynq ultrascale plus devices. - -2016.4: - * Version 5.3 (Rev. 3) - * Bug Fix: Internal GUI issues are fixed. - -2016.3: - * Version 5.3 (Rev. 2) - * Feature Enhancement: Added new option "Auto" under PRIMITIVE selection for ultrascale and above devices. This option allows the Wizard to instantiate appropriate primitive for the user inputs. - * Feature Enhancement: Added Matched Routing Option for better timing solutions. - * Feature Enhancement: Options 'Buffer' and 'Buffer_with_CE' are added to the buffer selection list. - * Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user - * Other: Added support for Spartan7 devices. - -2016.2: - * Version 5.3 (Rev. 1) - * Internal register bit update, no effect on customer designs. - -2016.1: - * Version 5.3 - * Added Clock Monitor Feature as part of clocking wizard - * DRP registers can be directly written through AXI without resource utilization - * Changes to HDL library management to support Vivado IP simulation library - -2015.4.2: - * Version 5.2 (Rev. 1) - * No changes - -2015.4.1: - * Version 5.2 (Rev. 1) - * No changes - -2015.4: - * Version 5.2 (Rev. 1) - * Internal device family change, no functional changes - -2015.3: - * Version 5.2 - * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances - * Port Renaming tab is hidden in the GUI in IP Integrator as this feature is not supported - * Phase alignment feature is removed for ultrascale PLL as primitve has limited capabilities of supporting this feature - * When clocking wizard is targetted on a board part, the frequency values that gets propagated to primary and secondary clocks are displayed in floating number format - * Example design and simulation files are delivered in verilog only - -2015.2.1: - * Version 5.1 (Rev. 6) - * No changes - -2015.2: - * Version 5.1 (Rev. 6) - * No changes - -2015.1: - * Version 5.1 (Rev. 6) - * Updated mmcm_pll_filter_lookup and mmcm_pll_lock_lookup functions in the header file for 7-Series and UltraScale devices - * Supported devices and production status are now determined automatically, to simplify support for future devices - -2014.4.1: - * Version 5.1 (Rev. 5) - * No changes - -2014.4: - * Version 5.1 (Rev. 5) - * Internal device family change, no functional changes - * updates related to the source selection based on board interface for zed board - -2014.3: - * Version 5.1 (Rev. 4) - * Option added to enable dynamic phase and duty cycle for resource optimization in AXI4-Lite interface - -2014.2: - * Version 5.1 (Rev. 3) - * Updated for AXI4-Lite interface locked status register address and bit mapping to align with the pg065 - -2014.1: - * Version 5.1 (Rev. 2) - * Updated to use inverted output CLKOUTB 0-3 of Clocking Primitive based on requested 180 phase w.r.t. previous clock - * Internal device family name change, no functional changes - -2013.4: - * Version 5.1 (Rev. 1) - * Added support for Ultrascale devices - * Updated Board Flow GUI to select the clock interfaces - * Fixed issue with Stub file parameter error for BUFR output driver - -2013.3: - * Version 5.1 - * Added AXI4-Lite interface to dynamically reconfigure MMCM/PLL - * Improved safe clock logic to remove glitches on clock outputs for odd multiples of input clock frequencies - * Fixed precision issues between displayed and actual frequencies - * Added tool tips to GUI - * Added Jitter and Phase error values to IP properties - * Added support for Cadence IES and Synopsys VCS simulators - * Reduced warnings in synthesis and simulation - * Enhanced support for IP Integrator - -2013.2: - * Version 5.0 (Rev. 1) - * Fixed issue with clock constraints for multiple instances of clocking wizard - * Updated Life-Cycle status of devices - -2013.1: - * Version 5.0 - * Lower case ports for Verilog - * Added Safe Clock Startup and Clock Sequencing - -(c) Copyright 2008 - 2019 Xilinx, Inc. All rights reserved. - -This file contains confidential and proprietary information -of Xilinx, Inc. and is protected under U.S. and -international copyright and other intellectual property -laws. - -DISCLAIMER -This disclaimer is not a license and does not grant any -rights to the materials distributed herewith. Except as -otherwise provided in a valid license issued to you by -Xilinx, and to the maximum extent permitted by applicable -law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -(2) Xilinx shall not be liable (whether in contract or tort, -including negligence, or under any other theory of -liability) for any loss or damage of any kind or nature -related to, arising under or in connection with these -materials, including for any direct, or any indirect, -special, incidental, or consequential loss or damage -(including loss of data, profits, goodwill, or any type of -loss or damage suffered as a result of any action brought -by a third party) even if such damage or loss was -reasonably foreseeable or Xilinx had been advised of the -possibility of the same. - -CRITICAL APPLICATIONS -Xilinx products are not designed or intended to be fail- -safe, or for use in any application requiring fail-safe -performance, such as life-support or safety devices or -systems, Class III medical devices, nuclear facilities, -applications related to the deployment of airbags, or any -other applications that could lead to death, personal -injury, or severe property or environmental damage -(individually and collectively, "Critical -Applications"). Customer assumes the sole risk and -liability of any use of Xilinx products in Critical -Applications, subject only to applicable laws and -regulations governing limitations on product liability. - -THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -PART OF THIS FILE AT ALL TIMES. diff --git a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_mmcm.vh b/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_mmcm.vh deleted file mode 100755 index 652d7d1..0000000 --- a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_mmcm.vh +++ /dev/null @@ -1,671 +0,0 @@ -/////////////////////////////////////////////////////////////////////////////// -// -// Company: Xilinx -// Engineer: Jim Tatsukawa, Karl Kurbjun and Carl Ribbing -// Date: 7/30/2014 -// Design Name: MMCME2 DRP -// Module Name: mmcme2_drp_func.h -// Version: 1.04 -// Target Devices: 7 Series || MMCM -// Tool versions: 2014.3 -// Description: This header provides the functions necessary to -// calculate the DRP register values for the V6 MMCM. -// -// Revision Notes: 3/12 - Updating lookup_low/lookup_high (CR) -// 4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807 -// -// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR -// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING -// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -// APPLICATION OR STANDARD, XILINX IS MAKING NO -// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE -// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY -// REQUIRE FOR YOUR IMPLEMENTATION. XILINX -// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH -// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, -// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE -// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES -// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -// PURPOSE. -// -// (c) Copyright 2009-2010 Xilinx, Inc. -// All rights reserved. -// -/////////////////////////////////////////////////////////////////////////////// - -// These are user functions that should not be modified. Changes to the defines -// or code within the functions may alter the accuracy of the calculations. - -// Define debug to provide extra messages durring elaboration -//`define DEBUG 1 - -// FRAC_PRECISION describes the width of the fractional portion of the fixed -// point numbers. These should not be modified, they are for development -// only -`define FRAC_PRECISION 10 -// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). -// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs -// greater than 32 -`define FIXED_WIDTH 32 - -// This function takes a fixed point number and rounds it to the nearest -// fractional precision bit. -function [`FIXED_WIDTH:1] round_frac - ( - // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number - input [`FIXED_WIDTH:1] decimal, - - // This describes the precision of the fraction, for example a value - // of 1 would modify the fractional so that instead of being a .16 - // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) - input [`FIXED_WIDTH:1] precision - ); - - begin - - `ifdef DEBUG - $display("round_frac - decimal: %h, precision: %h", decimal, precision); - `endif - // If the fractional precision bit is high then round up - if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin - round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); - end else begin - round_frac = decimal; - end - `ifdef DEBUG - $display("round_frac: %h", round_frac); - `endif - end -endfunction - -// This function calculates high_time, low_time, w_edge, and no_count -// of a non-fractional counter based on the divide and duty cycle -// -// NOTE: high_time and low_time are returned as integers between 0 and 63 -// inclusive. 64 should equal 6'b000000 (in other words it is okay to -// ignore the overflow) -function [13:0] mmcm_pll_divider - ( - input [7:0] divide, // Max divide is 128 - input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 - ); - - reg [`FIXED_WIDTH:1] duty_cycle_fix; - - // High/Low time is initially calculated with a wider integer to prevent a - // calculation error when it overflows to 64. - reg [6:0] high_time; - reg [6:0] low_time; - reg w_edge; - reg no_count; - - reg [`FIXED_WIDTH:1] temp; - - begin - // Duty Cycle must be between 0 and 1,000 - if(duty_cycle <=0 || duty_cycle >= 100000) begin -`ifndef SYNTHESIS - $display("ERROR: duty_cycle: %d is invalid", duty_cycle); - `endif - $finish; - end - - // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point - duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; - - `ifdef DEBUG - $display("duty_cycle_fix: %h", duty_cycle_fix); - `endif - - // If the divide is 1 nothing needs to be set except the no_count bit. - // Other values are dummies - if(divide == 7'h01) begin - high_time = 7'h01; - w_edge = 1'b0; - low_time = 7'h01; - no_count = 1'b1; - end else begin - temp = round_frac(duty_cycle_fix*divide, 1); - - // comes from above round_frac - high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; - // If the duty cycle * divide rounded is .5 or greater then this bit - // is set. - w_edge = temp[`FRAC_PRECISION]; // comes from round_frac - - // If the high time comes out to 0, it needs to be set to at least 1 - // and w_edge set to 0 - if(high_time == 7'h00) begin - high_time = 7'h01; - w_edge = 1'b0; - end - - if(high_time == divide) begin - high_time = divide - 1; - w_edge = 1'b1; - end - - // Calculate low_time based on the divide setting and set no_count to - // 0 as it is only used when divide is 1. - low_time = divide - high_time; - no_count = 1'b0; - end - - // Set the return value. - mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; - end -endfunction - -// This function calculates mx, delay_time, and phase_mux -// of a non-fractional counter based on the divide and phase -// -// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux -// is used. -function [10:0] mmcm_pll_phase - ( - // divide must be an integer (use fractional if not) - // assumed that divide already checked to be valid - input [7:0] divide, // Max divide is 128 - - // Phase is given in degrees (-360,000 to 360,000) - input signed [31:0] phase - ); - - reg [`FIXED_WIDTH:1] phase_in_cycles; - reg [`FIXED_WIDTH:1] phase_fixed; - reg [1:0] mx; - reg [5:0] delay_time; - reg [2:0] phase_mux; - - reg [`FIXED_WIDTH:1] temp; - - begin -`ifdef DEBUG - $display("mmcm_pll_phase-divide:%d,phase:%d", - divide, phase); -`endif - - if ((phase < -360000) || (phase > 360000)) begin -`ifndef SYNTHESIS - $display("ERROR: phase of $phase is not between -360000 and 360000"); - `endif - $finish; - end - - // If phase is less than 0, convert it to a positive phase shift - // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point - if(phase < 0) begin - phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; - end else begin - phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; - end - - // Put phase in terms of decimal number of vco clock cycles - phase_in_cycles = ( phase_fixed * divide ) / 360; - -`ifdef DEBUG - $display("phase_in_cycles: %h", phase_in_cycles); -`endif - - - temp = round_frac(phase_in_cycles, 3); - - // set mx to 2'b00 that the phase mux from the VCO is enabled - mx = 2'b00; - phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; - delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; - - `ifdef DEBUG - $display("temp: %h", temp); - `endif - - // Setup the return value - mmcm_pll_phase={mx, phase_mux, delay_time}; - end -endfunction - -// This function takes the divide value and outputs the necessary lock values -function [39:0] mmcm_pll_lock_lookup - ( - input [6:0] divide // Max divide is 64 - ); - - reg [2559:0] lookup; - - begin - lookup = { - // This table is composed of: - // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt - 40'b00110_00110_1111101000_1111101001_0000000001, - 40'b00110_00110_1111101000_1111101001_0000000001, - 40'b01000_01000_1111101000_1111101001_0000000001, - 40'b01011_01011_1111101000_1111101001_0000000001, - 40'b01110_01110_1111101000_1111101001_0000000001, - 40'b10001_10001_1111101000_1111101001_0000000001, - 40'b10011_10011_1111101000_1111101001_0000000001, - 40'b10110_10110_1111101000_1111101001_0000000001, - 40'b11001_11001_1111101000_1111101001_0000000001, - 40'b11100_11100_1111101000_1111101001_0000000001, - 40'b11111_11111_1110000100_1111101001_0000000001, - 40'b11111_11111_1100111001_1111101001_0000000001, - 40'b11111_11111_1011101110_1111101001_0000000001, - 40'b11111_11111_1010111100_1111101001_0000000001, - 40'b11111_11111_1010001010_1111101001_0000000001, - 40'b11111_11111_1001110001_1111101001_0000000001, - 40'b11111_11111_1000111111_1111101001_0000000001, - 40'b11111_11111_1000100110_1111101001_0000000001, - 40'b11111_11111_1000001101_1111101001_0000000001, - 40'b11111_11111_0111110100_1111101001_0000000001, - 40'b11111_11111_0111011011_1111101001_0000000001, - 40'b11111_11111_0111000010_1111101001_0000000001, - 40'b11111_11111_0110101001_1111101001_0000000001, - 40'b11111_11111_0110010000_1111101001_0000000001, - 40'b11111_11111_0110010000_1111101001_0000000001, - 40'b11111_11111_0101110111_1111101001_0000000001, - 40'b11111_11111_0101011110_1111101001_0000000001, - 40'b11111_11111_0101011110_1111101001_0000000001, - 40'b11111_11111_0101000101_1111101001_0000000001, - 40'b11111_11111_0101000101_1111101001_0000000001, - 40'b11111_11111_0100101100_1111101001_0000000001, - 40'b11111_11111_0100101100_1111101001_0000000001, - 40'b11111_11111_0100101100_1111101001_0000000001, - 40'b11111_11111_0100010011_1111101001_0000000001, - 40'b11111_11111_0100010011_1111101001_0000000001, - 40'b11111_11111_0100010011_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001 - }; - - // Set lookup_entry with the explicit bits from lookup with a part select - mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; - `ifdef DEBUG - $display("lock_lookup: %b", mmcm_pll_lock_lookup); - `endif - end -endfunction - -// This function takes the divide value and the bandwidth setting of the MMCM -// and outputs the digital filter settings necessary. -function [9:0] mmcm_pll_filter_lookup - ( - input [6:0] divide, // Max divide is 64 - input [8*9:0] BANDWIDTH - ); - - reg [639:0] lookup_low; - reg [639:0] lookup_high; - - reg [9:0] lookup_entry; - - begin - lookup_low = { - // CP_RES_LFHF - 10'b0010_1111_00, - 10'b0010_1111_00, - 10'b0010_1111_00, - 10'b0010_1111_00, - 10'b0010_0111_00, - 10'b0010_1011_00, - 10'b0010_1101_00, - 10'b0010_0011_00, - 10'b0010_0101_00, - 10'b0010_0101_00, - 10'b0010_1001_00, - 10'b0010_1110_00, - 10'b0010_1110_00, - 10'b0010_1110_00, - 10'b0010_1110_00, - 10'b0010_0001_00, - 10'b0010_0001_00, - 10'b0010_0001_00, - 10'b0010_0110_00, - 10'b0010_0110_00, - 10'b0010_0110_00, - 10'b0010_0110_00, - 10'b0010_0110_00, - 10'b0010_0110_00, - 10'b0010_0110_00, - 10'b0010_1010_00, - 10'b0010_1010_00, - 10'b0010_1010_00, - 10'b0010_1010_00, - 10'b0010_1010_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00 - }; - - lookup_high = { - // CP_RES_LFHF - 10'b0010_1111_00, - 10'b0100_1111_00, - 10'b0101_1011_00, - 10'b0111_0111_00, - 10'b1101_0111_00, - 10'b1110_1011_00, - 10'b1110_1101_00, - 10'b1111_0011_00, - 10'b1110_0101_00, - 10'b1111_0101_00, - 10'b1111_1001_00, - 10'b1101_0001_00, - 10'b1111_1001_00, - 10'b1111_1001_00, - 10'b1111_1001_00, - 10'b1111_1001_00, - 10'b1111_0101_00, - 10'b1111_0101_00, - 10'b1100_0001_00, - 10'b1100_0001_00, - 10'b1100_0001_00, - 10'b0101_1100_00, - 10'b0101_1100_00, - 10'b0101_1100_00, - 10'b0101_1100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0111_0001_00, - 10'b0111_0001_00, - 10'b0100_1100_00, - 10'b0100_1100_00, - 10'b0100_1100_00, - 10'b0100_1100_00, - 10'b0110_0001_00, - 10'b0110_0001_00, - 10'b0101_0110_00, - 10'b0101_0110_00, - 10'b0101_0110_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0100_1010_00, - 10'b0011_1100_00, - 10'b0011_1100_00 - }; - - // Set lookup_entry with the explicit bits from lookup with a part select - if(BANDWIDTH == "LOW") begin - // Low Bandwidth - mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; - end else begin - // High or optimized bandwidth - mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; - end - - `ifdef DEBUG - $display("filter_lookup: %b", mmcm_pll_filter_lookup); - `endif - end -endfunction - -// This function takes in the divide, phase, and duty cycle -// setting to calculate the upper and lower counter registers. -function [37:0] mmcm_pll_count_calc - ( - input [7:0] divide, // Max divide is 128 - input signed [31:0] phase, - input [31:0] duty_cycle // Multiplied by 100,000 - ); - - reg [13:0] div_calc; - reg [16:0] phase_calc; - - begin - `ifdef DEBUG - $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", - divide, phase, duty_cycle); - `endif - - // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] - div_calc = mmcm_pll_divider(divide, duty_cycle); - // mx[10:9], pm[8:6], dt[5:0] - phase_calc = mmcm_pll_phase(divide, phase); - - // Return value is the upper and lower address of counter - // Upper address is: - // RESERVED [31:26] - // MX [25:24] - // EDGE [23] - // NOCOUNT [22] - // DELAY_TIME [21:16] - // Lower Address is: - // PHASE_MUX [15:13] - // RESERVED [12] - // HIGH_TIME [11:6] - // LOW_TIME [5:0] - - `ifdef DEBUG - $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", - divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], - div_calc[13], div_calc[12], - phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); - `endif - - mmcm_pll_count_calc = - { - // Upper Address - 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], - // Lower Address - phase_calc[8:6], 1'b0, div_calc[11:0] - }; - end -endfunction - - -// This function takes in the divide, phase, and duty cycle -// setting to calculate the upper and lower counter registers. -// for fractional multiply/divide functions. -// -// -function [37:0] mmcm_frac_count_calc - ( - input [7:0] divide, // Max divide is 128 - input signed [31:0] phase, - input [31:0] duty_cycle, // Multiplied by 1,000 - input [9:0] frac // Multiplied by 1000 - ); - - //Required for fractional divide calculations - reg [7:0] lt_frac; - reg [7:0] ht_frac; - - reg /*[7:0]*/ wf_fall_frac; - reg /*[7:0]*/ wf_rise_frac; - - reg [31:0] a; - reg [7:0] pm_rise_frac_filtered ; - reg [7:0] pm_fall_frac_filtered ; - reg [7:0] clkout0_divide_int; - reg [2:0] clkout0_divide_frac; - reg [7:0] even_part_high; - reg [7:0] even_part_low; - - reg [7:0] odd; - reg [7:0] odd_and_frac; - - reg [7:0] pm_fall; - reg [7:0] pm_rise; - reg [7:0] dt; - reg [7:0] dt_int; - reg [63:0] dt_calc; - - reg [7:0] pm_rise_frac; - reg [7:0] pm_fall_frac; - - reg [31:0] a_per_in_octets; - reg [31:0] a_phase_in_cycles; - - parameter precision = 0.125; - - reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 - reg [31: 0] phase_pos; - reg [31: 0] phase_vco; - reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 - reg [13:0] div_calc; - reg [16:0] phase_calc; - - begin - `ifdef DEBUG - $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", - divide, phase, duty_cycle); - `endif - - //convert phase to fixed - if ((phase < -360000) || (phase > 360000)) begin -`ifndef SYNTHESIS - $display("ERROR: phase of $phase is not between -360000 and 360000"); - `endif - $finish; - end - - - // Return value is - // Transfer data - // RESERVED [37:36] - // FRAC_TIME [35:33] - // FRAC_WF_FALL [32] - // Upper address is: - // RESERVED [31:26] - // MX [25:24] - // EDGE [23] - // NOCOUNT [22] - // DELAY_TIME [21:16] - // Lower Address is: - // PHASE_MUX [15:13] - // RESERVED [12] - // HIGH_TIME [11:6] - // LOW_TIME [5:0] - - - - clkout0_divide_frac = frac / 125; - clkout0_divide_int = divide; - - even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); - even_part_low = even_part_high; - - odd = clkout0_divide_int - even_part_high - even_part_low; - odd_and_frac = (8*odd) + clkout0_divide_frac; - - lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) - ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) - - pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 - pm_rise = 0; //0 - - wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807 - wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) - - - - //Calculate phase in fractional cycles - a_per_in_octets = (8 * divide) + (frac / 125) ; - a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors - pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; - - dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) - dt = dt_calc[7:0]; - - pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; - - dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) - pm_fall_frac = pm_fall + pm_rise_frac; - pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; - - div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] - phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} - - mmcm_frac_count_calc[37:0] = - { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, - 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], - pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] - } ; - - `ifdef DEBUG - $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac); - `endif - - end -endfunction - diff --git a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_pll.vh b/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_pll.vh deleted file mode 100755 index 6a3e7c0..0000000 --- a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_pll.vh +++ /dev/null @@ -1,531 +0,0 @@ -/////////////////////////////////////////////////////////////////////////////// -// -// Company: Xilinx -// Engineer: Jim Tatsukawa, Karl Kurbjun and Carl Ribbing -// Date: 7/30/2014 -// Design Name: PLLE2 DRP -// Module Name: plle2_drp_func.h -// Version: 2.00 -// Target Devices: 7 Series || PLL -// Tool versions: 2014.3 -// Description: This header provides the functions necessary to -// calculate the DRP register values for the V6 PLL. -// Updated for CR663854. -// -// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR -// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING -// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -// APPLICATION OR STANDARD, XILINX IS MAKING NO -// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE -// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY -// REQUIRE FOR YOUR IMPLEMENTATION. XILINX -// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH -// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, -// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE -// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES -// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -// PURPOSE. -// -// (c) Copyright 2009-2010 Xilinx, Inc. -// All rights reserved. -// -/////////////////////////////////////////////////////////////////////////////// - -// These are user functions that should not be modified. Changes to the defines -// or code within the functions may alter the accuracy of the calculations. - -// Define debug to provide extra messages durring elaboration -//`define DEBUG 1 - -// FRAC_PRECISION describes the width of the fractional portion of the fixed -// point numbers. These should not be modified, they are for development -// only -`define FRAC_PRECISION 10 -// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). -// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs -// greater than 32 -`define FIXED_WIDTH 32 - -// This function takes a fixed point number and rounds it to the nearest -// fractional precision bit. -function [`FIXED_WIDTH:1] round_frac - ( - // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number - input [`FIXED_WIDTH:1] decimal, - - // This describes the precision of the fraction, for example a value - // of 1 would modify the fractional so that instead of being a .16 - // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) - input [`FIXED_WIDTH:1] precision - ); - - begin - -`ifdef DEBUG - $display("round_frac - decimal: %h, precision: %h", decimal, precision); -`endif - // If the fractional precision bit is high then round up - if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin - round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); - end else begin - round_frac = decimal; - end -`ifdef DEBUG - $display("round_frac: %h", round_frac); -`endif - end -endfunction - -// This function calculates high_time, low_time, w_edge, and no_count -// of a non-fractional counter based on the divide and duty cycle -// -// NOTE: high_time and low_time are returned as integers between 0 and 63 -// inclusive. 64 should equal 6'b000000 (in other words it is okay to -// ignore the overflow) -function [13:0] mmcm_pll_divider - ( - input [7:0] divide, // Max divide is 128 - input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 - ); - - reg [`FIXED_WIDTH:1] duty_cycle_fix; - - // High/Low time is initially calculated with a wider integer to prevent a - // calculation error when it overflows to 64. - reg [6:0] high_time; - reg [6:0] low_time; - reg w_edge; - reg no_count; - - reg [`FIXED_WIDTH:1] temp; - - begin - // Duty Cycle must be between 0 and 1,000 - if(duty_cycle <=0 || duty_cycle >= 100000) begin -`ifndef SYNTHESIS - $display("ERROR: duty_cycle: %d is invalid", duty_cycle); - `endif - $finish; - end - - // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point - duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; - -`ifdef DEBUG - $display("duty_cycle_fix: %h", duty_cycle_fix); -`endif - - // If the divide is 1 nothing needs to be set except the no_count bit. - // Other values are dummies - if(divide == 7'h01) begin - high_time = 7'h01; - w_edge = 1'b0; - low_time = 7'h01; - no_count = 1'b1; - end else begin - temp = round_frac(duty_cycle_fix*divide, 1); - - // comes from above round_frac - high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; - // If the duty cycle * divide rounded is .5 or greater then this bit - // is set. - w_edge = temp[`FRAC_PRECISION]; // comes from round_frac - - // If the high time comes out to 0, it needs to be set to at least 1 - // and w_edge set to 0 - if(high_time == 7'h00) begin - high_time = 7'h01; - w_edge = 1'b0; - end - - if(high_time == divide) begin - high_time = divide - 1; - w_edge = 1'b1; - end - - // Calculate low_time based on the divide setting and set no_count to - // 0 as it is only used when divide is 1. - low_time = divide - high_time; - no_count = 1'b0; - end - - // Set the return value. - mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; - end -endfunction - -// This function calculates mx, delay_time, and phase_mux -// of a non-fractional counter based on the divide and phase -// -// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux -// is used. -function [10:0] mmcm_pll_phase - ( - // divide must be an integer (use fractional if not) - // assumed that divide already checked to be valid - input [7:0] divide, // Max divide is 128 - - // Phase is given in degrees (-360,000 to 360,000) - input signed [31:0] phase - ); - - reg [`FIXED_WIDTH:1] phase_in_cycles; - reg [`FIXED_WIDTH:1] phase_fixed; - reg [1:0] mx; - reg [5:0] delay_time; - reg [2:0] phase_mux; - - reg [`FIXED_WIDTH:1] temp; - - begin -`ifdef DEBUG - $display("mmcm_pll_phase-divide:%d,phase:%d", - divide, phase); -`endif - - if ((phase < -360000) || (phase > 360000)) begin -`ifndef SYNTHESIS - $display("ERROR: phase of $phase is not between -360000 and 360000"); - `endif - $finish; - end - - // If phase is less than 0, convert it to a positive phase shift - // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point - if(phase < 0) begin - phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; - end else begin - phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; - end - - // Put phase in terms of decimal number of vco clock cycles - phase_in_cycles = ( phase_fixed * divide ) / 360; - -`ifdef DEBUG - $display("phase_in_cycles: %h", phase_in_cycles); -`endif - - - temp = round_frac(phase_in_cycles, 3); - - // set mx to 2'b00 that the phase mux from the VCO is enabled - mx = 2'b00; - phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; - delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; - -`ifdef DEBUG - $display("temp: %h", temp); -`endif - - // Setup the return value - mmcm_pll_phase={mx, phase_mux, delay_time}; - end -endfunction - -// This function takes the divide value and outputs the necessary lock values -function [39:0] mmcm_pll_lock_lookup - ( - input [6:0] divide // Max divide is 64 - ); - - reg [2559:0] lookup; - - begin - lookup = { - // This table is composed of: - // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt - 40'b00110_00110_1111101000_1111101001_0000000001, - 40'b00110_00110_1111101000_1111101001_0000000001, - 40'b01000_01000_1111101000_1111101001_0000000001, - 40'b01011_01011_1111101000_1111101001_0000000001, - 40'b01110_01110_1111101000_1111101001_0000000001, - 40'b10001_10001_1111101000_1111101001_0000000001, - 40'b10011_10011_1111101000_1111101001_0000000001, - 40'b10110_10110_1111101000_1111101001_0000000001, - 40'b11001_11001_1111101000_1111101001_0000000001, - 40'b11100_11100_1111101000_1111101001_0000000001, - 40'b11111_11111_1110000100_1111101001_0000000001, - 40'b11111_11111_1100111001_1111101001_0000000001, - 40'b11111_11111_1011101110_1111101001_0000000001, - 40'b11111_11111_1010111100_1111101001_0000000001, - 40'b11111_11111_1010001010_1111101001_0000000001, - 40'b11111_11111_1001110001_1111101001_0000000001, - 40'b11111_11111_1000111111_1111101001_0000000001, - 40'b11111_11111_1000100110_1111101001_0000000001, - 40'b11111_11111_1000001101_1111101001_0000000001, - 40'b11111_11111_0111110100_1111101001_0000000001, - 40'b11111_11111_0111011011_1111101001_0000000001, - 40'b11111_11111_0111000010_1111101001_0000000001, - 40'b11111_11111_0110101001_1111101001_0000000001, - 40'b11111_11111_0110010000_1111101001_0000000001, - 40'b11111_11111_0110010000_1111101001_0000000001, - 40'b11111_11111_0101110111_1111101001_0000000001, - 40'b11111_11111_0101011110_1111101001_0000000001, - 40'b11111_11111_0101011110_1111101001_0000000001, - 40'b11111_11111_0101000101_1111101001_0000000001, - 40'b11111_11111_0101000101_1111101001_0000000001, - 40'b11111_11111_0100101100_1111101001_0000000001, - 40'b11111_11111_0100101100_1111101001_0000000001, - 40'b11111_11111_0100101100_1111101001_0000000001, - 40'b11111_11111_0100010011_1111101001_0000000001, - 40'b11111_11111_0100010011_1111101001_0000000001, - 40'b11111_11111_0100010011_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001 - }; - - // Set lookup_entry with the explicit bits from lookup with a part select - mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; - `ifdef DEBUG - $display("lock_lookup: %b", mmcm_pll_lock_lookup); - `endif - end -endfunction - -// This function takes the divide value and the bandwidth setting of the PLL -// and outputs the digital filter settings necessary. -function [9:0] mmcm_pll_filter_lookup - ( - input [6:0] divide, // Max divide is 64 - input [8*9:0] BANDWIDTH - ); - - reg [639:0] lookup_low; - reg [639:0] lookup_high; - - reg [9:0] lookup_entry; - - begin - lookup_low = { - // CP_RES_LFHF - 10'b0010_1111_00, - 10'b0010_1111_00, - 10'b0010_0111_00, - 10'b0010_1101_00, - 10'b0010_0101_00, - 10'b0010_0101_00, - 10'b0010_1001_00, - 10'b0010_1110_00, - 10'b0010_1110_00, - 10'b0010_0001_00, - 10'b0010_0001_00, - 10'b0010_0110_00, - 10'b0010_0110_00, - 10'b0010_0110_00, - 10'b0010_0110_00, - 10'b0010_1010_00, - 10'b0010_1010_00, - 10'b0010_1010_00, - 10'b0010_1010_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0011_1100_00, - 10'b0011_1100_00, - 10'b0011_1100_00, - 10'b0011_1100_00, - 10'b0011_1100_00, - 10'b0011_1100_00, - 10'b0011_1100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00 - }; - - lookup_high = { - // CP_RES_LFHF - 10'b0011_0111_00, - 10'b0011_0111_00, - 10'b0101_1111_00, - 10'b0111_1111_00, - 10'b0111_1011_00, - 10'b1101_0111_00, - 10'b1110_1011_00, - 10'b1110_1101_00, - 10'b1111_1101_00, - 10'b1111_0111_00, - 10'b1111_1011_00, - 10'b1111_1101_00, - 10'b1111_0011_00, - 10'b1110_0101_00, - 10'b1111_0101_00, - 10'b1111_0101_00, - 10'b1111_0101_00, - 10'b1111_0101_00, - 10'b0111_0110_00, - 10'b0111_0110_00, - 10'b0111_0110_00, - 10'b0111_0110_00, - 10'b0101_1100_00, - 10'b0101_1100_00, - 10'b0101_1100_00, - 10'b1100_0001_00, - 10'b1100_0001_00, - 10'b1100_0001_00, - 10'b1100_0001_00, - 10'b1100_0001_00, - 10'b1100_0001_00, - 10'b1100_0001_00, - 10'b1100_0001_00, - 10'b0100_0010_00, - 10'b0100_0010_00, - 10'b0100_0010_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0011_0100_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0100_1100_00, - 10'b0100_1100_00, - 10'b0100_1100_00, - 10'b0100_1100_00, - 10'b0100_1100_00, - 10'b0100_1100_00, - 10'b0100_1100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00 - }; - - // Set lookup_entry with the explicit bits from lookup with a part select - if(BANDWIDTH == "LOW") begin - // Low Bandwidth - mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; - end else begin - // High or optimized bandwidth - mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; - end - - `ifdef DEBUG - $display("filter_lookup: %b", mmcm_pll_filter_lookup); - `endif - end -endfunction - -// This function takes in the divide, phase, and duty cycle -// setting to calculate the upper and lower counter registers. -function [37:0] mmcm_pll_count_calc - ( - input [7:0] divide, // Max divide is 128 - input signed [31:0] phase, - input [31:0] duty_cycle // Multiplied by 100,000 - ); - - reg [13:0] div_calc; - reg [16:0] phase_calc; - - begin - `ifdef DEBUG - $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", - divide, phase, duty_cycle); -`endif - - // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] - div_calc = mmcm_pll_divider(divide, duty_cycle); - // mx[10:9], pm[8:6], dt[5:0] - phase_calc = mmcm_pll_phase(divide, phase); - - // Return value is the upper and lower address of counter - // Upper address is: - // RESERVED [31:26] - // MX [25:24] - // EDGE [23] - // NOCOUNT [22] - // DELAY_TIME [21:16] - // Lower Address is: - // PHASE_MUX [15:13] - // RESERVED [12] - // HIGH_TIME [11:6] - // LOW_TIME [5:0] - -`ifdef DEBUG - $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", - divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], - div_calc[13], div_calc[12], - phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); -`endif - - mmcm_pll_count_calc = - { - // Upper Address - 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], - // Lower Address - phase_calc[8:6], 1'b0, div_calc[11:0] - }; - end -endfunction diff --git a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_mmcm.vh b/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_mmcm.vh deleted file mode 100755 index 2cffa9a..0000000 --- a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_mmcm.vh +++ /dev/null @@ -1,671 +0,0 @@ -/////////////////////////////////////////////////////////////////////////////// -// -// Company: Xilinx -// Engineer: Jim Tatsukawa -// Date: 7/30/2014 -// Design Name: MMCME2 DRP -// Module Name: mmcme2_drp_func.h -// Version: 1.04 -// Target Devices: UltraScale Architecture || MMCM -// Tool versions: 2014.3 -// Description: This header provides the functions necessary to -// calculate the DRP register values for the V6 MMCM. -// -// Revision Notes: 3/22 - Updating lookup_low/lookup_high (CR) -// 4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807 -// -// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR -// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING -// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -// APPLICATION OR STANDARD, XILINX IS MAKING NO -// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE -// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY -// REQUIRE FOR YOUR IMPLEMENTATION. XILINX -// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH -// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, -// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE -// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES -// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -// PURPOSE. -// -// (c) Copyright 2009-2010 Xilinx, Inc. -// All rights reserved. -// -/////////////////////////////////////////////////////////////////////////////// - -// These are user functions that should not be modified. Changes to the defines -// or code within the functions may alter the accuracy of the calculations. - -// Define debug to provide extra messages durring elaboration -//`define DEBUG 1 - -// FRAC_PRECISION describes the width of the fractional portion of the fixed -// point numbers. These should not be modified, they are for development -// only -`define FRAC_PRECISION 10 -// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). -// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs -// greater than 32 -`define FIXED_WIDTH 32 - -// This function takes a fixed point number and rounds it to the nearest -// fractional precision bit. -function [`FIXED_WIDTH:1] round_frac - ( - // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number - input [`FIXED_WIDTH:1] decimal, - - // This describes the precision of the fraction, for example a value - // of 1 would modify the fractional so that instead of being a .16 - // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) - input [`FIXED_WIDTH:1] precision - ); - - begin - - `ifdef DEBUG - $display("round_frac - decimal: %h, precision: %h", decimal, precision); - `endif - // If the fractional precision bit is high then round up - if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin - round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); - end else begin - round_frac = decimal; - end - `ifdef DEBUG - $display("round_frac: %h", round_frac); - `endif - end -endfunction - -// This function calculates high_time, low_time, w_edge, and no_count -// of a non-fractional counter based on the divide and duty cycle -// -// NOTE: high_time and low_time are returned as integers between 0 and 63 -// inclusive. 64 should equal 6'b000000 (in other words it is okay to -// ignore the overflow) -function [13:0] mmcm_pll_divider - ( - input [7:0] divide, // Max divide is 128 - input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 - ); - - reg [`FIXED_WIDTH:1] duty_cycle_fix; - - // High/Low time is initially calculated with a wider integer to prevent a - // calculation error when it overflows to 64. - reg [6:0] high_time; - reg [6:0] low_time; - reg w_edge; - reg no_count; - - reg [`FIXED_WIDTH:1] temp; - - begin - // Duty Cycle must be between 0 and 1,000 - if(duty_cycle <=0 || duty_cycle >= 100000) begin -`ifndef SYNTHESIS - $display("ERROR: duty_cycle: %d is invalid", duty_cycle); - `endif - $finish; - end - - // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point - duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; - - `ifdef DEBUG - $display("duty_cycle_fix: %h", duty_cycle_fix); - `endif - - // If the divide is 1 nothing needs to be set except the no_count bit. - // Other values are dummies - if(divide == 7'h01) begin - high_time = 7'h01; - w_edge = 1'b0; - low_time = 7'h01; - no_count = 1'b1; - end else begin - temp = round_frac(duty_cycle_fix*divide, 1); - - // comes from above round_frac - high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; - // If the duty cycle * divide rounded is .5 or greater then this bit - // is set. - w_edge = temp[`FRAC_PRECISION]; // comes from round_frac - - // If the high time comes out to 0, it needs to be set to at least 1 - // and w_edge set to 0 - if(high_time == 7'h00) begin - high_time = 7'h01; - w_edge = 1'b0; - end - - if(high_time == divide) begin - high_time = divide - 1; - w_edge = 1'b1; - end - - // Calculate low_time based on the divide setting and set no_count to - // 0 as it is only used when divide is 1. - low_time = divide - high_time; - no_count = 1'b0; - end - - // Set the return value. - mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; - end -endfunction - -// This function calculates mx, delay_time, and phase_mux -// of a non-fractional counter based on the divide and phase -// -// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux -// is used. -function [10:0] mmcm_pll_phase - ( - // divide must be an integer (use fractional if not) - // assumed that divide already checked to be valid - input [7:0] divide, // Max divide is 128 - - // Phase is given in degrees (-360,000 to 360,000) - input signed [31:0] phase - ); - - reg [`FIXED_WIDTH:1] phase_in_cycles; - reg [`FIXED_WIDTH:1] phase_fixed; - reg [1:0] mx; - reg [5:0] delay_time; - reg [2:0] phase_mux; - - reg [`FIXED_WIDTH:1] temp; - - begin -`ifdef DEBUG - $display("mmcm_pll_phase-divide:%d,phase:%d", - divide, phase); -`endif - - if ((phase < -360000) || (phase > 360000)) begin -`ifndef SYNTHESIS - $display("ERROR: phase of $phase is not between -360000 and 360000"); - `endif - $finish; - end - - // If phase is less than 0, convert it to a positive phase shift - // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point - if(phase < 0) begin - phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; - end else begin - phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; - end - - // Put phase in terms of decimal number of vco clock cycles - phase_in_cycles = ( phase_fixed * divide ) / 360; - -`ifdef DEBUG - $display("phase_in_cycles: %h", phase_in_cycles); -`endif - - - temp = round_frac(phase_in_cycles, 3); - - // set mx to 2'b00 that the phase mux from the VCO is enabled - mx = 2'b00; - phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; - delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; - - `ifdef DEBUG - $display("temp: %h", temp); - `endif - - // Setup the return value - mmcm_pll_phase={mx, phase_mux, delay_time}; - end -endfunction - -// This function takes the divide value and outputs the necessary lock values -function [39:0] mmcm_pll_lock_lookup - ( - input [6:0] divide // Max divide is 64 - ); - - reg [2559:0] lookup; - - begin - lookup = { - // This table is composed of: - // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt - 40'b00110_00110_1111101000_1111101001_0000000001, - 40'b00110_00110_1111101000_1111101001_0000000001, - 40'b01000_01000_1111101000_1111101001_0000000001, - 40'b01011_01011_1111101000_1111101001_0000000001, - 40'b01110_01110_1111101000_1111101001_0000000001, - 40'b10001_10001_1111101000_1111101001_0000000001, - 40'b10011_10011_1111101000_1111101001_0000000001, - 40'b10110_10110_1111101000_1111101001_0000000001, - 40'b11001_11001_1111101000_1111101001_0000000001, - 40'b11100_11100_1111101000_1111101001_0000000001, - 40'b11111_11111_1110000100_1111101001_0000000001, - 40'b11111_11111_1100111001_1111101001_0000000001, - 40'b11111_11111_1011101110_1111101001_0000000001, - 40'b11111_11111_1010111100_1111101001_0000000001, - 40'b11111_11111_1010001010_1111101001_0000000001, - 40'b11111_11111_1001110001_1111101001_0000000001, - 40'b11111_11111_1000111111_1111101001_0000000001, - 40'b11111_11111_1000100110_1111101001_0000000001, - 40'b11111_11111_1000001101_1111101001_0000000001, - 40'b11111_11111_0111110100_1111101001_0000000001, - 40'b11111_11111_0111011011_1111101001_0000000001, - 40'b11111_11111_0111000010_1111101001_0000000001, - 40'b11111_11111_0110101001_1111101001_0000000001, - 40'b11111_11111_0110010000_1111101001_0000000001, - 40'b11111_11111_0110010000_1111101001_0000000001, - 40'b11111_11111_0101110111_1111101001_0000000001, - 40'b11111_11111_0101011110_1111101001_0000000001, - 40'b11111_11111_0101011110_1111101001_0000000001, - 40'b11111_11111_0101000101_1111101001_0000000001, - 40'b11111_11111_0101000101_1111101001_0000000001, - 40'b11111_11111_0100101100_1111101001_0000000001, - 40'b11111_11111_0100101100_1111101001_0000000001, - 40'b11111_11111_0100101100_1111101001_0000000001, - 40'b11111_11111_0100010011_1111101001_0000000001, - 40'b11111_11111_0100010011_1111101001_0000000001, - 40'b11111_11111_0100010011_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001 - }; - - // Set lookup_entry with the explicit bits from lookup with a part select - mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; - `ifdef DEBUG - $display("lock_lookup: %b", mmcm_pll_lock_lookup); - `endif - end -endfunction - -// This function takes the divide value and the bandwidth setting of the MMCM -// and outputs the digital filter settings necessary. -function [9:0] mmcm_pll_filter_lookup - ( - input [6:0] divide, // Max divide is 64 - input [8*9:0] BANDWIDTH - ); - - reg [639:0] lookup_low; - reg [639:0] lookup_high; - - reg [9:0] lookup_entry; - - begin - lookup_low = { - // CP_RES_LFHF - 10'b0010_1111_11, - 10'b0010_1111_11, - 10'b0010_1111_11, - 10'b0010_1111_11, - 10'b0010_1111_11, - 10'b0010_1111_11, - 10'b0010_0111_11, - 10'b0010_0111_11, - 10'b0010_0111_11, - 10'b0010_1101_11, - 10'b0010_1101_11, - 10'b0010_1101_11, - 10'b0010_0011_11, - 10'b0010_0101_11, - 10'b0010_0101_11, - 10'b0010_0101_11, - 10'b0010_1001_11, - 10'b0010_1001_11, - 10'b0010_1110_11, - 10'b0010_1110_11, - 10'b0010_1110_11, - 10'b0010_1110_11, - 10'b0010_1110_11, - 10'b0010_1110_11, - 10'b0010_0001_11, - 10'b0010_0001_11, - 10'b0010_0001_11, - 10'b0010_0001_11, - 10'b0010_0001_11, - 10'b0010_0110_11, - 10'b0010_0110_11, - 10'b0010_0110_11, - 10'b0010_0110_11, - 10'b0010_0110_11, - 10'b0010_0110_11, - 10'b0010_0110_11, - 10'b0010_0110_11, - 10'b0010_0110_11, - 10'b0010_0110_11, - 10'b0010_1010_11, - 10'b0010_1010_11, - 10'b0010_1010_11, - 10'b0010_1010_11, - 10'b0010_1010_11, - 10'b0010_1010_11, - 10'b0010_1010_11, - 10'b0010_1010_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11 - }; - - lookup_high = { - // CP_RES_LFHF - 10'b0010_1111_11, - 10'b0010_1111_11, - 10'b0010_1011_11, - 10'b0011_1111_11, - 10'b0100_1111_11, - 10'b0100_1111_11, - 10'b0101_1111_11, - 10'b0110_1111_11, - 10'b0111_1111_11, - 10'b0111_1111_11, - 10'b1100_1111_11, - 10'b1101_1111_11, - 10'b1110_1111_11, - 10'b1111_1111_11, - 10'b1111_1111_11, - 10'b1110_0111_11, - 10'b1110_1011_11, - 10'b1111_0111_11, - 10'b1111_1011_11, - 10'b1111_1011_11, - 10'b1110_1101_11, - 10'b1111_1101_11, - 10'b1111_1101_11, - 10'b1111_0011_11, - 10'b1111_0011_11, - 10'b1111_0011_11, - 10'b1110_0101_11, - 10'b1110_0101_11, - 10'b1110_0101_11, - 10'b1111_0101_11, - 10'b1111_0101_11, - 10'b1111_0101_11, - 10'b1111_1001_11, - 10'b1111_1001_11, - 10'b1111_1001_11, - 10'b1111_1001_11, - 10'b1111_1001_11, - 10'b1110_1110_11, - 10'b1110_1110_11, - 10'b1110_1110_11, - 10'b1110_1110_11, - 10'b1111_1110_11, - 10'b1111_1110_11, - 10'b1111_1110_11, - 10'b1111_1110_11, - 10'b1111_1110_11, - 10'b1111_1110_11, - 10'b1111_1110_11, - 10'b1110_0001_11, - 10'b1110_0001_11, - 10'b1110_0001_11, - 10'b1110_0001_11, - 10'b1110_0001_11, - 10'b1100_0110_11, - 10'b1100_0110_11, - 10'b1100_0110_11, - 10'b1100_0110_11, - 10'b1100_0110_11, - 10'b1100_0110_11, - 10'b1100_0110_11, - 10'b1100_1010_11, - 10'b1100_1010_11, - 10'b1100_1010_11, - 10'b1100_1010_11 - }; - - // Set lookup_entry with the explicit bits from lookup with a part select - if(BANDWIDTH == "LOW") begin - // Low Bandwidth - mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; - end else begin - // High or optimized bandwidth - mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; - end - - `ifdef DEBUG - $display("filter_lookup: %b", mmcm_pll_filter_lookup); - `endif - end -endfunction - -// This function takes in the divide, phase, and duty cycle -// setting to calculate the upper and lower counter registers. -function [37:0] mmcm_pll_count_calc - ( - input [7:0] divide, // Max divide is 128 - input signed [31:0] phase, - input [31:0] duty_cycle // Multiplied by 100,000 - ); - - reg [13:0] div_calc; - reg [16:0] phase_calc; - - begin - `ifdef DEBUG - $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", - divide, phase, duty_cycle); - `endif - - // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] - div_calc = mmcm_pll_divider(divide, duty_cycle); - // mx[10:9], pm[8:6], dt[5:0] - phase_calc = mmcm_pll_phase(divide, phase); - - // Return value is the upper and lower address of counter - // Upper address is: - // RESERVED [31:26] - // MX [25:24] - // EDGE [23] - // NOCOUNT [22] - // DELAY_TIME [21:16] - // Lower Address is: - // PHASE_MUX [15:13] - // RESERVED [12] - // HIGH_TIME [11:6] - // LOW_TIME [5:0] - - `ifdef DEBUG - $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", - divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], - div_calc[13], div_calc[12], - phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); - `endif - - mmcm_pll_count_calc = - { - // Upper Address - 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], - // Lower Address - phase_calc[8:6], 1'b0, div_calc[11:0] - }; - end -endfunction - - -// This function takes in the divide, phase, and duty cycle -// setting to calculate the upper and lower counter registers. -// for fractional multiply/divide functions. -// -// -function [37:0] mmcm_frac_count_calc - ( - input [7:0] divide, // Max divide is 128 - input signed [31:0] phase, - input [31:0] duty_cycle, // Multiplied by 1,000 - input [9:0] frac // Multiplied by 1000 - ); - - //Required for fractional divide calculations - reg [7:0] lt_frac; - reg [7:0] ht_frac; - - reg /*[7:0]*/ wf_fall_frac; - reg /*[7:0]*/ wf_rise_frac; - - reg [31:0] a; - reg [7:0] pm_rise_frac_filtered ; - reg [7:0] pm_fall_frac_filtered ; - reg [7:0] clkout0_divide_int; - reg [2:0] clkout0_divide_frac; - reg [7:0] even_part_high; - reg [7:0] even_part_low; - - reg [7:0] odd; - reg [7:0] odd_and_frac; - - reg [7:0] pm_fall; - reg [7:0] pm_rise; - reg [7:0] dt; - reg [7:0] dt_int; - reg [63:0] dt_calc; - - reg [7:0] pm_rise_frac; - reg [7:0] pm_fall_frac; - - reg [31:0] a_per_in_octets; - reg [31:0] a_phase_in_cycles; - - parameter precision = 0.125; - - reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 - reg [31: 0] phase_pos; - reg [31: 0] phase_vco; - reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 - reg [13:0] div_calc; - reg [16:0] phase_calc; - - begin - `ifdef DEBUG - $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", - divide, phase, duty_cycle); - `endif - - //convert phase to fixed - if ((phase < -360000) || (phase > 360000)) begin -`ifndef SYNTHESIS - $display("ERROR: phase of $phase is not between -360000 and 360000"); - `endif - $finish; - end - - - // Return value is - // Transfer data - // RESERVED [37:36] - // FRAC_TIME [35:33] - // FRAC_WF_FALL [32] - // Upper address is: - // RESERVED [31:26] - // MX [25:24] - // EDGE [23] - // NOCOUNT [22] - // DELAY_TIME [21:16] - // Lower Address is: - // PHASE_MUX [15:13] - // RESERVED [12] - // HIGH_TIME [11:6] - // LOW_TIME [5:0] - - - - clkout0_divide_frac = frac / 125; - clkout0_divide_int = divide; - - even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); - even_part_low = even_part_high; - - odd = clkout0_divide_int - even_part_high - even_part_low; - odd_and_frac = (8*odd) + clkout0_divide_frac; - - lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) - ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) - - pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 - pm_rise = 0; //0 - - wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807 - wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) - - - - //Calculate phase in fractional cycles - a_per_in_octets = (8 * divide) + (frac / 125) ; - a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors - pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; - - dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) - dt = dt_calc[7:0]; - - pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; - - dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) - pm_fall_frac = pm_fall + pm_rise_frac; - pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; - - div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] - phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} - - mmcm_frac_count_calc[37:0] = - { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, - 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], - pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] - } ; - - `ifdef DEBUG - $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac); - `endif - - end -endfunction - diff --git a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_pll.vh b/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_pll.vh deleted file mode 100755 index 9439f23..0000000 --- a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_pll.vh +++ /dev/null @@ -1,530 +0,0 @@ -/////////////////////////////////////////////////////////////////////////////// -// -// Company: Xilinx -// Engineer: Jim Tatsukawa -// Date: 6/15/2015 -// Design Name: PLLE3 DRP -// Module Name: plle3_drp_func.h -// Version: 1.10 -// Target Devices: UltraScale Architecture -// Tool versions: 2015.1 -// Description: This header provides the functions necessary to -// calculate the DRP register values for the V6 PLL. -// -// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419 -// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19 -// PM_Rise bits have been removed for PLLE3 -// -// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR -// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING -// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -// APPLICATION OR STANDARD, XILINX IS MAKING NO -// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE -// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY -// REQUIRE FOR YOUR IMPLEMENTATION. XILINX -// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH -// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, -// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE -// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES -// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -// PURPOSE. -// -// (c) Copyright 2009-2010 Xilinx, Inc. -// All rights reserved. -// -/////////////////////////////////////////////////////////////////////////////// - -// These are user functions that should not be modified. Changes to the defines -// or code within the functions may alter the accuracy of the calculations. - -// Define debug to provide extra messages durring elaboration -//`define DEBUG 1 - -// FRAC_PRECISION describes the width of the fractional portion of the fixed -// point numbers. These should not be modified, they are for development -// only -`define FRAC_PRECISION 10 -// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). -// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs -// greater than 32 -`define FIXED_WIDTH 32 - -// This function takes a fixed point number and rounds it to the nearest -// fractional precision bit. -function [`FIXED_WIDTH:1] round_frac - ( - // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number - input [`FIXED_WIDTH:1] decimal, - - // This describes the precision of the fraction, for example a value - // of 1 would modify the fractional so that instead of being a .16 - // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) - input [`FIXED_WIDTH:1] precision - ); - - begin - - `ifdef DEBUG - $display("round_frac - decimal: %h, precision: %h", decimal, precision); - `endif - // If the fractional precision bit is high then round up - if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin - round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); - end else begin - round_frac = decimal; - end - `ifdef DEBUG - $display("round_frac: %h", round_frac); - `endif - end -endfunction - -// This function calculates high_time, low_time, w_edge, and no_count -// of a non-fractional counter based on the divide and duty cycle -// -// NOTE: high_time and low_time are returned as integers between 0 and 63 -// inclusive. 64 should equal 6'b000000 (in other words it is okay to -// ignore the overflow) -function [13:0] mmcm_pll_divider - ( - input [7:0] divide, // Max divide is 128 - input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 - ); - - reg [`FIXED_WIDTH:1] duty_cycle_fix; - - // High/Low time is initially calculated with a wider integer to prevent a - // calculation error when it overflows to 64. - reg [6:0] high_time; - reg [6:0] low_time; - reg w_edge; - reg no_count; - - reg [`FIXED_WIDTH:1] temp; - - begin - // Duty Cycle must be between 0 and 1,000 - if(duty_cycle <=0 || duty_cycle >= 100000) begin -`ifndef SYNTHESIS - $display("ERROR: duty_cycle: %d is invalid", duty_cycle); - `endif - $finish; - end - - // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point - duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; - - `ifdef DEBUG - $display("duty_cycle_fix: %h", duty_cycle_fix); - `endif - - // If the divide is 1 nothing needs to be set except the no_count bit. - // Other values are dummies - if(divide == 7'h01) begin - high_time = 7'h01; - w_edge = 1'b0; - low_time = 7'h01; - no_count = 1'b1; - end else begin - temp = round_frac(duty_cycle_fix*divide, 1); - - // comes from above round_frac - high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; - // If the duty cycle * divide rounded is .5 or greater then this bit - // is set. - w_edge = temp[`FRAC_PRECISION]; // comes from round_frac - - // If the high time comes out to 0, it needs to be set to at least 1 - // and w_edge set to 0 - if(high_time == 7'h00) begin - high_time = 7'h01; - w_edge = 1'b0; - end - - if(high_time == divide) begin - high_time = divide - 1; - w_edge = 1'b1; - end - - // Calculate low_time based on the divide setting and set no_count to - // 0 as it is only used when divide is 1. - low_time = divide - high_time; - no_count = 1'b0; - end - - // Set the return value. - mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; - end -endfunction - -// This function calculates mx, delay_time, and phase_mux -// of a non-fractional counter based on the divide and phase -// -// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux -// is used. -function [10:0] mmcm_pll_phase - ( - // divide must be an integer (use fractional if not) - // assumed that divide already checked to be valid - input [7:0] divide, // Max divide is 128 - - // Phase is given in degrees (-360,000 to 360,000) - input signed [31:0] phase - ); - - reg [`FIXED_WIDTH:1] phase_in_cycles; - reg [`FIXED_WIDTH:1] phase_fixed; - reg [1:0] mx; - reg [5:0] delay_time; - reg [2:0] phase_mux; - - reg [`FIXED_WIDTH:1] temp; - - begin -`ifdef DEBUG - $display("mmcm_pll_phase-divide:%d,phase:%d", - divide, phase); -`endif - - if ((phase < -360000) || (phase > 360000)) begin -`ifndef SYNTHESIS - $display("ERROR: phase of $phase is not between -360000 and 360000"); - `endif - $finish; - end - - // If phase is less than 0, convert it to a positive phase shift - // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point - if(phase < 0) begin - phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; - end else begin - phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; - end - - // Put phase in terms of decimal number of vco clock cycles - phase_in_cycles = ( phase_fixed * divide ) / 360; - -`ifdef DEBUG - $display("phase_in_cycles: %h", phase_in_cycles); -`endif - - - temp = round_frac(phase_in_cycles, 3); - - // set mx to 2'b00 that the phase mux from the VCO is enabled - mx = 2'b00; - phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; - delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; - - `ifdef DEBUG - $display("temp: %h", temp); - `endif - - // Setup the return value - mmcm_pll_phase={mx, phase_mux, delay_time}; - end -endfunction - -// This function takes the divide value and outputs the necessary lock values -function [39:0] mmcm_pll_lock_lookup - ( - input [6:0] divide // Max divide is 64 - ); - - reg [759:0] lookup; - - begin - lookup = { - // This table is composed of: - // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt - 40'b00110_00110_1111101000_1111101001_0000000001, //1 - 40'b00110_00110_1111101000_1111101001_0000000001, //2 - 40'b01000_01000_1111101000_1111101001_0000000001, //3 - 40'b01011_01011_1111101000_1111101001_0000000001, //4 - 40'b01110_01110_1111101000_1111101001_0000000001, //5 - 40'b10001_10001_1111101000_1111101001_0000000001, //6 - 40'b10011_10011_1111101000_1111101001_0000000001, //7 - 40'b10110_10110_1111101000_1111101001_0000000001, //8 - 40'b11001_11001_1111101000_1111101001_0000000001, //9 - 40'b11100_11100_1111101000_1111101001_0000000001, //10 - 40'b11111_11111_1110000100_1111101001_0000000001, //11 - 40'b11111_11111_1100111001_1111101001_0000000001, //12 - 40'b11111_11111_1011101110_1111101001_0000000001, //13 - 40'b11111_11111_1010111100_1111101001_0000000001, //14 - 40'b11111_11111_1010001010_1111101001_0000000001, //15 - 40'b11111_11111_1001110001_1111101001_0000000001, //16 - 40'b11111_11111_1000111111_1111101001_0000000001, //17 - 40'b11111_11111_1000100110_1111101001_0000000001, //18 - 40'b11111_11111_1000001101_1111101001_0000000001 //19 - - }; - - // Set lookup_entry with the explicit bits from lookup with a part select - mmcm_pll_lock_lookup = lookup[ ((19-divide)*40) +: 40]; - `ifdef DEBUG - $display("lock_lookup: %b", mmcm_pll_lock_lookup); - `endif - end -endfunction - -// This function takes the divide value and the bandwidth setting of the PLL -// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3. -function [9:0] mmcm_pll_filter_lookup - ( - input [6:0] divide // Max divide is 19 - ); - - reg [639:0] lookup; - reg [9:0] lookup_entry; - - begin - - lookup = { - // CP_RES_LFHF - 10'b0010_1111_01, //1 - 10'b0010_0011_11, //2 - 10'b0011_0011_11, //3 - 10'b0010_0001_11, //4 - 10'b0010_0110_11, //5 - 10'b0010_1010_11, //6 - 10'b0010_1010_11, //7 - 10'b0011_0110_11, //8 - 10'b0010_1100_11, //9 - 10'b0010_1100_11, //10 - 10'b0010_1100_11, //11 - 10'b0010_0010_11, //12 - 10'b0011_1100_11, //13 - 10'b0011_1100_11, //14 - 10'b0011_1100_11, //15 - 10'b0011_1100_11, //16 - 10'b0011_0010_11, //17 - 10'b0011_0010_11, //18 - 10'b0011_0010_11 //19 - }; - - mmcm_pll_filter_lookup = lookup [ ((19-divide)*10) +: 10]; - - `ifdef DEBUG - $display("filter_lookup: %b", mmcm_pll_filter_lookup); - `endif - end -endfunction - -// This function set the CLKOUTPHY divide settings to match -// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then -// the CLKOUTPHY will be set to 2'b00 since the VCO is internally -// doubled and 2'b00 will represent divide by 1. Similarly "VCO" // will need to divide the doubled clock VCO clock frequency by // 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will // need to divide the doubled VCO by 4, therefore 2'b10 -function [9:0] mmcm_pll_clkoutphy_calc - ( - input [8*9:0] CLKOUTPHY_MODE - ); - - if(CLKOUTPHY_MODE == "VCO_X2") begin - mmcm_pll_clkoutphy_calc= 2'b00; - end else if(CLKOUTPHY_MODE == "VCO") begin - mmcm_pll_clkoutphy_calc= 2'b01; - end else if(CLKOUTPHY_MODE == "CLKIN") begin - mmcm_pll_clkoutphy_calc= 2'b11; - end else begin // Assume "VCO_HALF" - mmcm_pll_clkoutphy_calc= 2'b10; - end - -endfunction - - -// This function takes in the divide, phase, and duty cycle -// setting to calculate the upper and lower counter registers. -function [37:0] mmcm_pll_count_calc - ( - input [7:0] divide, // Max divide is 128 - input signed [31:0] phase, - input [31:0] duty_cycle // Multiplied by 100,000 - ); - - reg [13:0] div_calc; - reg [16:0] phase_calc; - - begin - `ifdef DEBUG - $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", - divide, phase, duty_cycle); - `endif - - // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] - div_calc = mmcm_pll_divider(divide, duty_cycle); - // mx[10:9], pm[8:6], dt[5:0] - phase_calc = mmcm_pll_phase(divide, phase); - - // Return value is the upper and lower address of counter - // Upper address is: - // RESERVED [31:26] - // MX [25:24] - // EDGE [23] - // NOCOUNT [22] - // DELAY_TIME [21:16] - // Lower Address is: - // PHASE_MUX [15:13] - // RESERVED [12] - // HIGH_TIME [11:6] - // LOW_TIME [5:0] - - `ifdef DEBUG - $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", - divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], - div_calc[13], div_calc[12], - phase_calc[16:15], phase_calc[5:0], 3'b000);//Removed PM_Rise bits - `endif - - mmcm_pll_count_calc = - { - // Upper Address - 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], - // Lower Address - phase_calc[8:6], 1'b0, div_calc[11:0] - }; - end -endfunction - - -// This function takes in the divide, phase, and duty cycle -// setting to calculate the upper and lower counter registers. -// for fractional multiply/divide functions. -// -// -function [37:0] mmcm_pll_frac_count_calc - ( - input [7:0] divide, // Max divide is 128 - input signed [31:0] phase, - input [31:0] duty_cycle, // Multiplied by 1,000 - input [9:0] frac // Multiplied by 1000 - ); - - //Required for fractional divide calculations - reg [7:0] lt_frac; - reg [7:0] ht_frac; - - reg /*[7:0]*/ wf_fall_frac; - reg /*[7:0]*/ wf_rise_frac; - - reg [31:0] a; - reg [7:0] pm_rise_frac_filtered ; - reg [7:0] pm_fall_frac_filtered ; - reg [7:0] clkout0_divide_int; - reg [2:0] clkout0_divide_frac; - reg [7:0] even_part_high; - reg [7:0] even_part_low; - - reg [7:0] odd; - reg [7:0] odd_and_frac; - - reg [7:0] pm_fall; - reg [7:0] pm_rise; - reg [7:0] dt; - reg [7:0] dt_int; - reg [63:0] dt_calc; - - reg [7:0] pm_rise_frac; - reg [7:0] pm_fall_frac; - - reg [31:0] a_per_in_octets; - reg [31:0] a_phase_in_cycles; - - parameter precision = 0.125; - - reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 - reg [31: 0] phase_pos; - reg [31: 0] phase_vco; - reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 - reg [13:0] div_calc; - reg [16:0] phase_calc; - - begin - `ifdef DEBUG - $display("mmcm_pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", - divide, phase, duty_cycle); - `endif - - //convert phase to fixed - if ((phase < -360000) || (phase > 360000)) begin -`ifndef SYNTHESIS - $display("ERROR: phase of $phase is not between -360000 and 360000"); - `endif - $finish; - end - - - // Return value is - // Transfer data - // RESERVED [37:36] - // FRAC_TIME [35:33] - // FRAC_WF_FALL [32] - // Upper address is: - // RESERVED [31:26] - // MX [25:24] - // EDGE [23] - // NOCOUNT [22] - // DELAY_TIME [21:16] - // Lower Address is: - // PHASE_MUX [15:13] - // RESERVED [12] - // HIGH_TIME [11:6] - // LOW_TIME [5:0] - - - - clkout0_divide_frac = frac / 125; - clkout0_divide_int = divide; - - even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); - even_part_low = even_part_high; - - odd = clkout0_divide_int - even_part_high - even_part_low; - odd_and_frac = (8*odd) + clkout0_divide_frac; - - lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) - ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) - - pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 - pm_rise = 0; //0 - - wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0) - wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) - - - - //Calculate phase in fractional cycles - a_per_in_octets = (8 * divide) + (frac / 125) ; - a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors - pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; - - dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) - dt = dt_calc[7:0]; - - pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; - - dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) - pm_fall_frac = pm_fall + pm_rise_frac; - pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; - - div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] - phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} - - mmcm_pll_frac_count_calc[37:0] = - { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, - 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], - 3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits -// pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] - } ; - - `ifdef DEBUG - $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac); - `endif - - end -endfunction - - diff --git a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_mmcm.vh b/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_mmcm.vh deleted file mode 100755 index 61edf85..0000000 --- a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_mmcm.vh +++ /dev/null @@ -1,861 +0,0 @@ -/////////////////////////////////////////////////////////////////////////////// -// -// Company: Xilinx -// Engineer: Jim Tatsukawa. Updated by Ralf Krueger -// Date: 7/30/2014 -// Design Name: MMCME4 DRP -// Module Name: mmcme4_drp_func.h -// Version: 1.31 -// Target Devices: UltraScale Plus Architecture -// Tool versions: 2017.1 -// Description: This header provides the functions necessary to -// calculate the DRP register values for UltraScal+ MMCM. -// -// Revision Notes: 3/22 - Updating lookup_low/lookup_high (CR) -// 4/13 - Fractional divide function in mmcm_frac_count_calc function -// 2/28/17 - Updated for Ultrascale Plus -// -// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR -// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING -// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -// APPLICATION OR STANDARD, XILINX IS MAKING NO -// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE -// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY -// REQUIRE FOR YOUR IMPLEMENTATION. XILINX -// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH -// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, -// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE -// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES -// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -// PURPOSE. -// -// (c) Copyright 2009-2017 Xilinx, Inc. -// All rights reserved. -// -/////////////////////////////////////////////////////////////////////////////// - -// These are user functions that should not be modified. Changes to the defines -// or code within the functions may alter the accuracy of the calculations. - -// Define debug to provide extra messages during elaboration -//`define DEBUG 1 - -// FRAC_PRECISION describes the width of the fractional portion of the fixed -// point numbers. These should not be modified, they are for development only -`define FRAC_PRECISION 10 -// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). -// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs -// greater than 32 -`define FIXED_WIDTH 32 - -// This function takes a fixed point number and rounds it to the nearest -// fractional precision bit. -function [`FIXED_WIDTH:1] round_frac - ( - // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number - input [`FIXED_WIDTH:1] decimal, - - // This describes the precision of the fraction, for example a value - // of 1 would modify the fractional so that instead of being a .16 - // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) - input [`FIXED_WIDTH:1] precision - ); - - begin - - `ifdef DEBUG - $display("round_frac - decimal: %h, precision: %h", decimal, precision); - `endif - // If the fractional precision bit is high then round up - if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin - round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); - end else begin - round_frac = decimal; - end - `ifdef DEBUG - $display("round_frac: %h", round_frac); - `endif - end -endfunction - -// This function calculates high_time, low_time, w_edge, and no_count -// of a non-fractional counter based on the divide and duty cycle -// -// NOTE: high_time and low_time are returned as integers between 0 and 63 -// inclusive. 64 should equal 6'b000000 (in other words it is okay to -// ignore the overflow) -function [13:0] mmcm_pll_divider - ( - input [7:0] divide, // Max divide is 128 - input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 - ); - - reg [`FIXED_WIDTH:1] duty_cycle_fix; - - // High/Low time is initially calculated with a wider integer to prevent a - // calculation error when it overflows to 64. - reg [6:0] high_time; - reg [6:0] low_time; - reg w_edge; - reg no_count; - - reg [`FIXED_WIDTH:1] temp; - - begin - // Duty Cycle must be between 0 and 1,000 - if(duty_cycle <=0 || duty_cycle >= 100000) begin -`ifndef SYNTHESIS - $display("ERROR: duty_cycle: %d is invalid", duty_cycle); - `endif - $finish; - end - - // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point - duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; - - `ifdef DEBUG - $display("duty_cycle_fix: %h", duty_cycle_fix); - `endif - - // If the divide is 1 nothing needs to be set except the no_count bit. - // Other values are dummies - if(divide == 7'h01) begin - high_time = 7'h01; - w_edge = 1'b0; - low_time = 7'h01; - no_count = 1'b1; - end else begin - temp = round_frac(duty_cycle_fix*divide, 1); - - // comes from above round_frac - high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; - // If the duty cycle * divide rounded is .5 or greater then this bit - // is set. - w_edge = temp[`FRAC_PRECISION]; // comes from round_frac - - // If the high time comes out to 0, it needs to be set to at least 1 - // and w_edge set to 0 - if(high_time == 7'h00) begin - high_time = 7'h01; - w_edge = 1'b0; - end - - if(high_time == divide) begin - high_time = divide - 1; - w_edge = 1'b1; - end - - // Calculate low_time based on the divide setting and set no_count to - // 0 as it is only used when divide is 1. - low_time = divide - high_time; - no_count = 1'b0; - end - - // Set the return value. - mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; - end -endfunction - -// This function calculates mx, delay_time, and phase_mux -// of a non-fractional counter based on the divide and phase -// -// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux -// is used. -function [10:0] mmcm_pll_phase - ( - // divide must be an integer (use fractional if not) - // assumed that divide already checked to be valid - input [7:0] divide, // Max divide is 128 - - // Phase is given in degrees (-360,000 to 360,000) - input signed [31:0] phase - ); - - reg [`FIXED_WIDTH:1] phase_in_cycles; - reg [`FIXED_WIDTH:1] phase_fixed; - reg [1:0] mx; - reg [5:0] delay_time; - reg [2:0] phase_mux; - - reg [`FIXED_WIDTH:1] temp; - - begin -`ifdef DEBUG - $display("mmcm_phase-divide:%d,phase:%d", divide, phase); -`endif - - if ((phase < -360000) || (phase > 360000)) begin -`ifndef SYNTHESIS - $display("ERROR: phase of $phase is not between -360000 and 360000"); - `endif - $finish; - end - - // If phase is less than 0, convert it to a positive phase shift - // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point - if(phase < 0) begin - phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; - end else begin - phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; - end - - // Put phase in terms of decimal number of vco clock cycles - phase_in_cycles = ( phase_fixed * divide ) / 360; - -`ifdef DEBUG - $display("phase_in_cycles: %h", phase_in_cycles); -`endif - - temp = round_frac(phase_in_cycles, 3); - - // set mx to 2'b00 that the phase mux from the VCO is enabled - mx = 2'b00; - phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; - delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; - - `ifdef DEBUG - $display("temp: %h", temp); - `endif - - // Setup the return value - mmcm_pll_phase={mx, phase_mux, delay_time}; - end -endfunction - -// This function takes the divide value and outputs the necessary lock values -function [39:0] mmcm_pll_lock_lookup - ( - input [7:0] divide // Max M divide is 128 in UltrascalePlus - ); - - reg [5119:0] lookup; - - begin - lookup = { - // This table is composed of: - // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt - 40'b00110_00110_1111101000_1111101001_0000000001, // M=1 (not allowed) - 40'b00110_00110_1111101000_1111101001_0000000001, // M=2 - 40'b01000_01000_1111101000_1111101001_0000000001, // M=3 - 40'b01011_01011_1111101000_1111101001_0000000001, // M=4 - 40'b01110_01110_1111101000_1111101001_0000000001, // M=5 - 40'b10001_10001_1111101000_1111101001_0000000001, // M=6 - 40'b10011_10011_1111101000_1111101001_0000000001, // M=7 - 40'b10110_10110_1111101000_1111101001_0000000001, - 40'b11001_11001_1111101000_1111101001_0000000001, - 40'b11100_11100_1111101000_1111101001_0000000001, - 40'b11111_11111_1110000100_1111101001_0000000001, - 40'b11111_11111_1100111001_1111101001_0000000001, - 40'b11111_11111_1011101110_1111101001_0000000001, - 40'b11111_11111_1010111100_1111101001_0000000001, - 40'b11111_11111_1010001010_1111101001_0000000001, - 40'b11111_11111_1001110001_1111101001_0000000001, - 40'b11111_11111_1000111111_1111101001_0000000001, - 40'b11111_11111_1000100110_1111101001_0000000001, - 40'b11111_11111_1000001101_1111101001_0000000001, - 40'b11111_11111_0111110100_1111101001_0000000001, - 40'b11111_11111_0111011011_1111101001_0000000001, - 40'b11111_11111_0111000010_1111101001_0000000001, - 40'b11111_11111_0110101001_1111101001_0000000001, - 40'b11111_11111_0110010000_1111101001_0000000001, - 40'b11111_11111_0110010000_1111101001_0000000001, - 40'b11111_11111_0101110111_1111101001_0000000001, - 40'b11111_11111_0101011110_1111101001_0000000001, - 40'b11111_11111_0101011110_1111101001_0000000001, - 40'b11111_11111_0101000101_1111101001_0000000001, - 40'b11111_11111_0101000101_1111101001_0000000001, - 40'b11111_11111_0100101100_1111101001_0000000001, - 40'b11111_11111_0100101100_1111101001_0000000001, - 40'b11111_11111_0100101100_1111101001_0000000001, - 40'b11111_11111_0100010011_1111101001_0000000001, - 40'b11111_11111_0100010011_1111101001_0000000001, - 40'b11111_11111_0100010011_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, // M=127 - 40'b11111_11111_0011111010_1111101001_0000000001 // M=128 - }; - - // Set lookup_entry with the explicit bits from lookup with a part select - mmcm_pll_lock_lookup = lookup[ ((128-divide)*40) +: 40]; - `ifdef DEBUG - $display("lock_lookup: %b", mmcm_pll_lock_lookup); - `endif - end -endfunction - -// This function takes the divide value and the bandwidth setting of the MMCM -// and outputs the digital filter settings necessary. -function [9:0] mmcm_pll_filter_lookup - ( - input [7:0] divide, // input [7:0] divide // Max M divide is 128 in UltraScalePlus - input [8*9:0] BANDWIDTH - ); - - reg [1279:0] lookup_low; - reg [1279:0] lookup_high; - - reg [9:0] lookup_entry; - - begin - lookup_low = { - // CP_RES_LFHF - 10'b0011_1111_11, // M=1 - not legal - 10'b0011_1111_11, // M=2 - 10'b0011_1101_11, // M=3 - 10'b0011_0101_11, // M=4 - 10'b0011_1001_11, // M=5 - 10'b0011_1110_11, // M=6 - 10'b0011_1110_11, // M=7 - 10'b0011_0001_11, - 10'b0011_0110_11, - 10'b0011_0110_11, - 10'b0011_0110_11, - 10'b0011_1010_11, - 10'b0011_1010_11, - 10'b0011_1010_11, - 10'b0100_0110_11, - 10'b0011_1100_11, - 10'b1110_0110_11, - 10'b1111_0110_11, - 10'b1110_1010_11, - 10'b1110_1010_11, - 10'b1111_1010_11, - 10'b1111_1010_11, - 10'b1111_1010_11, - 10'b1111_1010_11, - 10'b1111_1010_11, - 10'b1101_1100_11, - 10'b1101_1100_11, - 10'b1101_1100_11, - 10'b1110_1100_11, - 10'b1110_1100_11, - 10'b1110_1100_11, - 10'b1111_1100_11, - 10'b1111_1100_11, - 10'b1111_1100_11, - 10'b1111_1100_11, - 10'b1111_1100_11, - 10'b1111_1100_11, - 10'b1110_0010_11, - 10'b1110_0010_11, - 10'b1110_0010_11, - 10'b1110_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1101_0100_11, - 10'b1101_0100_11, - 10'b1101_0100_11, - 10'b1101_0100_11, - 10'b1101_0100_11, - 10'b1101_0100_11, - 10'b1101_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1101_1000_11, - 10'b1101_1000_11, - 10'b1101_1000_11, - 10'b1101_1000_11, - 10'b1101_1000_11, - 10'b1101_1000_11, - 10'b1101_1000_11, - 10'b1101_1000_11, // M=127 - 10'b1101_1000_11 // M=128 -}; - - lookup_high = { - // CP_RES_LFHF - 10'b0111_1111_11, // M=1 - not legal - 10'b0111_1111_11, // M=2 - 10'b1110_1111_11, // M=3 - 10'b1111_1111_11, // M=4 - 10'b1111_1011_11, // M=5 - 10'b1111_1101_11, // M=6 - 10'b1111_0011_11, // M=7 - 10'b1110_0101_11, - 10'b1111_1001_11, - 10'b1111_1001_11, - 10'b1110_1110_11, - 10'b1111_1110_11, - 10'b1111_0001_11, - 10'b1111_0001_11, - 10'b1111_0001_11, - 10'b1110_0110_11, - 10'b1110_0110_11, - 10'b1111_0110_11, - 10'b1110_1010_11, - 10'b1110_1010_11, - 10'b1111_1010_11, - 10'b1111_1010_11, - 10'b1111_1010_11, - 10'b1111_1010_11, - 10'b1111_1010_11, - 10'b1101_1100_11, - 10'b1101_1100_11, - 10'b1101_1100_11, - 10'b1110_1100_11, - 10'b1110_1100_11, - 10'b1110_1100_11, - 10'b1111_1100_11, - 10'b1111_1100_11, - 10'b1111_1100_11, - 10'b1111_1100_11, - 10'b1111_1100_11, - 10'b1111_1100_11, - 10'b1110_0010_11, - 10'b1110_0010_11, - 10'b1110_0010_11, - 10'b1110_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1101_0100_11, - 10'b1101_0100_11, - 10'b1101_0100_11, - 10'b1101_0100_11, - 10'b1101_0100_11, - 10'b1101_0100_11, - 10'b1101_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1101_1000_11, - 10'b1101_1000_11, - 10'b1101_1000_11, - 10'b1101_1000_11, - 10'b1101_1000_11, - 10'b1101_1000_11, - 10'b1101_1000_11, - 10'b1101_1000_11, - 10'b1101_1000_11 // M=128 -}; - - // Set lookup_entry with the explicit bits from lookup with a part select - if(BANDWIDTH == "LOW") begin - // Low Bandwidth - mmcm_pll_filter_lookup = lookup_low[ ((128-divide)*10) +: 10]; - end else begin - // High or optimized bandwidth - mmcm_pll_filter_lookup = lookup_high[ ((128-divide)*10) +: 10]; - end - - `ifdef DEBUG - $display("filter_lookup: %b", mmcm_pll_filter_lookup); - `endif - end -endfunction - -// This function takes in the divide, phase, and duty cycle -// setting to calculate the upper and lower counter registers. -function [37:0] mmcm_pll_count_calc - ( - input [7:0] divide, // Max divide is 128 - input signed [31:0] phase, - input [31:0] duty_cycle // Multiplied by 100,000 - ); - - reg [13:0] div_calc; - reg [16:0] phase_calc; - - begin - `ifdef DEBUG - $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", - divide, phase, duty_cycle); - `endif - - // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] - div_calc = mmcm_pll_divider(divide, duty_cycle); - // mx[10:9], pm[8:6], dt[5:0] - phase_calc = mmcm_pll_phase(divide, phase); - - // Return value is the upper and lower address of counter - // Upper address is: - // RESERVED [31:26] - // MX [25:24] - // EDGE [23] - // NOCOUNT [22] - // DELAY_TIME [21:16] - // Lower Address is: - // PHASE_MUX [15:13] - // RESERVED [12] - // HIGH_TIME [11:6] - // LOW_TIME [5:0] - - `ifdef DEBUG - $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", - divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], - div_calc[13], div_calc[12], - phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); - `endif - - mmcm_pll_count_calc = - { - // Upper Address - 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], - // Lower Address - phase_calc[8:6], 1'b0, div_calc[11:0] - }; - end -endfunction - - -// This function takes in the divide, phase, and duty cycle -// setting to calculate the upper and lower counter registers. -// for fractional multiply/divide functions. -// -// -function [37:0] mmcm_frac_count_calc - ( - input [7:0] divide, // Max divide is 128 - input signed [31:0] phase, - input [31:0] duty_cycle, // Multiplied by 100,000. Not programmable in fractional - input [9:0] frac // Multiplied by 1000 - ); - - //Required for fractional divide calculations - reg [7:0] lt_frac; - reg [7:0] ht_frac; - - reg /*[7:0]*/ wf_fall_frac; - reg /*[7:0]*/ wf_rise_frac; - - reg [31:0] a; - reg [7:0] pm_rise_frac_filtered ; - reg [7:0] pm_fall_frac_filtered ; - reg [7:0] clkout0_divide_int; - reg [2:0] clkout0_divide_frac; - reg [7:0] even_part_high; - reg [7:0] even_part_low; - - reg [7:0] odd; - reg [7:0] odd_and_frac; - - reg [7:0] pm_fall; - reg [7:0] pm_rise; - reg [7:0] dt; - reg [7:0] dt_int; - reg [63:0] dt_calc; - - reg [7:0] pm_rise_frac; - reg [7:0] pm_fall_frac; - - reg [31:0] a_per_in_octets; - reg [31:0] a_phase_in_cycles; - - parameter precision = 0.125; - - reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 - reg [31: 0] phase_pos; - reg [31: 0] phase_vco; - reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 - reg [13:0] div_calc; - reg [16:0] phase_calc; - - begin - `ifdef DEBUG - $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", - divide, phase, duty_cycle); - `endif - - //convert phase to fixed - if ((phase < -360000) || (phase > 360000)) begin -`ifndef SYNTHESIS - $display("ERROR: phase of $phase is not between -360000 and 360000"); - `endif - $finish; - end - - - // Return value is - // Transfer data - // RESERVED [37:36] - // FRAC_TIME [35:33] - // FRAC_WF_FALL [32] - // Upper address is: - // RESERVED [31:26] - // MX [25:24] - // EDGE [23] - // NOCOUNT [22] - // DELAY_TIME [21:16] - // Lower Address is: - // PHASE_MUX [15:13] - // RESERVED [12] - // HIGH_TIME [11:6] - // LOW_TIME [5:0] - - - - clkout0_divide_frac = frac / 125; - clkout0_divide_int = divide; - - even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); - even_part_low = even_part_high; - - odd = clkout0_divide_int - even_part_high - even_part_low; - odd_and_frac = (8*odd) + clkout0_divide_frac; - - lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) - ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) - - pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 - pm_rise = 0; //0 - - wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || (clkout0_divide_int == 2 && clkout0_divide_frac == 1); //IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0) - wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8); //IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) - - - - //Calculate phase in fractional cycles - a_per_in_octets = (8 * divide) + (frac / 125) ; - a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors - pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; - - dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) - dt = dt_calc[7:0]; - - pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; - - dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) - pm_fall_frac = pm_fall + pm_rise_frac; - pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; - - div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] - phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} - - mmcm_frac_count_calc[37:0] = - { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, - 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], 2'b00, dt[5:0], - pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] - } ; - - `ifdef DEBUG - $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac); - `endif - - end -endfunction - diff --git a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_pll.vh b/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_pll.vh deleted file mode 100755 index 1d2dc69..0000000 --- a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_pll.vh +++ /dev/null @@ -1,536 +0,0 @@ -/////////////////////////////////////////////////////////////////////////////// -// -// Company: Xilinx -// Engineer: Jim Tatsukawa, Ralf Krueger, updated for Ultrascale+ -// Date: 6/15/2015 -// Design Name: PLLE4 DRP -// Module Name: plle4_drp_func.h -// Version: 2.0 -// Target Devices: UltraScale+ Architecture -// Tool versions: 2017.1 -// Description: This header provides the functions necessary to -// calculate the DRP register values for the V6 PLL. -// -// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419 -// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19 -// M_Rise bits have been removed for PLLE3 -// Revision Notes: 2/28/17 - pll_filter_lookup and CPRES updated for -// Ultrascale+ and for max M of 21 -// -// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR -// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING -// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -// APPLICATION OR STANDARD, XILINX IS MAKING NO -// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE -// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY -// REQUIRE FOR YOUR IMPLEMENTATION. XILINX -// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH -// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, -// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE -// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES -// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -// PURPOSE. -// -// (c) Copyright 2009-2017 Xilinx, Inc. -// All rights reserved. -// -/////////////////////////////////////////////////////////////////////////////// - -// These are user functions that should not be modified. Changes to the defines -// or code within the functions may alter the accuracy of the calculations. - -// Define debug to provide extra messages durring elaboration -//`define DEBUG 1 - -// FRAC_PRECISION describes the width of the fractional portion of the fixed -// point numbers. These should not be modified, they are for development -// only -`define FRAC_PRECISION 10 -// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). -// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs -// greater than 32 -`define FIXED_WIDTH 32 - -// This function takes a fixed point number and rounds it to the nearest -// fractional precision bit. -function [`FIXED_WIDTH:1] round_frac - ( - // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number - input [`FIXED_WIDTH:1] decimal, - - // This describes the precision of the fraction, for example a value - // of 1 would modify the fractional so that instead of being a .16 - // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) - input [`FIXED_WIDTH:1] precision - ); - - begin - - `ifdef DEBUG - $display("round_frac - decimal: %h, precision: %h", decimal, precision); - `endif - // If the fractional precision bit is high then round up - if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin - round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); - end else begin - round_frac = decimal; - end - `ifdef DEBUG - $display("round_frac: %h", round_frac); - `endif - end -endfunction - -// This function calculates high_time, low_time, w_edge, and no_count -// of a non-fractional counter based on the divide and duty cycle -// -// NOTE: high_time and low_time are returned as integers between 0 and 63 -// inclusive. 64 should equal 6'b000000 (in other words it is okay to -// ignore the overflow) -function [13:0] mmcm_pll_divider - ( - input [7:0] divide, // Max divide is 128 - input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 - ); - - reg [`FIXED_WIDTH:1] duty_cycle_fix; - - // High/Low time is initially calculated with a wider integer to prevent a - // calculation error when it overflows to 64. - reg [6:0] high_time; - reg [6:0] low_time; - reg w_edge; - reg no_count; - - reg [`FIXED_WIDTH:1] temp; - - begin - // Duty Cycle must be between 0 and 1,000 - if(duty_cycle <=0 || duty_cycle >= 100000) begin -`ifndef SYNTHESIS - $display("ERROR: duty_cycle: %d is invalid", duty_cycle); - `endif - $finish; - end - - // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point - duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; - - `ifdef DEBUG - $display("duty_cycle_fix: %h", duty_cycle_fix); - `endif - - // If the divide is 1 nothing needs to be set except the no_count bit. - // Other values are dummies - if(divide == 7'h01) begin - high_time = 7'h01; - w_edge = 1'b0; - low_time = 7'h01; - no_count = 1'b1; - end else begin - temp = round_frac(duty_cycle_fix*divide, 1); - - // comes from above round_frac - high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; - // If the duty cycle * divide rounded is .5 or greater then this bit - // is set. - w_edge = temp[`FRAC_PRECISION]; // comes from round_frac - - // If the high time comes out to 0, it needs to be set to at least 1 - // and w_edge set to 0 - if(high_time == 7'h00) begin - high_time = 7'h01; - w_edge = 1'b0; - end - - if(high_time == divide) begin - high_time = divide - 1; - w_edge = 1'b1; - end - - // Calculate low_time based on the divide setting and set no_count to - // 0 as it is only used when divide is 1. - low_time = divide - high_time; - no_count = 1'b0; - end - - // Set the return value. - mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; - end -endfunction - -// This function calculates mx, delay_time, and phase_mux -// of a non-fractional counter based on the divide and phase -// -// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux -// is used. -function [10:0] mmcm_pll_phase - ( - // divide must be an integer (use fractional if not) - // assumed that divide already checked to be valid - input [7:0] divide, // Max divide is 128 - - // Phase is given in degrees (-360,000 to 360,000) - input signed [31:0] phase - ); - - reg [`FIXED_WIDTH:1] phase_in_cycles; - reg [`FIXED_WIDTH:1] phase_fixed; - reg [1:0] mx; - reg [5:0] delay_time; - reg [2:0] phase_mux; - - reg [`FIXED_WIDTH:1] temp; - - begin -`ifdef DEBUG - $display("pll_phase-divide:%d,phase:%d", - divide, phase); -`endif - - if ((phase < -360000) || (phase > 360000)) begin -`ifndef SYNTHESIS - $display("ERROR: phase of $phase is not between -360000 and 360000"); -`endif - $finish; - end - - // If phase is less than 0, convert it to a positive phase shift - // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point - if(phase < 0) begin - phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; - end else begin - phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; - end - - // Put phase in terms of decimal number of vco clock cycles - phase_in_cycles = ( phase_fixed * divide ) / 360; - -`ifdef DEBUG - $display("phase_in_cycles: %h", phase_in_cycles); -`endif - - - temp = round_frac(phase_in_cycles, 3); - - // set mx to 2'b00 that the phase mux from the VCO is enabled - mx = 2'b00; - phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; - delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; - - `ifdef DEBUG - $display("temp: %h", temp); - `endif - - // Setup the return value - mmcm_pll_phase={mx, phase_mux, delay_time}; - end -endfunction - -// This function takes the divide value and outputs the necessary lock values -function [39:0] mmcm_pll_lock_lookup - ( - input [6:0] divide // Max divide is 21 - ); - - reg [839:0] lookup; - - begin - lookup = { - // This table is composed of: - // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt - 40'b00110_00110_1111101000_1111101001_0000000001, //1 illegal in Ultrascale+ - 40'b00110_00110_1111101000_1111101001_0000000001, //2 - 40'b01000_01000_1111101000_1111101001_0000000001, //3 - 40'b01011_01011_1111101000_1111101001_0000000001, //4 - 40'b01110_01110_1111101000_1111101001_0000000001, //5 - 40'b10001_10001_1111101000_1111101001_0000000001, //6 - 40'b10011_10011_1111101000_1111101001_0000000001, //7 - 40'b10110_10110_1111101000_1111101001_0000000001, //8 - 40'b11001_11001_1111101000_1111101001_0000000001, //9 - 40'b11100_11100_1111101000_1111101001_0000000001, //10 - 40'b11111_11111_1110000100_1111101001_0000000001, //11 - 40'b11111_11111_1100111001_1111101001_0000000001, //12 - 40'b11111_11111_1011101110_1111101001_0000000001, //13 - 40'b11111_11111_1010111100_1111101001_0000000001, //14 - 40'b11111_11111_1010001010_1111101001_0000000001, //15 - 40'b11111_11111_1001110001_1111101001_0000000001, //16 - 40'b11111_11111_1000111111_1111101001_0000000001, //17 - 40'b11111_11111_1000100110_1111101001_0000000001, //18 - 40'b11111_11111_1000001101_1111101001_0000000001, //19 - 40'b11111_11111_0111110100_1111101001_0000000001, //20 - 40'b11111_11111_0111011011_1111101001_0000000001 //21 - }; - - // Set lookup_entry with the explicit bits from lookup with a part select - mmcm_pll_lock_lookup = lookup[ ((21-divide)*40) +: 40]; - `ifdef DEBUG - $display("lock_lookup: %b", pll_lock_lookup); - `endif - end -endfunction - -// This function takes the divide value and the bandwidth setting of the PLL -// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3. -function [9:0] mmcm_pll_filter_lookup - ( - input [6:0] divide // Max divide is 21 - ); - - reg [209:0] lookup; - reg [9:0] lookup_entry; - - begin - - lookup = { - // CP_RES_LFHF - 10'b0011_0111_11, //1 not legal in Ultrascale+ - 10'b0011_0111_11, //2 - 10'b0011_0011_11, //3 - 10'b0011_1001_11, //4 - 10'b0011_0001_11, //5 - 10'b0100_1110_11, //6 - 10'b0011_0110_11, //7 - 10'b0011_1010_11, //8 - 10'b0111_1001_11, //9 - 10'b0111_1001_11, //10 - 10'b0101_0110_11, //11 - 10'b1100_0101_11, //12 - 10'b0101_1010_11, //13 - 10'b0110_0110_11, //14 - 10'b0110_1010_11, //15 - 10'b0111_0110_11, //16 - 10'b1111_0101_11, //17 - 10'b1100_0110_11, //18 - 10'b1110_0001_11, //19 - 10'b1101_0110_11, //20 - 10'b1111_0001_11 //21 - }; - - mmcm_pll_filter_lookup = lookup [ ((21-divide)*10) +: 10]; - - `ifdef DEBUG - $display("filter_lookup: %b", pll_filter_lookup); - `endif - end -endfunction - -// This function set the CLKOUTPHY divide settings to match -// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then -// the CLKOUTPHY will be set to 2'b00 since the VCO is internally -// doubled and 2'b00 will represent divide by 1. Similarly "VCO" -// will need to divide the doubled clock VCO clock frequency by -// 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will -// need to divide the doubled VCO by 4, therefore 2'b10 -function [9:0] mmcm_pll_clkoutphy_calc - ( - input [8*9:0] CLKOUTPHY_MODE - ); - - if(CLKOUTPHY_MODE == "VCO_X2") begin - mmcm_pll_clkoutphy_calc= 2'b00; - end else if(CLKOUTPHY_MODE == "VCO") begin - mmcm_pll_clkoutphy_calc= 2'b01; - end else if(CLKOUTPHY_MODE == "CLKIN") begin - mmcm_pll_clkoutphy_calc= 2'b11; - end else begin // Assume "VCO_HALF" - mmcm_pll_clkoutphy_calc= 2'b10; - end - -endfunction - - -// This function takes in the divide, phase, and duty cycle -// setting to calculate the upper and lower counter registers. -function [37:0] mmcm_pll_count_calc - ( - input [7:0] divide, // Max divide is 128 - input signed [31:0] phase, - input [31:0] duty_cycle // Multiplied by 100,000 - ); - - reg [13:0] div_calc; - reg [16:0] phase_calc; - - begin - `ifdef DEBUG - $display("pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", - divide, phase, duty_cycle); - `endif - - // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] - div_calc = mmcm_pll_divider(divide, duty_cycle); - // mx[10:9], pm[8:6], dt[5:0] - phase_calc = mmcm_pll_phase(divide, phase); - - // Return value is the upper and lower address of counter - // Upper address is: - // RESERVED [31:26] - // MX [25:24] - // EDGE [23] - // NOCOUNT [22] - // DELAY_TIME [21:16] - // Lower Address is: - // PHASE_MUX [15:13] - // RESERVED [12] - // HIGH_TIME [11:6] - // LOW_TIME [5:0] - - `ifdef DEBUG - $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", - divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], - div_calc[13], div_calc[12], - phase_calc[16:15], phase_calc[5:0], 3'b000); //Removed PM_Rise bits - `endif - - mmcm_pll_count_calc = - { - // Upper Address - 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], - // Lower Address - phase_calc[8:6], 1'b0, div_calc[11:0] - }; - end -endfunction - - -// This function takes in the divide, phase, and duty cycle -// setting to calculate the upper and lower counter registers. -// for fractional multiply/divide functions. -// -// -function [37:0] mmcm_pll_frac_count_calc - ( - input [7:0] divide, // Max divide is 128 - input signed [31:0] phase, - input [31:0] duty_cycle, // Multiplied by 1,000 - input [9:0] frac // Multiplied by 1000 - ); - - //Required for fractional divide calculations - reg [7:0] lt_frac; - reg [7:0] ht_frac; - - reg /*[7:0]*/ wf_fall_frac; - reg /*[7:0]*/ wf_rise_frac; - - reg [31:0] a; - reg [7:0] pm_rise_frac_filtered ; - reg [7:0] pm_fall_frac_filtered ; - reg [7:0] clkout0_divide_int; - reg [2:0] clkout0_divide_frac; - reg [7:0] even_part_high; - reg [7:0] even_part_low; - - reg [7:0] odd; - reg [7:0] odd_and_frac; - - reg [7:0] pm_fall; - reg [7:0] pm_rise; - reg [7:0] dt; - reg [7:0] dt_int; - reg [63:0] dt_calc; - - reg [7:0] pm_rise_frac; - reg [7:0] pm_fall_frac; - - reg [31:0] a_per_in_octets; - reg [31:0] a_phase_in_cycles; - - parameter precision = 0.125; - - reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 - reg [31: 0] phase_pos; - reg [31: 0] phase_vco; - reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 - reg [13:0] div_calc; - reg [16:0] phase_calc; - - begin - `ifdef DEBUG - $display("pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", - divide, phase, duty_cycle); - `endif - - //convert phase to fixed - if ((phase < -360000) || (phase > 360000)) begin -`ifndef SYNTHESIS - $display("ERROR: phase of $phase is not between -360000 and 360000"); - `endif - $finish; - end - - - // Return value is - // Transfer data - // RESERVED [37:36] - // FRAC_TIME [35:33] - // FRAC_WF_FALL [32] - // Upper address is: - // RESERVED [31:26] - // MX [25:24] - // EDGE [23] - // NOCOUNT [22] - // DELAY_TIME [21:16] - // Lower Address is: - // PHASE_MUX [15:13] - // RESERVED [12] - // HIGH_TIME [11:6] - // LOW_TIME [5:0] - - - - clkout0_divide_frac = frac / 125; - clkout0_divide_int = divide; - - even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); - even_part_low = even_part_high; - - odd = clkout0_divide_int - even_part_high - even_part_low; - odd_and_frac = (8*odd) + clkout0_divide_frac; - - lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) - ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) - - pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 - pm_rise = 0; //0 - - wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0) - wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) - - - - //Calculate phase in fractional cycles - a_per_in_octets = (8 * divide) + (frac / 125) ; - a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors - pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; - - dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) - dt = dt_calc[7:0]; - - pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; - - dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) - pm_fall_frac = pm_fall + pm_rise_frac; - pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; - - div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] - phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} - - mmcm_pll_frac_count_calc[37:0] = - { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, - 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], - 3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits - } ; - - `ifdef DEBUG - $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac); - `endif - - end -endfunction - diff --git a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/doc/vio_v3_0_changelog.txt b/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/doc/vio_v3_0_changelog.txt deleted file mode 100755 index 0165728..0000000 --- a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/doc/vio_v3_0_changelog.txt +++ /dev/null @@ -1,190 +0,0 @@ -2019.2: - * Version 3.0 (Rev. 19) - * No changes - -2019.1.3: - * Version 3.0 (Rev. 19) - * No changes - -2019.1.2: - * Version 3.0 (Rev. 19) - * No changes - -2019.1.1: - * Version 3.0 (Rev. 19) - * No changes - -2019.1: - * Version 3.0 (Rev. 19) - * No changes - -2018.3.1: - * Version 3.0 (Rev. 19) - * No changes - -2018.3: - * Version 3.0 (Rev. 19) - * No changes - -2018.2: - * Version 3.0 (Rev. 19) - * General: virtexuplus58g device support added - -2018.1: - * Version 3.0 (Rev. 18) - * General: Internal subcore reference changes - -2017.4: - * Version 3.0 (Rev. 17) - * No changes - -2017.3: - * Version 3.0 (Rev. 17) - * spartan7 automotive device support added - -2017.2: - * Version 3.0 (Rev. 16) - * azynquplus device support added - -2017.1: - * Version 3.0 (Rev. 15) - * XDC updated for zynquplus devices - * Revision change in one or more subcores - -2016.4: - * Version 3.0 (Rev. 14) - * Revision change in one or more subcores - -2016.3: - * Version 3.0 (Rev. 13) - * gui_tcl is changed to 2.0 - * Revision change in one or more subcores - -2016.2: - * Version 3.0 (Rev. 12) - * Re customization issue fixed - * Revision change in one or more subcores - -2016.1: - * Version 3.0 (Rev. 11) - * IP generation error for 256 probe_outs fixed - * Revision change in one or more subcores - -2015.4.2: - * Version 3.0 (Rev. 10) - * No changes - -2015.4.1: - * Version 3.0 (Rev. 10) - * No changes - -2015.4: - * Version 3.0 (Rev. 10) - * Revision change in one or more subcores - -2015.3: - * Version 3.0 (Rev. 9) - * family name change - zynqplus and virtexplus - * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances - * Revision change in one or more subcores - -2015.2.1: - * Version 3.0 (Rev. 8) - * No changes - -2015.2: - * Version 3.0 (Rev. 8) - * Added Support for zynque and virtexum - -2015.1: - * Version 3.0 (Rev. 7) - * Added synchronizer for cdc - -2014.4.1: - * Version 3.0 (Rev. 6) - * Updated example XDC pin location constraints for new devices - -2014.4: - * Version 3.0 (Rev. 5) - * Internal device family change, no functional changes - * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time - -2014.3: - * Version 3.0 (Rev. 4) - * activity generation bug fix - -2014.2: - * Version 3.0 (Rev. 3) - * simplified constraint defination - * Improved Distributed RAM usage - -2014.1: - * Version 3.0 (Rev. 2) - * Kintex UltraScale support - * xsdb stitching enhancements - * Internal device family name change, no functional changes - -2013.4: - * Version 3.0 (Rev. 1) - * Kintex UltraScale Pre-Production support - -2013.3: - * Version 3.0 - * Port Names changed to lower case - -2013.2: - * Version 2.0 (Rev. 1) - * Improved support for multiple instances. - * Improved Timing - * Made the following package changes for XQ7A200, 'FB484 to RB484, FB676 to RB676, SB484 to RS484 and XQ7Z030, FB484 to RB484, Removed -2L support from the XQ7V690T and XQ7A, all to match silicon planning changes' - -2013.1: - * Version 2.0 - * Native Vivado Release - * There have been no functional or interface changes to this IP. The version number has changed to support unique versioning in Vivado starting with 2013.1. - -(c) Copyright 2000 - 2019 Xilinx, Inc. All rights reserved. - -This file contains confidential and proprietary information -of Xilinx, Inc. and is protected under U.S. and -international copyright and other intellectual property -laws. - -DISCLAIMER -This disclaimer is not a license and does not grant any -rights to the materials distributed herewith. Except as -otherwise provided in a valid license issued to you by -Xilinx, and to the maximum extent permitted by applicable -law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -(2) Xilinx shall not be liable (whether in contract or tort, -including negligence, or under any other theory of -liability) for any loss or damage of any kind or nature -related to, arising under or in connection with these -materials, including for any direct, or any indirect, -special, incidental, or consequential loss or damage -(including loss of data, profits, goodwill, or any type of -loss or damage suffered as a result of any action brought -by a third party) even if such damage or loss was -reasonably foreseeable or Xilinx had been advised of the -possibility of the same. - -CRITICAL APPLICATIONS -Xilinx products are not designed or intended to be fail- -safe, or for use in any application requiring fail-safe -performance, such as life-support or safety devices or -systems, Class III medical devices, nuclear facilities, -applications related to the deployment of airbags, or any -other applications that could lead to death, personal -injury, or severe property or environmental damage -(individually and collectively, "Critical -Applications"). Customer assumes the sole risk and -liability of any use of Xilinx products in Critical -Applications, subject only to applicable laws and -regulations governing limitations on product liability. - -THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -PART OF THIS FILE AT ALL TIMES. diff --git a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/ltlib_v1_0_vl_rfs.v b/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/ltlib_v1_0_vl_rfs.v deleted file mode 100755 index dbf66f4..0000000 --- a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/ltlib_v1_0_vl_rfs.v +++ /dev/null @@ -1,1209 +0,0 @@ -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "XILINX" -`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1" -`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" -`pragma protect encoding = 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a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog/ltlib_v1_0_0_lib_fn.vh +++ /dev/null @@ -1,104 +0,0 @@ -/*---------------------------------------------------------------------------- - * Copyright (c) 2011 Xilinx, Inc. - * This design is confidential and proprietary of Xilinx, All Rights Reserved. - *----------------------------------------------------------------------------- - * ____ ____ - * / /\/ / - * /___/ \ / Vendor: Xilinx - * \ \ \/ Date Created: 2011/04/26 - * \ \ - * / / - * /___/ /\ - * \ \ / \ - * \___\/\___\ - * - *Device: All - *Purpose: - * General functions used by other Labtools IP cores. Functions will - * be added as needed. - * - *Notes: - * Include the file inside the Verilog module after the module and port - * section. Do not include at the top of the module. - * - *----------------------------------------------------------------------------*/ - -`include "ltlib_v1_0_0_ver.vh" - - function integer clogb2; - input integer depth; - integer d; - begin - if (depth == 0) - clogb2 = 1; - else - begin - d = depth; - for (clogb2=0; d > 0; clogb2 = clogb2+1) - d = d >> 1; - end - end - endfunction - - function string_contains; - input [`FAMILY_NAME_LENGTH*8-1:0] familyName; - input [`FAMILY_NAME_LENGTH*8-1:0] expectedName; - input integer expectedLength; - integer i; - integer j; - reg temp_contain; - begin - string_contains = 1; - temp_contain = 0; - for (i=0; i<`FAMILY_NAME_LENGTH; i=i+1) - begin - if (familyName[(8*i)+:8] == expectedName[0+:8]) - begin - temp_contain = 1; - for (j=0; j clk, - probe_in0 => probe_in0, - probe_in1 => probe_in1, - probe_out0 => probe_out0 - ); --- INST_TAG_END ------ End INSTANTIATION Template --------- - --- You must compile the wrapper file vio_0.vhd when simulating --- the core, vio_0. When compiling the wrapper file, be sure to --- reference the VHDL simulation library. - diff --git a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/vio_0.xdc b/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/vio_0.xdc deleted file mode 100755 index 4736aa9..0000000 --- a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/vio_0.xdc +++ /dev/null @@ -1,71 +0,0 @@ -# file: vio_0.xdc -#//////////////////////////////////////////////////////////////////////////// -#/$Date: 2012/02/06 10:34:16 $ -#/$RCSfile: $ -#/$Revision: 1.2 $ -#////////////////////////////////////////////////////////////////////////////// -#/ ____ ____ -#/ / /\/ / -#/ /___/ \ / Vendor: Xilinx -#/ \ \ \/ Version : 2.00 -#/ \ \ Application : VIO V2.00a -#/ / / Filename : vio_0.xdc -#/ /___/ /\ -#/ \ \ / \ -#/ \___\/\___\ -#/ -#/ (c) Copyright 2010 Xilinx, Inc. All rights reserved. -#/ -#/ This file contains confidential and proprietary information -#/ of Xilinx, Inc. and is protected under U.S. and -#/ international copyright and other intellectual property -#/ laws. -#/ -#/ DISCLAIMER -#/ This disclaimer is not a license and does not grant any -#/ rights to the materials distributed herewith. Except as -#/ otherwise provided in a valid license issued to you by -#/ Xilinx, and to the maximum extent permitted by applicable -#/ law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -#/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -#/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -#/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -#/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -#/ (2) Xilinx shall not be liable (whether in contract or tort, -#/ including negligence, or under any other theory of -#/ liability) for any loss or damage of any kind or nature -#/ related to, arising under or in connection with these -#/ materials, including for any direct, or any indirect, -#/ special, incidental, or consequential loss or damage -#/ (including loss of data, profits, goodwill, or any type of -#/ loss or damage suffered as a result of any action brought -#/ by a third party) even if such damage or loss was -#/ reasonably foreseeable or Xilinx had been advised of the -#/ possibility of the same. -#/ -#/ CRITICAL APPLICATIONS -#/ Xilinx products are not designed or intended to be fail- -#/ safe, or for use in any application requiring fail-safe -#/ performance, such as life-support or safety devices or -#/ systems, Class III medical devices, nuclear facilities, -#/ applications related to the deployment of airbags, or any -#/ other applications that could lead to death, personal -#/ injury, or severe property or environmental damage -#/ (individually and collectively, "Critical -#/ Applications"). Customer assumes the sole risk and -#/ liability of any use of Xilinx products in Critical -#/ Applications, subject only to applicable laws and -#/ regulations governing limitations on product liability. -#/ -#/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -#/ PART OF THIS FILE AT ALL TIMES. -#Created by Constraints Editor - - set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*Hold_probe_in*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*PROBE_IN_INST/probe_in_reg*" && IS_SEQUENTIAL} ] - set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*PROBE_IN_INST/probe_in_reg*" && IS_SEQUENTIAL} ] -to [get_cells -hierarchical -filter { NAME =~ "*data_int_sync1*" && IS_SEQUENTIAL } ] - - set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*committ_int*" && IS_SEQUENTIAL}] -to [get_cells -hierarchical -filter { NAME =~ "*Committ_1*" && IS_SEQUENTIAL} ] - set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*clear_int*" && IS_SEQUENTIAL}] -to [get_cells -hierarchical -filter { NAME =~ "*Probe_out*" && IS_SEQUENTIAL}] - set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*clear_int*" && IS_SEQUENTIAL }] -to [get_cells -hierarchical -filter { NAME =~ "*PROBE_OUT_ALL_INST/G_PROBE_OUT[*].PROBE_OUT0_INST/data_int*" && IS_SEQUENTIAL}] - set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*data_int_*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*Probe_out_*" && IS_SEQUENTIAL} ] - set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*clear_int*" && IS_SEQUENTIAL }] -to [get_cells -hierarchical -filter { NAME =~ "*PROBE_OUT_ALL_INST/G_PROBE_OUT[*].PROBE_OUT0_INST/LOOP_I[*].data_int*" && IS_SEQUENTIAL }] diff --git a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/vio_0.xml b/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/vio_0.xml deleted file mode 100755 index 9230380..0000000 --- a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/vio_0.xml +++ /dev/null @@ -1,20775 +0,0 @@ - - - xilinx.com - customized_ip - vio_0 - 1.0 - - - signal_clock - - - - - - - CLK - - - clk - - - - - - FREQ_HZ - aclk frequency - aclk frequency - 100000000 - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - - - xilinx_veriloginstantiationtemplate - Verilog Instantiation Template - verilogSource:vivado.xilinx.com:synthesis.template - verilog - - xilinx_veriloginstantiationtemplate_view_fileset - - - - GENtimestamp - Tue Mar 29 16:41:29 UTC 2022 - - - outputProductCRC - 9:a75fc7e5 - - - - - xilinx_anylanguagesynthesis - Synthesis - :vivado.xilinx.com:synthesis - vio_v3_0_19_vio - - xilinx_anylanguagesynthesis_xilinx_com_ip_ltlib_1_0__ref_view_fileset - - - xilinx_anylanguagesynthesis_xilinx_com_ip_xsdbs_1_0__ref_view_fileset - - - xilinx_anylanguagesynthesis_view_fileset - - - - GENtimestamp - Tue Mar 29 16:41:32 UTC 2022 - - - outputProductCRC - 9:a75fc7e5 - - - - - xilinx_synthesisconstraints - Synthesis Constraints - :vivado.xilinx.com:synthesis.constraints - - xilinx_synthesisconstraints_view_fileset - - - - GENtimestamp - Tue Mar 29 16:41:32 UTC 2022 - - - outputProductCRC - 9:a75fc7e5 - - - - - xilinx_verilogsynthesiswrapper - Verilog Synthesis Wrapper - verilogSource:vivado.xilinx.com:synthesis.wrapper - verilog - vio_0 - - xilinx_verilogsynthesiswrapper_view_fileset - - - - GENtimestamp - Tue Mar 29 16:41:32 UTC 2022 - - - outputProductCRC - 9:a75fc7e5 - - - - - xilinx_verilogsimulationwrapper - Verilog Simulation Wrapper - verilogSource:vivado.xilinx.com:simulation.wrapper - verilog - vio_0 - - xilinx_verilogsimulationwrapper_view_fileset - - - - GENtimestamp - Tue Mar 29 16:41:32 UTC 2022 - - - outputProductCRC - 9:969108a8 - - - - - xilinx_versioninformation - Version Information - :vivado.xilinx.com:docs.versioninfo - - xilinx_versioninformation_view_fileset - - - - GENtimestamp - Tue Mar 29 16:41:32 UTC 2022 - - - outputProductCRC - 9:a75fc7e5 - - - - - xilinx_externalfiles - External Files - :vivado.xilinx.com:external.files - - xilinx_externalfiles_view_fileset - - - - GENtimestamp - Fri Apr 01 12:55:36 UTC 2022 - - - outputProductCRC - 9:a75fc7e5 - - - - - - - clk - - in - - - std_logic - xilinx_anylanguagesynthesis - - - - - - probe_in0 - - in - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - - - - 0 - - - - - - true - - - - - - probe_in1 - - in - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - - - - 0 - - - - - - true - - - - - - probe_in2 - - in - - 0 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - - - - 0 - - - - - - false - - - - - - probe_in3 - - in - - 0 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - - - - 0 - - - - - - false - - - - - - probe_in4 - - in - - 0 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - - - - 0 - - - - - - false - - - - - - probe_in5 - - in - - 0 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - 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PROBE IN43 WIDTH - 1 - - - C_PROBE_IN42_WIDTH - PROBE IN42 WIDTH - 1 - - - C_PROBE_IN41_WIDTH - PROBE IN41 WIDTH - 1 - - - C_PROBE_IN40_WIDTH - PROBE IN40 WIDTH - 1 - - - C_PROBE_IN39_WIDTH - PROBE IN39 WIDTH - 1 - - - C_PROBE_IN38_WIDTH - PROBE IN38 WIDTH - 1 - - - C_PROBE_IN37_WIDTH - PROBE IN37 WIDTH - 1 - - - C_PROBE_IN36_WIDTH - PROBE IN36 WIDTH - 1 - - - C_PROBE_IN35_WIDTH - PROBE IN35 WIDTH - 1 - - - C_PROBE_IN34_WIDTH - PROBE IN34 WIDTH - 1 - - - C_PROBE_IN33_WIDTH - PROBE IN33 WIDTH - 1 - - - C_PROBE_IN32_WIDTH - PROBE IN32 WIDTH - 1 - - - C_PROBE_IN31_WIDTH - PROBE IN31 WIDTH - 1 - - - C_PROBE_IN30_WIDTH - PROBE IN30 WIDTH - 1 - - - C_PROBE_IN29_WIDTH - PROBE IN29 WIDTH - 1 - - - C_PROBE_IN28_WIDTH - PROBE IN28 WIDTH - 1 - - - C_PROBE_IN27_WIDTH - PROBE IN27 WIDTH - 1 - - - C_PROBE_IN26_WIDTH - PROBE IN26 WIDTH - 1 - - - C_PROBE_IN25_WIDTH - PROBE IN25 WIDTH - 1 - - - C_PROBE_IN24_WIDTH - PROBE IN24 WIDTH - 1 - - - C_PROBE_IN23_WIDTH - PROBE IN23 WIDTH - 1 - - - C_PROBE_IN22_WIDTH - PROBE IN22 WIDTH - 1 - - - C_PROBE_IN21_WIDTH - PROBE IN21 WIDTH - 1 - - - C_PROBE_IN20_WIDTH - PROBE IN20 WIDTH - 1 - - - C_PROBE_IN19_WIDTH - PROBE IN19 WIDTH - 1 - - - C_PROBE_IN18_WIDTH - PROBE IN18 WIDTH - 1 - - - C_PROBE_IN17_WIDTH - PROBE IN17 WIDTH - 1 - - - C_PROBE_IN16_WIDTH - PROBE IN16 WIDTH - 1 - - - C_PROBE_IN15_WIDTH - PROBE IN15 WIDTH - 1 - - - C_PROBE_IN14_WIDTH - PROBE IN14 WIDTH - 1 - - - C_PROBE_IN13_WIDTH - PROBE IN13 WIDTH - 1 - - - C_PROBE_IN12_WIDTH - PROBE IN12 WIDTH - 1 - - - C_PROBE_IN11_WIDTH - PROBE IN11 WIDTH - 1 - - - C_PROBE_IN10_WIDTH - PROBE IN10 WIDTH - 1 - - - C_PROBE_IN9_WIDTH - PROBE IN9 WIDTH - 1 - - - C_PROBE_IN8_WIDTH - PROBE IN8 WIDTH - 1 - - - C_PROBE_IN7_WIDTH - PROBE IN7 WIDTH - 1 - - - C_PROBE_IN6_WIDTH - PROBE IN6 WIDTH - 1 - - - C_PROBE_IN5_WIDTH - PROBE IN5 WIDTH - 1 - - - C_PROBE_IN4_WIDTH - PROBE IN4 WIDTH - 1 - - - C_PROBE_IN3_WIDTH - PROBE IN3 WIDTH - 1 - - - C_PROBE_IN2_WIDTH - PROBE IN2 WIDTH - 1 - - - C_PROBE_IN1_WIDTH - PROBE IN1 WIDTH - 32 - - - C_PROBE_IN0_WIDTH - PROBE IN0 WIDTH - 32 - - - C_EN_SYNCHRONIZATION - C En Synchronization - 1 - - - C_NUM_PROBE_OUT - Output Probe Count - 1 - - - C_EN_PROBE_IN_ACTIVITY - Enable Input Probe Activity Detectors - 1 - - - C_NUM_PROBE_IN - Input Probe Count - 2 - - - Component_Name - vio_0 - - - - - VIO (Virtual Input/Output) - 19 - - - - - - - - - 2019.2 - - - - - - - - diff --git a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/vio_0_ooc.xdc b/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/vio_0_ooc.xdc deleted file mode 100755 index e6a3cf8..0000000 --- a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/vio_0_ooc.xdc +++ /dev/null @@ -1,57 +0,0 @@ -# (c) Copyright 2012-2022 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# -# DO NOT MODIFY THIS FILE. -# ######################################################### -# -# This XDC is used only in OOC mode for synthesis, implementation -# -# ######################################################### - - -create_clock -period 10 -name clk [get_ports clk] - - diff --git a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/vio_0_sim_netlist.v b/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/vio_0_sim_netlist.v deleted file mode 100755 index a1cf416..0000000 --- a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/vio_0_sim_netlist.v +++ /dev/null @@ -1,13340 +0,0 @@ -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.2 (win64) Build 2700185 Thu Oct 24 18:46:05 MDT 2019 -// Date : Fri Apr 1 15:55:35 2022 -// Host : PAVLOV running 64-bit Service Pack 1 (build 7601) -// Command : write_verilog -force -mode funcsim -// J:/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/vio_0_sim_netlist.v -// Design : vio_0 -// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified -// or synthesized. This netlist cannot be used for SDF annotated simulation. -// Device : xc7z020clg400-1 -// -------------------------------------------------------------------------------- -`timescale 1 ps / 1 ps - -(* CHECK_LICENSE_TYPE = "vio_0,vio,{}" *) (* X_CORE_INFO = "vio,Vivado 2019.2" *) -(* NotValidForBitStream *) -module vio_0 - (clk, - probe_in0, - probe_in1, - probe_out0); - input clk; - input [31:0]probe_in0; - input [31:0]probe_in1; - output [31:0]probe_out0; - - wire clk; - wire [31:0]probe_in0; - wire [31:0]probe_in1; - wire [31:0]probe_out0; - wire [0:0]NLW_inst_probe_out1_UNCONNECTED; - wire [0:0]NLW_inst_probe_out10_UNCONNECTED; - wire [0:0]NLW_inst_probe_out100_UNCONNECTED; - wire [0:0]NLW_inst_probe_out101_UNCONNECTED; - wire [0:0]NLW_inst_probe_out102_UNCONNECTED; - wire [0:0]NLW_inst_probe_out103_UNCONNECTED; - wire [0:0]NLW_inst_probe_out104_UNCONNECTED; - wire [0:0]NLW_inst_probe_out105_UNCONNECTED; - wire [0:0]NLW_inst_probe_out106_UNCONNECTED; - wire [0:0]NLW_inst_probe_out107_UNCONNECTED; - wire [0:0]NLW_inst_probe_out108_UNCONNECTED; - wire [0:0]NLW_inst_probe_out109_UNCONNECTED; - wire [0:0]NLW_inst_probe_out11_UNCONNECTED; - wire [0:0]NLW_inst_probe_out110_UNCONNECTED; - wire [0:0]NLW_inst_probe_out111_UNCONNECTED; - wire [0:0]NLW_inst_probe_out112_UNCONNECTED; - wire [0:0]NLW_inst_probe_out113_UNCONNECTED; - wire [0:0]NLW_inst_probe_out114_UNCONNECTED; - wire [0:0]NLW_inst_probe_out115_UNCONNECTED; - wire [0:0]NLW_inst_probe_out116_UNCONNECTED; - wire [0:0]NLW_inst_probe_out117_UNCONNECTED; - wire [0:0]NLW_inst_probe_out118_UNCONNECTED; - wire [0:0]NLW_inst_probe_out119_UNCONNECTED; - wire [0:0]NLW_inst_probe_out12_UNCONNECTED; - wire [0:0]NLW_inst_probe_out120_UNCONNECTED; - wire [0:0]NLW_inst_probe_out121_UNCONNECTED; - wire [0:0]NLW_inst_probe_out122_UNCONNECTED; - wire [0:0]NLW_inst_probe_out123_UNCONNECTED; - wire [0:0]NLW_inst_probe_out124_UNCONNECTED; - wire [0:0]NLW_inst_probe_out125_UNCONNECTED; - wire [0:0]NLW_inst_probe_out126_UNCONNECTED; - wire [0:0]NLW_inst_probe_out127_UNCONNECTED; - wire [0:0]NLW_inst_probe_out128_UNCONNECTED; - wire [0:0]NLW_inst_probe_out129_UNCONNECTED; - wire [0:0]NLW_inst_probe_out13_UNCONNECTED; - wire [0:0]NLW_inst_probe_out130_UNCONNECTED; - wire [0:0]NLW_inst_probe_out131_UNCONNECTED; - wire [0:0]NLW_inst_probe_out132_UNCONNECTED; - wire [0:0]NLW_inst_probe_out133_UNCONNECTED; - wire [0:0]NLW_inst_probe_out134_UNCONNECTED; - wire [0:0]NLW_inst_probe_out135_UNCONNECTED; - wire [0:0]NLW_inst_probe_out136_UNCONNECTED; - wire [0:0]NLW_inst_probe_out137_UNCONNECTED; - wire [0:0]NLW_inst_probe_out138_UNCONNECTED; - wire [0:0]NLW_inst_probe_out139_UNCONNECTED; - wire [0:0]NLW_inst_probe_out14_UNCONNECTED; - wire [0:0]NLW_inst_probe_out140_UNCONNECTED; - wire [0:0]NLW_inst_probe_out141_UNCONNECTED; - wire [0:0]NLW_inst_probe_out142_UNCONNECTED; - wire [0:0]NLW_inst_probe_out143_UNCONNECTED; - wire [0:0]NLW_inst_probe_out144_UNCONNECTED; - wire [0:0]NLW_inst_probe_out145_UNCONNECTED; - wire [0:0]NLW_inst_probe_out146_UNCONNECTED; - wire [0:0]NLW_inst_probe_out147_UNCONNECTED; - wire [0:0]NLW_inst_probe_out148_UNCONNECTED; - wire [0:0]NLW_inst_probe_out149_UNCONNECTED; - wire [0:0]NLW_inst_probe_out15_UNCONNECTED; - wire [0:0]NLW_inst_probe_out150_UNCONNECTED; - wire [0:0]NLW_inst_probe_out151_UNCONNECTED; - wire [0:0]NLW_inst_probe_out152_UNCONNECTED; - wire [0:0]NLW_inst_probe_out153_UNCONNECTED; - wire [0:0]NLW_inst_probe_out154_UNCONNECTED; - wire [0:0]NLW_inst_probe_out155_UNCONNECTED; - wire [0:0]NLW_inst_probe_out156_UNCONNECTED; - wire [0:0]NLW_inst_probe_out157_UNCONNECTED; - wire [0:0]NLW_inst_probe_out158_UNCONNECTED; - wire [0:0]NLW_inst_probe_out159_UNCONNECTED; - wire [0:0]NLW_inst_probe_out16_UNCONNECTED; - wire [0:0]NLW_inst_probe_out160_UNCONNECTED; - wire [0:0]NLW_inst_probe_out161_UNCONNECTED; - wire [0:0]NLW_inst_probe_out162_UNCONNECTED; - wire [0:0]NLW_inst_probe_out163_UNCONNECTED; - wire [0:0]NLW_inst_probe_out164_UNCONNECTED; - wire [0:0]NLW_inst_probe_out165_UNCONNECTED; - wire [0:0]NLW_inst_probe_out166_UNCONNECTED; - wire [0:0]NLW_inst_probe_out167_UNCONNECTED; - wire [0:0]NLW_inst_probe_out168_UNCONNECTED; - wire [0:0]NLW_inst_probe_out169_UNCONNECTED; - wire [0:0]NLW_inst_probe_out17_UNCONNECTED; - wire [0:0]NLW_inst_probe_out170_UNCONNECTED; - wire [0:0]NLW_inst_probe_out171_UNCONNECTED; - wire [0:0]NLW_inst_probe_out172_UNCONNECTED; - wire [0:0]NLW_inst_probe_out173_UNCONNECTED; - wire [0:0]NLW_inst_probe_out174_UNCONNECTED; - wire [0:0]NLW_inst_probe_out175_UNCONNECTED; - wire [0:0]NLW_inst_probe_out176_UNCONNECTED; - wire [0:0]NLW_inst_probe_out177_UNCONNECTED; - wire [0:0]NLW_inst_probe_out178_UNCONNECTED; - wire [0:0]NLW_inst_probe_out179_UNCONNECTED; - wire [0:0]NLW_inst_probe_out18_UNCONNECTED; - wire [0:0]NLW_inst_probe_out180_UNCONNECTED; - wire [0:0]NLW_inst_probe_out181_UNCONNECTED; - wire [0:0]NLW_inst_probe_out182_UNCONNECTED; - wire [0:0]NLW_inst_probe_out183_UNCONNECTED; - wire [0:0]NLW_inst_probe_out184_UNCONNECTED; - wire [0:0]NLW_inst_probe_out185_UNCONNECTED; - wire [0:0]NLW_inst_probe_out186_UNCONNECTED; - wire [0:0]NLW_inst_probe_out187_UNCONNECTED; - wire [0:0]NLW_inst_probe_out188_UNCONNECTED; - wire [0:0]NLW_inst_probe_out189_UNCONNECTED; - wire [0:0]NLW_inst_probe_out19_UNCONNECTED; - wire [0:0]NLW_inst_probe_out190_UNCONNECTED; - wire [0:0]NLW_inst_probe_out191_UNCONNECTED; - wire [0:0]NLW_inst_probe_out192_UNCONNECTED; - wire [0:0]NLW_inst_probe_out193_UNCONNECTED; - wire [0:0]NLW_inst_probe_out194_UNCONNECTED; - wire [0:0]NLW_inst_probe_out195_UNCONNECTED; - wire [0:0]NLW_inst_probe_out196_UNCONNECTED; - wire [0:0]NLW_inst_probe_out197_UNCONNECTED; - wire [0:0]NLW_inst_probe_out198_UNCONNECTED; - wire [0:0]NLW_inst_probe_out199_UNCONNECTED; - wire [0:0]NLW_inst_probe_out2_UNCONNECTED; - wire [0:0]NLW_inst_probe_out20_UNCONNECTED; - wire [0:0]NLW_inst_probe_out200_UNCONNECTED; - wire [0:0]NLW_inst_probe_out201_UNCONNECTED; - wire [0:0]NLW_inst_probe_out202_UNCONNECTED; - wire [0:0]NLW_inst_probe_out203_UNCONNECTED; - wire [0:0]NLW_inst_probe_out204_UNCONNECTED; - wire [0:0]NLW_inst_probe_out205_UNCONNECTED; - wire [0:0]NLW_inst_probe_out206_UNCONNECTED; - wire [0:0]NLW_inst_probe_out207_UNCONNECTED; - wire [0:0]NLW_inst_probe_out208_UNCONNECTED; - wire [0:0]NLW_inst_probe_out209_UNCONNECTED; - wire [0:0]NLW_inst_probe_out21_UNCONNECTED; - wire [0:0]NLW_inst_probe_out210_UNCONNECTED; - wire [0:0]NLW_inst_probe_out211_UNCONNECTED; - wire [0:0]NLW_inst_probe_out212_UNCONNECTED; - wire [0:0]NLW_inst_probe_out213_UNCONNECTED; - wire [0:0]NLW_inst_probe_out214_UNCONNECTED; - wire [0:0]NLW_inst_probe_out215_UNCONNECTED; - wire [0:0]NLW_inst_probe_out216_UNCONNECTED; - wire [0:0]NLW_inst_probe_out217_UNCONNECTED; - wire [0:0]NLW_inst_probe_out218_UNCONNECTED; - wire [0:0]NLW_inst_probe_out219_UNCONNECTED; - wire [0:0]NLW_inst_probe_out22_UNCONNECTED; - wire [0:0]NLW_inst_probe_out220_UNCONNECTED; - wire [0:0]NLW_inst_probe_out221_UNCONNECTED; - wire [0:0]NLW_inst_probe_out222_UNCONNECTED; - wire [0:0]NLW_inst_probe_out223_UNCONNECTED; - wire [0:0]NLW_inst_probe_out224_UNCONNECTED; - wire [0:0]NLW_inst_probe_out225_UNCONNECTED; - wire [0:0]NLW_inst_probe_out226_UNCONNECTED; - wire [0:0]NLW_inst_probe_out227_UNCONNECTED; - wire [0:0]NLW_inst_probe_out228_UNCONNECTED; - wire [0:0]NLW_inst_probe_out229_UNCONNECTED; - wire [0:0]NLW_inst_probe_out23_UNCONNECTED; - wire [0:0]NLW_inst_probe_out230_UNCONNECTED; - wire [0:0]NLW_inst_probe_out231_UNCONNECTED; - wire [0:0]NLW_inst_probe_out232_UNCONNECTED; - wire [0:0]NLW_inst_probe_out233_UNCONNECTED; - wire [0:0]NLW_inst_probe_out234_UNCONNECTED; - wire [0:0]NLW_inst_probe_out235_UNCONNECTED; - wire [0:0]NLW_inst_probe_out236_UNCONNECTED; - wire [0:0]NLW_inst_probe_out237_UNCONNECTED; - wire [0:0]NLW_inst_probe_out238_UNCONNECTED; - wire [0:0]NLW_inst_probe_out239_UNCONNECTED; - wire [0:0]NLW_inst_probe_out24_UNCONNECTED; - wire [0:0]NLW_inst_probe_out240_UNCONNECTED; - wire [0:0]NLW_inst_probe_out241_UNCONNECTED; - wire [0:0]NLW_inst_probe_out242_UNCONNECTED; - wire [0:0]NLW_inst_probe_out243_UNCONNECTED; - wire [0:0]NLW_inst_probe_out244_UNCONNECTED; - wire [0:0]NLW_inst_probe_out245_UNCONNECTED; - wire [0:0]NLW_inst_probe_out246_UNCONNECTED; - wire [0:0]NLW_inst_probe_out247_UNCONNECTED; - wire [0:0]NLW_inst_probe_out248_UNCONNECTED; - wire [0:0]NLW_inst_probe_out249_UNCONNECTED; - wire [0:0]NLW_inst_probe_out25_UNCONNECTED; - wire [0:0]NLW_inst_probe_out250_UNCONNECTED; - wire [0:0]NLW_inst_probe_out251_UNCONNECTED; - wire [0:0]NLW_inst_probe_out252_UNCONNECTED; - wire [0:0]NLW_inst_probe_out253_UNCONNECTED; - wire [0:0]NLW_inst_probe_out254_UNCONNECTED; - wire [0:0]NLW_inst_probe_out255_UNCONNECTED; - wire [0:0]NLW_inst_probe_out26_UNCONNECTED; - wire [0:0]NLW_inst_probe_out27_UNCONNECTED; - wire [0:0]NLW_inst_probe_out28_UNCONNECTED; - wire [0:0]NLW_inst_probe_out29_UNCONNECTED; - wire [0:0]NLW_inst_probe_out3_UNCONNECTED; - wire [0:0]NLW_inst_probe_out30_UNCONNECTED; - wire [0:0]NLW_inst_probe_out31_UNCONNECTED; - wire [0:0]NLW_inst_probe_out32_UNCONNECTED; - wire [0:0]NLW_inst_probe_out33_UNCONNECTED; - wire [0:0]NLW_inst_probe_out34_UNCONNECTED; - wire [0:0]NLW_inst_probe_out35_UNCONNECTED; - wire [0:0]NLW_inst_probe_out36_UNCONNECTED; - wire [0:0]NLW_inst_probe_out37_UNCONNECTED; - wire [0:0]NLW_inst_probe_out38_UNCONNECTED; - wire [0:0]NLW_inst_probe_out39_UNCONNECTED; - wire [0:0]NLW_inst_probe_out4_UNCONNECTED; - wire [0:0]NLW_inst_probe_out40_UNCONNECTED; - wire [0:0]NLW_inst_probe_out41_UNCONNECTED; - wire [0:0]NLW_inst_probe_out42_UNCONNECTED; - wire [0:0]NLW_inst_probe_out43_UNCONNECTED; - wire [0:0]NLW_inst_probe_out44_UNCONNECTED; - wire [0:0]NLW_inst_probe_out45_UNCONNECTED; - wire [0:0]NLW_inst_probe_out46_UNCONNECTED; - wire [0:0]NLW_inst_probe_out47_UNCONNECTED; - wire [0:0]NLW_inst_probe_out48_UNCONNECTED; - wire [0:0]NLW_inst_probe_out49_UNCONNECTED; - wire [0:0]NLW_inst_probe_out5_UNCONNECTED; - wire [0:0]NLW_inst_probe_out50_UNCONNECTED; - wire [0:0]NLW_inst_probe_out51_UNCONNECTED; - wire [0:0]NLW_inst_probe_out52_UNCONNECTED; - wire [0:0]NLW_inst_probe_out53_UNCONNECTED; - wire [0:0]NLW_inst_probe_out54_UNCONNECTED; - wire [0:0]NLW_inst_probe_out55_UNCONNECTED; - wire [0:0]NLW_inst_probe_out56_UNCONNECTED; - wire [0:0]NLW_inst_probe_out57_UNCONNECTED; - wire [0:0]NLW_inst_probe_out58_UNCONNECTED; - wire [0:0]NLW_inst_probe_out59_UNCONNECTED; - wire [0:0]NLW_inst_probe_out6_UNCONNECTED; - wire [0:0]NLW_inst_probe_out60_UNCONNECTED; - wire [0:0]NLW_inst_probe_out61_UNCONNECTED; - wire [0:0]NLW_inst_probe_out62_UNCONNECTED; - wire [0:0]NLW_inst_probe_out63_UNCONNECTED; - wire [0:0]NLW_inst_probe_out64_UNCONNECTED; - wire [0:0]NLW_inst_probe_out65_UNCONNECTED; - wire [0:0]NLW_inst_probe_out66_UNCONNECTED; - wire [0:0]NLW_inst_probe_out67_UNCONNECTED; - wire [0:0]NLW_inst_probe_out68_UNCONNECTED; - wire [0:0]NLW_inst_probe_out69_UNCONNECTED; - wire [0:0]NLW_inst_probe_out7_UNCONNECTED; - wire [0:0]NLW_inst_probe_out70_UNCONNECTED; - wire [0:0]NLW_inst_probe_out71_UNCONNECTED; - wire [0:0]NLW_inst_probe_out72_UNCONNECTED; - wire [0:0]NLW_inst_probe_out73_UNCONNECTED; - wire [0:0]NLW_inst_probe_out74_UNCONNECTED; - wire [0:0]NLW_inst_probe_out75_UNCONNECTED; - wire [0:0]NLW_inst_probe_out76_UNCONNECTED; - wire [0:0]NLW_inst_probe_out77_UNCONNECTED; - wire [0:0]NLW_inst_probe_out78_UNCONNECTED; - wire [0:0]NLW_inst_probe_out79_UNCONNECTED; - wire [0:0]NLW_inst_probe_out8_UNCONNECTED; - wire [0:0]NLW_inst_probe_out80_UNCONNECTED; - wire [0:0]NLW_inst_probe_out81_UNCONNECTED; - wire [0:0]NLW_inst_probe_out82_UNCONNECTED; - wire [0:0]NLW_inst_probe_out83_UNCONNECTED; - wire [0:0]NLW_inst_probe_out84_UNCONNECTED; - wire [0:0]NLW_inst_probe_out85_UNCONNECTED; - wire [0:0]NLW_inst_probe_out86_UNCONNECTED; - wire [0:0]NLW_inst_probe_out87_UNCONNECTED; - wire [0:0]NLW_inst_probe_out88_UNCONNECTED; - wire [0:0]NLW_inst_probe_out89_UNCONNECTED; - wire [0:0]NLW_inst_probe_out9_UNCONNECTED; - wire [0:0]NLW_inst_probe_out90_UNCONNECTED; - wire [0:0]NLW_inst_probe_out91_UNCONNECTED; - wire [0:0]NLW_inst_probe_out92_UNCONNECTED; - wire [0:0]NLW_inst_probe_out93_UNCONNECTED; - wire [0:0]NLW_inst_probe_out94_UNCONNECTED; - wire [0:0]NLW_inst_probe_out95_UNCONNECTED; - wire [0:0]NLW_inst_probe_out96_UNCONNECTED; - wire [0:0]NLW_inst_probe_out97_UNCONNECTED; - wire [0:0]NLW_inst_probe_out98_UNCONNECTED; - wire [0:0]NLW_inst_probe_out99_UNCONNECTED; - wire [16:0]NLW_inst_sl_oport0_UNCONNECTED; - - (* C_BUILD_REVISION = "0" *) - (* C_BUS_ADDR_WIDTH = "17" *) - (* C_BUS_DATA_WIDTH = "16" *) - (* C_CORE_INFO1 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) - (* C_CORE_INFO2 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) - (* C_CORE_MAJOR_VER = "2" *) - (* C_CORE_MINOR_ALPHA_VER = "97" *) - (* C_CORE_MINOR_VER = "0" *) - (* C_CORE_TYPE = "2" *) - (* C_CSE_DRV_VER = "1" *) - (* C_EN_PROBE_IN_ACTIVITY = "1" *) - (* C_EN_SYNCHRONIZATION = "1" *) - (* C_MAJOR_VERSION = "2013" *) - (* C_MAX_NUM_PROBE = "256" *) - (* C_MAX_WIDTH_PER_PROBE = "256" *) - (* C_MINOR_VERSION = "1" *) - (* C_NEXT_SLAVE = "0" *) - (* C_NUM_PROBE_IN = "2" *) - (* C_NUM_PROBE_OUT = "1" *) - (* C_PIPE_IFACE = "0" *) - (* C_PROBE_IN0_WIDTH = "32" *) - (* C_PROBE_IN100_WIDTH = "1" *) - (* C_PROBE_IN101_WIDTH = "1" *) - (* C_PROBE_IN102_WIDTH = "1" *) - (* C_PROBE_IN103_WIDTH = "1" *) - (* C_PROBE_IN104_WIDTH = "1" *) - (* C_PROBE_IN105_WIDTH = "1" *) - (* C_PROBE_IN106_WIDTH = "1" *) - (* C_PROBE_IN107_WIDTH = "1" *) - (* C_PROBE_IN108_WIDTH = "1" *) - (* C_PROBE_IN109_WIDTH = "1" *) - (* C_PROBE_IN10_WIDTH = "1" *) - (* C_PROBE_IN110_WIDTH = "1" *) - (* C_PROBE_IN111_WIDTH = "1" *) - (* C_PROBE_IN112_WIDTH = "1" *) - (* C_PROBE_IN113_WIDTH = "1" *) - (* C_PROBE_IN114_WIDTH = "1" *) - (* C_PROBE_IN115_WIDTH = "1" *) - (* C_PROBE_IN116_WIDTH = "1" *) - (* C_PROBE_IN117_WIDTH = "1" *) - (* C_PROBE_IN118_WIDTH = "1" *) - (* C_PROBE_IN119_WIDTH = "1" *) - (* C_PROBE_IN11_WIDTH = "1" *) - (* C_PROBE_IN120_WIDTH = "1" *) - (* C_PROBE_IN121_WIDTH = "1" *) - (* C_PROBE_IN122_WIDTH = "1" *) - (* C_PROBE_IN123_WIDTH = "1" *) - (* C_PROBE_IN124_WIDTH = "1" *) - (* C_PROBE_IN125_WIDTH = "1" *) - (* C_PROBE_IN126_WIDTH = "1" *) - (* C_PROBE_IN127_WIDTH = "1" *) - (* C_PROBE_IN128_WIDTH = "1" *) - (* C_PROBE_IN129_WIDTH = "1" *) - (* C_PROBE_IN12_WIDTH = "1" *) - (* C_PROBE_IN130_WIDTH = "1" *) - (* C_PROBE_IN131_WIDTH = "1" *) - (* C_PROBE_IN132_WIDTH = "1" *) - (* C_PROBE_IN133_WIDTH = "1" *) - (* C_PROBE_IN134_WIDTH = "1" *) - (* C_PROBE_IN135_WIDTH = "1" *) - (* C_PROBE_IN136_WIDTH = "1" *) - (* C_PROBE_IN137_WIDTH = "1" *) - (* C_PROBE_IN138_WIDTH = "1" *) - (* C_PROBE_IN139_WIDTH = "1" *) - (* C_PROBE_IN13_WIDTH = "1" *) - (* C_PROBE_IN140_WIDTH = "1" *) - (* C_PROBE_IN141_WIDTH = "1" *) - (* C_PROBE_IN142_WIDTH = "1" *) - (* C_PROBE_IN143_WIDTH = "1" *) - (* C_PROBE_IN144_WIDTH = "1" *) - (* C_PROBE_IN145_WIDTH = "1" *) - (* C_PROBE_IN146_WIDTH = "1" *) - (* C_PROBE_IN147_WIDTH = "1" *) - (* C_PROBE_IN148_WIDTH = "1" *) - (* C_PROBE_IN149_WIDTH = "1" *) - (* C_PROBE_IN14_WIDTH = "1" *) - (* C_PROBE_IN150_WIDTH = "1" *) - (* C_PROBE_IN151_WIDTH = "1" *) - (* C_PROBE_IN152_WIDTH = "1" *) - (* C_PROBE_IN153_WIDTH = "1" *) - (* C_PROBE_IN154_WIDTH = "1" *) - (* C_PROBE_IN155_WIDTH = "1" *) - (* C_PROBE_IN156_WIDTH = "1" *) - (* C_PROBE_IN157_WIDTH = "1" *) - (* C_PROBE_IN158_WIDTH = "1" *) - (* C_PROBE_IN159_WIDTH = "1" *) - (* C_PROBE_IN15_WIDTH = "1" *) - (* C_PROBE_IN160_WIDTH = "1" *) - (* C_PROBE_IN161_WIDTH = "1" *) - (* C_PROBE_IN162_WIDTH = "1" *) - (* C_PROBE_IN163_WIDTH = "1" *) - (* C_PROBE_IN164_WIDTH = "1" *) - (* C_PROBE_IN165_WIDTH = "1" *) - (* C_PROBE_IN166_WIDTH = "1" *) - (* C_PROBE_IN167_WIDTH = "1" *) - (* C_PROBE_IN168_WIDTH = "1" *) - (* C_PROBE_IN169_WIDTH = "1" *) - (* C_PROBE_IN16_WIDTH = "1" *) - (* C_PROBE_IN170_WIDTH = "1" *) - (* C_PROBE_IN171_WIDTH = "1" *) - (* C_PROBE_IN172_WIDTH = "1" *) - (* C_PROBE_IN173_WIDTH = "1" *) - (* C_PROBE_IN174_WIDTH = "1" *) - (* C_PROBE_IN175_WIDTH = "1" *) - (* C_PROBE_IN176_WIDTH = "1" *) - (* C_PROBE_IN177_WIDTH = "1" *) - (* C_PROBE_IN178_WIDTH = "1" *) - (* C_PROBE_IN179_WIDTH = "1" *) - (* C_PROBE_IN17_WIDTH = "1" *) - (* C_PROBE_IN180_WIDTH = "1" *) - (* C_PROBE_IN181_WIDTH = "1" *) - (* C_PROBE_IN182_WIDTH = "1" *) - (* C_PROBE_IN183_WIDTH = "1" *) - (* C_PROBE_IN184_WIDTH = "1" *) - (* C_PROBE_IN185_WIDTH = "1" *) - (* C_PROBE_IN186_WIDTH = "1" *) - (* C_PROBE_IN187_WIDTH = "1" *) - (* C_PROBE_IN188_WIDTH = "1" *) - (* C_PROBE_IN189_WIDTH = "1" *) - (* C_PROBE_IN18_WIDTH = "1" *) - (* C_PROBE_IN190_WIDTH = "1" *) - (* C_PROBE_IN191_WIDTH = "1" *) - (* C_PROBE_IN192_WIDTH = "1" *) - (* C_PROBE_IN193_WIDTH = "1" *) - (* C_PROBE_IN194_WIDTH = "1" *) - (* C_PROBE_IN195_WIDTH = "1" *) - (* C_PROBE_IN196_WIDTH = "1" *) - (* C_PROBE_IN197_WIDTH = "1" *) - (* C_PROBE_IN198_WIDTH = "1" *) - (* C_PROBE_IN199_WIDTH = "1" *) - (* C_PROBE_IN19_WIDTH = "1" *) - (* C_PROBE_IN1_WIDTH = "32" *) - (* C_PROBE_IN200_WIDTH = "1" *) - (* C_PROBE_IN201_WIDTH = "1" *) - (* C_PROBE_IN202_WIDTH = "1" *) - (* C_PROBE_IN203_WIDTH = "1" *) - (* C_PROBE_IN204_WIDTH = "1" *) - (* C_PROBE_IN205_WIDTH = "1" *) - (* C_PROBE_IN206_WIDTH = "1" *) - (* C_PROBE_IN207_WIDTH = "1" *) - (* C_PROBE_IN208_WIDTH = "1" *) - (* C_PROBE_IN209_WIDTH = "1" *) - (* C_PROBE_IN20_WIDTH = "1" *) - (* C_PROBE_IN210_WIDTH = "1" *) - (* C_PROBE_IN211_WIDTH = "1" *) - (* C_PROBE_IN212_WIDTH = "1" *) - (* C_PROBE_IN213_WIDTH = "1" *) - (* C_PROBE_IN214_WIDTH = "1" *) - (* C_PROBE_IN215_WIDTH = "1" *) - (* C_PROBE_IN216_WIDTH = "1" *) - (* C_PROBE_IN217_WIDTH = "1" *) - (* C_PROBE_IN218_WIDTH = "1" *) - (* C_PROBE_IN219_WIDTH = "1" *) - (* C_PROBE_IN21_WIDTH = "1" *) - (* C_PROBE_IN220_WIDTH = "1" *) - (* C_PROBE_IN221_WIDTH = "1" *) - (* C_PROBE_IN222_WIDTH = "1" *) - (* C_PROBE_IN223_WIDTH = "1" *) - (* C_PROBE_IN224_WIDTH = "1" *) - (* C_PROBE_IN225_WIDTH = "1" *) - (* C_PROBE_IN226_WIDTH = "1" *) - (* C_PROBE_IN227_WIDTH = "1" *) - (* C_PROBE_IN228_WIDTH = "1" *) - (* C_PROBE_IN229_WIDTH = "1" *) - (* C_PROBE_IN22_WIDTH = "1" *) - (* C_PROBE_IN230_WIDTH = "1" *) - (* C_PROBE_IN231_WIDTH = "1" *) - (* C_PROBE_IN232_WIDTH = "1" *) - (* C_PROBE_IN233_WIDTH = "1" *) - (* C_PROBE_IN234_WIDTH = "1" *) - (* C_PROBE_IN235_WIDTH = "1" *) - (* C_PROBE_IN236_WIDTH = "1" *) - (* C_PROBE_IN237_WIDTH = "1" *) - (* C_PROBE_IN238_WIDTH = "1" *) - (* C_PROBE_IN239_WIDTH = "1" *) - (* C_PROBE_IN23_WIDTH = "1" *) - (* C_PROBE_IN240_WIDTH = "1" *) - (* C_PROBE_IN241_WIDTH = "1" *) - (* C_PROBE_IN242_WIDTH = "1" *) - (* C_PROBE_IN243_WIDTH = "1" *) - (* C_PROBE_IN244_WIDTH = "1" *) - (* C_PROBE_IN245_WIDTH = "1" *) - (* C_PROBE_IN246_WIDTH = "1" *) - (* C_PROBE_IN247_WIDTH = "1" *) - (* C_PROBE_IN248_WIDTH = "1" *) - (* C_PROBE_IN249_WIDTH = "1" *) - (* C_PROBE_IN24_WIDTH = "1" *) - (* C_PROBE_IN250_WIDTH = "1" *) - (* C_PROBE_IN251_WIDTH = "1" *) - (* C_PROBE_IN252_WIDTH = "1" *) - (* C_PROBE_IN253_WIDTH = "1" *) - (* C_PROBE_IN254_WIDTH = "1" *) - (* C_PROBE_IN255_WIDTH = "1" *) - (* C_PROBE_IN25_WIDTH = "1" *) - (* C_PROBE_IN26_WIDTH = "1" *) - (* C_PROBE_IN27_WIDTH = "1" *) - (* C_PROBE_IN28_WIDTH = "1" *) - (* C_PROBE_IN29_WIDTH = "1" *) - (* C_PROBE_IN2_WIDTH = "1" *) - (* C_PROBE_IN30_WIDTH = "1" *) - (* C_PROBE_IN31_WIDTH = "1" *) - (* C_PROBE_IN32_WIDTH = "1" *) - (* C_PROBE_IN33_WIDTH = "1" *) - (* C_PROBE_IN34_WIDTH = "1" *) - (* C_PROBE_IN35_WIDTH = "1" *) - (* C_PROBE_IN36_WIDTH = "1" *) - (* C_PROBE_IN37_WIDTH = "1" *) - (* C_PROBE_IN38_WIDTH = "1" *) - (* C_PROBE_IN39_WIDTH = "1" *) - (* C_PROBE_IN3_WIDTH = "1" *) - (* C_PROBE_IN40_WIDTH = "1" *) - (* C_PROBE_IN41_WIDTH = "1" *) - (* C_PROBE_IN42_WIDTH = "1" *) - (* C_PROBE_IN43_WIDTH = "1" *) - (* C_PROBE_IN44_WIDTH = "1" *) - (* C_PROBE_IN45_WIDTH = "1" *) - (* C_PROBE_IN46_WIDTH = "1" *) - (* C_PROBE_IN47_WIDTH = "1" *) - (* C_PROBE_IN48_WIDTH = "1" *) - (* C_PROBE_IN49_WIDTH = "1" *) - (* C_PROBE_IN4_WIDTH = "1" *) - (* C_PROBE_IN50_WIDTH = "1" *) - (* C_PROBE_IN51_WIDTH = "1" *) - (* C_PROBE_IN52_WIDTH = "1" *) - (* C_PROBE_IN53_WIDTH = "1" *) - (* C_PROBE_IN54_WIDTH = "1" *) - (* C_PROBE_IN55_WIDTH = "1" *) - (* C_PROBE_IN56_WIDTH = "1" *) - (* C_PROBE_IN57_WIDTH = "1" *) - (* C_PROBE_IN58_WIDTH = "1" *) - (* C_PROBE_IN59_WIDTH = "1" *) - (* C_PROBE_IN5_WIDTH = "1" *) - (* C_PROBE_IN60_WIDTH = "1" *) - (* C_PROBE_IN61_WIDTH = "1" *) - (* C_PROBE_IN62_WIDTH = "1" *) - (* C_PROBE_IN63_WIDTH = "1" *) - (* C_PROBE_IN64_WIDTH = "1" *) - (* C_PROBE_IN65_WIDTH = "1" *) - (* C_PROBE_IN66_WIDTH = "1" *) - (* C_PROBE_IN67_WIDTH = "1" *) - (* C_PROBE_IN68_WIDTH = "1" *) - (* C_PROBE_IN69_WIDTH = "1" *) - (* C_PROBE_IN6_WIDTH = "1" *) - (* C_PROBE_IN70_WIDTH = "1" *) - (* C_PROBE_IN71_WIDTH = "1" *) - (* C_PROBE_IN72_WIDTH = "1" *) - (* C_PROBE_IN73_WIDTH = "1" *) - (* C_PROBE_IN74_WIDTH = "1" *) - (* C_PROBE_IN75_WIDTH = "1" *) - (* C_PROBE_IN76_WIDTH = "1" *) - (* C_PROBE_IN77_WIDTH = "1" *) - (* C_PROBE_IN78_WIDTH = "1" *) - (* C_PROBE_IN79_WIDTH = "1" *) - (* C_PROBE_IN7_WIDTH = "1" *) - (* C_PROBE_IN80_WIDTH = "1" *) - (* C_PROBE_IN81_WIDTH = "1" *) - (* C_PROBE_IN82_WIDTH = "1" *) - (* C_PROBE_IN83_WIDTH = "1" *) - (* C_PROBE_IN84_WIDTH = "1" *) - (* C_PROBE_IN85_WIDTH = "1" *) - (* C_PROBE_IN86_WIDTH = "1" *) - (* C_PROBE_IN87_WIDTH = "1" *) - (* C_PROBE_IN88_WIDTH = "1" *) - (* C_PROBE_IN89_WIDTH = "1" *) - (* C_PROBE_IN8_WIDTH = "1" *) - (* C_PROBE_IN90_WIDTH = "1" *) - (* C_PROBE_IN91_WIDTH = "1" *) - (* C_PROBE_IN92_WIDTH = "1" *) - (* C_PROBE_IN93_WIDTH = "1" *) - (* C_PROBE_IN94_WIDTH = "1" *) - (* C_PROBE_IN95_WIDTH = "1" *) - (* C_PROBE_IN96_WIDTH = "1" *) - (* C_PROBE_IN97_WIDTH = "1" *) - (* C_PROBE_IN98_WIDTH = "1" *) - (* C_PROBE_IN99_WIDTH = "1" *) - (* C_PROBE_IN9_WIDTH = "1" *) - (* C_PROBE_OUT0_INIT_VAL = "32'b00000000000000000000000000000000" *) - (* C_PROBE_OUT0_WIDTH = "32" *) - (* C_PROBE_OUT100_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT100_WIDTH = "1" *) - (* C_PROBE_OUT101_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT101_WIDTH = "1" *) - (* C_PROBE_OUT102_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT102_WIDTH = "1" *) - (* C_PROBE_OUT103_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT103_WIDTH = "1" *) - (* C_PROBE_OUT104_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT104_WIDTH = "1" *) - (* C_PROBE_OUT105_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT105_WIDTH = "1" *) - (* C_PROBE_OUT106_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT106_WIDTH = "1" *) - (* C_PROBE_OUT107_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT107_WIDTH = "1" *) - (* C_PROBE_OUT108_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT108_WIDTH = "1" *) - (* C_PROBE_OUT109_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT109_WIDTH = "1" *) - (* C_PROBE_OUT10_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT10_WIDTH = "1" *) - (* C_PROBE_OUT110_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT110_WIDTH = "1" *) - (* C_PROBE_OUT111_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT111_WIDTH = "1" *) - (* C_PROBE_OUT112_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT112_WIDTH = "1" *) - (* C_PROBE_OUT113_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT113_WIDTH = "1" *) - (* C_PROBE_OUT114_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT114_WIDTH = "1" *) - (* C_PROBE_OUT115_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT115_WIDTH = "1" *) - (* C_PROBE_OUT116_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT116_WIDTH = "1" *) - (* C_PROBE_OUT117_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT117_WIDTH = "1" *) - (* C_PROBE_OUT118_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT118_WIDTH = "1" *) - (* C_PROBE_OUT119_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT119_WIDTH = "1" *) - (* C_PROBE_OUT11_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT11_WIDTH = "1" *) - (* C_PROBE_OUT120_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT120_WIDTH = "1" *) - (* C_PROBE_OUT121_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT121_WIDTH = "1" *) - (* C_PROBE_OUT122_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT122_WIDTH = "1" *) - (* C_PROBE_OUT123_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT123_WIDTH = "1" *) - (* C_PROBE_OUT124_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT124_WIDTH = "1" *) - (* C_PROBE_OUT125_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT125_WIDTH = "1" *) - (* C_PROBE_OUT126_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT126_WIDTH = "1" *) - (* C_PROBE_OUT127_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT127_WIDTH = "1" *) - (* C_PROBE_OUT128_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT128_WIDTH = "1" *) - (* C_PROBE_OUT129_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT129_WIDTH = "1" *) - (* C_PROBE_OUT12_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT12_WIDTH = "1" *) - (* C_PROBE_OUT130_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT130_WIDTH = "1" *) - (* C_PROBE_OUT131_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT131_WIDTH = "1" *) - (* C_PROBE_OUT132_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT132_WIDTH = "1" *) - (* C_PROBE_OUT133_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT133_WIDTH = "1" *) - (* C_PROBE_OUT134_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT134_WIDTH = "1" *) - (* C_PROBE_OUT135_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT135_WIDTH = "1" *) - (* C_PROBE_OUT136_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT136_WIDTH = "1" *) - (* C_PROBE_OUT137_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT137_WIDTH = "1" *) - (* C_PROBE_OUT138_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT138_WIDTH = "1" *) - (* C_PROBE_OUT139_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT139_WIDTH = "1" *) - (* C_PROBE_OUT13_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT13_WIDTH = "1" *) - (* C_PROBE_OUT140_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT140_WIDTH = "1" *) - (* C_PROBE_OUT141_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT141_WIDTH = "1" *) - (* C_PROBE_OUT142_INIT_VAL = "1'b0" *) - (* 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*) - (* C_PROBE_OUT54_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT54_WIDTH = "1" *) - (* C_PROBE_OUT55_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT55_WIDTH = "1" *) - (* C_PROBE_OUT56_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT56_WIDTH = "1" *) - (* C_PROBE_OUT57_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT57_WIDTH = "1" *) - (* C_PROBE_OUT58_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT58_WIDTH = "1" *) - (* C_PROBE_OUT59_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT59_WIDTH = "1" *) - (* C_PROBE_OUT5_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT5_WIDTH = "1" *) - (* C_PROBE_OUT60_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT60_WIDTH = "1" *) - (* C_PROBE_OUT61_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT61_WIDTH = "1" *) - (* C_PROBE_OUT62_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT62_WIDTH = "1" *) - (* C_PROBE_OUT63_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT63_WIDTH = "1" *) - (* C_PROBE_OUT64_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT64_WIDTH = "1" *) - (* C_PROBE_OUT65_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT65_WIDTH = "1" *) - (* C_PROBE_OUT66_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT66_WIDTH = "1" *) - (* C_PROBE_OUT67_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT67_WIDTH = "1" *) - (* C_PROBE_OUT68_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT68_WIDTH = "1" *) - (* C_PROBE_OUT69_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT69_WIDTH = "1" *) - (* C_PROBE_OUT6_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT6_WIDTH = "1" *) - (* C_PROBE_OUT70_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT70_WIDTH = "1" *) - (* C_PROBE_OUT71_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT71_WIDTH = "1" *) - (* C_PROBE_OUT72_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT72_WIDTH = "1" *) - (* C_PROBE_OUT73_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT73_WIDTH = "1" *) - (* C_PROBE_OUT74_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT74_WIDTH = "1" *) - (* C_PROBE_OUT75_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT75_WIDTH = "1" *) - (* C_PROBE_OUT76_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT76_WIDTH = "1" *) - (* C_PROBE_OUT77_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT77_WIDTH = "1" *) - (* C_PROBE_OUT78_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT78_WIDTH = "1" *) - (* C_PROBE_OUT79_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT79_WIDTH = "1" *) - (* C_PROBE_OUT7_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT7_WIDTH = "1" *) - (* C_PROBE_OUT80_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT80_WIDTH = "1" *) - (* C_PROBE_OUT81_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT81_WIDTH = "1" *) - (* C_PROBE_OUT82_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT82_WIDTH = "1" *) - (* C_PROBE_OUT83_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT83_WIDTH = "1" *) - (* C_PROBE_OUT84_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT84_WIDTH = "1" *) - (* C_PROBE_OUT85_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT85_WIDTH = "1" *) - (* C_PROBE_OUT86_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT86_WIDTH = "1" *) - (* C_PROBE_OUT87_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT87_WIDTH = "1" *) - (* C_PROBE_OUT88_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT88_WIDTH = "1" *) - (* C_PROBE_OUT89_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT89_WIDTH = "1" *) - (* C_PROBE_OUT8_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT8_WIDTH = "1" *) - (* C_PROBE_OUT90_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT90_WIDTH = "1" *) - (* C_PROBE_OUT91_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT91_WIDTH = "1" *) - (* C_PROBE_OUT92_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT92_WIDTH = "1" *) - (* C_PROBE_OUT93_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT93_WIDTH = "1" *) - (* C_PROBE_OUT94_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT94_WIDTH = "1" *) - (* C_PROBE_OUT95_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT95_WIDTH = "1" *) - (* C_PROBE_OUT96_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT96_WIDTH = "1" *) - (* C_PROBE_OUT97_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT97_WIDTH = "1" *) - (* C_PROBE_OUT98_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT98_WIDTH = "1" *) - (* C_PROBE_OUT99_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT99_WIDTH = "1" *) - (* C_PROBE_OUT9_INIT_VAL = "1'b0" *) - (* C_PROBE_OUT9_WIDTH = "1" *) - (* C_USE_TEST_REG = "1" *) - (* C_XDEVICEFAMILY = "zynq" *) - (* C_XLNX_HW_PROBE_INFO = "DEFAULT" *) - (* C_XSDB_SLAVE_TYPE = "33" *) - (* DONT_TOUCH *) - (* DowngradeIPIdentifiedWarnings = "yes" *) - (* LC_HIGH_BIT_POS_PROBE_OUT0 = "16'b0000000000011111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT1 = "16'b0000000000100000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT10 = "16'b0000000000101001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT100 = "16'b0000000010000011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT101 = "16'b0000000010000100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT102 = "16'b0000000010000101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT103 = "16'b0000000010000110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT104 = "16'b0000000010000111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT105 = "16'b0000000010001000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT106 = "16'b0000000010001001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT107 = "16'b0000000010001010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT108 = "16'b0000000010001011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT109 = "16'b0000000010001100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT11 = "16'b0000000000101010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT110 = "16'b0000000010001101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT111 = "16'b0000000010001110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT112 = "16'b0000000010001111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT113 = "16'b0000000010010000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT114 = "16'b0000000010010001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT115 = "16'b0000000010010010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT116 = "16'b0000000010010011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT117 = "16'b0000000010010100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT118 = "16'b0000000010010101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT119 = "16'b0000000010010110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT12 = "16'b0000000000101011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT120 = "16'b0000000010010111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT121 = "16'b0000000010011000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT122 = "16'b0000000010011001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT123 = "16'b0000000010011010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT124 = "16'b0000000010011011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT125 = "16'b0000000010011100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT126 = "16'b0000000010011101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT127 = "16'b0000000010011110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT128 = "16'b0000000010011111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT129 = "16'b0000000010100000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT13 = "16'b0000000000101100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT130 = "16'b0000000010100001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT131 = "16'b0000000010100010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT132 = "16'b0000000010100011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT133 = "16'b0000000010100100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT134 = "16'b0000000010100101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT135 = "16'b0000000010100110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT136 = "16'b0000000010100111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT137 = "16'b0000000010101000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT138 = "16'b0000000010101001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT139 = "16'b0000000010101010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT14 = "16'b0000000000101101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT140 = "16'b0000000010101011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT141 = "16'b0000000010101100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT142 = "16'b0000000010101101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT143 = "16'b0000000010101110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT144 = "16'b0000000010101111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT145 = "16'b0000000010110000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT146 = "16'b0000000010110001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT147 = "16'b0000000010110010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT148 = "16'b0000000010110011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT149 = "16'b0000000010110100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT15 = "16'b0000000000101110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT150 = "16'b0000000010110101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT151 = "16'b0000000010110110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT152 = "16'b0000000010110111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT153 = "16'b0000000010111000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT154 = "16'b0000000010111001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT155 = "16'b0000000010111010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT156 = "16'b0000000010111011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT157 = "16'b0000000010111100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT158 = "16'b0000000010111101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT159 = "16'b0000000010111110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT16 = "16'b0000000000101111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT160 = "16'b0000000010111111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT161 = "16'b0000000011000000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT162 = "16'b0000000011000001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT163 = "16'b0000000011000010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT164 = "16'b0000000011000011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT165 = "16'b0000000011000100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT166 = "16'b0000000011000101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT167 = "16'b0000000011000110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT168 = "16'b0000000011000111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT169 = "16'b0000000011001000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT17 = "16'b0000000000110000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT170 = "16'b0000000011001001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT171 = "16'b0000000011001010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT172 = "16'b0000000011001011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT173 = "16'b0000000011001100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT174 = "16'b0000000011001101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT175 = "16'b0000000011001110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT176 = "16'b0000000011001111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT177 = "16'b0000000011010000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT178 = "16'b0000000011010001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT179 = "16'b0000000011010010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT18 = "16'b0000000000110001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT180 = "16'b0000000011010011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT181 = "16'b0000000011010100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT182 = "16'b0000000011010101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT183 = "16'b0000000011010110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT184 = "16'b0000000011010111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT185 = "16'b0000000011011000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT186 = "16'b0000000011011001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT187 = "16'b0000000011011010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT188 = "16'b0000000011011011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT189 = "16'b0000000011011100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT19 = "16'b0000000000110010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT190 = "16'b0000000011011101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT191 = "16'b0000000011011110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT192 = "16'b0000000011011111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT193 = "16'b0000000011100000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT194 = "16'b0000000011100001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT195 = "16'b0000000011100010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT196 = "16'b0000000011100011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT197 = "16'b0000000011100100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT198 = "16'b0000000011100101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT199 = "16'b0000000011100110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT2 = "16'b0000000000100001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT20 = "16'b0000000000110011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT200 = "16'b0000000011100111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT201 = "16'b0000000011101000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT202 = "16'b0000000011101001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT203 = "16'b0000000011101010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT204 = "16'b0000000011101011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT205 = "16'b0000000011101100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT206 = "16'b0000000011101101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT207 = "16'b0000000011101110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT208 = "16'b0000000011101111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT209 = "16'b0000000011110000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT21 = "16'b0000000000110100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT210 = "16'b0000000011110001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT211 = "16'b0000000011110010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT212 = "16'b0000000011110011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT213 = "16'b0000000011110100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT214 = "16'b0000000011110101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT215 = "16'b0000000011110110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT216 = "16'b0000000011110111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT217 = "16'b0000000011111000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT218 = "16'b0000000011111001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT219 = "16'b0000000011111010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT22 = "16'b0000000000110101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT220 = "16'b0000000011111011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT221 = "16'b0000000011111100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT222 = "16'b0000000011111101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT223 = "16'b0000000011111110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT224 = "16'b0000000011111111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT225 = "16'b0000000100000000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT226 = "16'b0000000100000001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT227 = "16'b0000000100000010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT228 = "16'b0000000100000011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT229 = "16'b0000000100000100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT23 = "16'b0000000000110110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT230 = "16'b0000000100000101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT231 = "16'b0000000100000110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT232 = "16'b0000000100000111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT233 = "16'b0000000100001000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT234 = "16'b0000000100001001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT235 = "16'b0000000100001010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT236 = "16'b0000000100001011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT237 = "16'b0000000100001100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT238 = "16'b0000000100001101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT239 = "16'b0000000100001110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT24 = "16'b0000000000110111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT240 = "16'b0000000100001111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT241 = "16'b0000000100010000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT242 = "16'b0000000100010001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT243 = "16'b0000000100010010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT244 = "16'b0000000100010011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT245 = "16'b0000000100010100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT246 = "16'b0000000100010101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT247 = "16'b0000000100010110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT248 = "16'b0000000100010111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT249 = "16'b0000000100011000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT25 = "16'b0000000000111000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT250 = "16'b0000000100011001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT251 = "16'b0000000100011010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT252 = "16'b0000000100011011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT253 = "16'b0000000100011100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT254 = "16'b0000000100011101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT255 = "16'b0000000100011110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT26 = "16'b0000000000111001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT27 = "16'b0000000000111010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT28 = "16'b0000000000111011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT29 = "16'b0000000000111100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT3 = "16'b0000000000100010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT30 = "16'b0000000000111101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT31 = "16'b0000000000111110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT32 = "16'b0000000000111111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT33 = "16'b0000000001000000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT34 = "16'b0000000001000001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT35 = "16'b0000000001000010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT36 = "16'b0000000001000011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT37 = "16'b0000000001000100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT38 = "16'b0000000001000101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT39 = "16'b0000000001000110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT4 = "16'b0000000000100011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT40 = "16'b0000000001000111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT41 = "16'b0000000001001000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT42 = "16'b0000000001001001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT43 = "16'b0000000001001010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT44 = "16'b0000000001001011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT45 = "16'b0000000001001100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT46 = "16'b0000000001001101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT47 = "16'b0000000001001110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT48 = "16'b0000000001001111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT49 = "16'b0000000001010000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT5 = "16'b0000000000100100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT50 = "16'b0000000001010001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT51 = "16'b0000000001010010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT52 = "16'b0000000001010011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT53 = "16'b0000000001010100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT54 = "16'b0000000001010101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT55 = "16'b0000000001010110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT56 = "16'b0000000001010111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT57 = "16'b0000000001011000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT58 = "16'b0000000001011001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT59 = "16'b0000000001011010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT6 = "16'b0000000000100101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT60 = "16'b0000000001011011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT61 = "16'b0000000001011100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT62 = "16'b0000000001011101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT63 = "16'b0000000001011110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT64 = "16'b0000000001011111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT65 = "16'b0000000001100000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT66 = "16'b0000000001100001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT67 = "16'b0000000001100010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT68 = "16'b0000000001100011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT69 = "16'b0000000001100100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT7 = "16'b0000000000100110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT70 = "16'b0000000001100101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT71 = "16'b0000000001100110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT72 = "16'b0000000001100111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT73 = "16'b0000000001101000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT74 = "16'b0000000001101001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT75 = "16'b0000000001101010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT76 = "16'b0000000001101011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT77 = "16'b0000000001101100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT78 = "16'b0000000001101101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT79 = "16'b0000000001101110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT8 = "16'b0000000000100111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT80 = "16'b0000000001101111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT81 = "16'b0000000001110000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT82 = "16'b0000000001110001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT83 = "16'b0000000001110010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT84 = "16'b0000000001110011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT85 = "16'b0000000001110100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT86 = "16'b0000000001110101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT87 = "16'b0000000001110110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT88 = "16'b0000000001110111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT89 = "16'b0000000001111000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT9 = "16'b0000000000101000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT90 = "16'b0000000001111001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT91 = "16'b0000000001111010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT92 = "16'b0000000001111011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT93 = "16'b0000000001111100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT94 = "16'b0000000001111101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT95 = "16'b0000000001111110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT96 = "16'b0000000001111111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT97 = "16'b0000000010000000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT98 = "16'b0000000010000001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT99 = "16'b0000000010000010" *) - (* LC_LOW_BIT_POS_PROBE_OUT0 = "16'b0000000000000000" *) - (* LC_LOW_BIT_POS_PROBE_OUT1 = "16'b0000000000100000" *) - (* LC_LOW_BIT_POS_PROBE_OUT10 = "16'b0000000000101001" *) - (* LC_LOW_BIT_POS_PROBE_OUT100 = "16'b0000000010000011" *) - (* LC_LOW_BIT_POS_PROBE_OUT101 = "16'b0000000010000100" *) - (* LC_LOW_BIT_POS_PROBE_OUT102 = "16'b0000000010000101" *) - (* LC_LOW_BIT_POS_PROBE_OUT103 = "16'b0000000010000110" *) - (* LC_LOW_BIT_POS_PROBE_OUT104 = "16'b0000000010000111" *) - (* LC_LOW_BIT_POS_PROBE_OUT105 = "16'b0000000010001000" *) - (* LC_LOW_BIT_POS_PROBE_OUT106 = "16'b0000000010001001" *) - (* LC_LOW_BIT_POS_PROBE_OUT107 = "16'b0000000010001010" *) - (* LC_LOW_BIT_POS_PROBE_OUT108 = "16'b0000000010001011" *) - (* LC_LOW_BIT_POS_PROBE_OUT109 = "16'b0000000010001100" *) - (* LC_LOW_BIT_POS_PROBE_OUT11 = "16'b0000000000101010" *) - (* LC_LOW_BIT_POS_PROBE_OUT110 = "16'b0000000010001101" *) - (* LC_LOW_BIT_POS_PROBE_OUT111 = "16'b0000000010001110" *) - (* LC_LOW_BIT_POS_PROBE_OUT112 = "16'b0000000010001111" *) - (* LC_LOW_BIT_POS_PROBE_OUT113 = "16'b0000000010010000" *) - (* LC_LOW_BIT_POS_PROBE_OUT114 = "16'b0000000010010001" *) - (* LC_LOW_BIT_POS_PROBE_OUT115 = "16'b0000000010010010" *) - (* LC_LOW_BIT_POS_PROBE_OUT116 = "16'b0000000010010011" *) - (* LC_LOW_BIT_POS_PROBE_OUT117 = "16'b0000000010010100" *) - (* LC_LOW_BIT_POS_PROBE_OUT118 = "16'b0000000010010101" *) - (* LC_LOW_BIT_POS_PROBE_OUT119 = "16'b0000000010010110" *) - (* LC_LOW_BIT_POS_PROBE_OUT12 = "16'b0000000000101011" *) - (* LC_LOW_BIT_POS_PROBE_OUT120 = "16'b0000000010010111" *) - (* LC_LOW_BIT_POS_PROBE_OUT121 = "16'b0000000010011000" *) - (* LC_LOW_BIT_POS_PROBE_OUT122 = "16'b0000000010011001" *) - (* LC_LOW_BIT_POS_PROBE_OUT123 = "16'b0000000010011010" *) - (* LC_LOW_BIT_POS_PROBE_OUT124 = "16'b0000000010011011" *) - (* LC_LOW_BIT_POS_PROBE_OUT125 = "16'b0000000010011100" *) - (* LC_LOW_BIT_POS_PROBE_OUT126 = "16'b0000000010011101" *) - (* LC_LOW_BIT_POS_PROBE_OUT127 = "16'b0000000010011110" *) - (* LC_LOW_BIT_POS_PROBE_OUT128 = "16'b0000000010011111" *) - (* LC_LOW_BIT_POS_PROBE_OUT129 = "16'b0000000010100000" *) - (* LC_LOW_BIT_POS_PROBE_OUT13 = "16'b0000000000101100" *) - (* LC_LOW_BIT_POS_PROBE_OUT130 = "16'b0000000010100001" *) - (* LC_LOW_BIT_POS_PROBE_OUT131 = "16'b0000000010100010" *) - (* LC_LOW_BIT_POS_PROBE_OUT132 = "16'b0000000010100011" *) - (* LC_LOW_BIT_POS_PROBE_OUT133 = "16'b0000000010100100" *) - (* LC_LOW_BIT_POS_PROBE_OUT134 = "16'b0000000010100101" *) - (* LC_LOW_BIT_POS_PROBE_OUT135 = "16'b0000000010100110" *) - (* LC_LOW_BIT_POS_PROBE_OUT136 = "16'b0000000010100111" *) - (* LC_LOW_BIT_POS_PROBE_OUT137 = "16'b0000000010101000" *) - (* LC_LOW_BIT_POS_PROBE_OUT138 = "16'b0000000010101001" *) - (* LC_LOW_BIT_POS_PROBE_OUT139 = "16'b0000000010101010" *) - (* LC_LOW_BIT_POS_PROBE_OUT14 = "16'b0000000000101101" *) - (* LC_LOW_BIT_POS_PROBE_OUT140 = "16'b0000000010101011" *) - (* LC_LOW_BIT_POS_PROBE_OUT141 = "16'b0000000010101100" *) - (* LC_LOW_BIT_POS_PROBE_OUT142 = "16'b0000000010101101" *) - (* LC_LOW_BIT_POS_PROBE_OUT143 = "16'b0000000010101110" *) - (* LC_LOW_BIT_POS_PROBE_OUT144 = "16'b0000000010101111" *) - (* LC_LOW_BIT_POS_PROBE_OUT145 = "16'b0000000010110000" *) - (* LC_LOW_BIT_POS_PROBE_OUT146 = "16'b0000000010110001" *) - (* LC_LOW_BIT_POS_PROBE_OUT147 = "16'b0000000010110010" *) - (* LC_LOW_BIT_POS_PROBE_OUT148 = "16'b0000000010110011" *) - (* LC_LOW_BIT_POS_PROBE_OUT149 = "16'b0000000010110100" *) - (* LC_LOW_BIT_POS_PROBE_OUT15 = "16'b0000000000101110" *) - (* LC_LOW_BIT_POS_PROBE_OUT150 = "16'b0000000010110101" *) - (* LC_LOW_BIT_POS_PROBE_OUT151 = "16'b0000000010110110" *) - (* LC_LOW_BIT_POS_PROBE_OUT152 = "16'b0000000010110111" *) - (* LC_LOW_BIT_POS_PROBE_OUT153 = "16'b0000000010111000" *) - (* LC_LOW_BIT_POS_PROBE_OUT154 = "16'b0000000010111001" *) - (* LC_LOW_BIT_POS_PROBE_OUT155 = "16'b0000000010111010" *) - (* LC_LOW_BIT_POS_PROBE_OUT156 = "16'b0000000010111011" *) - (* LC_LOW_BIT_POS_PROBE_OUT157 = "16'b0000000010111100" *) - (* LC_LOW_BIT_POS_PROBE_OUT158 = "16'b0000000010111101" *) - (* LC_LOW_BIT_POS_PROBE_OUT159 = "16'b0000000010111110" *) - (* LC_LOW_BIT_POS_PROBE_OUT16 = "16'b0000000000101111" *) - (* LC_LOW_BIT_POS_PROBE_OUT160 = "16'b0000000010111111" *) - (* LC_LOW_BIT_POS_PROBE_OUT161 = "16'b0000000011000000" *) - (* LC_LOW_BIT_POS_PROBE_OUT162 = "16'b0000000011000001" *) - (* LC_LOW_BIT_POS_PROBE_OUT163 = "16'b0000000011000010" *) - (* LC_LOW_BIT_POS_PROBE_OUT164 = "16'b0000000011000011" *) - (* LC_LOW_BIT_POS_PROBE_OUT165 = "16'b0000000011000100" *) - (* LC_LOW_BIT_POS_PROBE_OUT166 = "16'b0000000011000101" *) - (* LC_LOW_BIT_POS_PROBE_OUT167 = "16'b0000000011000110" *) - (* LC_LOW_BIT_POS_PROBE_OUT168 = "16'b0000000011000111" *) - (* LC_LOW_BIT_POS_PROBE_OUT169 = "16'b0000000011001000" *) - (* LC_LOW_BIT_POS_PROBE_OUT17 = "16'b0000000000110000" *) - (* LC_LOW_BIT_POS_PROBE_OUT170 = "16'b0000000011001001" *) - (* LC_LOW_BIT_POS_PROBE_OUT171 = "16'b0000000011001010" *) - (* LC_LOW_BIT_POS_PROBE_OUT172 = "16'b0000000011001011" *) - (* LC_LOW_BIT_POS_PROBE_OUT173 = "16'b0000000011001100" *) - (* LC_LOW_BIT_POS_PROBE_OUT174 = "16'b0000000011001101" *) - (* LC_LOW_BIT_POS_PROBE_OUT175 = "16'b0000000011001110" *) - (* LC_LOW_BIT_POS_PROBE_OUT176 = "16'b0000000011001111" *) - (* LC_LOW_BIT_POS_PROBE_OUT177 = "16'b0000000011010000" *) - (* LC_LOW_BIT_POS_PROBE_OUT178 = "16'b0000000011010001" *) - (* LC_LOW_BIT_POS_PROBE_OUT179 = "16'b0000000011010010" *) - (* LC_LOW_BIT_POS_PROBE_OUT18 = "16'b0000000000110001" *) - (* LC_LOW_BIT_POS_PROBE_OUT180 = "16'b0000000011010011" *) - (* LC_LOW_BIT_POS_PROBE_OUT181 = "16'b0000000011010100" *) - (* LC_LOW_BIT_POS_PROBE_OUT182 = "16'b0000000011010101" *) - (* LC_LOW_BIT_POS_PROBE_OUT183 = "16'b0000000011010110" *) - (* LC_LOW_BIT_POS_PROBE_OUT184 = "16'b0000000011010111" *) - (* LC_LOW_BIT_POS_PROBE_OUT185 = "16'b0000000011011000" *) - (* LC_LOW_BIT_POS_PROBE_OUT186 = "16'b0000000011011001" *) - (* LC_LOW_BIT_POS_PROBE_OUT187 = "16'b0000000011011010" *) - (* LC_LOW_BIT_POS_PROBE_OUT188 = "16'b0000000011011011" *) - (* LC_LOW_BIT_POS_PROBE_OUT189 = "16'b0000000011011100" *) - (* LC_LOW_BIT_POS_PROBE_OUT19 = "16'b0000000000110010" *) - (* LC_LOW_BIT_POS_PROBE_OUT190 = "16'b0000000011011101" *) - (* LC_LOW_BIT_POS_PROBE_OUT191 = "16'b0000000011011110" *) - (* LC_LOW_BIT_POS_PROBE_OUT192 = "16'b0000000011011111" *) - (* LC_LOW_BIT_POS_PROBE_OUT193 = "16'b0000000011100000" *) - (* LC_LOW_BIT_POS_PROBE_OUT194 = "16'b0000000011100001" *) - (* LC_LOW_BIT_POS_PROBE_OUT195 = "16'b0000000011100010" *) - (* LC_LOW_BIT_POS_PROBE_OUT196 = "16'b0000000011100011" *) - (* LC_LOW_BIT_POS_PROBE_OUT197 = "16'b0000000011100100" *) - (* LC_LOW_BIT_POS_PROBE_OUT198 = "16'b0000000011100101" *) - (* LC_LOW_BIT_POS_PROBE_OUT199 = "16'b0000000011100110" *) - (* LC_LOW_BIT_POS_PROBE_OUT2 = "16'b0000000000100001" *) - (* LC_LOW_BIT_POS_PROBE_OUT20 = "16'b0000000000110011" *) - (* LC_LOW_BIT_POS_PROBE_OUT200 = "16'b0000000011100111" *) - (* LC_LOW_BIT_POS_PROBE_OUT201 = "16'b0000000011101000" *) - (* LC_LOW_BIT_POS_PROBE_OUT202 = "16'b0000000011101001" *) - (* LC_LOW_BIT_POS_PROBE_OUT203 = "16'b0000000011101010" *) - (* LC_LOW_BIT_POS_PROBE_OUT204 = "16'b0000000011101011" *) - (* LC_LOW_BIT_POS_PROBE_OUT205 = "16'b0000000011101100" *) - (* LC_LOW_BIT_POS_PROBE_OUT206 = "16'b0000000011101101" *) - (* LC_LOW_BIT_POS_PROBE_OUT207 = "16'b0000000011101110" *) - (* LC_LOW_BIT_POS_PROBE_OUT208 = "16'b0000000011101111" *) - (* LC_LOW_BIT_POS_PROBE_OUT209 = "16'b0000000011110000" *) - (* LC_LOW_BIT_POS_PROBE_OUT21 = "16'b0000000000110100" *) - (* LC_LOW_BIT_POS_PROBE_OUT210 = "16'b0000000011110001" *) - (* LC_LOW_BIT_POS_PROBE_OUT211 = "16'b0000000011110010" *) - (* LC_LOW_BIT_POS_PROBE_OUT212 = "16'b0000000011110011" *) - (* LC_LOW_BIT_POS_PROBE_OUT213 = "16'b0000000011110100" *) - (* LC_LOW_BIT_POS_PROBE_OUT214 = "16'b0000000011110101" *) - (* LC_LOW_BIT_POS_PROBE_OUT215 = "16'b0000000011110110" *) - (* LC_LOW_BIT_POS_PROBE_OUT216 = "16'b0000000011110111" *) - (* LC_LOW_BIT_POS_PROBE_OUT217 = "16'b0000000011111000" *) - (* LC_LOW_BIT_POS_PROBE_OUT218 = "16'b0000000011111001" *) - (* LC_LOW_BIT_POS_PROBE_OUT219 = "16'b0000000011111010" *) - (* LC_LOW_BIT_POS_PROBE_OUT22 = "16'b0000000000110101" *) - (* LC_LOW_BIT_POS_PROBE_OUT220 = "16'b0000000011111011" *) - (* LC_LOW_BIT_POS_PROBE_OUT221 = "16'b0000000011111100" *) - (* LC_LOW_BIT_POS_PROBE_OUT222 = "16'b0000000011111101" *) - (* LC_LOW_BIT_POS_PROBE_OUT223 = "16'b0000000011111110" *) - (* LC_LOW_BIT_POS_PROBE_OUT224 = "16'b0000000011111111" *) - (* LC_LOW_BIT_POS_PROBE_OUT225 = "16'b0000000100000000" *) - (* LC_LOW_BIT_POS_PROBE_OUT226 = "16'b0000000100000001" *) - (* LC_LOW_BIT_POS_PROBE_OUT227 = "16'b0000000100000010" *) - (* LC_LOW_BIT_POS_PROBE_OUT228 = "16'b0000000100000011" *) - (* LC_LOW_BIT_POS_PROBE_OUT229 = "16'b0000000100000100" *) - (* LC_LOW_BIT_POS_PROBE_OUT23 = "16'b0000000000110110" *) - (* LC_LOW_BIT_POS_PROBE_OUT230 = "16'b0000000100000101" *) - (* LC_LOW_BIT_POS_PROBE_OUT231 = "16'b0000000100000110" *) - (* LC_LOW_BIT_POS_PROBE_OUT232 = "16'b0000000100000111" *) - (* LC_LOW_BIT_POS_PROBE_OUT233 = "16'b0000000100001000" *) - (* LC_LOW_BIT_POS_PROBE_OUT234 = "16'b0000000100001001" *) - (* LC_LOW_BIT_POS_PROBE_OUT235 = "16'b0000000100001010" *) - (* LC_LOW_BIT_POS_PROBE_OUT236 = "16'b0000000100001011" *) - (* LC_LOW_BIT_POS_PROBE_OUT237 = "16'b0000000100001100" *) - (* LC_LOW_BIT_POS_PROBE_OUT238 = "16'b0000000100001101" *) - (* LC_LOW_BIT_POS_PROBE_OUT239 = "16'b0000000100001110" *) - (* LC_LOW_BIT_POS_PROBE_OUT24 = "16'b0000000000110111" *) - (* LC_LOW_BIT_POS_PROBE_OUT240 = "16'b0000000100001111" *) - (* LC_LOW_BIT_POS_PROBE_OUT241 = "16'b0000000100010000" *) - (* LC_LOW_BIT_POS_PROBE_OUT242 = "16'b0000000100010001" *) - (* LC_LOW_BIT_POS_PROBE_OUT243 = "16'b0000000100010010" *) - (* LC_LOW_BIT_POS_PROBE_OUT244 = "16'b0000000100010011" *) - (* LC_LOW_BIT_POS_PROBE_OUT245 = "16'b0000000100010100" *) - (* LC_LOW_BIT_POS_PROBE_OUT246 = "16'b0000000100010101" *) - (* LC_LOW_BIT_POS_PROBE_OUT247 = "16'b0000000100010110" *) - (* LC_LOW_BIT_POS_PROBE_OUT248 = "16'b0000000100010111" *) - (* LC_LOW_BIT_POS_PROBE_OUT249 = "16'b0000000100011000" *) - (* LC_LOW_BIT_POS_PROBE_OUT25 = "16'b0000000000111000" *) - (* LC_LOW_BIT_POS_PROBE_OUT250 = "16'b0000000100011001" *) - (* LC_LOW_BIT_POS_PROBE_OUT251 = "16'b0000000100011010" *) - (* LC_LOW_BIT_POS_PROBE_OUT252 = "16'b0000000100011011" *) - (* LC_LOW_BIT_POS_PROBE_OUT253 = "16'b0000000100011100" *) - (* LC_LOW_BIT_POS_PROBE_OUT254 = "16'b0000000100011101" *) - (* LC_LOW_BIT_POS_PROBE_OUT255 = "16'b0000000100011110" *) - (* LC_LOW_BIT_POS_PROBE_OUT26 = "16'b0000000000111001" *) - (* LC_LOW_BIT_POS_PROBE_OUT27 = "16'b0000000000111010" *) - (* LC_LOW_BIT_POS_PROBE_OUT28 = "16'b0000000000111011" *) - (* LC_LOW_BIT_POS_PROBE_OUT29 = "16'b0000000000111100" *) - (* LC_LOW_BIT_POS_PROBE_OUT3 = "16'b0000000000100010" *) - (* LC_LOW_BIT_POS_PROBE_OUT30 = "16'b0000000000111101" *) - (* LC_LOW_BIT_POS_PROBE_OUT31 = "16'b0000000000111110" *) - (* LC_LOW_BIT_POS_PROBE_OUT32 = "16'b0000000000111111" *) - (* LC_LOW_BIT_POS_PROBE_OUT33 = "16'b0000000001000000" *) - (* LC_LOW_BIT_POS_PROBE_OUT34 = "16'b0000000001000001" *) - (* LC_LOW_BIT_POS_PROBE_OUT35 = "16'b0000000001000010" *) - (* LC_LOW_BIT_POS_PROBE_OUT36 = "16'b0000000001000011" *) - (* LC_LOW_BIT_POS_PROBE_OUT37 = "16'b0000000001000100" *) - (* LC_LOW_BIT_POS_PROBE_OUT38 = "16'b0000000001000101" *) - (* LC_LOW_BIT_POS_PROBE_OUT39 = "16'b0000000001000110" *) - (* LC_LOW_BIT_POS_PROBE_OUT4 = "16'b0000000000100011" *) - (* LC_LOW_BIT_POS_PROBE_OUT40 = "16'b0000000001000111" *) - (* LC_LOW_BIT_POS_PROBE_OUT41 = "16'b0000000001001000" *) - (* LC_LOW_BIT_POS_PROBE_OUT42 = "16'b0000000001001001" *) - (* LC_LOW_BIT_POS_PROBE_OUT43 = "16'b0000000001001010" *) - (* LC_LOW_BIT_POS_PROBE_OUT44 = "16'b0000000001001011" *) - (* LC_LOW_BIT_POS_PROBE_OUT45 = "16'b0000000001001100" *) - (* LC_LOW_BIT_POS_PROBE_OUT46 = "16'b0000000001001101" *) - (* LC_LOW_BIT_POS_PROBE_OUT47 = "16'b0000000001001110" *) - (* LC_LOW_BIT_POS_PROBE_OUT48 = "16'b0000000001001111" *) - (* LC_LOW_BIT_POS_PROBE_OUT49 = "16'b0000000001010000" *) - (* LC_LOW_BIT_POS_PROBE_OUT5 = "16'b0000000000100100" *) - (* LC_LOW_BIT_POS_PROBE_OUT50 = "16'b0000000001010001" *) - (* LC_LOW_BIT_POS_PROBE_OUT51 = "16'b0000000001010010" *) - (* LC_LOW_BIT_POS_PROBE_OUT52 = "16'b0000000001010011" *) - (* LC_LOW_BIT_POS_PROBE_OUT53 = "16'b0000000001010100" *) - (* LC_LOW_BIT_POS_PROBE_OUT54 = "16'b0000000001010101" *) - (* LC_LOW_BIT_POS_PROBE_OUT55 = "16'b0000000001010110" *) - (* LC_LOW_BIT_POS_PROBE_OUT56 = "16'b0000000001010111" *) - (* LC_LOW_BIT_POS_PROBE_OUT57 = "16'b0000000001011000" *) - (* LC_LOW_BIT_POS_PROBE_OUT58 = "16'b0000000001011001" *) - (* LC_LOW_BIT_POS_PROBE_OUT59 = "16'b0000000001011010" *) - (* LC_LOW_BIT_POS_PROBE_OUT6 = "16'b0000000000100101" *) - (* LC_LOW_BIT_POS_PROBE_OUT60 = "16'b0000000001011011" *) - (* LC_LOW_BIT_POS_PROBE_OUT61 = "16'b0000000001011100" *) - (* LC_LOW_BIT_POS_PROBE_OUT62 = "16'b0000000001011101" *) - (* LC_LOW_BIT_POS_PROBE_OUT63 = "16'b0000000001011110" *) - (* LC_LOW_BIT_POS_PROBE_OUT64 = "16'b0000000001011111" *) - (* LC_LOW_BIT_POS_PROBE_OUT65 = "16'b0000000001100000" *) - (* LC_LOW_BIT_POS_PROBE_OUT66 = "16'b0000000001100001" *) - (* LC_LOW_BIT_POS_PROBE_OUT67 = "16'b0000000001100010" *) - (* LC_LOW_BIT_POS_PROBE_OUT68 = "16'b0000000001100011" *) - (* LC_LOW_BIT_POS_PROBE_OUT69 = "16'b0000000001100100" *) - (* LC_LOW_BIT_POS_PROBE_OUT7 = "16'b0000000000100110" *) - (* LC_LOW_BIT_POS_PROBE_OUT70 = "16'b0000000001100101" *) - (* LC_LOW_BIT_POS_PROBE_OUT71 = "16'b0000000001100110" *) - (* LC_LOW_BIT_POS_PROBE_OUT72 = "16'b0000000001100111" *) - (* LC_LOW_BIT_POS_PROBE_OUT73 = "16'b0000000001101000" *) - (* LC_LOW_BIT_POS_PROBE_OUT74 = "16'b0000000001101001" *) - (* LC_LOW_BIT_POS_PROBE_OUT75 = "16'b0000000001101010" *) - (* LC_LOW_BIT_POS_PROBE_OUT76 = "16'b0000000001101011" *) - (* LC_LOW_BIT_POS_PROBE_OUT77 = "16'b0000000001101100" *) - (* LC_LOW_BIT_POS_PROBE_OUT78 = "16'b0000000001101101" *) - (* LC_LOW_BIT_POS_PROBE_OUT79 = "16'b0000000001101110" *) - (* LC_LOW_BIT_POS_PROBE_OUT8 = "16'b0000000000100111" *) - (* LC_LOW_BIT_POS_PROBE_OUT80 = "16'b0000000001101111" *) - (* LC_LOW_BIT_POS_PROBE_OUT81 = "16'b0000000001110000" *) - (* LC_LOW_BIT_POS_PROBE_OUT82 = "16'b0000000001110001" *) - (* LC_LOW_BIT_POS_PROBE_OUT83 = "16'b0000000001110010" *) - (* LC_LOW_BIT_POS_PROBE_OUT84 = "16'b0000000001110011" *) - (* LC_LOW_BIT_POS_PROBE_OUT85 = "16'b0000000001110100" *) - (* LC_LOW_BIT_POS_PROBE_OUT86 = "16'b0000000001110101" *) - (* LC_LOW_BIT_POS_PROBE_OUT87 = "16'b0000000001110110" *) - (* LC_LOW_BIT_POS_PROBE_OUT88 = "16'b0000000001110111" *) - (* LC_LOW_BIT_POS_PROBE_OUT89 = "16'b0000000001111000" *) - (* LC_LOW_BIT_POS_PROBE_OUT9 = "16'b0000000000101000" *) - (* LC_LOW_BIT_POS_PROBE_OUT90 = "16'b0000000001111001" *) - (* LC_LOW_BIT_POS_PROBE_OUT91 = "16'b0000000001111010" *) - (* LC_LOW_BIT_POS_PROBE_OUT92 = "16'b0000000001111011" *) - (* LC_LOW_BIT_POS_PROBE_OUT93 = "16'b0000000001111100" *) - (* LC_LOW_BIT_POS_PROBE_OUT94 = "16'b0000000001111101" *) - (* LC_LOW_BIT_POS_PROBE_OUT95 = "16'b0000000001111110" *) - (* LC_LOW_BIT_POS_PROBE_OUT96 = "16'b0000000001111111" *) - (* LC_LOW_BIT_POS_PROBE_OUT97 = "16'b0000000010000000" *) - (* LC_LOW_BIT_POS_PROBE_OUT98 = "16'b0000000010000001" *) - (* LC_LOW_BIT_POS_PROBE_OUT99 = "16'b0000000010000010" *) - (* LC_PROBE_IN_WIDTH_STRING = "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111100011111" *) - (* LC_PROBE_OUT_HIGH_BIT_POS_STRING = "4096'b0000000100011110000000010001110100000001000111000000000100011011000000010001101000000001000110010000000100011000000000010001011100000001000101100000000100010101000000010001010000000001000100110000000100010010000000010001000100000001000100000000000100001111000000010000111000000001000011010000000100001100000000010000101100000001000010100000000100001001000000010000100000000001000001110000000100000110000000010000010100000001000001000000000100000011000000010000001000000001000000010000000100000000000000001111111100000000111111100000000011111101000000001111110000000000111110110000000011111010000000001111100100000000111110000000000011110111000000001111011000000000111101010000000011110100000000001111001100000000111100100000000011110001000000001111000000000000111011110000000011101110000000001110110100000000111011000000000011101011000000001110101000000000111010010000000011101000000000001110011100000000111001100000000011100101000000001110010000000000111000110000000011100010000000001110000100000000111000000000000011011111000000001101111000000000110111010000000011011100000000001101101100000000110110100000000011011001000000001101100000000000110101110000000011010110000000001101010100000000110101000000000011010011000000001101001000000000110100010000000011010000000000001100111100000000110011100000000011001101000000001100110000000000110010110000000011001010000000001100100100000000110010000000000011000111000000001100011000000000110001010000000011000100000000001100001100000000110000100000000011000001000000001100000000000000101111110000000010111110000000001011110100000000101111000000000010111011000000001011101000000000101110010000000010111000000000001011011100000000101101100000000010110101000000001011010000000000101100110000000010110010000000001011000100000000101100000000000010101111000000001010111000000000101011010000000010101100000000001010101100000000101010100000000010101001000000001010100000000000101001110000000010100110000000001010010100000000101001000000000010100011000000001010001000000000101000010000000010100000000000001001111100000000100111100000000010011101000000001001110000000000100110110000000010011010000000001001100100000000100110000000000010010111000000001001011000000000100101010000000010010100000000001001001100000000100100100000000010010001000000001001000000000000100011110000000010001110000000001000110100000000100011000000000010001011000000001000101000000000100010010000000010001000000000001000011100000000100001100000000010000101000000001000010000000000100000110000000010000010000000001000000100000000100000000000000001111111000000000111111000000000011111010000000001111100000000000111101100000000011110100000000001111001000000000111100000000000011101110000000001110110000000000111010100000000011101000000000001110011000000000111001000000000011100010000000001110000000000000110111100000000011011100000000001101101000000000110110000000000011010110000000001101010000000000110100100000000011010000000000001100111000000000110011000000000011001010000000001100100000000000110001100000000011000100000000001100001000000000110000000000000010111110000000001011110000000000101110100000000010111000000000001011011000000000101101000000000010110010000000001011000000000000101011100000000010101100000000001010101000000000101010000000000010100110000000001010010000000000101000100000000010100000000000001001111000000000100111000000000010011010000000001001100000000000100101100000000010010100000000001001001000000000100100000000000010001110000000001000110000000000100010100000000010001000000000001000011000000000100001000000000010000010000000001000000000000000011111100000000001111100000000000111101000000000011110000000000001110110000000000111010000000000011100100000000001110000000000000110111000000000011011000000000001101010000000000110100000000000011001100000000001100100000000000110001000000000011000000000000001011110000000000101110000000000010110100000000001011000000000000101011000000000010101000000000001010010000000000101000000000000010011100000000001001100000000000100101000000000010010000000000001000110000000000100010000000000010000100000000001000000000000000011111" *) - (* LC_PROBE_OUT_INIT_VAL_STRING = "287'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) - (* LC_PROBE_OUT_LOW_BIT_POS_STRING = "4096'b0000000100011110000000010001110100000001000111000000000100011011000000010001101000000001000110010000000100011000000000010001011100000001000101100000000100010101000000010001010000000001000100110000000100010010000000010001000100000001000100000000000100001111000000010000111000000001000011010000000100001100000000010000101100000001000010100000000100001001000000010000100000000001000001110000000100000110000000010000010100000001000001000000000100000011000000010000001000000001000000010000000100000000000000001111111100000000111111100000000011111101000000001111110000000000111110110000000011111010000000001111100100000000111110000000000011110111000000001111011000000000111101010000000011110100000000001111001100000000111100100000000011110001000000001111000000000000111011110000000011101110000000001110110100000000111011000000000011101011000000001110101000000000111010010000000011101000000000001110011100000000111001100000000011100101000000001110010000000000111000110000000011100010000000001110000100000000111000000000000011011111000000001101111000000000110111010000000011011100000000001101101100000000110110100000000011011001000000001101100000000000110101110000000011010110000000001101010100000000110101000000000011010011000000001101001000000000110100010000000011010000000000001100111100000000110011100000000011001101000000001100110000000000110010110000000011001010000000001100100100000000110010000000000011000111000000001100011000000000110001010000000011000100000000001100001100000000110000100000000011000001000000001100000000000000101111110000000010111110000000001011110100000000101111000000000010111011000000001011101000000000101110010000000010111000000000001011011100000000101101100000000010110101000000001011010000000000101100110000000010110010000000001011000100000000101100000000000010101111000000001010111000000000101011010000000010101100000000001010101100000000101010100000000010101001000000001010100000000000101001110000000010100110000000001010010100000000101001000000000010100011000000001010001000000000101000010000000010100000000000001001111100000000100111100000000010011101000000001001110000000000100110110000000010011010000000001001100100000000100110000000000010010111000000001001011000000000100101010000000010010100000000001001001100000000100100100000000010010001000000001001000000000000100011110000000010001110000000001000110100000000100011000000000010001011000000001000101000000000100010010000000010001000000000001000011100000000100001100000000010000101000000001000010000000000100000110000000010000010000000001000000100000000100000000000000001111111000000000111111000000000011111010000000001111100000000000111101100000000011110100000000001111001000000000111100000000000011101110000000001110110000000000111010100000000011101000000000001110011000000000111001000000000011100010000000001110000000000000110111100000000011011100000000001101101000000000110110000000000011010110000000001101010000000000110100100000000011010000000000001100111000000000110011000000000011001010000000001100100000000000110001100000000011000100000000001100001000000000110000000000000010111110000000001011110000000000101110100000000010111000000000001011011000000000101101000000000010110010000000001011000000000000101011100000000010101100000000001010101000000000101010000000000010100110000000001010010000000000101000100000000010100000000000001001111000000000100111000000000010011010000000001001100000000000100101100000000010010100000000001001001000000000100100000000000010001110000000001000110000000000100010100000000010001000000000001000011000000000100001000000000010000010000000001000000000000000011111100000000001111100000000000111101000000000011110000000000001110110000000000111010000000000011100100000000001110000000000000110111000000000011011000000000001101010000000000110100000000000011001100000000001100100000000000110001000000000011000000000000001011110000000000101110000000000010110100000000001011000000000000101011000000000010101000000000001010010000000000101000000000000010011100000000001001100000000000100101000000000010010000000000001000110000000000100010000000000010000100000000001000000000000000000000" *) - (* LC_PROBE_OUT_WIDTH_STRING = "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111" *) - (* LC_TOTAL_PROBE_IN_WIDTH = "64" *) - (* LC_TOTAL_PROBE_OUT_WIDTH = "32" *) - (* syn_noprune = "1" *) - vio_0_vio_v3_0_19_vio inst - (.clk(clk), - .probe_in0(probe_in0), - .probe_in1(probe_in1), - .probe_in10(1'b0), - .probe_in100(1'b0), - .probe_in101(1'b0), - .probe_in102(1'b0), - .probe_in103(1'b0), - .probe_in104(1'b0), - .probe_in105(1'b0), - .probe_in106(1'b0), - .probe_in107(1'b0), - .probe_in108(1'b0), - .probe_in109(1'b0), - .probe_in11(1'b0), - .probe_in110(1'b0), - .probe_in111(1'b0), - .probe_in112(1'b0), - .probe_in113(1'b0), - .probe_in114(1'b0), - .probe_in115(1'b0), - .probe_in116(1'b0), - .probe_in117(1'b0), - .probe_in118(1'b0), - .probe_in119(1'b0), - .probe_in12(1'b0), - .probe_in120(1'b0), - .probe_in121(1'b0), - .probe_in122(1'b0), - .probe_in123(1'b0), - .probe_in124(1'b0), - .probe_in125(1'b0), - .probe_in126(1'b0), - .probe_in127(1'b0), - .probe_in128(1'b0), - .probe_in129(1'b0), - .probe_in13(1'b0), - .probe_in130(1'b0), - .probe_in131(1'b0), - .probe_in132(1'b0), - .probe_in133(1'b0), - .probe_in134(1'b0), - .probe_in135(1'b0), - .probe_in136(1'b0), - .probe_in137(1'b0), - .probe_in138(1'b0), - .probe_in139(1'b0), - .probe_in14(1'b0), - .probe_in140(1'b0), - .probe_in141(1'b0), - .probe_in142(1'b0), - .probe_in143(1'b0), - .probe_in144(1'b0), - .probe_in145(1'b0), - .probe_in146(1'b0), - .probe_in147(1'b0), - .probe_in148(1'b0), - .probe_in149(1'b0), - .probe_in15(1'b0), - .probe_in150(1'b0), - .probe_in151(1'b0), - .probe_in152(1'b0), - .probe_in153(1'b0), - .probe_in154(1'b0), - .probe_in155(1'b0), - .probe_in156(1'b0), - .probe_in157(1'b0), - .probe_in158(1'b0), - .probe_in159(1'b0), - .probe_in16(1'b0), - .probe_in160(1'b0), - .probe_in161(1'b0), - .probe_in162(1'b0), - .probe_in163(1'b0), - .probe_in164(1'b0), - .probe_in165(1'b0), - .probe_in166(1'b0), - .probe_in167(1'b0), - .probe_in168(1'b0), - .probe_in169(1'b0), - .probe_in17(1'b0), - .probe_in170(1'b0), - .probe_in171(1'b0), - .probe_in172(1'b0), - .probe_in173(1'b0), - .probe_in174(1'b0), - .probe_in175(1'b0), - .probe_in176(1'b0), - .probe_in177(1'b0), - .probe_in178(1'b0), - .probe_in179(1'b0), - .probe_in18(1'b0), - .probe_in180(1'b0), - .probe_in181(1'b0), - .probe_in182(1'b0), - .probe_in183(1'b0), - .probe_in184(1'b0), - .probe_in185(1'b0), - .probe_in186(1'b0), - .probe_in187(1'b0), - .probe_in188(1'b0), - .probe_in189(1'b0), - .probe_in19(1'b0), - .probe_in190(1'b0), - .probe_in191(1'b0), - .probe_in192(1'b0), - .probe_in193(1'b0), - .probe_in194(1'b0), - .probe_in195(1'b0), - .probe_in196(1'b0), - .probe_in197(1'b0), - .probe_in198(1'b0), - .probe_in199(1'b0), - .probe_in2(1'b0), - .probe_in20(1'b0), - .probe_in200(1'b0), - .probe_in201(1'b0), - .probe_in202(1'b0), - .probe_in203(1'b0), - .probe_in204(1'b0), - .probe_in205(1'b0), - .probe_in206(1'b0), - .probe_in207(1'b0), - .probe_in208(1'b0), - .probe_in209(1'b0), - .probe_in21(1'b0), - .probe_in210(1'b0), - .probe_in211(1'b0), - .probe_in212(1'b0), - .probe_in213(1'b0), - .probe_in214(1'b0), - .probe_in215(1'b0), - .probe_in216(1'b0), - .probe_in217(1'b0), - .probe_in218(1'b0), - .probe_in219(1'b0), - .probe_in22(1'b0), - .probe_in220(1'b0), - .probe_in221(1'b0), - .probe_in222(1'b0), - .probe_in223(1'b0), - .probe_in224(1'b0), - .probe_in225(1'b0), - .probe_in226(1'b0), - .probe_in227(1'b0), - .probe_in228(1'b0), - .probe_in229(1'b0), - .probe_in23(1'b0), - .probe_in230(1'b0), - .probe_in231(1'b0), - .probe_in232(1'b0), - .probe_in233(1'b0), - .probe_in234(1'b0), - .probe_in235(1'b0), - .probe_in236(1'b0), - .probe_in237(1'b0), - .probe_in238(1'b0), - .probe_in239(1'b0), - .probe_in24(1'b0), - .probe_in240(1'b0), - .probe_in241(1'b0), - .probe_in242(1'b0), - .probe_in243(1'b0), - .probe_in244(1'b0), - .probe_in245(1'b0), - .probe_in246(1'b0), - .probe_in247(1'b0), - .probe_in248(1'b0), - .probe_in249(1'b0), - .probe_in25(1'b0), - .probe_in250(1'b0), - .probe_in251(1'b0), - .probe_in252(1'b0), - .probe_in253(1'b0), - .probe_in254(1'b0), - .probe_in255(1'b0), - .probe_in26(1'b0), - .probe_in27(1'b0), - .probe_in28(1'b0), - .probe_in29(1'b0), - .probe_in3(1'b0), - .probe_in30(1'b0), - .probe_in31(1'b0), - .probe_in32(1'b0), - .probe_in33(1'b0), - .probe_in34(1'b0), - .probe_in35(1'b0), - .probe_in36(1'b0), - .probe_in37(1'b0), - .probe_in38(1'b0), - .probe_in39(1'b0), - .probe_in4(1'b0), - .probe_in40(1'b0), - .probe_in41(1'b0), - .probe_in42(1'b0), - .probe_in43(1'b0), - .probe_in44(1'b0), - .probe_in45(1'b0), - .probe_in46(1'b0), - .probe_in47(1'b0), - .probe_in48(1'b0), - .probe_in49(1'b0), - .probe_in5(1'b0), - .probe_in50(1'b0), - .probe_in51(1'b0), - .probe_in52(1'b0), - .probe_in53(1'b0), - .probe_in54(1'b0), - .probe_in55(1'b0), - .probe_in56(1'b0), - .probe_in57(1'b0), - .probe_in58(1'b0), - .probe_in59(1'b0), - .probe_in6(1'b0), - .probe_in60(1'b0), - .probe_in61(1'b0), - .probe_in62(1'b0), - .probe_in63(1'b0), - .probe_in64(1'b0), - .probe_in65(1'b0), - .probe_in66(1'b0), - .probe_in67(1'b0), - .probe_in68(1'b0), - .probe_in69(1'b0), - .probe_in7(1'b0), - .probe_in70(1'b0), - .probe_in71(1'b0), - .probe_in72(1'b0), - .probe_in73(1'b0), - .probe_in74(1'b0), - .probe_in75(1'b0), - .probe_in76(1'b0), - .probe_in77(1'b0), - .probe_in78(1'b0), - .probe_in79(1'b0), - .probe_in8(1'b0), - .probe_in80(1'b0), - .probe_in81(1'b0), - .probe_in82(1'b0), - .probe_in83(1'b0), - .probe_in84(1'b0), - .probe_in85(1'b0), - .probe_in86(1'b0), - .probe_in87(1'b0), - .probe_in88(1'b0), - .probe_in89(1'b0), - .probe_in9(1'b0), - .probe_in90(1'b0), - .probe_in91(1'b0), - .probe_in92(1'b0), - .probe_in93(1'b0), - .probe_in94(1'b0), - .probe_in95(1'b0), - .probe_in96(1'b0), - .probe_in97(1'b0), - .probe_in98(1'b0), - .probe_in99(1'b0), - .probe_out0(probe_out0), - .probe_out1(NLW_inst_probe_out1_UNCONNECTED[0]), - .probe_out10(NLW_inst_probe_out10_UNCONNECTED[0]), - .probe_out100(NLW_inst_probe_out100_UNCONNECTED[0]), - .probe_out101(NLW_inst_probe_out101_UNCONNECTED[0]), - .probe_out102(NLW_inst_probe_out102_UNCONNECTED[0]), - .probe_out103(NLW_inst_probe_out103_UNCONNECTED[0]), - .probe_out104(NLW_inst_probe_out104_UNCONNECTED[0]), - .probe_out105(NLW_inst_probe_out105_UNCONNECTED[0]), - .probe_out106(NLW_inst_probe_out106_UNCONNECTED[0]), - .probe_out107(NLW_inst_probe_out107_UNCONNECTED[0]), - .probe_out108(NLW_inst_probe_out108_UNCONNECTED[0]), - .probe_out109(NLW_inst_probe_out109_UNCONNECTED[0]), - .probe_out11(NLW_inst_probe_out11_UNCONNECTED[0]), - .probe_out110(NLW_inst_probe_out110_UNCONNECTED[0]), - .probe_out111(NLW_inst_probe_out111_UNCONNECTED[0]), - .probe_out112(NLW_inst_probe_out112_UNCONNECTED[0]), - .probe_out113(NLW_inst_probe_out113_UNCONNECTED[0]), - .probe_out114(NLW_inst_probe_out114_UNCONNECTED[0]), - .probe_out115(NLW_inst_probe_out115_UNCONNECTED[0]), - .probe_out116(NLW_inst_probe_out116_UNCONNECTED[0]), - .probe_out117(NLW_inst_probe_out117_UNCONNECTED[0]), - .probe_out118(NLW_inst_probe_out118_UNCONNECTED[0]), - .probe_out119(NLW_inst_probe_out119_UNCONNECTED[0]), - .probe_out12(NLW_inst_probe_out12_UNCONNECTED[0]), - .probe_out120(NLW_inst_probe_out120_UNCONNECTED[0]), - .probe_out121(NLW_inst_probe_out121_UNCONNECTED[0]), - .probe_out122(NLW_inst_probe_out122_UNCONNECTED[0]), - .probe_out123(NLW_inst_probe_out123_UNCONNECTED[0]), - .probe_out124(NLW_inst_probe_out124_UNCONNECTED[0]), - .probe_out125(NLW_inst_probe_out125_UNCONNECTED[0]), - .probe_out126(NLW_inst_probe_out126_UNCONNECTED[0]), - .probe_out127(NLW_inst_probe_out127_UNCONNECTED[0]), - .probe_out128(NLW_inst_probe_out128_UNCONNECTED[0]), - .probe_out129(NLW_inst_probe_out129_UNCONNECTED[0]), - .probe_out13(NLW_inst_probe_out13_UNCONNECTED[0]), - .probe_out130(NLW_inst_probe_out130_UNCONNECTED[0]), - .probe_out131(NLW_inst_probe_out131_UNCONNECTED[0]), - .probe_out132(NLW_inst_probe_out132_UNCONNECTED[0]), - .probe_out133(NLW_inst_probe_out133_UNCONNECTED[0]), - .probe_out134(NLW_inst_probe_out134_UNCONNECTED[0]), - .probe_out135(NLW_inst_probe_out135_UNCONNECTED[0]), - .probe_out136(NLW_inst_probe_out136_UNCONNECTED[0]), - .probe_out137(NLW_inst_probe_out137_UNCONNECTED[0]), - .probe_out138(NLW_inst_probe_out138_UNCONNECTED[0]), - .probe_out139(NLW_inst_probe_out139_UNCONNECTED[0]), - .probe_out14(NLW_inst_probe_out14_UNCONNECTED[0]), - .probe_out140(NLW_inst_probe_out140_UNCONNECTED[0]), - .probe_out141(NLW_inst_probe_out141_UNCONNECTED[0]), - .probe_out142(NLW_inst_probe_out142_UNCONNECTED[0]), - .probe_out143(NLW_inst_probe_out143_UNCONNECTED[0]), - .probe_out144(NLW_inst_probe_out144_UNCONNECTED[0]), - .probe_out145(NLW_inst_probe_out145_UNCONNECTED[0]), - .probe_out146(NLW_inst_probe_out146_UNCONNECTED[0]), - .probe_out147(NLW_inst_probe_out147_UNCONNECTED[0]), - .probe_out148(NLW_inst_probe_out148_UNCONNECTED[0]), - .probe_out149(NLW_inst_probe_out149_UNCONNECTED[0]), - .probe_out15(NLW_inst_probe_out15_UNCONNECTED[0]), - .probe_out150(NLW_inst_probe_out150_UNCONNECTED[0]), - .probe_out151(NLW_inst_probe_out151_UNCONNECTED[0]), - .probe_out152(NLW_inst_probe_out152_UNCONNECTED[0]), - .probe_out153(NLW_inst_probe_out153_UNCONNECTED[0]), - .probe_out154(NLW_inst_probe_out154_UNCONNECTED[0]), - .probe_out155(NLW_inst_probe_out155_UNCONNECTED[0]), - .probe_out156(NLW_inst_probe_out156_UNCONNECTED[0]), - .probe_out157(NLW_inst_probe_out157_UNCONNECTED[0]), - .probe_out158(NLW_inst_probe_out158_UNCONNECTED[0]), - .probe_out159(NLW_inst_probe_out159_UNCONNECTED[0]), - .probe_out16(NLW_inst_probe_out16_UNCONNECTED[0]), - .probe_out160(NLW_inst_probe_out160_UNCONNECTED[0]), - .probe_out161(NLW_inst_probe_out161_UNCONNECTED[0]), - .probe_out162(NLW_inst_probe_out162_UNCONNECTED[0]), - .probe_out163(NLW_inst_probe_out163_UNCONNECTED[0]), - .probe_out164(NLW_inst_probe_out164_UNCONNECTED[0]), - .probe_out165(NLW_inst_probe_out165_UNCONNECTED[0]), - .probe_out166(NLW_inst_probe_out166_UNCONNECTED[0]), - .probe_out167(NLW_inst_probe_out167_UNCONNECTED[0]), - .probe_out168(NLW_inst_probe_out168_UNCONNECTED[0]), - .probe_out169(NLW_inst_probe_out169_UNCONNECTED[0]), - .probe_out17(NLW_inst_probe_out17_UNCONNECTED[0]), - .probe_out170(NLW_inst_probe_out170_UNCONNECTED[0]), - .probe_out171(NLW_inst_probe_out171_UNCONNECTED[0]), - .probe_out172(NLW_inst_probe_out172_UNCONNECTED[0]), - .probe_out173(NLW_inst_probe_out173_UNCONNECTED[0]), - .probe_out174(NLW_inst_probe_out174_UNCONNECTED[0]), - .probe_out175(NLW_inst_probe_out175_UNCONNECTED[0]), - .probe_out176(NLW_inst_probe_out176_UNCONNECTED[0]), - .probe_out177(NLW_inst_probe_out177_UNCONNECTED[0]), - .probe_out178(NLW_inst_probe_out178_UNCONNECTED[0]), - .probe_out179(NLW_inst_probe_out179_UNCONNECTED[0]), - .probe_out18(NLW_inst_probe_out18_UNCONNECTED[0]), - .probe_out180(NLW_inst_probe_out180_UNCONNECTED[0]), - .probe_out181(NLW_inst_probe_out181_UNCONNECTED[0]), - .probe_out182(NLW_inst_probe_out182_UNCONNECTED[0]), - .probe_out183(NLW_inst_probe_out183_UNCONNECTED[0]), - .probe_out184(NLW_inst_probe_out184_UNCONNECTED[0]), - .probe_out185(NLW_inst_probe_out185_UNCONNECTED[0]), - .probe_out186(NLW_inst_probe_out186_UNCONNECTED[0]), - .probe_out187(NLW_inst_probe_out187_UNCONNECTED[0]), - .probe_out188(NLW_inst_probe_out188_UNCONNECTED[0]), - .probe_out189(NLW_inst_probe_out189_UNCONNECTED[0]), - .probe_out19(NLW_inst_probe_out19_UNCONNECTED[0]), - .probe_out190(NLW_inst_probe_out190_UNCONNECTED[0]), - .probe_out191(NLW_inst_probe_out191_UNCONNECTED[0]), - .probe_out192(NLW_inst_probe_out192_UNCONNECTED[0]), - .probe_out193(NLW_inst_probe_out193_UNCONNECTED[0]), - .probe_out194(NLW_inst_probe_out194_UNCONNECTED[0]), - .probe_out195(NLW_inst_probe_out195_UNCONNECTED[0]), - .probe_out196(NLW_inst_probe_out196_UNCONNECTED[0]), - .probe_out197(NLW_inst_probe_out197_UNCONNECTED[0]), - .probe_out198(NLW_inst_probe_out198_UNCONNECTED[0]), - .probe_out199(NLW_inst_probe_out199_UNCONNECTED[0]), - .probe_out2(NLW_inst_probe_out2_UNCONNECTED[0]), - .probe_out20(NLW_inst_probe_out20_UNCONNECTED[0]), - .probe_out200(NLW_inst_probe_out200_UNCONNECTED[0]), - .probe_out201(NLW_inst_probe_out201_UNCONNECTED[0]), - .probe_out202(NLW_inst_probe_out202_UNCONNECTED[0]), - .probe_out203(NLW_inst_probe_out203_UNCONNECTED[0]), - .probe_out204(NLW_inst_probe_out204_UNCONNECTED[0]), - .probe_out205(NLW_inst_probe_out205_UNCONNECTED[0]), - .probe_out206(NLW_inst_probe_out206_UNCONNECTED[0]), - .probe_out207(NLW_inst_probe_out207_UNCONNECTED[0]), - .probe_out208(NLW_inst_probe_out208_UNCONNECTED[0]), - .probe_out209(NLW_inst_probe_out209_UNCONNECTED[0]), - .probe_out21(NLW_inst_probe_out21_UNCONNECTED[0]), - .probe_out210(NLW_inst_probe_out210_UNCONNECTED[0]), - .probe_out211(NLW_inst_probe_out211_UNCONNECTED[0]), - .probe_out212(NLW_inst_probe_out212_UNCONNECTED[0]), - .probe_out213(NLW_inst_probe_out213_UNCONNECTED[0]), - .probe_out214(NLW_inst_probe_out214_UNCONNECTED[0]), - .probe_out215(NLW_inst_probe_out215_UNCONNECTED[0]), - .probe_out216(NLW_inst_probe_out216_UNCONNECTED[0]), - .probe_out217(NLW_inst_probe_out217_UNCONNECTED[0]), - .probe_out218(NLW_inst_probe_out218_UNCONNECTED[0]), - .probe_out219(NLW_inst_probe_out219_UNCONNECTED[0]), - .probe_out22(NLW_inst_probe_out22_UNCONNECTED[0]), - .probe_out220(NLW_inst_probe_out220_UNCONNECTED[0]), - .probe_out221(NLW_inst_probe_out221_UNCONNECTED[0]), - .probe_out222(NLW_inst_probe_out222_UNCONNECTED[0]), - .probe_out223(NLW_inst_probe_out223_UNCONNECTED[0]), - .probe_out224(NLW_inst_probe_out224_UNCONNECTED[0]), - .probe_out225(NLW_inst_probe_out225_UNCONNECTED[0]), - .probe_out226(NLW_inst_probe_out226_UNCONNECTED[0]), - .probe_out227(NLW_inst_probe_out227_UNCONNECTED[0]), - .probe_out228(NLW_inst_probe_out228_UNCONNECTED[0]), - .probe_out229(NLW_inst_probe_out229_UNCONNECTED[0]), - .probe_out23(NLW_inst_probe_out23_UNCONNECTED[0]), - .probe_out230(NLW_inst_probe_out230_UNCONNECTED[0]), - .probe_out231(NLW_inst_probe_out231_UNCONNECTED[0]), - .probe_out232(NLW_inst_probe_out232_UNCONNECTED[0]), - .probe_out233(NLW_inst_probe_out233_UNCONNECTED[0]), - .probe_out234(NLW_inst_probe_out234_UNCONNECTED[0]), - .probe_out235(NLW_inst_probe_out235_UNCONNECTED[0]), - .probe_out236(NLW_inst_probe_out236_UNCONNECTED[0]), - .probe_out237(NLW_inst_probe_out237_UNCONNECTED[0]), - .probe_out238(NLW_inst_probe_out238_UNCONNECTED[0]), - .probe_out239(NLW_inst_probe_out239_UNCONNECTED[0]), - .probe_out24(NLW_inst_probe_out24_UNCONNECTED[0]), - .probe_out240(NLW_inst_probe_out240_UNCONNECTED[0]), - .probe_out241(NLW_inst_probe_out241_UNCONNECTED[0]), - .probe_out242(NLW_inst_probe_out242_UNCONNECTED[0]), - .probe_out243(NLW_inst_probe_out243_UNCONNECTED[0]), - .probe_out244(NLW_inst_probe_out244_UNCONNECTED[0]), - .probe_out245(NLW_inst_probe_out245_UNCONNECTED[0]), - .probe_out246(NLW_inst_probe_out246_UNCONNECTED[0]), - .probe_out247(NLW_inst_probe_out247_UNCONNECTED[0]), - .probe_out248(NLW_inst_probe_out248_UNCONNECTED[0]), - .probe_out249(NLW_inst_probe_out249_UNCONNECTED[0]), - .probe_out25(NLW_inst_probe_out25_UNCONNECTED[0]), - .probe_out250(NLW_inst_probe_out250_UNCONNECTED[0]), - .probe_out251(NLW_inst_probe_out251_UNCONNECTED[0]), - .probe_out252(NLW_inst_probe_out252_UNCONNECTED[0]), - .probe_out253(NLW_inst_probe_out253_UNCONNECTED[0]), - .probe_out254(NLW_inst_probe_out254_UNCONNECTED[0]), - .probe_out255(NLW_inst_probe_out255_UNCONNECTED[0]), - .probe_out26(NLW_inst_probe_out26_UNCONNECTED[0]), - .probe_out27(NLW_inst_probe_out27_UNCONNECTED[0]), - .probe_out28(NLW_inst_probe_out28_UNCONNECTED[0]), - .probe_out29(NLW_inst_probe_out29_UNCONNECTED[0]), - .probe_out3(NLW_inst_probe_out3_UNCONNECTED[0]), - .probe_out30(NLW_inst_probe_out30_UNCONNECTED[0]), - .probe_out31(NLW_inst_probe_out31_UNCONNECTED[0]), - .probe_out32(NLW_inst_probe_out32_UNCONNECTED[0]), - .probe_out33(NLW_inst_probe_out33_UNCONNECTED[0]), - .probe_out34(NLW_inst_probe_out34_UNCONNECTED[0]), - .probe_out35(NLW_inst_probe_out35_UNCONNECTED[0]), - .probe_out36(NLW_inst_probe_out36_UNCONNECTED[0]), - .probe_out37(NLW_inst_probe_out37_UNCONNECTED[0]), - .probe_out38(NLW_inst_probe_out38_UNCONNECTED[0]), - .probe_out39(NLW_inst_probe_out39_UNCONNECTED[0]), - .probe_out4(NLW_inst_probe_out4_UNCONNECTED[0]), - .probe_out40(NLW_inst_probe_out40_UNCONNECTED[0]), - .probe_out41(NLW_inst_probe_out41_UNCONNECTED[0]), - .probe_out42(NLW_inst_probe_out42_UNCONNECTED[0]), - .probe_out43(NLW_inst_probe_out43_UNCONNECTED[0]), - .probe_out44(NLW_inst_probe_out44_UNCONNECTED[0]), - .probe_out45(NLW_inst_probe_out45_UNCONNECTED[0]), - .probe_out46(NLW_inst_probe_out46_UNCONNECTED[0]), - .probe_out47(NLW_inst_probe_out47_UNCONNECTED[0]), - .probe_out48(NLW_inst_probe_out48_UNCONNECTED[0]), - .probe_out49(NLW_inst_probe_out49_UNCONNECTED[0]), - .probe_out5(NLW_inst_probe_out5_UNCONNECTED[0]), - .probe_out50(NLW_inst_probe_out50_UNCONNECTED[0]), - .probe_out51(NLW_inst_probe_out51_UNCONNECTED[0]), - .probe_out52(NLW_inst_probe_out52_UNCONNECTED[0]), - .probe_out53(NLW_inst_probe_out53_UNCONNECTED[0]), - .probe_out54(NLW_inst_probe_out54_UNCONNECTED[0]), - .probe_out55(NLW_inst_probe_out55_UNCONNECTED[0]), - .probe_out56(NLW_inst_probe_out56_UNCONNECTED[0]), - .probe_out57(NLW_inst_probe_out57_UNCONNECTED[0]), - .probe_out58(NLW_inst_probe_out58_UNCONNECTED[0]), - .probe_out59(NLW_inst_probe_out59_UNCONNECTED[0]), - .probe_out6(NLW_inst_probe_out6_UNCONNECTED[0]), - .probe_out60(NLW_inst_probe_out60_UNCONNECTED[0]), - .probe_out61(NLW_inst_probe_out61_UNCONNECTED[0]), - .probe_out62(NLW_inst_probe_out62_UNCONNECTED[0]), - .probe_out63(NLW_inst_probe_out63_UNCONNECTED[0]), - .probe_out64(NLW_inst_probe_out64_UNCONNECTED[0]), - .probe_out65(NLW_inst_probe_out65_UNCONNECTED[0]), - .probe_out66(NLW_inst_probe_out66_UNCONNECTED[0]), - .probe_out67(NLW_inst_probe_out67_UNCONNECTED[0]), - .probe_out68(NLW_inst_probe_out68_UNCONNECTED[0]), - .probe_out69(NLW_inst_probe_out69_UNCONNECTED[0]), - .probe_out7(NLW_inst_probe_out7_UNCONNECTED[0]), - .probe_out70(NLW_inst_probe_out70_UNCONNECTED[0]), - .probe_out71(NLW_inst_probe_out71_UNCONNECTED[0]), - .probe_out72(NLW_inst_probe_out72_UNCONNECTED[0]), - .probe_out73(NLW_inst_probe_out73_UNCONNECTED[0]), - .probe_out74(NLW_inst_probe_out74_UNCONNECTED[0]), - .probe_out75(NLW_inst_probe_out75_UNCONNECTED[0]), - .probe_out76(NLW_inst_probe_out76_UNCONNECTED[0]), - .probe_out77(NLW_inst_probe_out77_UNCONNECTED[0]), - .probe_out78(NLW_inst_probe_out78_UNCONNECTED[0]), - .probe_out79(NLW_inst_probe_out79_UNCONNECTED[0]), - .probe_out8(NLW_inst_probe_out8_UNCONNECTED[0]), - .probe_out80(NLW_inst_probe_out80_UNCONNECTED[0]), - .probe_out81(NLW_inst_probe_out81_UNCONNECTED[0]), - .probe_out82(NLW_inst_probe_out82_UNCONNECTED[0]), - .probe_out83(NLW_inst_probe_out83_UNCONNECTED[0]), - .probe_out84(NLW_inst_probe_out84_UNCONNECTED[0]), - .probe_out85(NLW_inst_probe_out85_UNCONNECTED[0]), - .probe_out86(NLW_inst_probe_out86_UNCONNECTED[0]), - .probe_out87(NLW_inst_probe_out87_UNCONNECTED[0]), - .probe_out88(NLW_inst_probe_out88_UNCONNECTED[0]), - .probe_out89(NLW_inst_probe_out89_UNCONNECTED[0]), - .probe_out9(NLW_inst_probe_out9_UNCONNECTED[0]), - .probe_out90(NLW_inst_probe_out90_UNCONNECTED[0]), - .probe_out91(NLW_inst_probe_out91_UNCONNECTED[0]), - .probe_out92(NLW_inst_probe_out92_UNCONNECTED[0]), - .probe_out93(NLW_inst_probe_out93_UNCONNECTED[0]), - .probe_out94(NLW_inst_probe_out94_UNCONNECTED[0]), - .probe_out95(NLW_inst_probe_out95_UNCONNECTED[0]), - .probe_out96(NLW_inst_probe_out96_UNCONNECTED[0]), - .probe_out97(NLW_inst_probe_out97_UNCONNECTED[0]), - .probe_out98(NLW_inst_probe_out98_UNCONNECTED[0]), - .probe_out99(NLW_inst_probe_out99_UNCONNECTED[0]), - .sl_iport0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .sl_oport0(NLW_inst_sl_oport0_UNCONNECTED[16:0])); -endmodule - -(* ORIG_REF_NAME = "vio_v3_0_19_decoder" *) -module vio_0_vio_v3_0_19_decoder - (s_drdy_i, - in0, - SR, - internal_cnt_rst, - \wr_en[2]_i_2_0 , - xsdb_wr__0, - \wr_en[2]_i_4_0 , - Read_int_i_7_0, - Read_int_i_7_1, - int_cnt_rst_reg_0, - E, - \Bus_data_out_reg[15]_0 , - s_rst_o, - Q, - CLK, - xsdb_rd, - s_daddr_o, - s_den_o, - s_dwe_o, - addr_count_reg1, - \Bus_data_out_reg[15]_1 , - \Bus_data_out_reg[15]_2 ); - output s_drdy_i; - output in0; - output [0:0]SR; - output internal_cnt_rst; - output \wr_en[2]_i_2_0 ; - output xsdb_wr__0; - output \wr_en[2]_i_4_0 ; - output Read_int_i_7_0; - output Read_int_i_7_1; - output [0:0]int_cnt_rst_reg_0; - output [0:0]E; - output [15:0]\Bus_data_out_reg[15]_0 ; - input s_rst_o; - input [15:0]Q; - input CLK; - input xsdb_rd; - input [16:0]s_daddr_o; - input s_den_o; - input s_dwe_o; - input addr_count_reg1; - input [15:0]\Bus_data_out_reg[15]_1 ; - input [15:0]\Bus_data_out_reg[15]_2 ; - - wire \Bus_data_out[0]_i_1_n_0 ; - wire \Bus_data_out[10]_i_1_n_0 ; - wire \Bus_data_out[10]_i_2_n_0 ; - wire \Bus_data_out[11]_i_1_n_0 ; - wire \Bus_data_out[11]_i_2_n_0 ; - wire \Bus_data_out[12]_i_1_n_0 ; - wire \Bus_data_out[12]_i_2_n_0 ; - wire \Bus_data_out[13]_i_1_n_0 ; - wire \Bus_data_out[14]_i_1_n_0 ; - wire \Bus_data_out[15]_i_1_n_0 ; - wire \Bus_data_out[15]_i_2_n_0 ; - wire \Bus_data_out[15]_i_3_n_0 ; - wire \Bus_data_out[1]_i_1_n_0 ; - wire \Bus_data_out[2]_i_1_n_0 ; - wire \Bus_data_out[2]_i_2_n_0 ; - wire \Bus_data_out[3]_i_1_n_0 ; - wire \Bus_data_out[3]_i_2_n_0 ; - wire \Bus_data_out[4]_i_1_n_0 ; - wire \Bus_data_out[4]_i_2_n_0 ; - wire \Bus_data_out[5]_i_1_n_0 ; - wire \Bus_data_out[6]_i_1_n_0 ; - wire \Bus_data_out[7]_i_1_n_0 ; - wire \Bus_data_out[8]_i_1_n_0 ; - wire \Bus_data_out[8]_i_2_n_0 ; - wire \Bus_data_out[9]_i_1_n_0 ; - wire \Bus_data_out[9]_i_2_n_0 ; - wire [15:0]\Bus_data_out_reg[15]_0 ; - wire [15:0]\Bus_data_out_reg[15]_1 ; - wire [15:0]\Bus_data_out_reg[15]_2 ; - wire CLK; - wire [0:0]E; - wire Hold_probe_in; - wire [15:0]Q; - wire Read_int_i_7_0; - wire Read_int_i_7_1; - wire [0:0]SR; - wire addr_count_reg1; - wire [1:0]data_info_probe_in; - wire in0; - wire [0:0]int_cnt_rst_reg_0; - wire internal_cnt_rst; - wire [15:0]probe_out_modified; - wire rd_en_p1; - wire rd_en_p2; - wire [16:0]s_daddr_o; - wire s_den_o; - wire s_drdy_i; - wire s_dwe_o; - wire s_rst_o; - wire wr_control_reg; - wire \wr_en[2]_i_1_n_0 ; - wire \wr_en[2]_i_2_0 ; - wire \wr_en[2]_i_4_0 ; - wire \wr_en[4]_i_1_n_0 ; - wire \wr_en[4]_i_2_n_0 ; - wire wr_probe_out_modified; - wire [2:0]xsdb_addr_2_0_p1; - wire [2:0]xsdb_addr_2_0_p2; - wire xsdb_addr_8_p1; - wire xsdb_addr_8_p2; - wire xsdb_drdy_i_1_n_0; - wire xsdb_rd; - wire xsdb_wr__0; - - LUT3 #( - .INIT(8'hB8)) - \Bus_data_out[0]_i_1 - (.I0(\Bus_data_out_reg[15]_2 [0]), - .I1(xsdb_addr_8_p2), - .I2(data_info_probe_in[0]), - .O(\Bus_data_out[0]_i_1_n_0 )); - LUT6 #( - .INIT(64'hCFFACFFAFFF0F0F0)) - \Bus_data_out[0]_i_2 - (.I0(probe_out_modified[0]), - .I1(\Bus_data_out_reg[15]_1 [0]), - .I2(xsdb_addr_2_0_p2[0]), - .I3(xsdb_addr_2_0_p2[1]), - .I4(in0), - .I5(xsdb_addr_2_0_p2[2]), - .O(data_info_probe_in[0])); - (* SOFT_HLUTNM = "soft_lutpair11" *) - LUT3 #( - .INIT(8'hF8)) - \Bus_data_out[10]_i_1 - (.I0(xsdb_addr_8_p2), - .I1(\Bus_data_out_reg[15]_2 [10]), - .I2(\Bus_data_out[10]_i_2_n_0 ), - .O(\Bus_data_out[10]_i_1_n_0 )); - LUT6 #( - .INIT(64'h4000400044444400)) - \Bus_data_out[10]_i_2 - (.I0(xsdb_addr_8_p2), - .I1(xsdb_addr_2_0_p2[2]), - .I2(\Bus_data_out_reg[15]_1 [10]), - .I3(xsdb_addr_2_0_p2[0]), - .I4(probe_out_modified[10]), - .I5(xsdb_addr_2_0_p2[1]), - .O(\Bus_data_out[10]_i_2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair14" *) - LUT3 #( - .INIT(8'hF8)) - \Bus_data_out[11]_i_1 - (.I0(xsdb_addr_8_p2), - .I1(\Bus_data_out_reg[15]_2 [11]), - .I2(\Bus_data_out[11]_i_2_n_0 ), - .O(\Bus_data_out[11]_i_1_n_0 )); - LUT6 #( - .INIT(64'h4000400044444400)) - \Bus_data_out[11]_i_2 - (.I0(xsdb_addr_8_p2), - .I1(xsdb_addr_2_0_p2[2]), - .I2(\Bus_data_out_reg[15]_1 [11]), - .I3(xsdb_addr_2_0_p2[0]), - .I4(probe_out_modified[11]), - .I5(xsdb_addr_2_0_p2[1]), - .O(\Bus_data_out[11]_i_2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair12" *) - LUT3 #( - .INIT(8'hF8)) - \Bus_data_out[12]_i_1 - (.I0(xsdb_addr_8_p2), - .I1(\Bus_data_out_reg[15]_2 [12]), - .I2(\Bus_data_out[12]_i_2_n_0 ), - .O(\Bus_data_out[12]_i_1_n_0 )); - LUT6 #( - .INIT(64'h4000400044444400)) - \Bus_data_out[12]_i_2 - (.I0(xsdb_addr_8_p2), - .I1(xsdb_addr_2_0_p2[2]), - .I2(\Bus_data_out_reg[15]_1 [12]), - .I3(xsdb_addr_2_0_p2[0]), - .I4(probe_out_modified[12]), - .I5(xsdb_addr_2_0_p2[1]), - .O(\Bus_data_out[12]_i_2_n_0 )); - LUT6 #( - .INIT(64'hFFFFF888F888F888)) - \Bus_data_out[13]_i_1 - (.I0(\Bus_data_out[15]_i_2_n_0 ), - .I1(probe_out_modified[13]), - .I2(\Bus_data_out[15]_i_3_n_0 ), - .I3(\Bus_data_out_reg[15]_1 [13]), - .I4(xsdb_addr_8_p2), - .I5(\Bus_data_out_reg[15]_2 [13]), - .O(\Bus_data_out[13]_i_1_n_0 )); - LUT6 #( - .INIT(64'hFFFFF888F888F888)) - \Bus_data_out[14]_i_1 - (.I0(\Bus_data_out[15]_i_2_n_0 ), - .I1(probe_out_modified[14]), - .I2(\Bus_data_out[15]_i_3_n_0 ), - .I3(\Bus_data_out_reg[15]_1 [14]), - .I4(xsdb_addr_8_p2), - .I5(\Bus_data_out_reg[15]_2 [14]), - .O(\Bus_data_out[14]_i_1_n_0 )); - LUT6 #( - .INIT(64'hFFFFF888F888F888)) - \Bus_data_out[15]_i_1 - (.I0(\Bus_data_out[15]_i_2_n_0 ), - .I1(probe_out_modified[15]), - .I2(\Bus_data_out[15]_i_3_n_0 ), - .I3(\Bus_data_out_reg[15]_1 [15]), - .I4(xsdb_addr_8_p2), - .I5(\Bus_data_out_reg[15]_2 [15]), - .O(\Bus_data_out[15]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair10" *) - LUT4 #( - .INIT(16'h0100)) - \Bus_data_out[15]_i_2 - (.I0(xsdb_addr_2_0_p2[1]), - .I1(xsdb_addr_2_0_p2[0]), - .I2(xsdb_addr_8_p2), - .I3(xsdb_addr_2_0_p2[2]), - .O(\Bus_data_out[15]_i_2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair10" *) - LUT4 #( - .INIT(16'h0800)) - \Bus_data_out[15]_i_3 - (.I0(xsdb_addr_2_0_p2[1]), - .I1(xsdb_addr_2_0_p2[0]), - .I2(xsdb_addr_8_p2), - .I3(xsdb_addr_2_0_p2[2]), - .O(\Bus_data_out[15]_i_3_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair14" *) - LUT3 #( - .INIT(8'hB8)) - \Bus_data_out[1]_i_1 - (.I0(\Bus_data_out_reg[15]_2 [1]), - .I1(xsdb_addr_8_p2), - .I2(data_info_probe_in[1]), - .O(\Bus_data_out[1]_i_1_n_0 )); - LUT6 #( - .INIT(64'hB0B0FFF3B0B0CFC3)) - \Bus_data_out[1]_i_2 - (.I0(\Bus_data_out_reg[15]_1 [1]), - .I1(xsdb_addr_2_0_p2[1]), - .I2(xsdb_addr_2_0_p2[2]), - .I3(SR), - .I4(xsdb_addr_2_0_p2[0]), - .I5(probe_out_modified[1]), - .O(data_info_probe_in[1])); - LUT6 #( - .INIT(64'hFFFFBAAAAAAABAAA)) - \Bus_data_out[2]_i_1 - (.I0(\Bus_data_out[2]_i_2_n_0 ), - .I1(xsdb_addr_2_0_p2[0]), - .I2(internal_cnt_rst), - .I3(xsdb_addr_2_0_p2[1]), - .I4(xsdb_addr_8_p2), - .I5(\Bus_data_out_reg[15]_2 [2]), - .O(\Bus_data_out[2]_i_1_n_0 )); - LUT6 #( - .INIT(64'h4044404444444400)) - \Bus_data_out[2]_i_2 - (.I0(xsdb_addr_8_p2), - .I1(xsdb_addr_2_0_p2[2]), - .I2(\Bus_data_out_reg[15]_1 [2]), - .I3(xsdb_addr_2_0_p2[1]), - .I4(probe_out_modified[2]), - .I5(xsdb_addr_2_0_p2[0]), - .O(\Bus_data_out[2]_i_2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair11" *) - LUT3 #( - .INIT(8'hF8)) - \Bus_data_out[3]_i_1 - (.I0(xsdb_addr_8_p2), - .I1(\Bus_data_out_reg[15]_2 [3]), - .I2(\Bus_data_out[3]_i_2_n_0 ), - .O(\Bus_data_out[3]_i_1_n_0 )); - LUT6 #( - .INIT(64'h4044404444444400)) - \Bus_data_out[3]_i_2 - (.I0(xsdb_addr_8_p2), - .I1(xsdb_addr_2_0_p2[2]), - .I2(\Bus_data_out_reg[15]_1 [3]), - .I3(xsdb_addr_2_0_p2[1]), - .I4(probe_out_modified[3]), - .I5(xsdb_addr_2_0_p2[0]), - .O(\Bus_data_out[3]_i_2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair12" *) - LUT3 #( - .INIT(8'hF8)) - \Bus_data_out[4]_i_1 - (.I0(xsdb_addr_8_p2), - .I1(\Bus_data_out_reg[15]_2 [4]), - .I2(\Bus_data_out[4]_i_2_n_0 ), - .O(\Bus_data_out[4]_i_1_n_0 )); - LUT6 #( - .INIT(64'h4044404444444400)) - \Bus_data_out[4]_i_2 - (.I0(xsdb_addr_8_p2), - .I1(xsdb_addr_2_0_p2[2]), - .I2(\Bus_data_out_reg[15]_1 [4]), - .I3(xsdb_addr_2_0_p2[1]), - .I4(probe_out_modified[4]), - .I5(xsdb_addr_2_0_p2[0]), - .O(\Bus_data_out[4]_i_2_n_0 )); - LUT6 #( - .INIT(64'hFFFFF888F888F888)) - \Bus_data_out[5]_i_1 - (.I0(\Bus_data_out[15]_i_2_n_0 ), - .I1(probe_out_modified[5]), - .I2(\Bus_data_out[15]_i_3_n_0 ), - .I3(\Bus_data_out_reg[15]_1 [5]), - .I4(xsdb_addr_8_p2), - .I5(\Bus_data_out_reg[15]_2 [5]), - .O(\Bus_data_out[5]_i_1_n_0 )); - LUT6 #( - .INIT(64'hFFFFF888F888F888)) - \Bus_data_out[6]_i_1 - (.I0(\Bus_data_out[15]_i_2_n_0 ), - .I1(probe_out_modified[6]), - .I2(\Bus_data_out[15]_i_3_n_0 ), - .I3(\Bus_data_out_reg[15]_1 [6]), - .I4(xsdb_addr_8_p2), - .I5(\Bus_data_out_reg[15]_2 [6]), - .O(\Bus_data_out[6]_i_1_n_0 )); - LUT6 #( - .INIT(64'hFFFFF888F888F888)) - \Bus_data_out[7]_i_1 - (.I0(\Bus_data_out[15]_i_2_n_0 ), - .I1(probe_out_modified[7]), - .I2(\Bus_data_out[15]_i_3_n_0 ), - .I3(\Bus_data_out_reg[15]_1 [7]), - .I4(xsdb_addr_8_p2), - .I5(\Bus_data_out_reg[15]_2 [7]), - .O(\Bus_data_out[7]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair13" *) - LUT3 #( - .INIT(8'hF8)) - \Bus_data_out[8]_i_1 - (.I0(xsdb_addr_8_p2), - .I1(\Bus_data_out_reg[15]_2 [8]), - .I2(\Bus_data_out[8]_i_2_n_0 ), - .O(\Bus_data_out[8]_i_1_n_0 )); - LUT6 #( - .INIT(64'h4000400044444400)) - \Bus_data_out[8]_i_2 - (.I0(xsdb_addr_8_p2), - .I1(xsdb_addr_2_0_p2[2]), - .I2(\Bus_data_out_reg[15]_1 [8]), - .I3(xsdb_addr_2_0_p2[0]), - .I4(probe_out_modified[8]), - .I5(xsdb_addr_2_0_p2[1]), - .O(\Bus_data_out[8]_i_2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair13" *) - LUT3 #( - .INIT(8'hF8)) - \Bus_data_out[9]_i_1 - (.I0(xsdb_addr_8_p2), - .I1(\Bus_data_out_reg[15]_2 [9]), - .I2(\Bus_data_out[9]_i_2_n_0 ), - .O(\Bus_data_out[9]_i_1_n_0 )); - LUT6 #( - .INIT(64'h4000400044444400)) - \Bus_data_out[9]_i_2 - (.I0(xsdb_addr_8_p2), - .I1(xsdb_addr_2_0_p2[2]), - .I2(\Bus_data_out_reg[15]_1 [9]), - .I3(xsdb_addr_2_0_p2[0]), - .I4(probe_out_modified[9]), - .I5(xsdb_addr_2_0_p2[1]), - .O(\Bus_data_out[9]_i_2_n_0 )); - FDRE \Bus_data_out_reg[0] - (.C(CLK), - .CE(1'b1), - .D(\Bus_data_out[0]_i_1_n_0 ), - .Q(\Bus_data_out_reg[15]_0 [0]), - .R(1'b0)); - FDRE \Bus_data_out_reg[10] - (.C(CLK), - .CE(1'b1), - .D(\Bus_data_out[10]_i_1_n_0 ), - .Q(\Bus_data_out_reg[15]_0 [10]), - .R(1'b0)); - FDRE \Bus_data_out_reg[11] - (.C(CLK), - .CE(1'b1), - .D(\Bus_data_out[11]_i_1_n_0 ), - .Q(\Bus_data_out_reg[15]_0 [11]), - .R(1'b0)); - FDRE \Bus_data_out_reg[12] - (.C(CLK), - .CE(1'b1), - .D(\Bus_data_out[12]_i_1_n_0 ), - .Q(\Bus_data_out_reg[15]_0 [12]), - .R(1'b0)); - FDRE \Bus_data_out_reg[13] - (.C(CLK), - .CE(1'b1), - .D(\Bus_data_out[13]_i_1_n_0 ), - .Q(\Bus_data_out_reg[15]_0 [13]), - .R(1'b0)); - FDRE \Bus_data_out_reg[14] - (.C(CLK), - .CE(1'b1), - .D(\Bus_data_out[14]_i_1_n_0 ), - .Q(\Bus_data_out_reg[15]_0 [14]), - .R(1'b0)); - FDRE \Bus_data_out_reg[15] - (.C(CLK), - .CE(1'b1), - .D(\Bus_data_out[15]_i_1_n_0 ), - .Q(\Bus_data_out_reg[15]_0 [15]), - .R(1'b0)); - FDRE \Bus_data_out_reg[1] - (.C(CLK), - .CE(1'b1), - .D(\Bus_data_out[1]_i_1_n_0 ), - .Q(\Bus_data_out_reg[15]_0 [1]), - .R(1'b0)); - FDRE \Bus_data_out_reg[2] - (.C(CLK), - .CE(1'b1), - .D(\Bus_data_out[2]_i_1_n_0 ), - .Q(\Bus_data_out_reg[15]_0 [2]), - .R(1'b0)); - FDRE \Bus_data_out_reg[3] - (.C(CLK), - .CE(1'b1), - .D(\Bus_data_out[3]_i_1_n_0 ), - .Q(\Bus_data_out_reg[15]_0 [3]), - .R(1'b0)); - FDRE \Bus_data_out_reg[4] - (.C(CLK), - .CE(1'b1), - .D(\Bus_data_out[4]_i_1_n_0 ), - .Q(\Bus_data_out_reg[15]_0 [4]), - .R(1'b0)); - FDRE \Bus_data_out_reg[5] - (.C(CLK), - .CE(1'b1), - .D(\Bus_data_out[5]_i_1_n_0 ), - .Q(\Bus_data_out_reg[15]_0 [5]), - .R(1'b0)); - FDRE \Bus_data_out_reg[6] - (.C(CLK), - .CE(1'b1), - .D(\Bus_data_out[6]_i_1_n_0 ), - .Q(\Bus_data_out_reg[15]_0 [6]), - .R(1'b0)); - FDRE \Bus_data_out_reg[7] - (.C(CLK), - .CE(1'b1), - .D(\Bus_data_out[7]_i_1_n_0 ), - .Q(\Bus_data_out_reg[15]_0 [7]), - .R(1'b0)); - FDRE \Bus_data_out_reg[8] - (.C(CLK), - .CE(1'b1), - .D(\Bus_data_out[8]_i_1_n_0 ), - .Q(\Bus_data_out_reg[15]_0 [8]), - .R(1'b0)); - FDRE \Bus_data_out_reg[9] - (.C(CLK), - .CE(1'b1), - .D(\Bus_data_out[9]_i_1_n_0 ), - .Q(\Bus_data_out_reg[15]_0 [9]), - .R(1'b0)); - FDRE Hold_probe_in_reg - (.C(CLK), - .CE(wr_control_reg), - .D(Q[3]), - .Q(Hold_probe_in), - .R(s_rst_o)); - LUT2 #( - .INIT(4'hE)) - Read_int_i_7 - (.I0(s_daddr_o[11]), - .I1(s_daddr_o[10]), - .O(Read_int_i_7_1)); - LUT3 #( - .INIT(8'hFE)) - \addr_count[4]_i_1 - (.I0(internal_cnt_rst), - .I1(s_rst_o), - .I2(addr_count_reg1), - .O(int_cnt_rst_reg_0)); - FDRE clear_int_reg - (.C(CLK), - .CE(wr_control_reg), - .D(Q[1]), - .Q(SR), - .R(s_rst_o)); - FDRE committ_int_reg - (.C(CLK), - .CE(wr_control_reg), - .D(Q[0]), - .Q(in0), - .R(s_rst_o)); - FDRE int_cnt_rst_reg - (.C(CLK), - .CE(wr_control_reg), - .D(Q[2]), - .Q(internal_cnt_rst), - .R(s_rst_o)); - LUT1 #( - .INIT(2'h1)) - \probe_in_reg[63]_i_1 - (.I0(Hold_probe_in), - .O(E)); - FDRE \probe_out_modified_reg[0] - (.C(CLK), - .CE(wr_probe_out_modified), - .D(Q[0]), - .Q(probe_out_modified[0]), - .R(SR)); - FDRE \probe_out_modified_reg[10] - (.C(CLK), - .CE(wr_probe_out_modified), - .D(Q[10]), - .Q(probe_out_modified[10]), - .R(SR)); - FDRE \probe_out_modified_reg[11] - (.C(CLK), - .CE(wr_probe_out_modified), - .D(Q[11]), - .Q(probe_out_modified[11]), - .R(SR)); - FDRE \probe_out_modified_reg[12] - (.C(CLK), - .CE(wr_probe_out_modified), - .D(Q[12]), - .Q(probe_out_modified[12]), - .R(SR)); - FDRE \probe_out_modified_reg[13] - (.C(CLK), - .CE(wr_probe_out_modified), - .D(Q[13]), - .Q(probe_out_modified[13]), - .R(SR)); - FDRE \probe_out_modified_reg[14] - (.C(CLK), - .CE(wr_probe_out_modified), - .D(Q[14]), - .Q(probe_out_modified[14]), - .R(SR)); - FDRE \probe_out_modified_reg[15] - (.C(CLK), - .CE(wr_probe_out_modified), - .D(Q[15]), - .Q(probe_out_modified[15]), - .R(SR)); - FDRE \probe_out_modified_reg[1] - (.C(CLK), - .CE(wr_probe_out_modified), - .D(Q[1]), - .Q(probe_out_modified[1]), - .R(SR)); - FDRE \probe_out_modified_reg[2] - (.C(CLK), - .CE(wr_probe_out_modified), - .D(Q[2]), - .Q(probe_out_modified[2]), - .R(SR)); - FDRE \probe_out_modified_reg[3] - (.C(CLK), - .CE(wr_probe_out_modified), - .D(Q[3]), - .Q(probe_out_modified[3]), - .R(SR)); - FDRE \probe_out_modified_reg[4] - (.C(CLK), - .CE(wr_probe_out_modified), - .D(Q[4]), - .Q(probe_out_modified[4]), - .R(SR)); - FDRE \probe_out_modified_reg[5] - (.C(CLK), - .CE(wr_probe_out_modified), - .D(Q[5]), - .Q(probe_out_modified[5]), - .R(SR)); - FDRE \probe_out_modified_reg[6] - (.C(CLK), - .CE(wr_probe_out_modified), - .D(Q[6]), - .Q(probe_out_modified[6]), - .R(SR)); - FDRE \probe_out_modified_reg[7] - (.C(CLK), - .CE(wr_probe_out_modified), - .D(Q[7]), - .Q(probe_out_modified[7]), - .R(SR)); - FDRE \probe_out_modified_reg[8] - (.C(CLK), - .CE(wr_probe_out_modified), - .D(Q[8]), - .Q(probe_out_modified[8]), - .R(SR)); - FDRE \probe_out_modified_reg[9] - (.C(CLK), - .CE(wr_probe_out_modified), - .D(Q[9]), - .Q(probe_out_modified[9]), - .R(SR)); - FDRE rd_en_p1_reg - (.C(CLK), - .CE(1'b1), - .D(xsdb_rd), - .Q(rd_en_p1), - .R(s_rst_o)); - FDRE rd_en_p2_reg - (.C(CLK), - .CE(1'b1), - .D(rd_en_p1), - .Q(rd_en_p2), - .R(s_rst_o)); - LUT6 #( - .INIT(64'h0000000000000080)) - \wr_en[2]_i_1 - (.I0(\wr_en[2]_i_2_0 ), - .I1(s_daddr_o[1]), - .I2(xsdb_wr__0), - .I3(\wr_en[2]_i_4_0 ), - .I4(s_daddr_o[8]), - .I5(Read_int_i_7_0), - .O(\wr_en[2]_i_1_n_0 )); - LUT6 #( - .INIT(64'h0000000000000001)) - \wr_en[2]_i_2 - (.I0(s_daddr_o[0]), - .I1(s_daddr_o[4]), - .I2(s_daddr_o[5]), - .I3(s_daddr_o[6]), - .I4(s_daddr_o[7]), - .I5(s_daddr_o[16]), - .O(\wr_en[2]_i_2_0 )); - (* SOFT_HLUTNM = "soft_lutpair15" *) - LUT2 #( - .INIT(4'h8)) - \wr_en[2]_i_3 - (.I0(s_den_o), - .I1(s_dwe_o), - .O(xsdb_wr__0)); - LUT2 #( - .INIT(4'hE)) - \wr_en[2]_i_4 - (.I0(s_daddr_o[3]), - .I1(s_daddr_o[2]), - .O(\wr_en[2]_i_4_0 )); - LUT3 #( - .INIT(8'h02)) - \wr_en[4]_i_1 - (.I0(\wr_en[4]_i_2_n_0 ), - .I1(s_daddr_o[8]), - .I2(Read_int_i_7_0), - .O(\wr_en[4]_i_1_n_0 )); - LUT6 #( - .INIT(64'h0000080000000000)) - \wr_en[4]_i_2 - (.I0(s_den_o), - .I1(s_dwe_o), - .I2(s_daddr_o[3]), - .I3(s_daddr_o[2]), - .I4(s_daddr_o[1]), - .I5(\wr_en[2]_i_2_0 ), - .O(\wr_en[4]_i_2_n_0 )); - LUT6 #( - .INIT(64'hFFFFFFFFFFFFFFFE)) - \wr_en[4]_i_3 - (.I0(s_daddr_o[9]), - .I1(Read_int_i_7_1), - .I2(s_daddr_o[15]), - .I3(s_daddr_o[14]), - .I4(s_daddr_o[13]), - .I5(s_daddr_o[12]), - .O(Read_int_i_7_0)); - FDRE \wr_en_reg[2] - (.C(CLK), - .CE(1'b1), - .D(\wr_en[2]_i_1_n_0 ), - .Q(wr_control_reg), - .R(1'b0)); - FDRE \wr_en_reg[4] - (.C(CLK), - .CE(1'b1), - .D(\wr_en[4]_i_1_n_0 ), - .Q(wr_probe_out_modified), - .R(1'b0)); - FDRE \xsdb_addr_2_0_p1_reg[0] - (.C(CLK), - .CE(1'b1), - .D(s_daddr_o[0]), - .Q(xsdb_addr_2_0_p1[0]), - .R(1'b0)); - FDRE \xsdb_addr_2_0_p1_reg[1] - (.C(CLK), - .CE(1'b1), - .D(s_daddr_o[1]), - .Q(xsdb_addr_2_0_p1[1]), - .R(1'b0)); - FDRE \xsdb_addr_2_0_p1_reg[2] - (.C(CLK), - .CE(1'b1), - .D(s_daddr_o[2]), - .Q(xsdb_addr_2_0_p1[2]), - .R(1'b0)); - FDRE \xsdb_addr_2_0_p2_reg[0] - (.C(CLK), - .CE(1'b1), - .D(xsdb_addr_2_0_p1[0]), - .Q(xsdb_addr_2_0_p2[0]), - .R(1'b0)); - FDRE \xsdb_addr_2_0_p2_reg[1] - (.C(CLK), - .CE(1'b1), - .D(xsdb_addr_2_0_p1[1]), - .Q(xsdb_addr_2_0_p2[1]), - .R(1'b0)); - FDRE \xsdb_addr_2_0_p2_reg[2] - (.C(CLK), - .CE(1'b1), - .D(xsdb_addr_2_0_p1[2]), - .Q(xsdb_addr_2_0_p2[2]), - .R(1'b0)); - FDRE xsdb_addr_8_p1_reg - (.C(CLK), - .CE(1'b1), - .D(s_daddr_o[8]), - .Q(xsdb_addr_8_p1), - .R(1'b0)); - FDRE xsdb_addr_8_p2_reg - (.C(CLK), - .CE(1'b1), - .D(xsdb_addr_8_p1), - .Q(xsdb_addr_8_p2), - .R(1'b0)); - (* SOFT_HLUTNM = "soft_lutpair15" *) - LUT3 #( - .INIT(8'hF8)) - xsdb_drdy_i_1 - (.I0(s_dwe_o), - .I1(s_den_o), - .I2(rd_en_p2), - .O(xsdb_drdy_i_1_n_0)); - FDRE xsdb_drdy_reg - (.C(CLK), - .CE(1'b1), - .D(xsdb_drdy_i_1_n_0), - .Q(s_drdy_i), - .R(s_rst_o)); -endmodule - -(* ORIG_REF_NAME = "vio_v3_0_19_probe_in_one" *) -module vio_0_vio_v3_0_19_probe_in_one - (addr_count_reg1, - xsdb_rd, - Q, - CLK, - s_daddr_o, - Read_int_reg_0, - s_den_o, - s_dwe_o, - E, - D, - clk, - SR); - output addr_count_reg1; - output xsdb_rd; - output [15:0]Q; - input CLK; - input [16:0]s_daddr_o; - input Read_int_reg_0; - input s_den_o; - input s_dwe_o; - input [0:0]E; - input [63:0]D; - input clk; - input [0:0]SR; - - wire \Bus_Data_out[0]_i_2_n_0 ; - wire \Bus_Data_out[0]_i_3_n_0 ; - wire \Bus_Data_out[0]_i_4_n_0 ; - wire \Bus_Data_out[10]_i_2_n_0 ; - wire \Bus_Data_out[10]_i_3_n_0 ; - wire \Bus_Data_out[10]_i_4_n_0 ; - wire \Bus_Data_out[11]_i_2_n_0 ; - wire \Bus_Data_out[11]_i_3_n_0 ; - wire \Bus_Data_out[11]_i_4_n_0 ; - wire \Bus_Data_out[12]_i_2_n_0 ; - wire \Bus_Data_out[12]_i_3_n_0 ; - wire \Bus_Data_out[12]_i_4_n_0 ; - wire \Bus_Data_out[13]_i_2_n_0 ; - wire \Bus_Data_out[13]_i_3_n_0 ; - wire \Bus_Data_out[13]_i_4_n_0 ; - wire \Bus_Data_out[14]_i_2_n_0 ; - wire \Bus_Data_out[14]_i_3_n_0 ; - wire \Bus_Data_out[14]_i_4_n_0 ; - wire \Bus_Data_out[15]_i_2_n_0 ; - wire \Bus_Data_out[15]_i_3_n_0 ; - wire \Bus_Data_out[15]_i_4_n_0 ; - wire \Bus_Data_out[1]_i_2_n_0 ; - wire \Bus_Data_out[1]_i_3_n_0 ; - wire \Bus_Data_out[1]_i_4_n_0 ; - wire \Bus_Data_out[2]_i_2_n_0 ; - wire \Bus_Data_out[2]_i_3_n_0 ; - wire \Bus_Data_out[2]_i_4_n_0 ; - wire \Bus_Data_out[3]_i_2_n_0 ; - wire \Bus_Data_out[3]_i_3_n_0 ; - wire \Bus_Data_out[3]_i_4_n_0 ; - wire \Bus_Data_out[4]_i_2_n_0 ; - wire \Bus_Data_out[4]_i_3_n_0 ; - wire \Bus_Data_out[4]_i_4_n_0 ; - wire \Bus_Data_out[5]_i_2_n_0 ; - wire \Bus_Data_out[5]_i_3_n_0 ; - wire \Bus_Data_out[5]_i_4_n_0 ; - wire \Bus_Data_out[6]_i_2_n_0 ; - wire \Bus_Data_out[6]_i_3_n_0 ; - wire \Bus_Data_out[6]_i_4_n_0 ; - wire \Bus_Data_out[7]_i_2_n_0 ; - wire \Bus_Data_out[7]_i_3_n_0 ; - wire \Bus_Data_out[7]_i_4_n_0 ; - wire \Bus_Data_out[8]_i_2_n_0 ; - wire \Bus_Data_out[8]_i_3_n_0 ; - wire \Bus_Data_out[8]_i_4_n_0 ; - wire \Bus_Data_out[9]_i_2_n_0 ; - wire \Bus_Data_out[9]_i_3_n_0 ; - wire \Bus_Data_out[9]_i_4_n_0 ; - wire CLK; - wire [63:0]D; - wire \DECODER_INST/rd_en_int_7 ; - wire [0:0]E; - wire [15:0]Q; - wire Read_int; - wire Read_int_i_2_n_0; - wire Read_int_i_3_n_0; - wire Read_int_i_4_n_0; - wire Read_int_i_5_n_0; - wire Read_int_i_6_n_0; - wire Read_int_reg_0; - wire [0:0]SR; - wire [4:0]addr_count; - wire \addr_count[0]_i_1_n_0 ; - wire \addr_count[1]_i_1_n_0 ; - wire \addr_count[2]_i_1_n_0 ; - wire \addr_count[3]_i_1_n_0 ; - wire \addr_count[4]_i_2_n_0 ; - wire addr_count_reg1; - wire clk; - (* async_reg = "true" *) wire [63:0]data_int_sync1; - (* async_reg = "true" *) wire [63:0]data_int_sync2; - wire dn_activity0; - wire dn_activity0102_out; - wire dn_activity0106_out; - wire dn_activity010_out; - wire dn_activity0110_out; - wire dn_activity0114_out; - wire dn_activity0118_out; - wire dn_activity0122_out; - wire dn_activity0126_out; - wire dn_activity0130_out; - wire dn_activity0134_out; - wire dn_activity0138_out; - wire dn_activity0142_out; - wire dn_activity0146_out; - wire dn_activity014_out; - wire dn_activity0150_out; - wire dn_activity0154_out; - wire dn_activity0158_out; - wire dn_activity0162_out; - wire dn_activity0166_out; - wire dn_activity0170_out; - wire dn_activity0174_out; - wire dn_activity0178_out; - wire dn_activity0182_out; - wire dn_activity0186_out; - wire dn_activity018_out; - wire dn_activity0190_out; - wire dn_activity0194_out; - wire dn_activity0198_out; - wire dn_activity0202_out; - wire dn_activity0206_out; - wire dn_activity0210_out; - wire dn_activity0214_out; - wire dn_activity0218_out; - wire dn_activity0222_out; - wire dn_activity0226_out; - wire dn_activity022_out; - wire dn_activity0230_out; - wire dn_activity0234_out; - wire dn_activity0238_out; - wire dn_activity0242_out; - wire dn_activity0246_out; - wire dn_activity0250_out; - wire dn_activity026_out; - wire dn_activity02_out; - wire dn_activity030_out; - wire dn_activity034_out; - wire dn_activity038_out; - wire dn_activity042_out; - wire dn_activity046_out; - wire dn_activity050_out; - wire dn_activity054_out; - wire dn_activity058_out; - wire dn_activity062_out; - wire dn_activity066_out; - wire dn_activity06_out; - wire dn_activity070_out; - wire dn_activity074_out; - wire dn_activity078_out; - wire dn_activity082_out; - wire dn_activity086_out; - wire dn_activity090_out; - wire dn_activity094_out; - wire dn_activity098_out; - wire [15:0]mem_probe_in; - wire [15:0]\mem_probe_in[10]__0 ; - wire [15:0]\mem_probe_in[11]__0 ; - wire [15:0]\mem_probe_in[4]__0 ; - wire [15:0]\mem_probe_in[5]__0 ; - wire [15:0]\mem_probe_in[6]__0 ; - wire [15:0]\mem_probe_in[7]__0 ; - wire [15:0]\mem_probe_in[8]__0 ; - wire [15:0]\mem_probe_in[9]__0 ; - (* DONT_TOUCH *) wire [63:0]probe_in_reg; - (* MAX_FANOUT = "200" *) (* RTL_MAX_FANOUT = "found" *) wire read_done; - wire [16:0]s_daddr_o; - wire s_den_o; - wire s_dwe_o; - wire up_activity0; - wire up_activity0256_out; - wire up_activity0260_out; - wire up_activity0264_out; - wire up_activity0268_out; - wire up_activity0272_out; - wire up_activity0276_out; - wire up_activity0280_out; - wire up_activity0284_out; - wire up_activity0288_out; - wire up_activity0292_out; - wire up_activity0296_out; - wire up_activity0300_out; - wire up_activity0304_out; - wire up_activity0308_out; - wire up_activity0312_out; - wire up_activity0316_out; - wire up_activity0320_out; - wire up_activity0324_out; - wire up_activity0328_out; - wire up_activity0332_out; - wire up_activity0336_out; - wire up_activity0340_out; - wire up_activity0344_out; - wire up_activity0348_out; - wire up_activity0352_out; - wire up_activity0356_out; - wire up_activity0360_out; - wire up_activity0364_out; - wire up_activity0368_out; - wire up_activity0372_out; - wire up_activity0376_out; - wire up_activity0380_out; - wire up_activity0384_out; - wire up_activity0388_out; - wire up_activity0392_out; - wire up_activity0396_out; - wire up_activity0400_out; - wire up_activity0404_out; - wire up_activity0408_out; - wire up_activity0412_out; - wire up_activity0416_out; - wire up_activity0420_out; - wire up_activity0424_out; - wire up_activity0428_out; - wire up_activity0432_out; - wire up_activity0436_out; - wire up_activity0440_out; - wire up_activity0444_out; - wire up_activity0448_out; - wire up_activity0452_out; - wire up_activity0456_out; - wire up_activity0460_out; - wire up_activity0464_out; - wire up_activity0468_out; - wire up_activity0472_out; - wire up_activity0476_out; - wire up_activity0480_out; - wire up_activity0484_out; - wire up_activity0488_out; - wire up_activity0492_out; - wire up_activity0496_out; - wire up_activity0500_out; - wire up_activity0504_out; - wire xsdb_rd; - - LUT5 #( - .INIT(32'hFFE400E4)) - \Bus_Data_out[0]_i_1 - (.I0(addr_count[2]), - .I1(\Bus_Data_out[0]_i_2_n_0 ), - .I2(\Bus_Data_out[0]_i_3_n_0 ), - .I3(addr_count[3]), - .I4(\Bus_Data_out[0]_i_4_n_0 ), - .O(mem_probe_in[0])); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[0]_i_2 - (.I0(data_int_sync2[16]), - .I1(data_int_sync2[48]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(data_int_sync2[0]), - .I5(data_int_sync2[32]), - .O(\Bus_Data_out[0]_i_2_n_0 )); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[0]_i_3 - (.I0(\mem_probe_in[5]__0 [0]), - .I1(\mem_probe_in[7]__0 [0]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(\mem_probe_in[4]__0 [0]), - .I5(\mem_probe_in[6]__0 [0]), - .O(\Bus_Data_out[0]_i_3_n_0 )); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[0]_i_4 - (.I0(\mem_probe_in[9]__0 [0]), - .I1(\mem_probe_in[11]__0 [0]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(\mem_probe_in[8]__0 [0]), - .I5(\mem_probe_in[10]__0 [0]), - .O(\Bus_Data_out[0]_i_4_n_0 )); - LUT5 #( - .INIT(32'hFFE400E4)) - \Bus_Data_out[10]_i_1 - (.I0(addr_count[2]), - .I1(\Bus_Data_out[10]_i_2_n_0 ), - .I2(\Bus_Data_out[10]_i_3_n_0 ), - .I3(addr_count[3]), - .I4(\Bus_Data_out[10]_i_4_n_0 ), - .O(mem_probe_in[10])); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[10]_i_2 - (.I0(data_int_sync2[26]), - .I1(data_int_sync2[58]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(data_int_sync2[10]), - .I5(data_int_sync2[42]), - .O(\Bus_Data_out[10]_i_2_n_0 )); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[10]_i_3 - (.I0(\mem_probe_in[5]__0 [10]), - .I1(\mem_probe_in[7]__0 [10]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(\mem_probe_in[4]__0 [10]), - .I5(\mem_probe_in[6]__0 [10]), - .O(\Bus_Data_out[10]_i_3_n_0 )); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[10]_i_4 - (.I0(\mem_probe_in[9]__0 [10]), - .I1(\mem_probe_in[11]__0 [10]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(\mem_probe_in[8]__0 [10]), - .I5(\mem_probe_in[10]__0 [10]), - .O(\Bus_Data_out[10]_i_4_n_0 )); - LUT5 #( - .INIT(32'hFFE400E4)) - \Bus_Data_out[11]_i_1 - (.I0(addr_count[2]), - .I1(\Bus_Data_out[11]_i_2_n_0 ), - .I2(\Bus_Data_out[11]_i_3_n_0 ), - .I3(addr_count[3]), - .I4(\Bus_Data_out[11]_i_4_n_0 ), - .O(mem_probe_in[11])); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[11]_i_2 - (.I0(data_int_sync2[27]), - .I1(data_int_sync2[59]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(data_int_sync2[11]), - .I5(data_int_sync2[43]), - .O(\Bus_Data_out[11]_i_2_n_0 )); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[11]_i_3 - (.I0(\mem_probe_in[5]__0 [11]), - .I1(\mem_probe_in[7]__0 [11]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(\mem_probe_in[4]__0 [11]), - .I5(\mem_probe_in[6]__0 [11]), - .O(\Bus_Data_out[11]_i_3_n_0 )); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[11]_i_4 - (.I0(\mem_probe_in[9]__0 [11]), - .I1(\mem_probe_in[11]__0 [11]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(\mem_probe_in[8]__0 [11]), - .I5(\mem_probe_in[10]__0 [11]), - .O(\Bus_Data_out[11]_i_4_n_0 )); - LUT5 #( - .INIT(32'hFFE400E4)) - \Bus_Data_out[12]_i_1 - (.I0(addr_count[2]), - .I1(\Bus_Data_out[12]_i_2_n_0 ), - .I2(\Bus_Data_out[12]_i_3_n_0 ), - .I3(addr_count[3]), - .I4(\Bus_Data_out[12]_i_4_n_0 ), - .O(mem_probe_in[12])); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[12]_i_2 - (.I0(data_int_sync2[28]), - .I1(data_int_sync2[60]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(data_int_sync2[12]), - .I5(data_int_sync2[44]), - .O(\Bus_Data_out[12]_i_2_n_0 )); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[12]_i_3 - (.I0(\mem_probe_in[5]__0 [12]), - .I1(\mem_probe_in[7]__0 [12]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(\mem_probe_in[4]__0 [12]), - .I5(\mem_probe_in[6]__0 [12]), - .O(\Bus_Data_out[12]_i_3_n_0 )); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[12]_i_4 - (.I0(\mem_probe_in[9]__0 [12]), - .I1(\mem_probe_in[11]__0 [12]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(\mem_probe_in[8]__0 [12]), - .I5(\mem_probe_in[10]__0 [12]), - .O(\Bus_Data_out[12]_i_4_n_0 )); - LUT5 #( - .INIT(32'hFFE400E4)) - \Bus_Data_out[13]_i_1 - (.I0(addr_count[2]), - .I1(\Bus_Data_out[13]_i_2_n_0 ), - .I2(\Bus_Data_out[13]_i_3_n_0 ), - .I3(addr_count[3]), - .I4(\Bus_Data_out[13]_i_4_n_0 ), - .O(mem_probe_in[13])); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[13]_i_2 - (.I0(data_int_sync2[29]), - .I1(data_int_sync2[61]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(data_int_sync2[13]), - .I5(data_int_sync2[45]), - .O(\Bus_Data_out[13]_i_2_n_0 )); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[13]_i_3 - (.I0(\mem_probe_in[5]__0 [13]), - .I1(\mem_probe_in[7]__0 [13]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(\mem_probe_in[4]__0 [13]), - .I5(\mem_probe_in[6]__0 [13]), - .O(\Bus_Data_out[13]_i_3_n_0 )); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[13]_i_4 - (.I0(\mem_probe_in[9]__0 [13]), - .I1(\mem_probe_in[11]__0 [13]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(\mem_probe_in[8]__0 [13]), - .I5(\mem_probe_in[10]__0 [13]), - .O(\Bus_Data_out[13]_i_4_n_0 )); - LUT5 #( - .INIT(32'hFFE400E4)) - \Bus_Data_out[14]_i_1 - (.I0(addr_count[2]), - .I1(\Bus_Data_out[14]_i_2_n_0 ), - .I2(\Bus_Data_out[14]_i_3_n_0 ), - .I3(addr_count[3]), - .I4(\Bus_Data_out[14]_i_4_n_0 ), - .O(mem_probe_in[14])); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[14]_i_2 - (.I0(data_int_sync2[30]), - .I1(data_int_sync2[62]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(data_int_sync2[14]), - .I5(data_int_sync2[46]), - .O(\Bus_Data_out[14]_i_2_n_0 )); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[14]_i_3 - (.I0(\mem_probe_in[5]__0 [14]), - .I1(\mem_probe_in[7]__0 [14]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(\mem_probe_in[4]__0 [14]), - .I5(\mem_probe_in[6]__0 [14]), - .O(\Bus_Data_out[14]_i_3_n_0 )); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[14]_i_4 - (.I0(\mem_probe_in[9]__0 [14]), - .I1(\mem_probe_in[11]__0 [14]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(\mem_probe_in[8]__0 [14]), - .I5(\mem_probe_in[10]__0 [14]), - .O(\Bus_Data_out[14]_i_4_n_0 )); - LUT5 #( - .INIT(32'hFFE400E4)) - \Bus_Data_out[15]_i_1 - (.I0(addr_count[2]), - .I1(\Bus_Data_out[15]_i_2_n_0 ), - .I2(\Bus_Data_out[15]_i_3_n_0 ), - .I3(addr_count[3]), - .I4(\Bus_Data_out[15]_i_4_n_0 ), - .O(mem_probe_in[15])); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[15]_i_2 - (.I0(data_int_sync2[31]), - .I1(data_int_sync2[63]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(data_int_sync2[15]), - .I5(data_int_sync2[47]), - .O(\Bus_Data_out[15]_i_2_n_0 )); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[15]_i_3 - (.I0(\mem_probe_in[5]__0 [15]), - .I1(\mem_probe_in[7]__0 [15]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(\mem_probe_in[4]__0 [15]), - .I5(\mem_probe_in[6]__0 [15]), - .O(\Bus_Data_out[15]_i_3_n_0 )); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[15]_i_4 - (.I0(\mem_probe_in[9]__0 [15]), - .I1(\mem_probe_in[11]__0 [15]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(\mem_probe_in[8]__0 [15]), - .I5(\mem_probe_in[10]__0 [15]), - .O(\Bus_Data_out[15]_i_4_n_0 )); - LUT5 #( - .INIT(32'hFFE400E4)) - \Bus_Data_out[1]_i_1 - (.I0(addr_count[2]), - .I1(\Bus_Data_out[1]_i_2_n_0 ), - .I2(\Bus_Data_out[1]_i_3_n_0 ), - .I3(addr_count[3]), - .I4(\Bus_Data_out[1]_i_4_n_0 ), - .O(mem_probe_in[1])); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[1]_i_2 - (.I0(data_int_sync2[17]), - .I1(data_int_sync2[49]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(data_int_sync2[1]), - .I5(data_int_sync2[33]), - .O(\Bus_Data_out[1]_i_2_n_0 )); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[1]_i_3 - (.I0(\mem_probe_in[5]__0 [1]), - .I1(\mem_probe_in[7]__0 [1]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(\mem_probe_in[4]__0 [1]), - .I5(\mem_probe_in[6]__0 [1]), - .O(\Bus_Data_out[1]_i_3_n_0 )); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[1]_i_4 - (.I0(\mem_probe_in[9]__0 [1]), - .I1(\mem_probe_in[11]__0 [1]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(\mem_probe_in[8]__0 [1]), - .I5(\mem_probe_in[10]__0 [1]), - .O(\Bus_Data_out[1]_i_4_n_0 )); - LUT5 #( - .INIT(32'hFFE400E4)) - \Bus_Data_out[2]_i_1 - (.I0(addr_count[2]), - .I1(\Bus_Data_out[2]_i_2_n_0 ), - .I2(\Bus_Data_out[2]_i_3_n_0 ), - .I3(addr_count[3]), - .I4(\Bus_Data_out[2]_i_4_n_0 ), - .O(mem_probe_in[2])); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[2]_i_2 - (.I0(data_int_sync2[18]), - .I1(data_int_sync2[50]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(data_int_sync2[2]), - .I5(data_int_sync2[34]), - .O(\Bus_Data_out[2]_i_2_n_0 )); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[2]_i_3 - (.I0(\mem_probe_in[5]__0 [2]), - .I1(\mem_probe_in[7]__0 [2]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(\mem_probe_in[4]__0 [2]), - .I5(\mem_probe_in[6]__0 [2]), - .O(\Bus_Data_out[2]_i_3_n_0 )); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[2]_i_4 - (.I0(\mem_probe_in[9]__0 [2]), - .I1(\mem_probe_in[11]__0 [2]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(\mem_probe_in[8]__0 [2]), - .I5(\mem_probe_in[10]__0 [2]), - .O(\Bus_Data_out[2]_i_4_n_0 )); - LUT5 #( - .INIT(32'hFFE400E4)) - \Bus_Data_out[3]_i_1 - (.I0(addr_count[2]), - .I1(\Bus_Data_out[3]_i_2_n_0 ), - .I2(\Bus_Data_out[3]_i_3_n_0 ), - .I3(addr_count[3]), - .I4(\Bus_Data_out[3]_i_4_n_0 ), - .O(mem_probe_in[3])); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[3]_i_2 - (.I0(data_int_sync2[19]), - .I1(data_int_sync2[51]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(data_int_sync2[3]), - .I5(data_int_sync2[35]), - .O(\Bus_Data_out[3]_i_2_n_0 )); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[3]_i_3 - (.I0(\mem_probe_in[5]__0 [3]), - .I1(\mem_probe_in[7]__0 [3]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(\mem_probe_in[4]__0 [3]), - .I5(\mem_probe_in[6]__0 [3]), - .O(\Bus_Data_out[3]_i_3_n_0 )); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[3]_i_4 - (.I0(\mem_probe_in[9]__0 [3]), - .I1(\mem_probe_in[11]__0 [3]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(\mem_probe_in[8]__0 [3]), - .I5(\mem_probe_in[10]__0 [3]), - .O(\Bus_Data_out[3]_i_4_n_0 )); - LUT5 #( - .INIT(32'hFFE400E4)) - \Bus_Data_out[4]_i_1 - (.I0(addr_count[2]), - .I1(\Bus_Data_out[4]_i_2_n_0 ), - .I2(\Bus_Data_out[4]_i_3_n_0 ), - .I3(addr_count[3]), - .I4(\Bus_Data_out[4]_i_4_n_0 ), - .O(mem_probe_in[4])); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[4]_i_2 - (.I0(data_int_sync2[20]), - .I1(data_int_sync2[52]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(data_int_sync2[4]), - .I5(data_int_sync2[36]), - .O(\Bus_Data_out[4]_i_2_n_0 )); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[4]_i_3 - (.I0(\mem_probe_in[5]__0 [4]), - .I1(\mem_probe_in[7]__0 [4]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(\mem_probe_in[4]__0 [4]), - .I5(\mem_probe_in[6]__0 [4]), - .O(\Bus_Data_out[4]_i_3_n_0 )); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[4]_i_4 - (.I0(\mem_probe_in[9]__0 [4]), - .I1(\mem_probe_in[11]__0 [4]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(\mem_probe_in[8]__0 [4]), - .I5(\mem_probe_in[10]__0 [4]), - .O(\Bus_Data_out[4]_i_4_n_0 )); - LUT5 #( - .INIT(32'hFFE400E4)) - \Bus_Data_out[5]_i_1 - (.I0(addr_count[2]), - .I1(\Bus_Data_out[5]_i_2_n_0 ), - .I2(\Bus_Data_out[5]_i_3_n_0 ), - .I3(addr_count[3]), - .I4(\Bus_Data_out[5]_i_4_n_0 ), - .O(mem_probe_in[5])); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[5]_i_2 - (.I0(data_int_sync2[21]), - .I1(data_int_sync2[53]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(data_int_sync2[5]), - .I5(data_int_sync2[37]), - .O(\Bus_Data_out[5]_i_2_n_0 )); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[5]_i_3 - (.I0(\mem_probe_in[5]__0 [5]), - .I1(\mem_probe_in[7]__0 [5]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(\mem_probe_in[4]__0 [5]), - .I5(\mem_probe_in[6]__0 [5]), - .O(\Bus_Data_out[5]_i_3_n_0 )); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[5]_i_4 - (.I0(\mem_probe_in[9]__0 [5]), - .I1(\mem_probe_in[11]__0 [5]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(\mem_probe_in[8]__0 [5]), - .I5(\mem_probe_in[10]__0 [5]), - .O(\Bus_Data_out[5]_i_4_n_0 )); - LUT5 #( - .INIT(32'hFFE400E4)) - \Bus_Data_out[6]_i_1 - (.I0(addr_count[2]), - .I1(\Bus_Data_out[6]_i_2_n_0 ), - .I2(\Bus_Data_out[6]_i_3_n_0 ), - .I3(addr_count[3]), - .I4(\Bus_Data_out[6]_i_4_n_0 ), - .O(mem_probe_in[6])); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[6]_i_2 - (.I0(data_int_sync2[22]), - .I1(data_int_sync2[54]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(data_int_sync2[6]), - .I5(data_int_sync2[38]), - .O(\Bus_Data_out[6]_i_2_n_0 )); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[6]_i_3 - (.I0(\mem_probe_in[5]__0 [6]), - .I1(\mem_probe_in[7]__0 [6]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(\mem_probe_in[4]__0 [6]), - .I5(\mem_probe_in[6]__0 [6]), - .O(\Bus_Data_out[6]_i_3_n_0 )); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[6]_i_4 - (.I0(\mem_probe_in[9]__0 [6]), - .I1(\mem_probe_in[11]__0 [6]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(\mem_probe_in[8]__0 [6]), - .I5(\mem_probe_in[10]__0 [6]), - .O(\Bus_Data_out[6]_i_4_n_0 )); - LUT5 #( - .INIT(32'hFFE400E4)) - \Bus_Data_out[7]_i_1 - (.I0(addr_count[2]), - .I1(\Bus_Data_out[7]_i_2_n_0 ), - .I2(\Bus_Data_out[7]_i_3_n_0 ), - .I3(addr_count[3]), - .I4(\Bus_Data_out[7]_i_4_n_0 ), - .O(mem_probe_in[7])); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[7]_i_2 - (.I0(data_int_sync2[23]), - .I1(data_int_sync2[55]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(data_int_sync2[7]), - .I5(data_int_sync2[39]), - .O(\Bus_Data_out[7]_i_2_n_0 )); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[7]_i_3 - (.I0(\mem_probe_in[5]__0 [7]), - .I1(\mem_probe_in[7]__0 [7]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(\mem_probe_in[4]__0 [7]), - .I5(\mem_probe_in[6]__0 [7]), - .O(\Bus_Data_out[7]_i_3_n_0 )); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[7]_i_4 - (.I0(\mem_probe_in[9]__0 [7]), - .I1(\mem_probe_in[11]__0 [7]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(\mem_probe_in[8]__0 [7]), - .I5(\mem_probe_in[10]__0 [7]), - .O(\Bus_Data_out[7]_i_4_n_0 )); - LUT5 #( - .INIT(32'hFFE400E4)) - \Bus_Data_out[8]_i_1 - (.I0(addr_count[2]), - .I1(\Bus_Data_out[8]_i_2_n_0 ), - .I2(\Bus_Data_out[8]_i_3_n_0 ), - .I3(addr_count[3]), - .I4(\Bus_Data_out[8]_i_4_n_0 ), - .O(mem_probe_in[8])); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[8]_i_2 - (.I0(data_int_sync2[24]), - .I1(data_int_sync2[56]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(data_int_sync2[8]), - .I5(data_int_sync2[40]), - .O(\Bus_Data_out[8]_i_2_n_0 )); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[8]_i_3 - (.I0(\mem_probe_in[5]__0 [8]), - .I1(\mem_probe_in[7]__0 [8]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(\mem_probe_in[4]__0 [8]), - .I5(\mem_probe_in[6]__0 [8]), - .O(\Bus_Data_out[8]_i_3_n_0 )); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[8]_i_4 - (.I0(\mem_probe_in[9]__0 [8]), - .I1(\mem_probe_in[11]__0 [8]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(\mem_probe_in[8]__0 [8]), - .I5(\mem_probe_in[10]__0 [8]), - .O(\Bus_Data_out[8]_i_4_n_0 )); - LUT5 #( - .INIT(32'hFFE400E4)) - \Bus_Data_out[9]_i_1 - (.I0(addr_count[2]), - .I1(\Bus_Data_out[9]_i_2_n_0 ), - .I2(\Bus_Data_out[9]_i_3_n_0 ), - .I3(addr_count[3]), - .I4(\Bus_Data_out[9]_i_4_n_0 ), - .O(mem_probe_in[9])); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[9]_i_2 - (.I0(data_int_sync2[25]), - .I1(data_int_sync2[57]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(data_int_sync2[9]), - .I5(data_int_sync2[41]), - .O(\Bus_Data_out[9]_i_2_n_0 )); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[9]_i_3 - (.I0(\mem_probe_in[5]__0 [9]), - .I1(\mem_probe_in[7]__0 [9]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(\mem_probe_in[4]__0 [9]), - .I5(\mem_probe_in[6]__0 [9]), - .O(\Bus_Data_out[9]_i_3_n_0 )); - LUT6 #( - .INIT(64'hCFAFCFA0C0AFC0A0)) - \Bus_Data_out[9]_i_4 - (.I0(\mem_probe_in[9]__0 [9]), - .I1(\mem_probe_in[11]__0 [9]), - .I2(addr_count[0]), - .I3(addr_count[1]), - .I4(\mem_probe_in[8]__0 [9]), - .I5(\mem_probe_in[10]__0 [9]), - .O(\Bus_Data_out[9]_i_4_n_0 )); - FDRE \Bus_Data_out_reg[0] - (.C(CLK), - .CE(1'b1), - .D(mem_probe_in[0]), - .Q(Q[0]), - .R(1'b0)); - FDRE \Bus_Data_out_reg[10] - (.C(CLK), - .CE(1'b1), - .D(mem_probe_in[10]), - .Q(Q[10]), - .R(1'b0)); - FDRE \Bus_Data_out_reg[11] - (.C(CLK), - .CE(1'b1), - .D(mem_probe_in[11]), - .Q(Q[11]), - .R(1'b0)); - FDRE \Bus_Data_out_reg[12] - (.C(CLK), - .CE(1'b1), - .D(mem_probe_in[12]), - .Q(Q[12]), - .R(1'b0)); - FDRE \Bus_Data_out_reg[13] - (.C(CLK), - .CE(1'b1), - .D(mem_probe_in[13]), - .Q(Q[13]), - .R(1'b0)); - FDRE \Bus_Data_out_reg[14] - (.C(CLK), - .CE(1'b1), - .D(mem_probe_in[14]), - .Q(Q[14]), - .R(1'b0)); - FDRE \Bus_Data_out_reg[15] - (.C(CLK), - .CE(1'b1), - .D(mem_probe_in[15]), - .Q(Q[15]), - .R(1'b0)); - FDRE \Bus_Data_out_reg[1] - (.C(CLK), - .CE(1'b1), - .D(mem_probe_in[1]), - .Q(Q[1]), - .R(1'b0)); - FDRE \Bus_Data_out_reg[2] - (.C(CLK), - .CE(1'b1), - .D(mem_probe_in[2]), - .Q(Q[2]), - .R(1'b0)); - FDRE \Bus_Data_out_reg[3] - (.C(CLK), - .CE(1'b1), - .D(mem_probe_in[3]), - .Q(Q[3]), - .R(1'b0)); - FDRE \Bus_Data_out_reg[4] - (.C(CLK), - .CE(1'b1), - .D(mem_probe_in[4]), - .Q(Q[4]), - .R(1'b0)); - FDRE \Bus_Data_out_reg[5] - (.C(CLK), - .CE(1'b1), - .D(mem_probe_in[5]), - .Q(Q[5]), - .R(1'b0)); - FDRE \Bus_Data_out_reg[6] - (.C(CLK), - .CE(1'b1), - .D(mem_probe_in[6]), - .Q(Q[6]), - .R(1'b0)); - FDRE \Bus_Data_out_reg[7] - (.C(CLK), - .CE(1'b1), - .D(mem_probe_in[7]), - .Q(Q[7]), - .R(1'b0)); - FDRE \Bus_Data_out_reg[8] - (.C(CLK), - .CE(1'b1), - .D(mem_probe_in[8]), - .Q(Q[8]), - .R(1'b0)); - FDRE \Bus_Data_out_reg[9] - (.C(CLK), - .CE(1'b1), - .D(mem_probe_in[9]), - .Q(Q[9]), - .R(1'b0)); - LUT4 #( - .INIT(16'h8000)) - Read_int_i_1 - (.I0(Read_int_i_2_n_0), - .I1(Read_int_i_3_n_0), - .I2(Read_int_i_4_n_0), - .I3(Read_int_i_5_n_0), - .O(\DECODER_INST/rd_en_int_7 )); - LUT6 #( - .INIT(64'h0000000000000080)) - Read_int_i_2 - (.I0(s_daddr_o[0]), - .I1(s_daddr_o[1]), - .I2(s_daddr_o[2]), - .I3(Read_int_i_6_n_0), - .I4(s_daddr_o[7]), - .I5(s_daddr_o[8]), - .O(Read_int_i_2_n_0)); - LUT6 #( - .INIT(64'h0000000000000010)) - Read_int_i_3 - (.I0(s_daddr_o[15]), - .I1(s_daddr_o[16]), - .I2(xsdb_rd), - .I3(Read_int_reg_0), - .I4(s_daddr_o[13]), - .I5(s_daddr_o[14]), - .O(Read_int_i_3_n_0)); - LUT6 #( - .INIT(64'h0000230000002323)) - Read_int_i_4 - (.I0(s_daddr_o[7]), - .I1(s_daddr_o[8]), - .I2(s_daddr_o[6]), - .I3(s_daddr_o[4]), - .I4(s_daddr_o[5]), - .I5(s_daddr_o[3]), - .O(Read_int_i_4_n_0)); - LUT6 #( - .INIT(64'h0000230000002323)) - Read_int_i_5 - (.I0(s_daddr_o[13]), - .I1(s_daddr_o[14]), - .I2(s_daddr_o[12]), - .I3(s_daddr_o[10]), - .I4(s_daddr_o[11]), - .I5(s_daddr_o[9]), - .O(Read_int_i_5_n_0)); - LUT2 #( - .INIT(4'hE)) - Read_int_i_6 - (.I0(s_daddr_o[5]), - .I1(s_daddr_o[4]), - .O(Read_int_i_6_n_0)); - FDRE Read_int_reg - (.C(CLK), - .CE(1'b1), - .D(\DECODER_INST/rd_en_int_7 ), - .Q(Read_int), - .R(1'b0)); - LUT1 #( - .INIT(2'h1)) - \addr_count[0]_i_1 - (.I0(addr_count[0]), - .O(\addr_count[0]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair17" *) - LUT2 #( - .INIT(4'h6)) - \addr_count[1]_i_1 - (.I0(addr_count[1]), - .I1(addr_count[0]), - .O(\addr_count[1]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair17" *) - LUT3 #( - .INIT(8'h78)) - \addr_count[2]_i_1 - (.I0(addr_count[0]), - .I1(addr_count[1]), - .I2(addr_count[2]), - .O(\addr_count[2]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair16" *) - LUT4 #( - .INIT(16'h7F80)) - \addr_count[3]_i_1 - (.I0(addr_count[1]), - .I1(addr_count[0]), - .I2(addr_count[2]), - .I3(addr_count[3]), - .O(\addr_count[3]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair16" *) - LUT5 #( - .INIT(32'h7FFF8000)) - \addr_count[4]_i_2 - (.I0(addr_count[2]), - .I1(addr_count[0]), - .I2(addr_count[1]), - .I3(addr_count[3]), - .I4(addr_count[4]), - .O(\addr_count[4]_i_2_n_0 )); - (* MAX_FANOUT = "100" *) - FDRE \addr_count_reg[0] - (.C(CLK), - .CE(Read_int), - .D(\addr_count[0]_i_1_n_0 ), - .Q(addr_count[0]), - .R(SR)); - (* MAX_FANOUT = "100" *) - FDRE \addr_count_reg[1] - (.C(CLK), - .CE(Read_int), - .D(\addr_count[1]_i_1_n_0 ), - .Q(addr_count[1]), - .R(SR)); - (* MAX_FANOUT = "100" *) - FDRE \addr_count_reg[2] - (.C(CLK), - .CE(Read_int), - .D(\addr_count[2]_i_1_n_0 ), - .Q(addr_count[2]), - .R(SR)); - (* MAX_FANOUT = "100" *) - FDRE \addr_count_reg[3] - (.C(CLK), - .CE(Read_int), - .D(\addr_count[3]_i_1_n_0 ), - .Q(addr_count[3]), - .R(SR)); - (* MAX_FANOUT = "100" *) - FDRE \addr_count_reg[4] - (.C(CLK), - .CE(Read_int), - .D(\addr_count[4]_i_2_n_0 ), - .Q(addr_count[4]), - .R(SR)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[0] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[0]), - .Q(data_int_sync1[0]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[10] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[10]), - .Q(data_int_sync1[10]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[11] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[11]), - .Q(data_int_sync1[11]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[12] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[12]), - .Q(data_int_sync1[12]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[13] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[13]), - .Q(data_int_sync1[13]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[14] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[14]), - .Q(data_int_sync1[14]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[15] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[15]), - .Q(data_int_sync1[15]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[16] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[16]), - .Q(data_int_sync1[16]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[17] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[17]), - .Q(data_int_sync1[17]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[18] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[18]), - .Q(data_int_sync1[18]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[19] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[19]), - .Q(data_int_sync1[19]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[1] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[1]), - .Q(data_int_sync1[1]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[20] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[20]), - .Q(data_int_sync1[20]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[21] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[21]), - .Q(data_int_sync1[21]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[22] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[22]), - .Q(data_int_sync1[22]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[23] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[23]), - .Q(data_int_sync1[23]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[24] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[24]), - .Q(data_int_sync1[24]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[25] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[25]), - .Q(data_int_sync1[25]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[26] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[26]), - .Q(data_int_sync1[26]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[27] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[27]), - .Q(data_int_sync1[27]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[28] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[28]), - .Q(data_int_sync1[28]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[29] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[29]), - .Q(data_int_sync1[29]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[2] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[2]), - .Q(data_int_sync1[2]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[30] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[30]), - .Q(data_int_sync1[30]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[31] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[31]), - .Q(data_int_sync1[31]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[32] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[32]), - .Q(data_int_sync1[32]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[33] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[33]), - .Q(data_int_sync1[33]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[34] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[34]), - .Q(data_int_sync1[34]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[35] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[35]), - .Q(data_int_sync1[35]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[36] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[36]), - .Q(data_int_sync1[36]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[37] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[37]), - .Q(data_int_sync1[37]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[38] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[38]), - .Q(data_int_sync1[38]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[39] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[39]), - .Q(data_int_sync1[39]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[3] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[3]), - .Q(data_int_sync1[3]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[40] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[40]), - .Q(data_int_sync1[40]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[41] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[41]), - .Q(data_int_sync1[41]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[42] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[42]), - .Q(data_int_sync1[42]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[43] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[43]), - .Q(data_int_sync1[43]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[44] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[44]), - .Q(data_int_sync1[44]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[45] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[45]), - .Q(data_int_sync1[45]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[46] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[46]), - .Q(data_int_sync1[46]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[47] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[47]), - .Q(data_int_sync1[47]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[48] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[48]), - .Q(data_int_sync1[48]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[49] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[49]), - .Q(data_int_sync1[49]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[4] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[4]), - .Q(data_int_sync1[4]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[50] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[50]), - .Q(data_int_sync1[50]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[51] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[51]), - .Q(data_int_sync1[51]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[52] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[52]), - .Q(data_int_sync1[52]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[53] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[53]), - .Q(data_int_sync1[53]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[54] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[54]), - .Q(data_int_sync1[54]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[55] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[55]), - .Q(data_int_sync1[55]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[56] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[56]), - .Q(data_int_sync1[56]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[57] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[57]), - .Q(data_int_sync1[57]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[58] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[58]), - .Q(data_int_sync1[58]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[59] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[59]), - .Q(data_int_sync1[59]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[5] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[5]), - .Q(data_int_sync1[5]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[60] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[60]), - .Q(data_int_sync1[60]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[61] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[61]), - .Q(data_int_sync1[61]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[62] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[62]), - .Q(data_int_sync1[62]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[63] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[63]), - .Q(data_int_sync1[63]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[6] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[6]), - .Q(data_int_sync1[6]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[7] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[7]), - .Q(data_int_sync1[7]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[8] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[8]), - .Q(data_int_sync1[8]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync1_reg[9] - (.C(CLK), - .CE(1'b1), - .D(probe_in_reg[9]), - .Q(data_int_sync1[9]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[0] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[0]), - .Q(data_int_sync2[0]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[10] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[10]), - .Q(data_int_sync2[10]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[11] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[11]), - .Q(data_int_sync2[11]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[12] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[12]), - .Q(data_int_sync2[12]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[13] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[13]), - .Q(data_int_sync2[13]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[14] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[14]), - .Q(data_int_sync2[14]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[15] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[15]), - .Q(data_int_sync2[15]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[16] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[16]), - .Q(data_int_sync2[16]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[17] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[17]), - .Q(data_int_sync2[17]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[18] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[18]), - .Q(data_int_sync2[18]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[19] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[19]), - .Q(data_int_sync2[19]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[1] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[1]), - .Q(data_int_sync2[1]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[20] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[20]), - .Q(data_int_sync2[20]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[21] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[21]), - .Q(data_int_sync2[21]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[22] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[22]), - .Q(data_int_sync2[22]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[23] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[23]), - .Q(data_int_sync2[23]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[24] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[24]), - .Q(data_int_sync2[24]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[25] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[25]), - .Q(data_int_sync2[25]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[26] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[26]), - .Q(data_int_sync2[26]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[27] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[27]), - .Q(data_int_sync2[27]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[28] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[28]), - .Q(data_int_sync2[28]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[29] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[29]), - .Q(data_int_sync2[29]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[2] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[2]), - .Q(data_int_sync2[2]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[30] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[30]), - .Q(data_int_sync2[30]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[31] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[31]), - .Q(data_int_sync2[31]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[32] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[32]), - .Q(data_int_sync2[32]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[33] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[33]), - .Q(data_int_sync2[33]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[34] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[34]), - .Q(data_int_sync2[34]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[35] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[35]), - .Q(data_int_sync2[35]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[36] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[36]), - .Q(data_int_sync2[36]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[37] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[37]), - .Q(data_int_sync2[37]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[38] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[38]), - .Q(data_int_sync2[38]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[39] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[39]), - .Q(data_int_sync2[39]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[3] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[3]), - .Q(data_int_sync2[3]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[40] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[40]), - .Q(data_int_sync2[40]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[41] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[41]), - .Q(data_int_sync2[41]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[42] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[42]), - .Q(data_int_sync2[42]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[43] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[43]), - .Q(data_int_sync2[43]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[44] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[44]), - .Q(data_int_sync2[44]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[45] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[45]), - .Q(data_int_sync2[45]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[46] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[46]), - .Q(data_int_sync2[46]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[47] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[47]), - .Q(data_int_sync2[47]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[48] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[48]), - .Q(data_int_sync2[48]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[49] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[49]), - .Q(data_int_sync2[49]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[4] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[4]), - .Q(data_int_sync2[4]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[50] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[50]), - .Q(data_int_sync2[50]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[51] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[51]), - .Q(data_int_sync2[51]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[52] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[52]), - .Q(data_int_sync2[52]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[53] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[53]), - .Q(data_int_sync2[53]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[54] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[54]), - .Q(data_int_sync2[54]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[55] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[55]), - .Q(data_int_sync2[55]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[56] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[56]), - .Q(data_int_sync2[56]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[57] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[57]), - .Q(data_int_sync2[57]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[58] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[58]), - .Q(data_int_sync2[58]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[59] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[59]), - .Q(data_int_sync2[59]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[5] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[5]), - .Q(data_int_sync2[5]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[60] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[60]), - .Q(data_int_sync2[60]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[61] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[61]), - .Q(data_int_sync2[61]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[62] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[62]), - .Q(data_int_sync2[62]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[63] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[63]), - .Q(data_int_sync2[63]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[6] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[6]), - .Q(data_int_sync2[6]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[7] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[7]), - .Q(data_int_sync2[7]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[8] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[8]), - .Q(data_int_sync2[8]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \data_int_sync2_reg[9] - (.C(CLK), - .CE(1'b1), - .D(data_int_sync1[9]), - .Q(data_int_sync2[9]), - .R(1'b0)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[0]_i_1 - (.I0(data_int_sync2[0]), - .I1(data_int_sync1[0]), - .I2(read_done), - .I3(\mem_probe_in[8]__0 [0]), - .O(dn_activity0)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[10]_i_1 - (.I0(data_int_sync2[10]), - .I1(data_int_sync1[10]), - .I2(read_done), - .I3(\mem_probe_in[8]__0 [10]), - .O(dn_activity038_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[11]_i_1 - (.I0(data_int_sync2[11]), - .I1(data_int_sync1[11]), - .I2(read_done), - .I3(\mem_probe_in[8]__0 [11]), - .O(dn_activity042_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[12]_i_1 - (.I0(data_int_sync2[12]), - .I1(data_int_sync1[12]), - .I2(read_done), - .I3(\mem_probe_in[8]__0 [12]), - .O(dn_activity046_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[13]_i_1 - (.I0(data_int_sync2[13]), - .I1(data_int_sync1[13]), - .I2(read_done), - .I3(\mem_probe_in[8]__0 [13]), - .O(dn_activity050_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[14]_i_1 - (.I0(data_int_sync2[14]), - .I1(data_int_sync1[14]), - .I2(read_done), - .I3(\mem_probe_in[8]__0 [14]), - .O(dn_activity054_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[15]_i_1 - (.I0(data_int_sync2[15]), - .I1(data_int_sync1[15]), - .I2(read_done), - .I3(\mem_probe_in[8]__0 [15]), - .O(dn_activity058_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[16]_i_1 - (.I0(data_int_sync2[16]), - .I1(data_int_sync1[16]), - .I2(read_done), - .I3(\mem_probe_in[9]__0 [0]), - .O(dn_activity062_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[17]_i_1 - (.I0(data_int_sync2[17]), - .I1(data_int_sync1[17]), - .I2(read_done), - .I3(\mem_probe_in[9]__0 [1]), - .O(dn_activity066_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[18]_i_1 - (.I0(data_int_sync2[18]), - .I1(data_int_sync1[18]), - .I2(read_done), - .I3(\mem_probe_in[9]__0 [2]), - .O(dn_activity070_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[19]_i_1 - (.I0(data_int_sync2[19]), - .I1(data_int_sync1[19]), - .I2(read_done), - .I3(\mem_probe_in[9]__0 [3]), - .O(dn_activity074_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[1]_i_1 - (.I0(data_int_sync2[1]), - .I1(data_int_sync1[1]), - .I2(read_done), - .I3(\mem_probe_in[8]__0 [1]), - .O(dn_activity02_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[20]_i_1 - (.I0(data_int_sync2[20]), - .I1(data_int_sync1[20]), - .I2(read_done), - .I3(\mem_probe_in[9]__0 [4]), - .O(dn_activity078_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[21]_i_1 - (.I0(data_int_sync2[21]), - .I1(data_int_sync1[21]), - .I2(read_done), - .I3(\mem_probe_in[9]__0 [5]), - .O(dn_activity082_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[22]_i_1 - (.I0(data_int_sync2[22]), - .I1(data_int_sync1[22]), - .I2(read_done), - .I3(\mem_probe_in[9]__0 [6]), - .O(dn_activity086_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[23]_i_1 - (.I0(data_int_sync2[23]), - .I1(data_int_sync1[23]), - .I2(read_done), - .I3(\mem_probe_in[9]__0 [7]), - .O(dn_activity090_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[24]_i_1 - (.I0(data_int_sync2[24]), - .I1(data_int_sync1[24]), - .I2(read_done), - .I3(\mem_probe_in[9]__0 [8]), - .O(dn_activity094_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[25]_i_1 - (.I0(data_int_sync2[25]), - .I1(data_int_sync1[25]), - .I2(read_done), - .I3(\mem_probe_in[9]__0 [9]), - .O(dn_activity098_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[26]_i_1 - (.I0(data_int_sync2[26]), - .I1(data_int_sync1[26]), - .I2(read_done), - .I3(\mem_probe_in[9]__0 [10]), - .O(dn_activity0102_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[27]_i_1 - (.I0(data_int_sync2[27]), - .I1(data_int_sync1[27]), - .I2(read_done), - .I3(\mem_probe_in[9]__0 [11]), - .O(dn_activity0106_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[28]_i_1 - (.I0(data_int_sync2[28]), - .I1(data_int_sync1[28]), - .I2(read_done), - .I3(\mem_probe_in[9]__0 [12]), - .O(dn_activity0110_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[29]_i_1 - (.I0(data_int_sync2[29]), - .I1(data_int_sync1[29]), - .I2(read_done), - .I3(\mem_probe_in[9]__0 [13]), - .O(dn_activity0114_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[2]_i_1 - (.I0(data_int_sync2[2]), - .I1(data_int_sync1[2]), - .I2(read_done), - .I3(\mem_probe_in[8]__0 [2]), - .O(dn_activity06_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[30]_i_1 - (.I0(data_int_sync2[30]), - .I1(data_int_sync1[30]), - .I2(read_done), - .I3(\mem_probe_in[9]__0 [14]), - .O(dn_activity0118_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[31]_i_1 - (.I0(data_int_sync2[31]), - .I1(data_int_sync1[31]), - .I2(read_done), - .I3(\mem_probe_in[9]__0 [15]), - .O(dn_activity0122_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[32]_i_1 - (.I0(data_int_sync2[32]), - .I1(data_int_sync1[32]), - .I2(read_done), - .I3(\mem_probe_in[10]__0 [0]), - .O(dn_activity0126_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[33]_i_1 - (.I0(data_int_sync2[33]), - .I1(data_int_sync1[33]), - .I2(read_done), - .I3(\mem_probe_in[10]__0 [1]), - .O(dn_activity0130_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[34]_i_1 - (.I0(data_int_sync2[34]), - .I1(data_int_sync1[34]), - .I2(read_done), - .I3(\mem_probe_in[10]__0 [2]), - .O(dn_activity0134_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[35]_i_1 - (.I0(data_int_sync2[35]), - .I1(data_int_sync1[35]), - .I2(read_done), - .I3(\mem_probe_in[10]__0 [3]), - .O(dn_activity0138_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[36]_i_1 - (.I0(data_int_sync2[36]), - .I1(data_int_sync1[36]), - .I2(read_done), - .I3(\mem_probe_in[10]__0 [4]), - .O(dn_activity0142_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[37]_i_1 - (.I0(data_int_sync2[37]), - .I1(data_int_sync1[37]), - .I2(read_done), - .I3(\mem_probe_in[10]__0 [5]), - .O(dn_activity0146_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[38]_i_1 - (.I0(data_int_sync2[38]), - .I1(data_int_sync1[38]), - .I2(read_done), - .I3(\mem_probe_in[10]__0 [6]), - .O(dn_activity0150_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[39]_i_1 - (.I0(data_int_sync2[39]), - .I1(data_int_sync1[39]), - .I2(read_done), - .I3(\mem_probe_in[10]__0 [7]), - .O(dn_activity0154_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[3]_i_1 - (.I0(data_int_sync2[3]), - .I1(data_int_sync1[3]), - .I2(read_done), - .I3(\mem_probe_in[8]__0 [3]), - .O(dn_activity010_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[40]_i_1 - (.I0(data_int_sync2[40]), - .I1(data_int_sync1[40]), - .I2(read_done), - .I3(\mem_probe_in[10]__0 [8]), - .O(dn_activity0158_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[41]_i_1 - (.I0(data_int_sync2[41]), - .I1(data_int_sync1[41]), - .I2(read_done), - .I3(\mem_probe_in[10]__0 [9]), - .O(dn_activity0162_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[42]_i_1 - (.I0(data_int_sync2[42]), - .I1(data_int_sync1[42]), - .I2(read_done), - .I3(\mem_probe_in[10]__0 [10]), - .O(dn_activity0166_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[43]_i_1 - (.I0(data_int_sync2[43]), - .I1(data_int_sync1[43]), - .I2(read_done), - .I3(\mem_probe_in[10]__0 [11]), - .O(dn_activity0170_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[44]_i_1 - (.I0(data_int_sync2[44]), - .I1(data_int_sync1[44]), - .I2(read_done), - .I3(\mem_probe_in[10]__0 [12]), - .O(dn_activity0174_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[45]_i_1 - (.I0(data_int_sync2[45]), - .I1(data_int_sync1[45]), - .I2(read_done), - .I3(\mem_probe_in[10]__0 [13]), - .O(dn_activity0178_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[46]_i_1 - (.I0(data_int_sync2[46]), - .I1(data_int_sync1[46]), - .I2(read_done), - .I3(\mem_probe_in[10]__0 [14]), - .O(dn_activity0182_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[47]_i_1 - (.I0(data_int_sync2[47]), - .I1(data_int_sync1[47]), - .I2(read_done), - .I3(\mem_probe_in[10]__0 [15]), - .O(dn_activity0186_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[48]_i_1 - (.I0(data_int_sync2[48]), - .I1(data_int_sync1[48]), - .I2(read_done), - .I3(\mem_probe_in[11]__0 [0]), - .O(dn_activity0190_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[49]_i_1 - (.I0(data_int_sync2[49]), - .I1(data_int_sync1[49]), - .I2(read_done), - .I3(\mem_probe_in[11]__0 [1]), - .O(dn_activity0194_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[4]_i_1 - (.I0(data_int_sync2[4]), - .I1(data_int_sync1[4]), - .I2(read_done), - .I3(\mem_probe_in[8]__0 [4]), - .O(dn_activity014_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[50]_i_1 - (.I0(data_int_sync2[50]), - .I1(data_int_sync1[50]), - .I2(read_done), - .I3(\mem_probe_in[11]__0 [2]), - .O(dn_activity0198_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[51]_i_1 - (.I0(data_int_sync2[51]), - .I1(data_int_sync1[51]), - .I2(read_done), - .I3(\mem_probe_in[11]__0 [3]), - .O(dn_activity0202_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[52]_i_1 - (.I0(data_int_sync2[52]), - .I1(data_int_sync1[52]), - .I2(read_done), - .I3(\mem_probe_in[11]__0 [4]), - .O(dn_activity0206_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[53]_i_1 - (.I0(data_int_sync2[53]), - .I1(data_int_sync1[53]), - .I2(read_done), - .I3(\mem_probe_in[11]__0 [5]), - .O(dn_activity0210_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[54]_i_1 - (.I0(data_int_sync2[54]), - .I1(data_int_sync1[54]), - .I2(read_done), - .I3(\mem_probe_in[11]__0 [6]), - .O(dn_activity0214_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[55]_i_1 - (.I0(data_int_sync2[55]), - .I1(data_int_sync1[55]), - .I2(read_done), - .I3(\mem_probe_in[11]__0 [7]), - .O(dn_activity0218_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[56]_i_1 - (.I0(data_int_sync2[56]), - .I1(data_int_sync1[56]), - .I2(read_done), - .I3(\mem_probe_in[11]__0 [8]), - .O(dn_activity0222_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[57]_i_1 - (.I0(data_int_sync2[57]), - .I1(data_int_sync1[57]), - .I2(read_done), - .I3(\mem_probe_in[11]__0 [9]), - .O(dn_activity0226_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[58]_i_1 - (.I0(data_int_sync2[58]), - .I1(data_int_sync1[58]), - .I2(read_done), - .I3(\mem_probe_in[11]__0 [10]), - .O(dn_activity0230_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[59]_i_1 - (.I0(data_int_sync2[59]), - .I1(data_int_sync1[59]), - .I2(read_done), - .I3(\mem_probe_in[11]__0 [11]), - .O(dn_activity0234_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[5]_i_1 - (.I0(data_int_sync2[5]), - .I1(data_int_sync1[5]), - .I2(read_done), - .I3(\mem_probe_in[8]__0 [5]), - .O(dn_activity018_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[60]_i_1 - (.I0(data_int_sync2[60]), - .I1(data_int_sync1[60]), - .I2(read_done), - .I3(\mem_probe_in[11]__0 [12]), - .O(dn_activity0238_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[61]_i_1 - (.I0(data_int_sync2[61]), - .I1(data_int_sync1[61]), - .I2(read_done), - .I3(\mem_probe_in[11]__0 [13]), - .O(dn_activity0242_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[62]_i_1 - (.I0(data_int_sync2[62]), - .I1(data_int_sync1[62]), - .I2(read_done), - .I3(\mem_probe_in[11]__0 [14]), - .O(dn_activity0246_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[63]_i_1 - (.I0(data_int_sync2[63]), - .I1(data_int_sync1[63]), - .I2(read_done), - .I3(\mem_probe_in[11]__0 [15]), - .O(dn_activity0250_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[6]_i_1 - (.I0(data_int_sync2[6]), - .I1(data_int_sync1[6]), - .I2(read_done), - .I3(\mem_probe_in[8]__0 [6]), - .O(dn_activity022_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[7]_i_1 - (.I0(data_int_sync2[7]), - .I1(data_int_sync1[7]), - .I2(read_done), - .I3(\mem_probe_in[8]__0 [7]), - .O(dn_activity026_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[8]_i_1 - (.I0(data_int_sync2[8]), - .I1(data_int_sync1[8]), - .I2(read_done), - .I3(\mem_probe_in[8]__0 [8]), - .O(dn_activity030_out)); - LUT4 #( - .INIT(16'h0F02)) - \dn_activity[9]_i_1 - (.I0(data_int_sync2[9]), - .I1(data_int_sync1[9]), - .I2(read_done), - .I3(\mem_probe_in[8]__0 [9]), - .O(dn_activity034_out)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[0] - (.C(CLK), - .CE(1'b1), - .D(dn_activity0), - .Q(\mem_probe_in[8]__0 [0]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[10] - (.C(CLK), - .CE(1'b1), - .D(dn_activity038_out), - .Q(\mem_probe_in[8]__0 [10]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[11] - (.C(CLK), - .CE(1'b1), - .D(dn_activity042_out), - .Q(\mem_probe_in[8]__0 [11]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[12] - (.C(CLK), - .CE(1'b1), - .D(dn_activity046_out), - .Q(\mem_probe_in[8]__0 [12]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[13] - (.C(CLK), - .CE(1'b1), - .D(dn_activity050_out), - .Q(\mem_probe_in[8]__0 [13]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[14] - (.C(CLK), - .CE(1'b1), - .D(dn_activity054_out), - .Q(\mem_probe_in[8]__0 [14]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[15] - (.C(CLK), - .CE(1'b1), - .D(dn_activity058_out), - .Q(\mem_probe_in[8]__0 [15]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[16] - (.C(CLK), - .CE(1'b1), - .D(dn_activity062_out), - .Q(\mem_probe_in[9]__0 [0]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[17] - (.C(CLK), - .CE(1'b1), - .D(dn_activity066_out), - .Q(\mem_probe_in[9]__0 [1]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[18] - (.C(CLK), - .CE(1'b1), - .D(dn_activity070_out), - .Q(\mem_probe_in[9]__0 [2]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[19] - (.C(CLK), - .CE(1'b1), - .D(dn_activity074_out), - .Q(\mem_probe_in[9]__0 [3]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[1] - (.C(CLK), - .CE(1'b1), - .D(dn_activity02_out), - .Q(\mem_probe_in[8]__0 [1]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[20] - (.C(CLK), - .CE(1'b1), - .D(dn_activity078_out), - .Q(\mem_probe_in[9]__0 [4]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[21] - (.C(CLK), - .CE(1'b1), - .D(dn_activity082_out), - .Q(\mem_probe_in[9]__0 [5]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[22] - (.C(CLK), - .CE(1'b1), - .D(dn_activity086_out), - .Q(\mem_probe_in[9]__0 [6]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[23] - (.C(CLK), - .CE(1'b1), - .D(dn_activity090_out), - .Q(\mem_probe_in[9]__0 [7]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[24] - (.C(CLK), - .CE(1'b1), - .D(dn_activity094_out), - .Q(\mem_probe_in[9]__0 [8]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[25] - (.C(CLK), - .CE(1'b1), - .D(dn_activity098_out), - .Q(\mem_probe_in[9]__0 [9]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[26] - (.C(CLK), - .CE(1'b1), - .D(dn_activity0102_out), - .Q(\mem_probe_in[9]__0 [10]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[27] - (.C(CLK), - .CE(1'b1), - .D(dn_activity0106_out), - .Q(\mem_probe_in[9]__0 [11]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[28] - (.C(CLK), - .CE(1'b1), - .D(dn_activity0110_out), - .Q(\mem_probe_in[9]__0 [12]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[29] - (.C(CLK), - .CE(1'b1), - .D(dn_activity0114_out), - .Q(\mem_probe_in[9]__0 [13]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[2] - (.C(CLK), - .CE(1'b1), - .D(dn_activity06_out), - .Q(\mem_probe_in[8]__0 [2]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[30] - (.C(CLK), - .CE(1'b1), - .D(dn_activity0118_out), - .Q(\mem_probe_in[9]__0 [14]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[31] - (.C(CLK), - .CE(1'b1), - .D(dn_activity0122_out), - .Q(\mem_probe_in[9]__0 [15]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[32] - (.C(CLK), - .CE(1'b1), - .D(dn_activity0126_out), - .Q(\mem_probe_in[10]__0 [0]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[33] - (.C(CLK), - .CE(1'b1), - .D(dn_activity0130_out), - .Q(\mem_probe_in[10]__0 [1]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[34] - (.C(CLK), - .CE(1'b1), - .D(dn_activity0134_out), - .Q(\mem_probe_in[10]__0 [2]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[35] - (.C(CLK), - .CE(1'b1), - .D(dn_activity0138_out), - .Q(\mem_probe_in[10]__0 [3]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[36] - (.C(CLK), - .CE(1'b1), - .D(dn_activity0142_out), - .Q(\mem_probe_in[10]__0 [4]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[37] - (.C(CLK), - .CE(1'b1), - .D(dn_activity0146_out), - .Q(\mem_probe_in[10]__0 [5]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[38] - (.C(CLK), - .CE(1'b1), - .D(dn_activity0150_out), - .Q(\mem_probe_in[10]__0 [6]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[39] - (.C(CLK), - .CE(1'b1), - .D(dn_activity0154_out), - .Q(\mem_probe_in[10]__0 [7]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[3] - (.C(CLK), - .CE(1'b1), - .D(dn_activity010_out), - .Q(\mem_probe_in[8]__0 [3]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[40] - (.C(CLK), - .CE(1'b1), - .D(dn_activity0158_out), - .Q(\mem_probe_in[10]__0 [8]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[41] - (.C(CLK), - .CE(1'b1), - .D(dn_activity0162_out), - .Q(\mem_probe_in[10]__0 [9]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[42] - (.C(CLK), - .CE(1'b1), - .D(dn_activity0166_out), - .Q(\mem_probe_in[10]__0 [10]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[43] - (.C(CLK), - .CE(1'b1), - .D(dn_activity0170_out), - .Q(\mem_probe_in[10]__0 [11]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[44] - (.C(CLK), - .CE(1'b1), - .D(dn_activity0174_out), - .Q(\mem_probe_in[10]__0 [12]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[45] - (.C(CLK), - .CE(1'b1), - .D(dn_activity0178_out), - .Q(\mem_probe_in[10]__0 [13]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[46] - (.C(CLK), - .CE(1'b1), - .D(dn_activity0182_out), - .Q(\mem_probe_in[10]__0 [14]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[47] - (.C(CLK), - .CE(1'b1), - .D(dn_activity0186_out), - .Q(\mem_probe_in[10]__0 [15]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[48] - (.C(CLK), - .CE(1'b1), - .D(dn_activity0190_out), - .Q(\mem_probe_in[11]__0 [0]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[49] - (.C(CLK), - .CE(1'b1), - .D(dn_activity0194_out), - .Q(\mem_probe_in[11]__0 [1]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[4] - (.C(CLK), - .CE(1'b1), - .D(dn_activity014_out), - .Q(\mem_probe_in[8]__0 [4]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[50] - (.C(CLK), - .CE(1'b1), - .D(dn_activity0198_out), - .Q(\mem_probe_in[11]__0 [2]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[51] - (.C(CLK), - .CE(1'b1), - .D(dn_activity0202_out), - .Q(\mem_probe_in[11]__0 [3]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[52] - (.C(CLK), - .CE(1'b1), - .D(dn_activity0206_out), - .Q(\mem_probe_in[11]__0 [4]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[53] - (.C(CLK), - .CE(1'b1), - .D(dn_activity0210_out), - .Q(\mem_probe_in[11]__0 [5]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[54] - (.C(CLK), - .CE(1'b1), - .D(dn_activity0214_out), - .Q(\mem_probe_in[11]__0 [6]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[55] - (.C(CLK), - .CE(1'b1), - .D(dn_activity0218_out), - .Q(\mem_probe_in[11]__0 [7]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[56] - (.C(CLK), - .CE(1'b1), - .D(dn_activity0222_out), - .Q(\mem_probe_in[11]__0 [8]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[57] - (.C(CLK), - .CE(1'b1), - .D(dn_activity0226_out), - .Q(\mem_probe_in[11]__0 [9]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[58] - (.C(CLK), - .CE(1'b1), - .D(dn_activity0230_out), - .Q(\mem_probe_in[11]__0 [10]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[59] - (.C(CLK), - .CE(1'b1), - .D(dn_activity0234_out), - .Q(\mem_probe_in[11]__0 [11]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[5] - (.C(CLK), - .CE(1'b1), - .D(dn_activity018_out), - .Q(\mem_probe_in[8]__0 [5]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[60] - (.C(CLK), - .CE(1'b1), - .D(dn_activity0238_out), - .Q(\mem_probe_in[11]__0 [12]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[61] - (.C(CLK), - .CE(1'b1), - .D(dn_activity0242_out), - .Q(\mem_probe_in[11]__0 [13]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[62] - (.C(CLK), - .CE(1'b1), - .D(dn_activity0246_out), - .Q(\mem_probe_in[11]__0 [14]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[63] - (.C(CLK), - .CE(1'b1), - .D(dn_activity0250_out), - .Q(\mem_probe_in[11]__0 [15]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[6] - (.C(CLK), - .CE(1'b1), - .D(dn_activity022_out), - .Q(\mem_probe_in[8]__0 [6]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[7] - (.C(CLK), - .CE(1'b1), - .D(dn_activity026_out), - .Q(\mem_probe_in[8]__0 [7]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[8] - (.C(CLK), - .CE(1'b1), - .D(dn_activity030_out), - .Q(\mem_probe_in[8]__0 [8]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \dn_activity_reg[9] - (.C(CLK), - .CE(1'b1), - .D(dn_activity034_out), - .Q(\mem_probe_in[8]__0 [9]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[0] - (.C(clk), - .CE(E), - .D(D[0]), - .Q(probe_in_reg[0]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[10] - (.C(clk), - .CE(E), - .D(D[10]), - .Q(probe_in_reg[10]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[11] - (.C(clk), - .CE(E), - .D(D[11]), - .Q(probe_in_reg[11]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[12] - (.C(clk), - .CE(E), - .D(D[12]), - .Q(probe_in_reg[12]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[13] - (.C(clk), - .CE(E), - .D(D[13]), - .Q(probe_in_reg[13]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[14] - (.C(clk), - .CE(E), - .D(D[14]), - .Q(probe_in_reg[14]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[15] - (.C(clk), - .CE(E), - .D(D[15]), - .Q(probe_in_reg[15]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[16] - (.C(clk), - .CE(E), - .D(D[16]), - .Q(probe_in_reg[16]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[17] - (.C(clk), - .CE(E), - .D(D[17]), - .Q(probe_in_reg[17]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[18] - (.C(clk), - .CE(E), - .D(D[18]), - .Q(probe_in_reg[18]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[19] - (.C(clk), - .CE(E), - .D(D[19]), - .Q(probe_in_reg[19]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[1] - (.C(clk), - .CE(E), - .D(D[1]), - .Q(probe_in_reg[1]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[20] - (.C(clk), - .CE(E), - .D(D[20]), - .Q(probe_in_reg[20]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[21] - (.C(clk), - .CE(E), - .D(D[21]), - .Q(probe_in_reg[21]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[22] - (.C(clk), - .CE(E), - .D(D[22]), - .Q(probe_in_reg[22]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[23] - (.C(clk), - .CE(E), - .D(D[23]), - .Q(probe_in_reg[23]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[24] - (.C(clk), - .CE(E), - .D(D[24]), - .Q(probe_in_reg[24]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[25] - (.C(clk), - .CE(E), - .D(D[25]), - .Q(probe_in_reg[25]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[26] - (.C(clk), - .CE(E), - .D(D[26]), - .Q(probe_in_reg[26]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[27] - (.C(clk), - .CE(E), - .D(D[27]), - .Q(probe_in_reg[27]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[28] - (.C(clk), - .CE(E), - .D(D[28]), - .Q(probe_in_reg[28]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[29] - (.C(clk), - .CE(E), - .D(D[29]), - .Q(probe_in_reg[29]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[2] - (.C(clk), - .CE(E), - .D(D[2]), - .Q(probe_in_reg[2]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[30] - (.C(clk), - .CE(E), - .D(D[30]), - .Q(probe_in_reg[30]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[31] - (.C(clk), - .CE(E), - .D(D[31]), - .Q(probe_in_reg[31]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[32] - (.C(clk), - .CE(E), - .D(D[32]), - .Q(probe_in_reg[32]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[33] - (.C(clk), - .CE(E), - .D(D[33]), - .Q(probe_in_reg[33]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[34] - (.C(clk), - .CE(E), - .D(D[34]), - .Q(probe_in_reg[34]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[35] - (.C(clk), - .CE(E), - .D(D[35]), - .Q(probe_in_reg[35]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[36] - (.C(clk), - .CE(E), - .D(D[36]), - .Q(probe_in_reg[36]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[37] - (.C(clk), - .CE(E), - .D(D[37]), - .Q(probe_in_reg[37]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[38] - (.C(clk), - .CE(E), - .D(D[38]), - .Q(probe_in_reg[38]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[39] - (.C(clk), - .CE(E), - .D(D[39]), - .Q(probe_in_reg[39]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[3] - (.C(clk), - .CE(E), - .D(D[3]), - .Q(probe_in_reg[3]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[40] - (.C(clk), - .CE(E), - .D(D[40]), - .Q(probe_in_reg[40]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[41] - (.C(clk), - .CE(E), - .D(D[41]), - .Q(probe_in_reg[41]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[42] - (.C(clk), - .CE(E), - .D(D[42]), - .Q(probe_in_reg[42]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[43] - (.C(clk), - .CE(E), - .D(D[43]), - .Q(probe_in_reg[43]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[44] - (.C(clk), - .CE(E), - .D(D[44]), - .Q(probe_in_reg[44]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[45] - (.C(clk), - .CE(E), - .D(D[45]), - .Q(probe_in_reg[45]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[46] - (.C(clk), - .CE(E), - .D(D[46]), - .Q(probe_in_reg[46]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[47] - (.C(clk), - .CE(E), - .D(D[47]), - .Q(probe_in_reg[47]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[48] - (.C(clk), - .CE(E), - .D(D[48]), - .Q(probe_in_reg[48]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[49] - (.C(clk), - .CE(E), - .D(D[49]), - .Q(probe_in_reg[49]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[4] - (.C(clk), - .CE(E), - .D(D[4]), - .Q(probe_in_reg[4]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[50] - (.C(clk), - .CE(E), - .D(D[50]), - .Q(probe_in_reg[50]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[51] - (.C(clk), - .CE(E), - .D(D[51]), - .Q(probe_in_reg[51]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[52] - (.C(clk), - .CE(E), - .D(D[52]), - .Q(probe_in_reg[52]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[53] - (.C(clk), - .CE(E), - .D(D[53]), - .Q(probe_in_reg[53]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[54] - (.C(clk), - .CE(E), - .D(D[54]), - .Q(probe_in_reg[54]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[55] - (.C(clk), - .CE(E), - .D(D[55]), - .Q(probe_in_reg[55]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[56] - (.C(clk), - .CE(E), - .D(D[56]), - .Q(probe_in_reg[56]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[57] - (.C(clk), - .CE(E), - .D(D[57]), - .Q(probe_in_reg[57]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[58] - (.C(clk), - .CE(E), - .D(D[58]), - .Q(probe_in_reg[58]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[59] - (.C(clk), - .CE(E), - .D(D[59]), - .Q(probe_in_reg[59]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[5] - (.C(clk), - .CE(E), - .D(D[5]), - .Q(probe_in_reg[5]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[60] - (.C(clk), - .CE(E), - .D(D[60]), - .Q(probe_in_reg[60]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[61] - (.C(clk), - .CE(E), - .D(D[61]), - .Q(probe_in_reg[61]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[62] - (.C(clk), - .CE(E), - .D(D[62]), - .Q(probe_in_reg[62]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[63] - (.C(clk), - .CE(E), - .D(D[63]), - .Q(probe_in_reg[63]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[6] - (.C(clk), - .CE(E), - .D(D[6]), - .Q(probe_in_reg[6]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[7] - (.C(clk), - .CE(E), - .D(D[7]), - .Q(probe_in_reg[7]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[8] - (.C(clk), - .CE(E), - .D(D[8]), - .Q(probe_in_reg[8]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \probe_in_reg_reg[9] - (.C(clk), - .CE(E), - .D(D[9]), - .Q(probe_in_reg[9]), - .R(1'b0)); - LUT2 #( - .INIT(4'h2)) - rd_en_p1_i_1 - (.I0(s_den_o), - .I1(s_dwe_o), - .O(xsdb_rd)); - LUT6 #( - .INIT(64'h0020000000000000)) - read_done_i_1 - (.I0(addr_count[3]), - .I1(addr_count[4]), - .I2(Read_int), - .I3(addr_count[2]), - .I4(addr_count[0]), - .I5(addr_count[1]), - .O(addr_count_reg1)); - (* RTL_MAX_FANOUT = "found" *) - FDRE read_done_reg - (.C(CLK), - .CE(1'b1), - .D(addr_count_reg1), - .Q(read_done), - .R(1'b0)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[0]_i_1 - (.I0(data_int_sync1[0]), - .I1(data_int_sync2[0]), - .I2(read_done), - .I3(\mem_probe_in[4]__0 [0]), - .O(up_activity0)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[10]_i_1 - (.I0(data_int_sync1[10]), - .I1(data_int_sync2[10]), - .I2(read_done), - .I3(\mem_probe_in[4]__0 [10]), - .O(up_activity0292_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[11]_i_1 - (.I0(data_int_sync1[11]), - .I1(data_int_sync2[11]), - .I2(read_done), - .I3(\mem_probe_in[4]__0 [11]), - .O(up_activity0296_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[12]_i_1 - (.I0(data_int_sync1[12]), - .I1(data_int_sync2[12]), - .I2(read_done), - .I3(\mem_probe_in[4]__0 [12]), - .O(up_activity0300_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[13]_i_1 - (.I0(data_int_sync1[13]), - .I1(data_int_sync2[13]), - .I2(read_done), - .I3(\mem_probe_in[4]__0 [13]), - .O(up_activity0304_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[14]_i_1 - (.I0(data_int_sync1[14]), - .I1(data_int_sync2[14]), - .I2(read_done), - .I3(\mem_probe_in[4]__0 [14]), - .O(up_activity0308_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[15]_i_1 - (.I0(data_int_sync1[15]), - .I1(data_int_sync2[15]), - .I2(read_done), - .I3(\mem_probe_in[4]__0 [15]), - .O(up_activity0312_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[16]_i_1 - (.I0(data_int_sync1[16]), - .I1(data_int_sync2[16]), - .I2(read_done), - .I3(\mem_probe_in[5]__0 [0]), - .O(up_activity0316_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[17]_i_1 - (.I0(data_int_sync1[17]), - .I1(data_int_sync2[17]), - .I2(read_done), - .I3(\mem_probe_in[5]__0 [1]), - .O(up_activity0320_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[18]_i_1 - (.I0(data_int_sync1[18]), - .I1(data_int_sync2[18]), - .I2(read_done), - .I3(\mem_probe_in[5]__0 [2]), - .O(up_activity0324_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[19]_i_1 - (.I0(data_int_sync1[19]), - .I1(data_int_sync2[19]), - .I2(read_done), - .I3(\mem_probe_in[5]__0 [3]), - .O(up_activity0328_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[1]_i_1 - (.I0(data_int_sync1[1]), - .I1(data_int_sync2[1]), - .I2(read_done), - .I3(\mem_probe_in[4]__0 [1]), - .O(up_activity0256_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[20]_i_1 - (.I0(data_int_sync1[20]), - .I1(data_int_sync2[20]), - .I2(read_done), - .I3(\mem_probe_in[5]__0 [4]), - .O(up_activity0332_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[21]_i_1 - (.I0(data_int_sync1[21]), - .I1(data_int_sync2[21]), - .I2(read_done), - .I3(\mem_probe_in[5]__0 [5]), - .O(up_activity0336_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[22]_i_1 - (.I0(data_int_sync1[22]), - .I1(data_int_sync2[22]), - .I2(read_done), - .I3(\mem_probe_in[5]__0 [6]), - .O(up_activity0340_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[23]_i_1 - (.I0(data_int_sync1[23]), - .I1(data_int_sync2[23]), - .I2(read_done), - .I3(\mem_probe_in[5]__0 [7]), - .O(up_activity0344_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[24]_i_1 - (.I0(data_int_sync1[24]), - .I1(data_int_sync2[24]), - .I2(read_done), - .I3(\mem_probe_in[5]__0 [8]), - .O(up_activity0348_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[25]_i_1 - (.I0(data_int_sync1[25]), - .I1(data_int_sync2[25]), - .I2(read_done), - .I3(\mem_probe_in[5]__0 [9]), - .O(up_activity0352_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[26]_i_1 - (.I0(data_int_sync1[26]), - .I1(data_int_sync2[26]), - .I2(read_done), - .I3(\mem_probe_in[5]__0 [10]), - .O(up_activity0356_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[27]_i_1 - (.I0(data_int_sync1[27]), - .I1(data_int_sync2[27]), - .I2(read_done), - .I3(\mem_probe_in[5]__0 [11]), - .O(up_activity0360_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[28]_i_1 - (.I0(data_int_sync1[28]), - .I1(data_int_sync2[28]), - .I2(read_done), - .I3(\mem_probe_in[5]__0 [12]), - .O(up_activity0364_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[29]_i_1 - (.I0(data_int_sync1[29]), - .I1(data_int_sync2[29]), - .I2(read_done), - .I3(\mem_probe_in[5]__0 [13]), - .O(up_activity0368_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[2]_i_1 - (.I0(data_int_sync1[2]), - .I1(data_int_sync2[2]), - .I2(read_done), - .I3(\mem_probe_in[4]__0 [2]), - .O(up_activity0260_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[30]_i_1 - (.I0(data_int_sync1[30]), - .I1(data_int_sync2[30]), - .I2(read_done), - .I3(\mem_probe_in[5]__0 [14]), - .O(up_activity0372_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[31]_i_1 - (.I0(data_int_sync1[31]), - .I1(data_int_sync2[31]), - .I2(read_done), - .I3(\mem_probe_in[5]__0 [15]), - .O(up_activity0376_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[32]_i_1 - (.I0(data_int_sync1[32]), - .I1(data_int_sync2[32]), - .I2(read_done), - .I3(\mem_probe_in[6]__0 [0]), - .O(up_activity0380_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[33]_i_1 - (.I0(data_int_sync1[33]), - .I1(data_int_sync2[33]), - .I2(read_done), - .I3(\mem_probe_in[6]__0 [1]), - .O(up_activity0384_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[34]_i_1 - (.I0(data_int_sync1[34]), - .I1(data_int_sync2[34]), - .I2(read_done), - .I3(\mem_probe_in[6]__0 [2]), - .O(up_activity0388_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[35]_i_1 - (.I0(data_int_sync1[35]), - .I1(data_int_sync2[35]), - .I2(read_done), - .I3(\mem_probe_in[6]__0 [3]), - .O(up_activity0392_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[36]_i_1 - (.I0(data_int_sync1[36]), - .I1(data_int_sync2[36]), - .I2(read_done), - .I3(\mem_probe_in[6]__0 [4]), - .O(up_activity0396_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[37]_i_1 - (.I0(data_int_sync1[37]), - .I1(data_int_sync2[37]), - .I2(read_done), - .I3(\mem_probe_in[6]__0 [5]), - .O(up_activity0400_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[38]_i_1 - (.I0(data_int_sync1[38]), - .I1(data_int_sync2[38]), - .I2(read_done), - .I3(\mem_probe_in[6]__0 [6]), - .O(up_activity0404_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[39]_i_1 - (.I0(data_int_sync1[39]), - .I1(data_int_sync2[39]), - .I2(read_done), - .I3(\mem_probe_in[6]__0 [7]), - .O(up_activity0408_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[3]_i_1 - (.I0(data_int_sync1[3]), - .I1(data_int_sync2[3]), - .I2(read_done), - .I3(\mem_probe_in[4]__0 [3]), - .O(up_activity0264_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[40]_i_1 - (.I0(data_int_sync1[40]), - .I1(data_int_sync2[40]), - .I2(read_done), - .I3(\mem_probe_in[6]__0 [8]), - .O(up_activity0412_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[41]_i_1 - (.I0(data_int_sync1[41]), - .I1(data_int_sync2[41]), - .I2(read_done), - .I3(\mem_probe_in[6]__0 [9]), - .O(up_activity0416_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[42]_i_1 - (.I0(data_int_sync1[42]), - .I1(data_int_sync2[42]), - .I2(read_done), - .I3(\mem_probe_in[6]__0 [10]), - .O(up_activity0420_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[43]_i_1 - (.I0(data_int_sync1[43]), - .I1(data_int_sync2[43]), - .I2(read_done), - .I3(\mem_probe_in[6]__0 [11]), - .O(up_activity0424_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[44]_i_1 - (.I0(data_int_sync1[44]), - .I1(data_int_sync2[44]), - .I2(read_done), - .I3(\mem_probe_in[6]__0 [12]), - .O(up_activity0428_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[45]_i_1 - (.I0(data_int_sync1[45]), - .I1(data_int_sync2[45]), - .I2(read_done), - .I3(\mem_probe_in[6]__0 [13]), - .O(up_activity0432_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[46]_i_1 - (.I0(data_int_sync1[46]), - .I1(data_int_sync2[46]), - .I2(read_done), - .I3(\mem_probe_in[6]__0 [14]), - .O(up_activity0436_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[47]_i_1 - (.I0(data_int_sync1[47]), - .I1(data_int_sync2[47]), - .I2(read_done), - .I3(\mem_probe_in[6]__0 [15]), - .O(up_activity0440_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[48]_i_1 - (.I0(data_int_sync1[48]), - .I1(data_int_sync2[48]), - .I2(read_done), - .I3(\mem_probe_in[7]__0 [0]), - .O(up_activity0444_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[49]_i_1 - (.I0(data_int_sync1[49]), - .I1(data_int_sync2[49]), - .I2(read_done), - .I3(\mem_probe_in[7]__0 [1]), - .O(up_activity0448_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[4]_i_1 - (.I0(data_int_sync1[4]), - .I1(data_int_sync2[4]), - .I2(read_done), - .I3(\mem_probe_in[4]__0 [4]), - .O(up_activity0268_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[50]_i_1 - (.I0(data_int_sync1[50]), - .I1(data_int_sync2[50]), - .I2(read_done), - .I3(\mem_probe_in[7]__0 [2]), - .O(up_activity0452_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[51]_i_1 - (.I0(data_int_sync1[51]), - .I1(data_int_sync2[51]), - .I2(read_done), - .I3(\mem_probe_in[7]__0 [3]), - .O(up_activity0456_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[52]_i_1 - (.I0(data_int_sync1[52]), - .I1(data_int_sync2[52]), - .I2(read_done), - .I3(\mem_probe_in[7]__0 [4]), - .O(up_activity0460_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[53]_i_1 - (.I0(data_int_sync1[53]), - .I1(data_int_sync2[53]), - .I2(read_done), - .I3(\mem_probe_in[7]__0 [5]), - .O(up_activity0464_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[54]_i_1 - (.I0(data_int_sync1[54]), - .I1(data_int_sync2[54]), - .I2(read_done), - .I3(\mem_probe_in[7]__0 [6]), - .O(up_activity0468_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[55]_i_1 - (.I0(data_int_sync1[55]), - .I1(data_int_sync2[55]), - .I2(read_done), - .I3(\mem_probe_in[7]__0 [7]), - .O(up_activity0472_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[56]_i_1 - (.I0(data_int_sync1[56]), - .I1(data_int_sync2[56]), - .I2(read_done), - .I3(\mem_probe_in[7]__0 [8]), - .O(up_activity0476_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[57]_i_1 - (.I0(data_int_sync1[57]), - .I1(data_int_sync2[57]), - .I2(read_done), - .I3(\mem_probe_in[7]__0 [9]), - .O(up_activity0480_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[58]_i_1 - (.I0(data_int_sync1[58]), - .I1(data_int_sync2[58]), - .I2(read_done), - .I3(\mem_probe_in[7]__0 [10]), - .O(up_activity0484_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[59]_i_1 - (.I0(data_int_sync1[59]), - .I1(data_int_sync2[59]), - .I2(read_done), - .I3(\mem_probe_in[7]__0 [11]), - .O(up_activity0488_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[5]_i_1 - (.I0(data_int_sync1[5]), - .I1(data_int_sync2[5]), - .I2(read_done), - .I3(\mem_probe_in[4]__0 [5]), - .O(up_activity0272_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[60]_i_1 - (.I0(data_int_sync1[60]), - .I1(data_int_sync2[60]), - .I2(read_done), - .I3(\mem_probe_in[7]__0 [12]), - .O(up_activity0492_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[61]_i_1 - (.I0(data_int_sync1[61]), - .I1(data_int_sync2[61]), - .I2(read_done), - .I3(\mem_probe_in[7]__0 [13]), - .O(up_activity0496_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[62]_i_1 - (.I0(data_int_sync1[62]), - .I1(data_int_sync2[62]), - .I2(read_done), - .I3(\mem_probe_in[7]__0 [14]), - .O(up_activity0500_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[63]_i_1 - (.I0(data_int_sync1[63]), - .I1(data_int_sync2[63]), - .I2(read_done), - .I3(\mem_probe_in[7]__0 [15]), - .O(up_activity0504_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[6]_i_1 - (.I0(data_int_sync1[6]), - .I1(data_int_sync2[6]), - .I2(read_done), - .I3(\mem_probe_in[4]__0 [6]), - .O(up_activity0276_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[7]_i_1 - (.I0(data_int_sync1[7]), - .I1(data_int_sync2[7]), - .I2(read_done), - .I3(\mem_probe_in[4]__0 [7]), - .O(up_activity0280_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[8]_i_1 - (.I0(data_int_sync1[8]), - .I1(data_int_sync2[8]), - .I2(read_done), - .I3(\mem_probe_in[4]__0 [8]), - .O(up_activity0284_out)); - LUT4 #( - .INIT(16'h0F02)) - \up_activity[9]_i_1 - (.I0(data_int_sync1[9]), - .I1(data_int_sync2[9]), - .I2(read_done), - .I3(\mem_probe_in[4]__0 [9]), - .O(up_activity0288_out)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[0] - (.C(CLK), - .CE(1'b1), - .D(up_activity0), - .Q(\mem_probe_in[4]__0 [0]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[10] - (.C(CLK), - .CE(1'b1), - .D(up_activity0292_out), - .Q(\mem_probe_in[4]__0 [10]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[11] - (.C(CLK), - .CE(1'b1), - .D(up_activity0296_out), - .Q(\mem_probe_in[4]__0 [11]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[12] - (.C(CLK), - .CE(1'b1), - .D(up_activity0300_out), - .Q(\mem_probe_in[4]__0 [12]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[13] - (.C(CLK), - .CE(1'b1), - .D(up_activity0304_out), - .Q(\mem_probe_in[4]__0 [13]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[14] - (.C(CLK), - .CE(1'b1), - .D(up_activity0308_out), - .Q(\mem_probe_in[4]__0 [14]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[15] - (.C(CLK), - .CE(1'b1), - .D(up_activity0312_out), - .Q(\mem_probe_in[4]__0 [15]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[16] - (.C(CLK), - .CE(1'b1), - .D(up_activity0316_out), - .Q(\mem_probe_in[5]__0 [0]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[17] - (.C(CLK), - .CE(1'b1), - .D(up_activity0320_out), - .Q(\mem_probe_in[5]__0 [1]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[18] - (.C(CLK), - .CE(1'b1), - .D(up_activity0324_out), - .Q(\mem_probe_in[5]__0 [2]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[19] - (.C(CLK), - .CE(1'b1), - .D(up_activity0328_out), - .Q(\mem_probe_in[5]__0 [3]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[1] - (.C(CLK), - .CE(1'b1), - .D(up_activity0256_out), - .Q(\mem_probe_in[4]__0 [1]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[20] - (.C(CLK), - .CE(1'b1), - .D(up_activity0332_out), - .Q(\mem_probe_in[5]__0 [4]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[21] - (.C(CLK), - .CE(1'b1), - .D(up_activity0336_out), - .Q(\mem_probe_in[5]__0 [5]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[22] - (.C(CLK), - .CE(1'b1), - .D(up_activity0340_out), - .Q(\mem_probe_in[5]__0 [6]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[23] - (.C(CLK), - .CE(1'b1), - .D(up_activity0344_out), - .Q(\mem_probe_in[5]__0 [7]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[24] - (.C(CLK), - .CE(1'b1), - .D(up_activity0348_out), - .Q(\mem_probe_in[5]__0 [8]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[25] - (.C(CLK), - .CE(1'b1), - .D(up_activity0352_out), - .Q(\mem_probe_in[5]__0 [9]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[26] - (.C(CLK), - .CE(1'b1), - .D(up_activity0356_out), - .Q(\mem_probe_in[5]__0 [10]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[27] - (.C(CLK), - .CE(1'b1), - .D(up_activity0360_out), - .Q(\mem_probe_in[5]__0 [11]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[28] - (.C(CLK), - .CE(1'b1), - .D(up_activity0364_out), - .Q(\mem_probe_in[5]__0 [12]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[29] - (.C(CLK), - .CE(1'b1), - .D(up_activity0368_out), - .Q(\mem_probe_in[5]__0 [13]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[2] - (.C(CLK), - .CE(1'b1), - .D(up_activity0260_out), - .Q(\mem_probe_in[4]__0 [2]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[30] - (.C(CLK), - .CE(1'b1), - .D(up_activity0372_out), - .Q(\mem_probe_in[5]__0 [14]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[31] - (.C(CLK), - .CE(1'b1), - .D(up_activity0376_out), - .Q(\mem_probe_in[5]__0 [15]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[32] - (.C(CLK), - .CE(1'b1), - .D(up_activity0380_out), - .Q(\mem_probe_in[6]__0 [0]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[33] - (.C(CLK), - .CE(1'b1), - .D(up_activity0384_out), - .Q(\mem_probe_in[6]__0 [1]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[34] - (.C(CLK), - .CE(1'b1), - .D(up_activity0388_out), - .Q(\mem_probe_in[6]__0 [2]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[35] - (.C(CLK), - .CE(1'b1), - .D(up_activity0392_out), - .Q(\mem_probe_in[6]__0 [3]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[36] - (.C(CLK), - .CE(1'b1), - .D(up_activity0396_out), - .Q(\mem_probe_in[6]__0 [4]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[37] - (.C(CLK), - .CE(1'b1), - .D(up_activity0400_out), - .Q(\mem_probe_in[6]__0 [5]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[38] - (.C(CLK), - .CE(1'b1), - .D(up_activity0404_out), - .Q(\mem_probe_in[6]__0 [6]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[39] - (.C(CLK), - .CE(1'b1), - .D(up_activity0408_out), - .Q(\mem_probe_in[6]__0 [7]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[3] - (.C(CLK), - .CE(1'b1), - .D(up_activity0264_out), - .Q(\mem_probe_in[4]__0 [3]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[40] - (.C(CLK), - .CE(1'b1), - .D(up_activity0412_out), - .Q(\mem_probe_in[6]__0 [8]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[41] - (.C(CLK), - .CE(1'b1), - .D(up_activity0416_out), - .Q(\mem_probe_in[6]__0 [9]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[42] - (.C(CLK), - .CE(1'b1), - .D(up_activity0420_out), - .Q(\mem_probe_in[6]__0 [10]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[43] - (.C(CLK), - .CE(1'b1), - .D(up_activity0424_out), - .Q(\mem_probe_in[6]__0 [11]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[44] - (.C(CLK), - .CE(1'b1), - .D(up_activity0428_out), - .Q(\mem_probe_in[6]__0 [12]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[45] - (.C(CLK), - .CE(1'b1), - .D(up_activity0432_out), - .Q(\mem_probe_in[6]__0 [13]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[46] - (.C(CLK), - .CE(1'b1), - .D(up_activity0436_out), - .Q(\mem_probe_in[6]__0 [14]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[47] - (.C(CLK), - .CE(1'b1), - .D(up_activity0440_out), - .Q(\mem_probe_in[6]__0 [15]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[48] - (.C(CLK), - .CE(1'b1), - .D(up_activity0444_out), - .Q(\mem_probe_in[7]__0 [0]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[49] - (.C(CLK), - .CE(1'b1), - .D(up_activity0448_out), - .Q(\mem_probe_in[7]__0 [1]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[4] - (.C(CLK), - .CE(1'b1), - .D(up_activity0268_out), - .Q(\mem_probe_in[4]__0 [4]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[50] - (.C(CLK), - .CE(1'b1), - .D(up_activity0452_out), - .Q(\mem_probe_in[7]__0 [2]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[51] - (.C(CLK), - .CE(1'b1), - .D(up_activity0456_out), - .Q(\mem_probe_in[7]__0 [3]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[52] - (.C(CLK), - .CE(1'b1), - .D(up_activity0460_out), - .Q(\mem_probe_in[7]__0 [4]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[53] - (.C(CLK), - .CE(1'b1), - .D(up_activity0464_out), - .Q(\mem_probe_in[7]__0 [5]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[54] - (.C(CLK), - .CE(1'b1), - .D(up_activity0468_out), - .Q(\mem_probe_in[7]__0 [6]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[55] - (.C(CLK), - .CE(1'b1), - .D(up_activity0472_out), - .Q(\mem_probe_in[7]__0 [7]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[56] - (.C(CLK), - .CE(1'b1), - .D(up_activity0476_out), - .Q(\mem_probe_in[7]__0 [8]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[57] - (.C(CLK), - .CE(1'b1), - .D(up_activity0480_out), - .Q(\mem_probe_in[7]__0 [9]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[58] - (.C(CLK), - .CE(1'b1), - .D(up_activity0484_out), - .Q(\mem_probe_in[7]__0 [10]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[59] - (.C(CLK), - .CE(1'b1), - .D(up_activity0488_out), - .Q(\mem_probe_in[7]__0 [11]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[5] - (.C(CLK), - .CE(1'b1), - .D(up_activity0272_out), - .Q(\mem_probe_in[4]__0 [5]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[60] - (.C(CLK), - .CE(1'b1), - .D(up_activity0492_out), - .Q(\mem_probe_in[7]__0 [12]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[61] - (.C(CLK), - .CE(1'b1), - .D(up_activity0496_out), - .Q(\mem_probe_in[7]__0 [13]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[62] - (.C(CLK), - .CE(1'b1), - .D(up_activity0500_out), - .Q(\mem_probe_in[7]__0 [14]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[63] - (.C(CLK), - .CE(1'b1), - .D(up_activity0504_out), - .Q(\mem_probe_in[7]__0 [15]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[6] - (.C(CLK), - .CE(1'b1), - .D(up_activity0276_out), - .Q(\mem_probe_in[4]__0 [6]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[7] - (.C(CLK), - .CE(1'b1), - .D(up_activity0280_out), - .Q(\mem_probe_in[4]__0 [7]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[8] - (.C(CLK), - .CE(1'b1), - .D(up_activity0284_out), - .Q(\mem_probe_in[4]__0 [8]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \up_activity_reg[9] - (.C(CLK), - .CE(1'b1), - .D(up_activity0288_out), - .Q(\mem_probe_in[4]__0 [9]), - .R(1'b0)); -endmodule - -(* ORIG_REF_NAME = "vio_v3_0_19_probe_out_all" *) -module vio_0_vio_v3_0_19_probe_out_all - (probe_out0, - \Probe_out_reg_int_reg[15]_0 , - SR, - in0, - clk, - CLK, - s_daddr_o, - \G_PROBE_OUT[0].wr_probe_out_reg[0]_0 , - s_den_o, - s_dwe_o, - \G_PROBE_OUT[0].wr_probe_out_reg[0]_1 , - xsdb_wr__0, - \G_PROBE_OUT[0].wr_probe_out_reg[0]_2 , - internal_cnt_rst, - Q); - output [31:0]probe_out0; - output [15:0]\Probe_out_reg_int_reg[15]_0 ; - input [0:0]SR; - input in0; - input clk; - input CLK; - input [10:0]s_daddr_o; - input \G_PROBE_OUT[0].wr_probe_out_reg[0]_0 ; - input s_den_o; - input s_dwe_o; - input \G_PROBE_OUT[0].wr_probe_out_reg[0]_1 ; - input xsdb_wr__0; - input \G_PROBE_OUT[0].wr_probe_out_reg[0]_2 ; - input internal_cnt_rst; - input [15:0]Q; - - wire [15:0]Bus_Data_out_int; - wire CLK; - (* async_reg = "true" *) wire Committ_1; - (* async_reg = "true" *) wire Committ_2; - wire \G_PROBE_OUT[0].wr_probe_out[0]_i_1_n_0 ; - wire \G_PROBE_OUT[0].wr_probe_out_reg[0]_0 ; - wire \G_PROBE_OUT[0].wr_probe_out_reg[0]_1 ; - wire \G_PROBE_OUT[0].wr_probe_out_reg[0]_2 ; - wire [15:0]\Probe_out_reg_int_reg[15]_0 ; - wire [15:0]Q; - wire [0:0]SR; - wire clk; - wire in0; - wire internal_cnt_rst; - wire [31:0]probe_out0; - wire [10:0]s_daddr_o; - wire s_den_o; - wire s_dwe_o; - wire wr_probe_out; - wire xsdb_wr__0; - - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE Committ_1_reg - (.C(clk), - .CE(1'b1), - .D(in0), - .Q(Committ_1), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE Committ_2_reg - (.C(clk), - .CE(1'b1), - .D(Committ_1), - .Q(Committ_2), - .R(1'b0)); - vio_0_vio_v3_0_19_probe_out_one \G_PROBE_OUT[0].PROBE_OUT0_INST - (.\Bus_Data_out_int_reg[15]_0 (Bus_Data_out_int), - .CLK(CLK), - .E(wr_probe_out), - .\Probe_out_reg[31]_0 (Committ_2), - .Q(Q), - .SR(SR), - .\addr_count_reg[0]_0 (\G_PROBE_OUT[0].wr_probe_out_reg[0]_0 ), - .clk(clk), - .internal_cnt_rst(internal_cnt_rst), - .probe_out0(probe_out0), - .s_daddr_o(s_daddr_o), - .s_den_o(s_den_o), - .s_dwe_o(s_dwe_o)); - LUT6 #( - .INIT(64'h0000004000000000)) - \G_PROBE_OUT[0].wr_probe_out[0]_i_1 - (.I0(\G_PROBE_OUT[0].wr_probe_out_reg[0]_1 ), - .I1(xsdb_wr__0), - .I2(s_daddr_o[3]), - .I3(s_daddr_o[0]), - .I4(\G_PROBE_OUT[0].wr_probe_out_reg[0]_2 ), - .I5(\G_PROBE_OUT[0].wr_probe_out_reg[0]_0 ), - .O(\G_PROBE_OUT[0].wr_probe_out[0]_i_1_n_0 )); - FDRE \G_PROBE_OUT[0].wr_probe_out_reg[0] - (.C(CLK), - .CE(1'b1), - .D(\G_PROBE_OUT[0].wr_probe_out[0]_i_1_n_0 ), - .Q(wr_probe_out), - .R(1'b0)); - FDRE \Probe_out_reg_int_reg[0] - (.C(CLK), - .CE(1'b1), - .D(Bus_Data_out_int[0]), - .Q(\Probe_out_reg_int_reg[15]_0 [0]), - .R(1'b0)); - FDRE \Probe_out_reg_int_reg[10] - (.C(CLK), - .CE(1'b1), - .D(Bus_Data_out_int[10]), - .Q(\Probe_out_reg_int_reg[15]_0 [10]), - .R(1'b0)); - FDRE \Probe_out_reg_int_reg[11] - (.C(CLK), - .CE(1'b1), - .D(Bus_Data_out_int[11]), - .Q(\Probe_out_reg_int_reg[15]_0 [11]), - .R(1'b0)); - FDRE \Probe_out_reg_int_reg[12] - (.C(CLK), - .CE(1'b1), - .D(Bus_Data_out_int[12]), - .Q(\Probe_out_reg_int_reg[15]_0 [12]), - .R(1'b0)); - FDRE \Probe_out_reg_int_reg[13] - (.C(CLK), - .CE(1'b1), - .D(Bus_Data_out_int[13]), - .Q(\Probe_out_reg_int_reg[15]_0 [13]), - .R(1'b0)); - FDRE \Probe_out_reg_int_reg[14] - (.C(CLK), - .CE(1'b1), - .D(Bus_Data_out_int[14]), - .Q(\Probe_out_reg_int_reg[15]_0 [14]), - .R(1'b0)); - FDRE \Probe_out_reg_int_reg[15] - (.C(CLK), - .CE(1'b1), - .D(Bus_Data_out_int[15]), - .Q(\Probe_out_reg_int_reg[15]_0 [15]), - .R(1'b0)); - FDRE \Probe_out_reg_int_reg[1] - (.C(CLK), - .CE(1'b1), - .D(Bus_Data_out_int[1]), - .Q(\Probe_out_reg_int_reg[15]_0 [1]), - .R(1'b0)); - FDRE \Probe_out_reg_int_reg[2] - (.C(CLK), - .CE(1'b1), - .D(Bus_Data_out_int[2]), - .Q(\Probe_out_reg_int_reg[15]_0 [2]), - .R(1'b0)); - FDRE \Probe_out_reg_int_reg[3] - (.C(CLK), - .CE(1'b1), - .D(Bus_Data_out_int[3]), - .Q(\Probe_out_reg_int_reg[15]_0 [3]), - .R(1'b0)); - FDRE \Probe_out_reg_int_reg[4] - (.C(CLK), - .CE(1'b1), - .D(Bus_Data_out_int[4]), - .Q(\Probe_out_reg_int_reg[15]_0 [4]), - .R(1'b0)); - FDRE \Probe_out_reg_int_reg[5] - (.C(CLK), - .CE(1'b1), - .D(Bus_Data_out_int[5]), - .Q(\Probe_out_reg_int_reg[15]_0 [5]), - .R(1'b0)); - FDRE \Probe_out_reg_int_reg[6] - (.C(CLK), - .CE(1'b1), - .D(Bus_Data_out_int[6]), - .Q(\Probe_out_reg_int_reg[15]_0 [6]), - .R(1'b0)); - FDRE \Probe_out_reg_int_reg[7] - (.C(CLK), - .CE(1'b1), - .D(Bus_Data_out_int[7]), - .Q(\Probe_out_reg_int_reg[15]_0 [7]), - .R(1'b0)); - FDRE \Probe_out_reg_int_reg[8] - (.C(CLK), - .CE(1'b1), - .D(Bus_Data_out_int[8]), - .Q(\Probe_out_reg_int_reg[15]_0 [8]), - .R(1'b0)); - FDRE \Probe_out_reg_int_reg[9] - (.C(CLK), - .CE(1'b1), - .D(Bus_Data_out_int[9]), - .Q(\Probe_out_reg_int_reg[15]_0 [9]), - .R(1'b0)); -endmodule - -(* ORIG_REF_NAME = "vio_v3_0_19_probe_out_one" *) -module vio_0_vio_v3_0_19_probe_out_one - (probe_out0, - \Bus_Data_out_int_reg[15]_0 , - SR, - s_daddr_o, - \addr_count_reg[0]_0 , - s_den_o, - s_dwe_o, - internal_cnt_rst, - CLK, - E, - Q, - \Probe_out_reg[31]_0 , - clk); - output [31:0]probe_out0; - output [15:0]\Bus_Data_out_int_reg[15]_0 ; - input [0:0]SR; - input [10:0]s_daddr_o; - input \addr_count_reg[0]_0 ; - input s_den_o; - input s_dwe_o; - input internal_cnt_rst; - input CLK; - input [0:0]E; - input [15:0]Q; - input [0:0]\Probe_out_reg[31]_0 ; - input clk; - - wire \Bus_Data_out_int[0]_i_1_n_0 ; - wire \Bus_Data_out_int[10]_i_1_n_0 ; - wire \Bus_Data_out_int[11]_i_1_n_0 ; - wire \Bus_Data_out_int[12]_i_1_n_0 ; - wire \Bus_Data_out_int[13]_i_1_n_0 ; - wire \Bus_Data_out_int[14]_i_1_n_0 ; - wire \Bus_Data_out_int[15]_i_1_n_0 ; - wire \Bus_Data_out_int[1]_i_1_n_0 ; - wire \Bus_Data_out_int[2]_i_1_n_0 ; - wire \Bus_Data_out_int[3]_i_1_n_0 ; - wire \Bus_Data_out_int[4]_i_1_n_0 ; - wire \Bus_Data_out_int[5]_i_1_n_0 ; - wire \Bus_Data_out_int[6]_i_1_n_0 ; - wire \Bus_Data_out_int[7]_i_1_n_0 ; - wire \Bus_Data_out_int[8]_i_1_n_0 ; - wire \Bus_Data_out_int[9]_i_1_n_0 ; - wire [15:0]\Bus_Data_out_int_reg[15]_0 ; - wire CLK; - wire [0:0]E; - wire [0:0]\Probe_out_reg[31]_0 ; - wire [15:0]Q; - (* DIRECT_RESET *) wire [0:0]SR; - wire [1:0]addr_count; - wire \addr_count[0]_i_1_n_0 ; - wire \addr_count[1]_i_1_n_0 ; - wire \addr_count[1]_i_3_n_0 ; - wire \addr_count[1]_i_4_n_0 ; - wire \addr_count_reg[0]_0 ; - wire clk; - wire internal_cnt_rst; - wire [31:0]\mem_probe_out[0] ; - (* DONT_TOUCH *) wire [31:0]probe_out0; - wire rd_probe_out; - wire [10:0]s_daddr_o; - wire s_den_o; - wire s_dwe_o; - - (* SOFT_HLUTNM = "soft_lutpair25" *) - LUT3 #( - .INIT(8'hB8)) - \Bus_Data_out_int[0]_i_1 - (.I0(\mem_probe_out[0] [16]), - .I1(addr_count[0]), - .I2(\mem_probe_out[0] [0]), - .O(\Bus_Data_out_int[0]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair20" *) - LUT3 #( - .INIT(8'hB8)) - \Bus_Data_out_int[10]_i_1 - (.I0(\mem_probe_out[0] [26]), - .I1(addr_count[0]), - .I2(\mem_probe_out[0] [10]), - .O(\Bus_Data_out_int[10]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair20" *) - LUT3 #( - .INIT(8'hB8)) - \Bus_Data_out_int[11]_i_1 - (.I0(\mem_probe_out[0] [27]), - .I1(addr_count[0]), - .I2(\mem_probe_out[0] [11]), - .O(\Bus_Data_out_int[11]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair19" *) - LUT3 #( - .INIT(8'hB8)) - \Bus_Data_out_int[12]_i_1 - (.I0(\mem_probe_out[0] [28]), - .I1(addr_count[0]), - .I2(\mem_probe_out[0] [12]), - .O(\Bus_Data_out_int[12]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair19" *) - LUT3 #( - .INIT(8'hB8)) - \Bus_Data_out_int[13]_i_1 - (.I0(\mem_probe_out[0] [29]), - .I1(addr_count[0]), - .I2(\mem_probe_out[0] [13]), - .O(\Bus_Data_out_int[13]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair18" *) - LUT3 #( - .INIT(8'hB8)) - \Bus_Data_out_int[14]_i_1 - (.I0(\mem_probe_out[0] [30]), - .I1(addr_count[0]), - .I2(\mem_probe_out[0] [14]), - .O(\Bus_Data_out_int[14]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair18" *) - LUT3 #( - .INIT(8'hB8)) - \Bus_Data_out_int[15]_i_1 - (.I0(\mem_probe_out[0] [31]), - .I1(addr_count[0]), - .I2(\mem_probe_out[0] [15]), - .O(\Bus_Data_out_int[15]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair25" *) - LUT3 #( - .INIT(8'hB8)) - \Bus_Data_out_int[1]_i_1 - (.I0(\mem_probe_out[0] [17]), - .I1(addr_count[0]), - .I2(\mem_probe_out[0] [1]), - .O(\Bus_Data_out_int[1]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair24" *) - LUT3 #( - .INIT(8'hB8)) - \Bus_Data_out_int[2]_i_1 - (.I0(\mem_probe_out[0] [18]), - .I1(addr_count[0]), - .I2(\mem_probe_out[0] [2]), - .O(\Bus_Data_out_int[2]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair24" *) - LUT3 #( - .INIT(8'hB8)) - \Bus_Data_out_int[3]_i_1 - (.I0(\mem_probe_out[0] [19]), - .I1(addr_count[0]), - .I2(\mem_probe_out[0] [3]), - .O(\Bus_Data_out_int[3]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair23" *) - LUT3 #( - .INIT(8'hB8)) - \Bus_Data_out_int[4]_i_1 - (.I0(\mem_probe_out[0] [20]), - .I1(addr_count[0]), - .I2(\mem_probe_out[0] [4]), - .O(\Bus_Data_out_int[4]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair23" *) - LUT3 #( - .INIT(8'hB8)) - \Bus_Data_out_int[5]_i_1 - (.I0(\mem_probe_out[0] [21]), - .I1(addr_count[0]), - .I2(\mem_probe_out[0] [5]), - .O(\Bus_Data_out_int[5]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair22" *) - LUT3 #( - .INIT(8'hB8)) - \Bus_Data_out_int[6]_i_1 - (.I0(\mem_probe_out[0] [22]), - .I1(addr_count[0]), - .I2(\mem_probe_out[0] [6]), - .O(\Bus_Data_out_int[6]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair22" *) - LUT3 #( - .INIT(8'hB8)) - \Bus_Data_out_int[7]_i_1 - (.I0(\mem_probe_out[0] [23]), - .I1(addr_count[0]), - .I2(\mem_probe_out[0] [7]), - .O(\Bus_Data_out_int[7]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair21" *) - LUT3 #( - .INIT(8'hB8)) - \Bus_Data_out_int[8]_i_1 - (.I0(\mem_probe_out[0] [24]), - .I1(addr_count[0]), - .I2(\mem_probe_out[0] [8]), - .O(\Bus_Data_out_int[8]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair21" *) - LUT3 #( - .INIT(8'hB8)) - \Bus_Data_out_int[9]_i_1 - (.I0(\mem_probe_out[0] [25]), - .I1(addr_count[0]), - .I2(\mem_probe_out[0] [9]), - .O(\Bus_Data_out_int[9]_i_1_n_0 )); - FDRE \Bus_Data_out_int_reg[0] - (.C(CLK), - .CE(1'b1), - .D(\Bus_Data_out_int[0]_i_1_n_0 ), - .Q(\Bus_Data_out_int_reg[15]_0 [0]), - .R(1'b0)); - FDRE \Bus_Data_out_int_reg[10] - (.C(CLK), - .CE(1'b1), - .D(\Bus_Data_out_int[10]_i_1_n_0 ), - .Q(\Bus_Data_out_int_reg[15]_0 [10]), - .R(1'b0)); - FDRE \Bus_Data_out_int_reg[11] - (.C(CLK), - .CE(1'b1), - .D(\Bus_Data_out_int[11]_i_1_n_0 ), - .Q(\Bus_Data_out_int_reg[15]_0 [11]), - .R(1'b0)); - FDRE \Bus_Data_out_int_reg[12] - (.C(CLK), - .CE(1'b1), - .D(\Bus_Data_out_int[12]_i_1_n_0 ), - .Q(\Bus_Data_out_int_reg[15]_0 [12]), - .R(1'b0)); - FDRE \Bus_Data_out_int_reg[13] - (.C(CLK), - .CE(1'b1), - .D(\Bus_Data_out_int[13]_i_1_n_0 ), - .Q(\Bus_Data_out_int_reg[15]_0 [13]), - .R(1'b0)); - FDRE \Bus_Data_out_int_reg[14] - (.C(CLK), - .CE(1'b1), - .D(\Bus_Data_out_int[14]_i_1_n_0 ), - .Q(\Bus_Data_out_int_reg[15]_0 [14]), - .R(1'b0)); - FDRE \Bus_Data_out_int_reg[15] - (.C(CLK), - .CE(1'b1), - .D(\Bus_Data_out_int[15]_i_1_n_0 ), - .Q(\Bus_Data_out_int_reg[15]_0 [15]), - .R(1'b0)); - FDRE \Bus_Data_out_int_reg[1] - (.C(CLK), - .CE(1'b1), - .D(\Bus_Data_out_int[1]_i_1_n_0 ), - .Q(\Bus_Data_out_int_reg[15]_0 [1]), - .R(1'b0)); - FDRE \Bus_Data_out_int_reg[2] - (.C(CLK), - .CE(1'b1), - .D(\Bus_Data_out_int[2]_i_1_n_0 ), - .Q(\Bus_Data_out_int_reg[15]_0 [2]), - .R(1'b0)); - FDRE \Bus_Data_out_int_reg[3] - (.C(CLK), - .CE(1'b1), - .D(\Bus_Data_out_int[3]_i_1_n_0 ), - .Q(\Bus_Data_out_int_reg[15]_0 [3]), - .R(1'b0)); - FDRE \Bus_Data_out_int_reg[4] - (.C(CLK), - .CE(1'b1), - .D(\Bus_Data_out_int[4]_i_1_n_0 ), - .Q(\Bus_Data_out_int_reg[15]_0 [4]), - .R(1'b0)); - FDRE \Bus_Data_out_int_reg[5] - (.C(CLK), - .CE(1'b1), - .D(\Bus_Data_out_int[5]_i_1_n_0 ), - .Q(\Bus_Data_out_int_reg[15]_0 [5]), - .R(1'b0)); - FDRE \Bus_Data_out_int_reg[6] - (.C(CLK), - .CE(1'b1), - .D(\Bus_Data_out_int[6]_i_1_n_0 ), - .Q(\Bus_Data_out_int_reg[15]_0 [6]), - .R(1'b0)); - FDRE \Bus_Data_out_int_reg[7] - (.C(CLK), - .CE(1'b1), - .D(\Bus_Data_out_int[7]_i_1_n_0 ), - .Q(\Bus_Data_out_int_reg[15]_0 [7]), - .R(1'b0)); - FDRE \Bus_Data_out_int_reg[8] - (.C(CLK), - .CE(1'b1), - .D(\Bus_Data_out_int[8]_i_1_n_0 ), - .Q(\Bus_Data_out_int_reg[15]_0 [8]), - .R(1'b0)); - FDRE \Bus_Data_out_int_reg[9] - (.C(CLK), - .CE(1'b1), - .D(\Bus_Data_out_int[9]_i_1_n_0 ), - .Q(\Bus_Data_out_int_reg[15]_0 [9]), - .R(1'b0)); - FDRE \LOOP_I[1].data_int_reg[16] - (.C(CLK), - .CE(E), - .D(\mem_probe_out[0] [0]), - .Q(\mem_probe_out[0] [16]), - .R(SR)); - FDRE \LOOP_I[1].data_int_reg[17] - (.C(CLK), - .CE(E), - .D(\mem_probe_out[0] [1]), - .Q(\mem_probe_out[0] [17]), - .R(SR)); - FDRE \LOOP_I[1].data_int_reg[18] - (.C(CLK), - .CE(E), - .D(\mem_probe_out[0] [2]), - .Q(\mem_probe_out[0] [18]), - .R(SR)); - FDRE \LOOP_I[1].data_int_reg[19] - (.C(CLK), - .CE(E), - .D(\mem_probe_out[0] [3]), - .Q(\mem_probe_out[0] [19]), - .R(SR)); - FDRE \LOOP_I[1].data_int_reg[20] - (.C(CLK), - .CE(E), - .D(\mem_probe_out[0] [4]), - .Q(\mem_probe_out[0] [20]), - .R(SR)); - FDRE \LOOP_I[1].data_int_reg[21] - (.C(CLK), - .CE(E), - .D(\mem_probe_out[0] [5]), - .Q(\mem_probe_out[0] [21]), - .R(SR)); - FDRE \LOOP_I[1].data_int_reg[22] - (.C(CLK), - .CE(E), - .D(\mem_probe_out[0] [6]), - .Q(\mem_probe_out[0] [22]), - .R(SR)); - FDRE \LOOP_I[1].data_int_reg[23] - (.C(CLK), - .CE(E), - .D(\mem_probe_out[0] [7]), - .Q(\mem_probe_out[0] [23]), - .R(SR)); - FDRE \LOOP_I[1].data_int_reg[24] - (.C(CLK), - .CE(E), - .D(\mem_probe_out[0] [8]), - .Q(\mem_probe_out[0] [24]), - .R(SR)); - FDRE \LOOP_I[1].data_int_reg[25] - (.C(CLK), - .CE(E), - .D(\mem_probe_out[0] [9]), - .Q(\mem_probe_out[0] [25]), - .R(SR)); - FDRE \LOOP_I[1].data_int_reg[26] - (.C(CLK), - .CE(E), - .D(\mem_probe_out[0] [10]), - .Q(\mem_probe_out[0] [26]), - .R(SR)); - FDRE \LOOP_I[1].data_int_reg[27] - (.C(CLK), - .CE(E), - .D(\mem_probe_out[0] [11]), - .Q(\mem_probe_out[0] [27]), - .R(SR)); - FDRE \LOOP_I[1].data_int_reg[28] - (.C(CLK), - .CE(E), - .D(\mem_probe_out[0] [12]), - .Q(\mem_probe_out[0] [28]), - .R(SR)); - FDRE \LOOP_I[1].data_int_reg[29] - (.C(CLK), - .CE(E), - .D(\mem_probe_out[0] [13]), - .Q(\mem_probe_out[0] [29]), - .R(SR)); - FDRE \LOOP_I[1].data_int_reg[30] - (.C(CLK), - .CE(E), - .D(\mem_probe_out[0] [14]), - .Q(\mem_probe_out[0] [30]), - .R(SR)); - FDRE \LOOP_I[1].data_int_reg[31] - (.C(CLK), - .CE(E), - .D(\mem_probe_out[0] [15]), - .Q(\mem_probe_out[0] [31]), - .R(SR)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE \Probe_out_reg[0] - (.C(clk), - .CE(\Probe_out_reg[31]_0 ), - .D(\mem_probe_out[0] [0]), - .Q(probe_out0[0]), - .R(SR)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE \Probe_out_reg[10] - (.C(clk), - .CE(\Probe_out_reg[31]_0 ), - .D(\mem_probe_out[0] [10]), - .Q(probe_out0[10]), - .R(SR)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE \Probe_out_reg[11] - (.C(clk), - .CE(\Probe_out_reg[31]_0 ), - .D(\mem_probe_out[0] [11]), - .Q(probe_out0[11]), - .R(SR)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE \Probe_out_reg[12] - (.C(clk), - .CE(\Probe_out_reg[31]_0 ), - .D(\mem_probe_out[0] [12]), - .Q(probe_out0[12]), - .R(SR)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE \Probe_out_reg[13] - (.C(clk), - .CE(\Probe_out_reg[31]_0 ), - .D(\mem_probe_out[0] [13]), - .Q(probe_out0[13]), - .R(SR)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE \Probe_out_reg[14] - (.C(clk), - .CE(\Probe_out_reg[31]_0 ), - .D(\mem_probe_out[0] [14]), - .Q(probe_out0[14]), - .R(SR)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE \Probe_out_reg[15] - (.C(clk), - .CE(\Probe_out_reg[31]_0 ), - .D(\mem_probe_out[0] [15]), - .Q(probe_out0[15]), - .R(SR)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE \Probe_out_reg[16] - (.C(clk), - .CE(\Probe_out_reg[31]_0 ), - .D(\mem_probe_out[0] [16]), - .Q(probe_out0[16]), - .R(SR)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE \Probe_out_reg[17] - (.C(clk), - .CE(\Probe_out_reg[31]_0 ), - .D(\mem_probe_out[0] [17]), - .Q(probe_out0[17]), - .R(SR)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE \Probe_out_reg[18] - (.C(clk), - .CE(\Probe_out_reg[31]_0 ), - .D(\mem_probe_out[0] [18]), - .Q(probe_out0[18]), - .R(SR)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE \Probe_out_reg[19] - (.C(clk), - .CE(\Probe_out_reg[31]_0 ), - .D(\mem_probe_out[0] [19]), - .Q(probe_out0[19]), - .R(SR)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE \Probe_out_reg[1] - (.C(clk), - .CE(\Probe_out_reg[31]_0 ), - .D(\mem_probe_out[0] [1]), - .Q(probe_out0[1]), - .R(SR)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE \Probe_out_reg[20] - (.C(clk), - .CE(\Probe_out_reg[31]_0 ), - .D(\mem_probe_out[0] [20]), - .Q(probe_out0[20]), - .R(SR)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE \Probe_out_reg[21] - (.C(clk), - .CE(\Probe_out_reg[31]_0 ), - .D(\mem_probe_out[0] [21]), - .Q(probe_out0[21]), - .R(SR)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE \Probe_out_reg[22] - (.C(clk), - .CE(\Probe_out_reg[31]_0 ), - .D(\mem_probe_out[0] [22]), - .Q(probe_out0[22]), - .R(SR)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE \Probe_out_reg[23] - (.C(clk), - .CE(\Probe_out_reg[31]_0 ), - .D(\mem_probe_out[0] [23]), - .Q(probe_out0[23]), - .R(SR)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE \Probe_out_reg[24] - (.C(clk), - .CE(\Probe_out_reg[31]_0 ), - .D(\mem_probe_out[0] [24]), - .Q(probe_out0[24]), - .R(SR)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE \Probe_out_reg[25] - (.C(clk), - .CE(\Probe_out_reg[31]_0 ), - .D(\mem_probe_out[0] [25]), - .Q(probe_out0[25]), - .R(SR)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE \Probe_out_reg[26] - (.C(clk), - .CE(\Probe_out_reg[31]_0 ), - .D(\mem_probe_out[0] [26]), - .Q(probe_out0[26]), - .R(SR)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE \Probe_out_reg[27] - (.C(clk), - .CE(\Probe_out_reg[31]_0 ), - .D(\mem_probe_out[0] [27]), - .Q(probe_out0[27]), - .R(SR)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE \Probe_out_reg[28] - (.C(clk), - .CE(\Probe_out_reg[31]_0 ), - .D(\mem_probe_out[0] [28]), - .Q(probe_out0[28]), - .R(SR)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE \Probe_out_reg[29] - (.C(clk), - .CE(\Probe_out_reg[31]_0 ), - .D(\mem_probe_out[0] [29]), - .Q(probe_out0[29]), - .R(SR)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE \Probe_out_reg[2] - (.C(clk), - .CE(\Probe_out_reg[31]_0 ), - .D(\mem_probe_out[0] [2]), - .Q(probe_out0[2]), - .R(SR)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE \Probe_out_reg[30] - (.C(clk), - .CE(\Probe_out_reg[31]_0 ), - .D(\mem_probe_out[0] [30]), - .Q(probe_out0[30]), - .R(SR)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE \Probe_out_reg[31] - (.C(clk), - .CE(\Probe_out_reg[31]_0 ), - .D(\mem_probe_out[0] [31]), - .Q(probe_out0[31]), - .R(SR)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE \Probe_out_reg[3] - (.C(clk), - .CE(\Probe_out_reg[31]_0 ), - .D(\mem_probe_out[0] [3]), - .Q(probe_out0[3]), - .R(SR)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE \Probe_out_reg[4] - (.C(clk), - .CE(\Probe_out_reg[31]_0 ), - .D(\mem_probe_out[0] [4]), - .Q(probe_out0[4]), - .R(SR)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE \Probe_out_reg[5] - (.C(clk), - .CE(\Probe_out_reg[31]_0 ), - .D(\mem_probe_out[0] [5]), - .Q(probe_out0[5]), - .R(SR)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE \Probe_out_reg[6] - (.C(clk), - .CE(\Probe_out_reg[31]_0 ), - .D(\mem_probe_out[0] [6]), - .Q(probe_out0[6]), - .R(SR)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE \Probe_out_reg[7] - (.C(clk), - .CE(\Probe_out_reg[31]_0 ), - .D(\mem_probe_out[0] [7]), - .Q(probe_out0[7]), - .R(SR)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE \Probe_out_reg[8] - (.C(clk), - .CE(\Probe_out_reg[31]_0 ), - .D(\mem_probe_out[0] [8]), - .Q(probe_out0[8]), - .R(SR)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE \Probe_out_reg[9] - (.C(clk), - .CE(\Probe_out_reg[31]_0 ), - .D(\mem_probe_out[0] [9]), - .Q(probe_out0[9]), - .R(SR)); - LUT4 #( - .INIT(16'h0322)) - \addr_count[0]_i_1 - (.I0(addr_count[0]), - .I1(internal_cnt_rst), - .I2(addr_count[0]), - .I3(rd_probe_out), - .O(\addr_count[0]_i_1_n_0 )); - LUT5 #( - .INIT(32'h00302222)) - \addr_count[1]_i_1 - (.I0(addr_count[1]), - .I1(internal_cnt_rst), - .I2(addr_count[1]), - .I3(addr_count[0]), - .I4(rd_probe_out), - .O(\addr_count[1]_i_1_n_0 )); - LUT6 #( - .INIT(64'h0001000000000000)) - \addr_count[1]_i_2 - (.I0(s_daddr_o[4]), - .I1(s_daddr_o[6]), - .I2(s_daddr_o[5]), - .I3(\addr_count[1]_i_3_n_0 ), - .I4(\addr_count[1]_i_4_n_0 ), - .I5(\addr_count_reg[0]_0 ), - .O(rd_probe_out)); - LUT4 #( - .INIT(16'hFFFE)) - \addr_count[1]_i_3 - (.I0(s_daddr_o[7]), - .I1(s_daddr_o[8]), - .I2(s_daddr_o[9]), - .I3(s_daddr_o[10]), - .O(\addr_count[1]_i_3_n_0 )); - LUT6 #( - .INIT(64'h0000000000000020)) - \addr_count[1]_i_4 - (.I0(s_den_o), - .I1(s_dwe_o), - .I2(s_daddr_o[3]), - .I3(s_daddr_o[0]), - .I4(s_daddr_o[1]), - .I5(s_daddr_o[2]), - .O(\addr_count[1]_i_4_n_0 )); - (* MAX_FANOUT = "200" *) - FDRE \addr_count_reg[0] - (.C(CLK), - .CE(1'b1), - .D(\addr_count[0]_i_1_n_0 ), - .Q(addr_count[0]), - .R(1'b0)); - (* MAX_FANOUT = "200" *) - FDRE \addr_count_reg[1] - (.C(CLK), - .CE(1'b1), - .D(\addr_count[1]_i_1_n_0 ), - .Q(addr_count[1]), - .R(1'b0)); - FDRE \data_int_reg[0] - (.C(CLK), - .CE(E), - .D(Q[0]), - .Q(\mem_probe_out[0] [0]), - .R(SR)); - FDRE \data_int_reg[10] - (.C(CLK), - .CE(E), - .D(Q[10]), - .Q(\mem_probe_out[0] [10]), - .R(SR)); - FDRE \data_int_reg[11] - (.C(CLK), - .CE(E), - .D(Q[11]), - .Q(\mem_probe_out[0] [11]), - .R(SR)); - FDRE \data_int_reg[12] - (.C(CLK), - .CE(E), - .D(Q[12]), - .Q(\mem_probe_out[0] [12]), - .R(SR)); - FDRE \data_int_reg[13] - (.C(CLK), - .CE(E), - .D(Q[13]), - .Q(\mem_probe_out[0] [13]), - .R(SR)); - FDRE \data_int_reg[14] - (.C(CLK), - .CE(E), - .D(Q[14]), - .Q(\mem_probe_out[0] [14]), - .R(SR)); - FDRE \data_int_reg[15] - (.C(CLK), - .CE(E), - .D(Q[15]), - .Q(\mem_probe_out[0] [15]), - .R(SR)); - FDRE \data_int_reg[1] - (.C(CLK), - .CE(E), - .D(Q[1]), - .Q(\mem_probe_out[0] [1]), - .R(SR)); - FDRE \data_int_reg[2] - (.C(CLK), - .CE(E), - .D(Q[2]), - .Q(\mem_probe_out[0] [2]), - .R(SR)); - FDRE \data_int_reg[3] - (.C(CLK), - .CE(E), - .D(Q[3]), - .Q(\mem_probe_out[0] [3]), - .R(SR)); - FDRE \data_int_reg[4] - (.C(CLK), - .CE(E), - .D(Q[4]), - .Q(\mem_probe_out[0] [4]), - .R(SR)); - FDRE \data_int_reg[5] - (.C(CLK), - .CE(E), - .D(Q[5]), - .Q(\mem_probe_out[0] [5]), - .R(SR)); - FDRE \data_int_reg[6] - (.C(CLK), - .CE(E), - .D(Q[6]), - .Q(\mem_probe_out[0] [6]), - .R(SR)); - FDRE \data_int_reg[7] - (.C(CLK), - .CE(E), - .D(Q[7]), - .Q(\mem_probe_out[0] [7]), - .R(SR)); - FDRE \data_int_reg[8] - (.C(CLK), - .CE(E), - .D(Q[8]), - .Q(\mem_probe_out[0] [8]), - .R(SR)); - FDRE \data_int_reg[9] - (.C(CLK), - .CE(E), - .D(Q[9]), - .Q(\mem_probe_out[0] [9]), - .R(SR)); -endmodule - -(* C_BUILD_REVISION = "0" *) (* C_BUS_ADDR_WIDTH = "17" *) (* C_BUS_DATA_WIDTH = "16" *) -(* C_CORE_INFO1 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_CORE_INFO2 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_CORE_MAJOR_VER = "2" *) -(* C_CORE_MINOR_ALPHA_VER = "97" *) (* C_CORE_MINOR_VER = "0" *) (* C_CORE_TYPE = "2" *) -(* C_CSE_DRV_VER = "1" *) (* C_EN_PROBE_IN_ACTIVITY = "1" *) (* C_EN_SYNCHRONIZATION = "1" *) -(* C_MAJOR_VERSION = "2013" *) (* C_MAX_NUM_PROBE = "256" *) (* C_MAX_WIDTH_PER_PROBE = "256" *) -(* C_MINOR_VERSION = "1" *) (* C_NEXT_SLAVE = "0" *) (* C_NUM_PROBE_IN = "2" *) -(* C_NUM_PROBE_OUT = "1" *) (* C_PIPE_IFACE = "0" *) (* C_PROBE_IN0_WIDTH = "32" *) -(* C_PROBE_IN100_WIDTH = "1" *) (* C_PROBE_IN101_WIDTH = "1" *) (* C_PROBE_IN102_WIDTH = "1" *) -(* C_PROBE_IN103_WIDTH = "1" *) (* C_PROBE_IN104_WIDTH = "1" *) (* C_PROBE_IN105_WIDTH = "1" *) -(* C_PROBE_IN106_WIDTH = "1" *) (* C_PROBE_IN107_WIDTH = "1" *) (* C_PROBE_IN108_WIDTH = "1" *) -(* C_PROBE_IN109_WIDTH = "1" *) (* C_PROBE_IN10_WIDTH = "1" *) (* C_PROBE_IN110_WIDTH = "1" *) -(* C_PROBE_IN111_WIDTH = "1" *) (* C_PROBE_IN112_WIDTH = "1" *) (* C_PROBE_IN113_WIDTH = "1" *) -(* C_PROBE_IN114_WIDTH = "1" *) (* C_PROBE_IN115_WIDTH = "1" *) (* C_PROBE_IN116_WIDTH = "1" *) -(* C_PROBE_IN117_WIDTH = "1" *) (* C_PROBE_IN118_WIDTH = "1" *) (* C_PROBE_IN119_WIDTH = "1" *) -(* C_PROBE_IN11_WIDTH = "1" *) (* C_PROBE_IN120_WIDTH = "1" *) (* C_PROBE_IN121_WIDTH = "1" *) -(* C_PROBE_IN122_WIDTH = "1" *) (* C_PROBE_IN123_WIDTH = "1" *) (* C_PROBE_IN124_WIDTH = "1" *) -(* C_PROBE_IN125_WIDTH = "1" *) (* C_PROBE_IN126_WIDTH = "1" *) (* C_PROBE_IN127_WIDTH = "1" *) -(* C_PROBE_IN128_WIDTH = "1" *) (* C_PROBE_IN129_WIDTH = "1" *) (* C_PROBE_IN12_WIDTH = "1" *) -(* C_PROBE_IN130_WIDTH = "1" *) (* C_PROBE_IN131_WIDTH = "1" *) (* C_PROBE_IN132_WIDTH = "1" *) -(* C_PROBE_IN133_WIDTH = "1" *) (* C_PROBE_IN134_WIDTH = "1" *) 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C_PROBE_OUT19_INIT_VAL = "1'b0" *) (* C_PROBE_OUT19_WIDTH = "1" *) -(* C_PROBE_OUT1_INIT_VAL = "1'b0" *) (* C_PROBE_OUT1_WIDTH = "1" *) (* C_PROBE_OUT200_INIT_VAL = "1'b0" *) -(* C_PROBE_OUT200_WIDTH = "1" *) (* C_PROBE_OUT201_INIT_VAL = "1'b0" *) (* C_PROBE_OUT201_WIDTH = "1" *) -(* C_PROBE_OUT202_INIT_VAL = "1'b0" *) (* C_PROBE_OUT202_WIDTH = "1" *) (* C_PROBE_OUT203_INIT_VAL = "1'b0" *) -(* C_PROBE_OUT203_WIDTH = "1" *) (* C_PROBE_OUT204_INIT_VAL = "1'b0" *) (* C_PROBE_OUT204_WIDTH = "1" *) -(* C_PROBE_OUT205_INIT_VAL = "1'b0" *) (* C_PROBE_OUT205_WIDTH = "1" *) (* C_PROBE_OUT206_INIT_VAL = "1'b0" *) -(* C_PROBE_OUT206_WIDTH = "1" *) (* C_PROBE_OUT207_INIT_VAL = "1'b0" *) (* C_PROBE_OUT207_WIDTH = "1" *) -(* C_PROBE_OUT208_INIT_VAL = "1'b0" *) (* C_PROBE_OUT208_WIDTH = "1" *) (* C_PROBE_OUT209_INIT_VAL = "1'b0" *) -(* C_PROBE_OUT209_WIDTH = "1" *) (* C_PROBE_OUT20_INIT_VAL = "1'b0" *) (* C_PROBE_OUT20_WIDTH = "1" *) -(* C_PROBE_OUT210_INIT_VAL = "1'b0" *) (* C_PROBE_OUT210_WIDTH = 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C_PROBE_OUT223_WIDTH = "1" *) -(* C_PROBE_OUT224_INIT_VAL = "1'b0" *) (* C_PROBE_OUT224_WIDTH = "1" *) (* C_PROBE_OUT225_INIT_VAL = "1'b0" *) -(* C_PROBE_OUT225_WIDTH = "1" *) (* C_PROBE_OUT226_INIT_VAL = "1'b0" *) (* C_PROBE_OUT226_WIDTH = "1" *) -(* C_PROBE_OUT227_INIT_VAL = "1'b0" *) (* C_PROBE_OUT227_WIDTH = "1" *) (* C_PROBE_OUT228_INIT_VAL = "1'b0" *) -(* C_PROBE_OUT228_WIDTH = "1" *) (* C_PROBE_OUT229_INIT_VAL = "1'b0" *) (* C_PROBE_OUT229_WIDTH = "1" *) -(* C_PROBE_OUT22_INIT_VAL = "1'b0" *) (* C_PROBE_OUT22_WIDTH = "1" *) (* C_PROBE_OUT230_INIT_VAL = "1'b0" *) -(* C_PROBE_OUT230_WIDTH = "1" *) (* C_PROBE_OUT231_INIT_VAL = "1'b0" *) (* C_PROBE_OUT231_WIDTH = "1" *) -(* C_PROBE_OUT232_INIT_VAL = "1'b0" *) (* C_PROBE_OUT232_WIDTH = "1" *) (* C_PROBE_OUT233_INIT_VAL = "1'b0" *) -(* C_PROBE_OUT233_WIDTH = "1" *) (* C_PROBE_OUT234_INIT_VAL = "1'b0" *) (* C_PROBE_OUT234_WIDTH = "1" *) -(* C_PROBE_OUT235_INIT_VAL = "1'b0" *) (* C_PROBE_OUT235_WIDTH = "1" *) (* C_PROBE_OUT236_INIT_VAL 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C_PROBE_OUT249_INIT_VAL = "1'b0" *) (* C_PROBE_OUT249_WIDTH = "1" *) (* C_PROBE_OUT24_INIT_VAL = "1'b0" *) -(* C_PROBE_OUT24_WIDTH = "1" *) (* C_PROBE_OUT250_INIT_VAL = "1'b0" *) (* C_PROBE_OUT250_WIDTH = "1" *) -(* C_PROBE_OUT251_INIT_VAL = "1'b0" *) (* C_PROBE_OUT251_WIDTH = "1" *) (* C_PROBE_OUT252_INIT_VAL = "1'b0" *) -(* C_PROBE_OUT252_WIDTH = "1" *) (* C_PROBE_OUT253_INIT_VAL = "1'b0" *) (* C_PROBE_OUT253_WIDTH = "1" *) -(* C_PROBE_OUT254_INIT_VAL = "1'b0" *) (* C_PROBE_OUT254_WIDTH = "1" *) (* C_PROBE_OUT255_INIT_VAL = "1'b0" *) -(* C_PROBE_OUT255_WIDTH = "1" *) (* C_PROBE_OUT25_INIT_VAL = "1'b0" *) (* C_PROBE_OUT25_WIDTH = "1" *) -(* C_PROBE_OUT26_INIT_VAL = "1'b0" *) (* C_PROBE_OUT26_WIDTH = "1" *) (* C_PROBE_OUT27_INIT_VAL = "1'b0" *) -(* C_PROBE_OUT27_WIDTH = "1" *) (* C_PROBE_OUT28_INIT_VAL = "1'b0" *) (* C_PROBE_OUT28_WIDTH = "1" *) -(* C_PROBE_OUT29_INIT_VAL = "1'b0" *) (* C_PROBE_OUT29_WIDTH = "1" *) (* C_PROBE_OUT2_INIT_VAL = "1'b0" *) -(* C_PROBE_OUT2_WIDTH = "1" *) (* C_PROBE_OUT30_INIT_VAL = "1'b0" *) (* C_PROBE_OUT30_WIDTH = "1" *) -(* C_PROBE_OUT31_INIT_VAL = "1'b0" *) (* C_PROBE_OUT31_WIDTH = "1" *) (* C_PROBE_OUT32_INIT_VAL = "1'b0" *) -(* C_PROBE_OUT32_WIDTH = "1" *) (* C_PROBE_OUT33_INIT_VAL = "1'b0" *) (* C_PROBE_OUT33_WIDTH = "1" *) -(* C_PROBE_OUT34_INIT_VAL = "1'b0" *) (* C_PROBE_OUT34_WIDTH = "1" *) (* C_PROBE_OUT35_INIT_VAL = "1'b0" *) -(* C_PROBE_OUT35_WIDTH = "1" *) (* C_PROBE_OUT36_INIT_VAL = "1'b0" *) (* C_PROBE_OUT36_WIDTH = "1" *) -(* C_PROBE_OUT37_INIT_VAL = "1'b0" *) (* C_PROBE_OUT37_WIDTH = "1" *) (* C_PROBE_OUT38_INIT_VAL = "1'b0" *) -(* C_PROBE_OUT38_WIDTH = "1" *) (* C_PROBE_OUT39_INIT_VAL = "1'b0" *) (* C_PROBE_OUT39_WIDTH = "1" *) -(* C_PROBE_OUT3_INIT_VAL = "1'b0" *) (* C_PROBE_OUT3_WIDTH = "1" *) (* C_PROBE_OUT40_INIT_VAL = "1'b0" *) -(* C_PROBE_OUT40_WIDTH = "1" *) (* C_PROBE_OUT41_INIT_VAL = "1'b0" *) (* C_PROBE_OUT41_WIDTH = "1" *) -(* C_PROBE_OUT42_INIT_VAL = "1'b0" *) (* C_PROBE_OUT42_WIDTH = "1" *) (* C_PROBE_OUT43_INIT_VAL = "1'b0" *) -(* C_PROBE_OUT43_WIDTH = "1" *) (* C_PROBE_OUT44_INIT_VAL = "1'b0" *) (* C_PROBE_OUT44_WIDTH = "1" *) -(* C_PROBE_OUT45_INIT_VAL = "1'b0" *) (* C_PROBE_OUT45_WIDTH = "1" *) (* C_PROBE_OUT46_INIT_VAL = "1'b0" *) -(* C_PROBE_OUT46_WIDTH = "1" *) (* C_PROBE_OUT47_INIT_VAL = "1'b0" *) (* C_PROBE_OUT47_WIDTH = "1" *) -(* C_PROBE_OUT48_INIT_VAL = "1'b0" *) (* C_PROBE_OUT48_WIDTH = "1" *) (* C_PROBE_OUT49_INIT_VAL = "1'b0" *) -(* C_PROBE_OUT49_WIDTH = "1" *) (* C_PROBE_OUT4_INIT_VAL = "1'b0" *) (* C_PROBE_OUT4_WIDTH = "1" *) -(* C_PROBE_OUT50_INIT_VAL = "1'b0" *) (* C_PROBE_OUT50_WIDTH = "1" *) (* C_PROBE_OUT51_INIT_VAL = "1'b0" *) -(* C_PROBE_OUT51_WIDTH = "1" *) (* C_PROBE_OUT52_INIT_VAL = "1'b0" *) (* C_PROBE_OUT52_WIDTH = "1" *) -(* C_PROBE_OUT53_INIT_VAL = "1'b0" *) (* C_PROBE_OUT53_WIDTH = "1" *) (* C_PROBE_OUT54_INIT_VAL = "1'b0" *) -(* C_PROBE_OUT54_WIDTH = "1" *) (* C_PROBE_OUT55_INIT_VAL = "1'b0" *) (* C_PROBE_OUT55_WIDTH = "1" *) -(* C_PROBE_OUT56_INIT_VAL = "1'b0" *) (* C_PROBE_OUT56_WIDTH = "1" *) (* C_PROBE_OUT57_INIT_VAL = "1'b0" *) -(* C_PROBE_OUT57_WIDTH = "1" *) (* C_PROBE_OUT58_INIT_VAL = "1'b0" *) (* C_PROBE_OUT58_WIDTH = "1" *) -(* C_PROBE_OUT59_INIT_VAL = "1'b0" *) (* C_PROBE_OUT59_WIDTH = "1" *) (* C_PROBE_OUT5_INIT_VAL = "1'b0" *) -(* C_PROBE_OUT5_WIDTH = "1" *) (* C_PROBE_OUT60_INIT_VAL = "1'b0" *) (* C_PROBE_OUT60_WIDTH = "1" *) -(* C_PROBE_OUT61_INIT_VAL = "1'b0" *) (* C_PROBE_OUT61_WIDTH = "1" *) (* C_PROBE_OUT62_INIT_VAL = "1'b0" *) -(* C_PROBE_OUT62_WIDTH = "1" *) (* C_PROBE_OUT63_INIT_VAL = "1'b0" *) (* C_PROBE_OUT63_WIDTH = "1" *) -(* C_PROBE_OUT64_INIT_VAL = "1'b0" *) (* C_PROBE_OUT64_WIDTH = "1" *) (* C_PROBE_OUT65_INIT_VAL = "1'b0" *) -(* C_PROBE_OUT65_WIDTH = "1" *) (* C_PROBE_OUT66_INIT_VAL = "1'b0" *) (* C_PROBE_OUT66_WIDTH = "1" *) -(* C_PROBE_OUT67_INIT_VAL = "1'b0" *) (* C_PROBE_OUT67_WIDTH = "1" *) (* C_PROBE_OUT68_INIT_VAL = "1'b0" *) -(* C_PROBE_OUT68_WIDTH = "1" *) (* C_PROBE_OUT69_INIT_VAL = "1'b0" *) (* C_PROBE_OUT69_WIDTH = "1" *) -(* C_PROBE_OUT6_INIT_VAL = "1'b0" *) (* C_PROBE_OUT6_WIDTH = "1" *) (* C_PROBE_OUT70_INIT_VAL = "1'b0" *) -(* C_PROBE_OUT70_WIDTH = "1" *) (* C_PROBE_OUT71_INIT_VAL = "1'b0" *) (* C_PROBE_OUT71_WIDTH = "1" *) -(* C_PROBE_OUT72_INIT_VAL = "1'b0" *) (* C_PROBE_OUT72_WIDTH = "1" *) (* C_PROBE_OUT73_INIT_VAL = "1'b0" *) -(* C_PROBE_OUT73_WIDTH = "1" *) (* C_PROBE_OUT74_INIT_VAL = "1'b0" *) (* C_PROBE_OUT74_WIDTH = "1" *) -(* C_PROBE_OUT75_INIT_VAL = "1'b0" *) (* C_PROBE_OUT75_WIDTH = "1" *) (* C_PROBE_OUT76_INIT_VAL = "1'b0" *) -(* C_PROBE_OUT76_WIDTH = "1" *) (* C_PROBE_OUT77_INIT_VAL = "1'b0" *) (* C_PROBE_OUT77_WIDTH = "1" *) -(* C_PROBE_OUT78_INIT_VAL = "1'b0" *) (* C_PROBE_OUT78_WIDTH = "1" *) (* C_PROBE_OUT79_INIT_VAL = "1'b0" *) -(* C_PROBE_OUT79_WIDTH = "1" *) (* C_PROBE_OUT7_INIT_VAL = "1'b0" *) (* C_PROBE_OUT7_WIDTH = "1" *) -(* C_PROBE_OUT80_INIT_VAL = "1'b0" *) (* C_PROBE_OUT80_WIDTH = "1" *) (* C_PROBE_OUT81_INIT_VAL = "1'b0" *) -(* C_PROBE_OUT81_WIDTH = "1" *) (* C_PROBE_OUT82_INIT_VAL = "1'b0" *) (* C_PROBE_OUT82_WIDTH = "1" *) -(* C_PROBE_OUT83_INIT_VAL = "1'b0" *) (* C_PROBE_OUT83_WIDTH = "1" *) (* C_PROBE_OUT84_INIT_VAL = "1'b0" *) -(* C_PROBE_OUT84_WIDTH = "1" *) (* C_PROBE_OUT85_INIT_VAL = "1'b0" *) (* C_PROBE_OUT85_WIDTH = "1" *) -(* C_PROBE_OUT86_INIT_VAL = "1'b0" *) (* C_PROBE_OUT86_WIDTH = "1" *) (* C_PROBE_OUT87_INIT_VAL = "1'b0" *) -(* C_PROBE_OUT87_WIDTH = "1" *) (* C_PROBE_OUT88_INIT_VAL = "1'b0" *) (* C_PROBE_OUT88_WIDTH = "1" *) -(* C_PROBE_OUT89_INIT_VAL = "1'b0" *) (* C_PROBE_OUT89_WIDTH = "1" *) (* C_PROBE_OUT8_INIT_VAL = "1'b0" *) -(* C_PROBE_OUT8_WIDTH = "1" *) (* C_PROBE_OUT90_INIT_VAL = "1'b0" *) (* C_PROBE_OUT90_WIDTH = "1" *) -(* C_PROBE_OUT91_INIT_VAL = "1'b0" *) (* C_PROBE_OUT91_WIDTH = "1" *) (* C_PROBE_OUT92_INIT_VAL = "1'b0" *) -(* C_PROBE_OUT92_WIDTH = "1" *) (* C_PROBE_OUT93_INIT_VAL = "1'b0" *) (* C_PROBE_OUT93_WIDTH = "1" *) -(* C_PROBE_OUT94_INIT_VAL = "1'b0" *) (* C_PROBE_OUT94_WIDTH = "1" *) (* C_PROBE_OUT95_INIT_VAL = "1'b0" *) -(* C_PROBE_OUT95_WIDTH = "1" *) (* C_PROBE_OUT96_INIT_VAL = "1'b0" *) (* C_PROBE_OUT96_WIDTH = "1" *) -(* C_PROBE_OUT97_INIT_VAL = "1'b0" *) (* C_PROBE_OUT97_WIDTH = "1" *) (* C_PROBE_OUT98_INIT_VAL = "1'b0" *) -(* C_PROBE_OUT98_WIDTH = "1" *) (* C_PROBE_OUT99_INIT_VAL = "1'b0" *) (* C_PROBE_OUT99_WIDTH = "1" *) -(* C_PROBE_OUT9_INIT_VAL = "1'b0" *) (* C_PROBE_OUT9_WIDTH = "1" *) (* C_USE_TEST_REG = "1" *) -(* C_XDEVICEFAMILY = "zynq" *) (* C_XLNX_HW_PROBE_INFO = "DEFAULT" *) (* C_XSDB_SLAVE_TYPE = "33" *) -(* DowngradeIPIdentifiedWarnings = "yes" *) (* LC_HIGH_BIT_POS_PROBE_OUT0 = "16'b0000000000011111" *) (* LC_HIGH_BIT_POS_PROBE_OUT1 = "16'b0000000000100000" *) -(* LC_HIGH_BIT_POS_PROBE_OUT10 = "16'b0000000000101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT100 = "16'b0000000010000011" *) (* LC_HIGH_BIT_POS_PROBE_OUT101 = "16'b0000000010000100" *) -(* LC_HIGH_BIT_POS_PROBE_OUT102 = "16'b0000000010000101" *) (* LC_HIGH_BIT_POS_PROBE_OUT103 = "16'b0000000010000110" *) (* LC_HIGH_BIT_POS_PROBE_OUT104 = "16'b0000000010000111" *) -(* LC_HIGH_BIT_POS_PROBE_OUT105 = "16'b0000000010001000" *) (* LC_HIGH_BIT_POS_PROBE_OUT106 = "16'b0000000010001001" *) (* LC_HIGH_BIT_POS_PROBE_OUT107 = "16'b0000000010001010" *) -(* LC_HIGH_BIT_POS_PROBE_OUT108 = "16'b0000000010001011" *) (* LC_HIGH_BIT_POS_PROBE_OUT109 = "16'b0000000010001100" *) (* LC_HIGH_BIT_POS_PROBE_OUT11 = "16'b0000000000101010" *) -(* LC_HIGH_BIT_POS_PROBE_OUT110 = "16'b0000000010001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT111 = "16'b0000000010001110" *) (* LC_HIGH_BIT_POS_PROBE_OUT112 = "16'b0000000010001111" *) -(* LC_HIGH_BIT_POS_PROBE_OUT113 = "16'b0000000010010000" *) (* LC_HIGH_BIT_POS_PROBE_OUT114 = "16'b0000000010010001" *) (* LC_HIGH_BIT_POS_PROBE_OUT115 = "16'b0000000010010010" *) -(* LC_HIGH_BIT_POS_PROBE_OUT116 = "16'b0000000010010011" *) (* LC_HIGH_BIT_POS_PROBE_OUT117 = "16'b0000000010010100" *) (* LC_HIGH_BIT_POS_PROBE_OUT118 = "16'b0000000010010101" *) -(* LC_HIGH_BIT_POS_PROBE_OUT119 = "16'b0000000010010110" *) (* LC_HIGH_BIT_POS_PROBE_OUT12 = "16'b0000000000101011" *) (* LC_HIGH_BIT_POS_PROBE_OUT120 = "16'b0000000010010111" *) -(* LC_HIGH_BIT_POS_PROBE_OUT121 = "16'b0000000010011000" *) (* LC_HIGH_BIT_POS_PROBE_OUT122 = "16'b0000000010011001" *) (* LC_HIGH_BIT_POS_PROBE_OUT123 = "16'b0000000010011010" *) -(* LC_HIGH_BIT_POS_PROBE_OUT124 = "16'b0000000010011011" *) (* LC_HIGH_BIT_POS_PROBE_OUT125 = "16'b0000000010011100" *) (* LC_HIGH_BIT_POS_PROBE_OUT126 = "16'b0000000010011101" *) -(* LC_HIGH_BIT_POS_PROBE_OUT127 = "16'b0000000010011110" *) (* LC_HIGH_BIT_POS_PROBE_OUT128 = "16'b0000000010011111" *) (* LC_HIGH_BIT_POS_PROBE_OUT129 = "16'b0000000010100000" *) -(* LC_HIGH_BIT_POS_PROBE_OUT13 = "16'b0000000000101100" *) (* LC_HIGH_BIT_POS_PROBE_OUT130 = "16'b0000000010100001" *) (* LC_HIGH_BIT_POS_PROBE_OUT131 = "16'b0000000010100010" *) -(* LC_HIGH_BIT_POS_PROBE_OUT132 = "16'b0000000010100011" *) (* LC_HIGH_BIT_POS_PROBE_OUT133 = "16'b0000000010100100" *) (* LC_HIGH_BIT_POS_PROBE_OUT134 = "16'b0000000010100101" *) -(* LC_HIGH_BIT_POS_PROBE_OUT135 = "16'b0000000010100110" *) (* LC_HIGH_BIT_POS_PROBE_OUT136 = "16'b0000000010100111" *) (* LC_HIGH_BIT_POS_PROBE_OUT137 = "16'b0000000010101000" *) -(* LC_HIGH_BIT_POS_PROBE_OUT138 = "16'b0000000010101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT139 = "16'b0000000010101010" *) (* LC_HIGH_BIT_POS_PROBE_OUT14 = "16'b0000000000101101" *) -(* LC_HIGH_BIT_POS_PROBE_OUT140 = "16'b0000000010101011" *) (* LC_HIGH_BIT_POS_PROBE_OUT141 = "16'b0000000010101100" *) (* LC_HIGH_BIT_POS_PROBE_OUT142 = "16'b0000000010101101" *) -(* LC_HIGH_BIT_POS_PROBE_OUT143 = "16'b0000000010101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT144 = "16'b0000000010101111" *) (* LC_HIGH_BIT_POS_PROBE_OUT145 = "16'b0000000010110000" *) -(* LC_HIGH_BIT_POS_PROBE_OUT146 = "16'b0000000010110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT147 = "16'b0000000010110010" *) (* LC_HIGH_BIT_POS_PROBE_OUT148 = "16'b0000000010110011" *) -(* LC_HIGH_BIT_POS_PROBE_OUT149 = "16'b0000000010110100" *) (* LC_HIGH_BIT_POS_PROBE_OUT15 = "16'b0000000000101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT150 = "16'b0000000010110101" *) -(* LC_HIGH_BIT_POS_PROBE_OUT151 = "16'b0000000010110110" *) (* LC_HIGH_BIT_POS_PROBE_OUT152 = "16'b0000000010110111" *) (* LC_HIGH_BIT_POS_PROBE_OUT153 = "16'b0000000010111000" *) -(* LC_HIGH_BIT_POS_PROBE_OUT154 = "16'b0000000010111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT155 = "16'b0000000010111010" *) (* LC_HIGH_BIT_POS_PROBE_OUT156 = "16'b0000000010111011" *) -(* LC_HIGH_BIT_POS_PROBE_OUT157 = "16'b0000000010111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT158 = "16'b0000000010111101" *) (* LC_HIGH_BIT_POS_PROBE_OUT159 = "16'b0000000010111110" *) -(* LC_HIGH_BIT_POS_PROBE_OUT16 = "16'b0000000000101111" *) (* LC_HIGH_BIT_POS_PROBE_OUT160 = "16'b0000000010111111" *) (* LC_HIGH_BIT_POS_PROBE_OUT161 = "16'b0000000011000000" *) -(* LC_HIGH_BIT_POS_PROBE_OUT162 = "16'b0000000011000001" *) (* LC_HIGH_BIT_POS_PROBE_OUT163 = "16'b0000000011000010" *) (* LC_HIGH_BIT_POS_PROBE_OUT164 = "16'b0000000011000011" *) -(* LC_HIGH_BIT_POS_PROBE_OUT165 = "16'b0000000011000100" *) (* LC_HIGH_BIT_POS_PROBE_OUT166 = "16'b0000000011000101" *) (* LC_HIGH_BIT_POS_PROBE_OUT167 = "16'b0000000011000110" *) -(* LC_HIGH_BIT_POS_PROBE_OUT168 = "16'b0000000011000111" *) (* LC_HIGH_BIT_POS_PROBE_OUT169 = "16'b0000000011001000" *) (* LC_HIGH_BIT_POS_PROBE_OUT17 = "16'b0000000000110000" *) -(* LC_HIGH_BIT_POS_PROBE_OUT170 = "16'b0000000011001001" *) (* LC_HIGH_BIT_POS_PROBE_OUT171 = "16'b0000000011001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT172 = "16'b0000000011001011" *) -(* LC_HIGH_BIT_POS_PROBE_OUT173 = "16'b0000000011001100" *) (* LC_HIGH_BIT_POS_PROBE_OUT174 = "16'b0000000011001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT175 = "16'b0000000011001110" *) -(* LC_HIGH_BIT_POS_PROBE_OUT176 = "16'b0000000011001111" *) (* LC_HIGH_BIT_POS_PROBE_OUT177 = "16'b0000000011010000" *) (* LC_HIGH_BIT_POS_PROBE_OUT178 = "16'b0000000011010001" *) -(* LC_HIGH_BIT_POS_PROBE_OUT179 = "16'b0000000011010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT18 = "16'b0000000000110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT180 = "16'b0000000011010011" *) -(* LC_HIGH_BIT_POS_PROBE_OUT181 = "16'b0000000011010100" *) (* LC_HIGH_BIT_POS_PROBE_OUT182 = "16'b0000000011010101" *) (* LC_HIGH_BIT_POS_PROBE_OUT183 = "16'b0000000011010110" *) -(* LC_HIGH_BIT_POS_PROBE_OUT184 = "16'b0000000011010111" *) (* LC_HIGH_BIT_POS_PROBE_OUT185 = "16'b0000000011011000" *) (* LC_HIGH_BIT_POS_PROBE_OUT186 = "16'b0000000011011001" *) -(* LC_HIGH_BIT_POS_PROBE_OUT187 = "16'b0000000011011010" *) (* LC_HIGH_BIT_POS_PROBE_OUT188 = "16'b0000000011011011" *) (* LC_HIGH_BIT_POS_PROBE_OUT189 = "16'b0000000011011100" *) -(* LC_HIGH_BIT_POS_PROBE_OUT19 = "16'b0000000000110010" *) (* LC_HIGH_BIT_POS_PROBE_OUT190 = "16'b0000000011011101" *) (* LC_HIGH_BIT_POS_PROBE_OUT191 = "16'b0000000011011110" *) -(* LC_HIGH_BIT_POS_PROBE_OUT192 = "16'b0000000011011111" *) (* LC_HIGH_BIT_POS_PROBE_OUT193 = "16'b0000000011100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT194 = "16'b0000000011100001" *) -(* LC_HIGH_BIT_POS_PROBE_OUT195 = "16'b0000000011100010" *) (* LC_HIGH_BIT_POS_PROBE_OUT196 = "16'b0000000011100011" *) (* LC_HIGH_BIT_POS_PROBE_OUT197 = "16'b0000000011100100" *) -(* LC_HIGH_BIT_POS_PROBE_OUT198 = "16'b0000000011100101" *) (* LC_HIGH_BIT_POS_PROBE_OUT199 = "16'b0000000011100110" *) (* LC_HIGH_BIT_POS_PROBE_OUT2 = "16'b0000000000100001" *) -(* LC_HIGH_BIT_POS_PROBE_OUT20 = "16'b0000000000110011" *) (* LC_HIGH_BIT_POS_PROBE_OUT200 = "16'b0000000011100111" *) (* LC_HIGH_BIT_POS_PROBE_OUT201 = "16'b0000000011101000" *) -(* LC_HIGH_BIT_POS_PROBE_OUT202 = "16'b0000000011101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT203 = "16'b0000000011101010" *) (* LC_HIGH_BIT_POS_PROBE_OUT204 = "16'b0000000011101011" *) -(* LC_HIGH_BIT_POS_PROBE_OUT205 = "16'b0000000011101100" *) (* LC_HIGH_BIT_POS_PROBE_OUT206 = "16'b0000000011101101" *) (* LC_HIGH_BIT_POS_PROBE_OUT207 = "16'b0000000011101110" *) -(* LC_HIGH_BIT_POS_PROBE_OUT208 = "16'b0000000011101111" *) (* LC_HIGH_BIT_POS_PROBE_OUT209 = "16'b0000000011110000" *) (* LC_HIGH_BIT_POS_PROBE_OUT21 = "16'b0000000000110100" *) -(* LC_HIGH_BIT_POS_PROBE_OUT210 = "16'b0000000011110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT211 = "16'b0000000011110010" *) (* LC_HIGH_BIT_POS_PROBE_OUT212 = "16'b0000000011110011" *) -(* LC_HIGH_BIT_POS_PROBE_OUT213 = "16'b0000000011110100" *) (* LC_HIGH_BIT_POS_PROBE_OUT214 = "16'b0000000011110101" *) (* LC_HIGH_BIT_POS_PROBE_OUT215 = "16'b0000000011110110" *) -(* LC_HIGH_BIT_POS_PROBE_OUT216 = "16'b0000000011110111" *) (* LC_HIGH_BIT_POS_PROBE_OUT217 = "16'b0000000011111000" *) (* LC_HIGH_BIT_POS_PROBE_OUT218 = "16'b0000000011111001" *) -(* LC_HIGH_BIT_POS_PROBE_OUT219 = "16'b0000000011111010" *) (* LC_HIGH_BIT_POS_PROBE_OUT22 = "16'b0000000000110101" *) (* LC_HIGH_BIT_POS_PROBE_OUT220 = "16'b0000000011111011" *) -(* LC_HIGH_BIT_POS_PROBE_OUT221 = "16'b0000000011111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT222 = "16'b0000000011111101" *) (* LC_HIGH_BIT_POS_PROBE_OUT223 = "16'b0000000011111110" *) -(* LC_HIGH_BIT_POS_PROBE_OUT224 = "16'b0000000011111111" *) (* LC_HIGH_BIT_POS_PROBE_OUT225 = "16'b0000000100000000" *) (* LC_HIGH_BIT_POS_PROBE_OUT226 = "16'b0000000100000001" *) -(* LC_HIGH_BIT_POS_PROBE_OUT227 = "16'b0000000100000010" *) (* LC_HIGH_BIT_POS_PROBE_OUT228 = "16'b0000000100000011" *) (* LC_HIGH_BIT_POS_PROBE_OUT229 = "16'b0000000100000100" *) -(* LC_HIGH_BIT_POS_PROBE_OUT23 = "16'b0000000000110110" *) (* LC_HIGH_BIT_POS_PROBE_OUT230 = "16'b0000000100000101" *) (* LC_HIGH_BIT_POS_PROBE_OUT231 = "16'b0000000100000110" *) -(* LC_HIGH_BIT_POS_PROBE_OUT232 = "16'b0000000100000111" *) (* LC_HIGH_BIT_POS_PROBE_OUT233 = "16'b0000000100001000" *) (* LC_HIGH_BIT_POS_PROBE_OUT234 = "16'b0000000100001001" *) -(* LC_HIGH_BIT_POS_PROBE_OUT235 = "16'b0000000100001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT236 = "16'b0000000100001011" *) (* LC_HIGH_BIT_POS_PROBE_OUT237 = "16'b0000000100001100" *) -(* LC_HIGH_BIT_POS_PROBE_OUT238 = "16'b0000000100001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT239 = "16'b0000000100001110" *) (* LC_HIGH_BIT_POS_PROBE_OUT24 = "16'b0000000000110111" *) -(* LC_HIGH_BIT_POS_PROBE_OUT240 = "16'b0000000100001111" *) (* LC_HIGH_BIT_POS_PROBE_OUT241 = "16'b0000000100010000" *) (* LC_HIGH_BIT_POS_PROBE_OUT242 = "16'b0000000100010001" *) -(* LC_HIGH_BIT_POS_PROBE_OUT243 = "16'b0000000100010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT244 = "16'b0000000100010011" *) (* LC_HIGH_BIT_POS_PROBE_OUT245 = "16'b0000000100010100" *) -(* LC_HIGH_BIT_POS_PROBE_OUT246 = "16'b0000000100010101" *) (* LC_HIGH_BIT_POS_PROBE_OUT247 = "16'b0000000100010110" *) (* LC_HIGH_BIT_POS_PROBE_OUT248 = "16'b0000000100010111" *) -(* LC_HIGH_BIT_POS_PROBE_OUT249 = "16'b0000000100011000" *) (* LC_HIGH_BIT_POS_PROBE_OUT25 = "16'b0000000000111000" *) (* LC_HIGH_BIT_POS_PROBE_OUT250 = "16'b0000000100011001" *) -(* LC_HIGH_BIT_POS_PROBE_OUT251 = "16'b0000000100011010" *) (* LC_HIGH_BIT_POS_PROBE_OUT252 = "16'b0000000100011011" *) (* LC_HIGH_BIT_POS_PROBE_OUT253 = "16'b0000000100011100" *) -(* LC_HIGH_BIT_POS_PROBE_OUT254 = "16'b0000000100011101" *) (* LC_HIGH_BIT_POS_PROBE_OUT255 = "16'b0000000100011110" *) (* LC_HIGH_BIT_POS_PROBE_OUT26 = "16'b0000000000111001" *) -(* LC_HIGH_BIT_POS_PROBE_OUT27 = "16'b0000000000111010" *) (* LC_HIGH_BIT_POS_PROBE_OUT28 = "16'b0000000000111011" *) (* LC_HIGH_BIT_POS_PROBE_OUT29 = "16'b0000000000111100" *) -(* LC_HIGH_BIT_POS_PROBE_OUT3 = "16'b0000000000100010" *) (* LC_HIGH_BIT_POS_PROBE_OUT30 = "16'b0000000000111101" *) (* LC_HIGH_BIT_POS_PROBE_OUT31 = "16'b0000000000111110" *) -(* LC_HIGH_BIT_POS_PROBE_OUT32 = "16'b0000000000111111" *) (* LC_HIGH_BIT_POS_PROBE_OUT33 = "16'b0000000001000000" *) (* LC_HIGH_BIT_POS_PROBE_OUT34 = "16'b0000000001000001" *) -(* LC_HIGH_BIT_POS_PROBE_OUT35 = "16'b0000000001000010" *) (* LC_HIGH_BIT_POS_PROBE_OUT36 = "16'b0000000001000011" *) (* LC_HIGH_BIT_POS_PROBE_OUT37 = "16'b0000000001000100" *) -(* LC_HIGH_BIT_POS_PROBE_OUT38 = "16'b0000000001000101" *) (* LC_HIGH_BIT_POS_PROBE_OUT39 = "16'b0000000001000110" *) (* LC_HIGH_BIT_POS_PROBE_OUT4 = "16'b0000000000100011" *) -(* LC_HIGH_BIT_POS_PROBE_OUT40 = "16'b0000000001000111" *) (* LC_HIGH_BIT_POS_PROBE_OUT41 = "16'b0000000001001000" *) (* LC_HIGH_BIT_POS_PROBE_OUT42 = "16'b0000000001001001" *) -(* LC_HIGH_BIT_POS_PROBE_OUT43 = "16'b0000000001001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT44 = "16'b0000000001001011" *) (* LC_HIGH_BIT_POS_PROBE_OUT45 = "16'b0000000001001100" *) -(* LC_HIGH_BIT_POS_PROBE_OUT46 = "16'b0000000001001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT47 = "16'b0000000001001110" *) (* LC_HIGH_BIT_POS_PROBE_OUT48 = "16'b0000000001001111" *) -(* LC_HIGH_BIT_POS_PROBE_OUT49 = "16'b0000000001010000" *) (* LC_HIGH_BIT_POS_PROBE_OUT5 = "16'b0000000000100100" *) (* LC_HIGH_BIT_POS_PROBE_OUT50 = "16'b0000000001010001" *) -(* LC_HIGH_BIT_POS_PROBE_OUT51 = "16'b0000000001010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT52 = "16'b0000000001010011" *) (* LC_HIGH_BIT_POS_PROBE_OUT53 = "16'b0000000001010100" *) -(* LC_HIGH_BIT_POS_PROBE_OUT54 = "16'b0000000001010101" *) (* LC_HIGH_BIT_POS_PROBE_OUT55 = "16'b0000000001010110" *) (* LC_HIGH_BIT_POS_PROBE_OUT56 = "16'b0000000001010111" *) -(* LC_HIGH_BIT_POS_PROBE_OUT57 = "16'b0000000001011000" *) (* LC_HIGH_BIT_POS_PROBE_OUT58 = "16'b0000000001011001" *) (* LC_HIGH_BIT_POS_PROBE_OUT59 = "16'b0000000001011010" *) -(* LC_HIGH_BIT_POS_PROBE_OUT6 = "16'b0000000000100101" *) (* LC_HIGH_BIT_POS_PROBE_OUT60 = "16'b0000000001011011" *) (* LC_HIGH_BIT_POS_PROBE_OUT61 = "16'b0000000001011100" *) -(* LC_HIGH_BIT_POS_PROBE_OUT62 = "16'b0000000001011101" *) (* LC_HIGH_BIT_POS_PROBE_OUT63 = "16'b0000000001011110" *) (* LC_HIGH_BIT_POS_PROBE_OUT64 = "16'b0000000001011111" *) -(* LC_HIGH_BIT_POS_PROBE_OUT65 = "16'b0000000001100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT66 = "16'b0000000001100001" *) (* LC_HIGH_BIT_POS_PROBE_OUT67 = "16'b0000000001100010" *) -(* LC_HIGH_BIT_POS_PROBE_OUT68 = "16'b0000000001100011" *) (* LC_HIGH_BIT_POS_PROBE_OUT69 = "16'b0000000001100100" *) (* LC_HIGH_BIT_POS_PROBE_OUT7 = "16'b0000000000100110" *) -(* LC_HIGH_BIT_POS_PROBE_OUT70 = "16'b0000000001100101" *) (* LC_HIGH_BIT_POS_PROBE_OUT71 = "16'b0000000001100110" *) (* LC_HIGH_BIT_POS_PROBE_OUT72 = "16'b0000000001100111" *) -(* LC_HIGH_BIT_POS_PROBE_OUT73 = "16'b0000000001101000" *) (* LC_HIGH_BIT_POS_PROBE_OUT74 = "16'b0000000001101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT75 = "16'b0000000001101010" *) -(* LC_HIGH_BIT_POS_PROBE_OUT76 = "16'b0000000001101011" *) (* LC_HIGH_BIT_POS_PROBE_OUT77 = "16'b0000000001101100" *) (* LC_HIGH_BIT_POS_PROBE_OUT78 = "16'b0000000001101101" *) -(* LC_HIGH_BIT_POS_PROBE_OUT79 = "16'b0000000001101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT8 = "16'b0000000000100111" *) (* LC_HIGH_BIT_POS_PROBE_OUT80 = "16'b0000000001101111" *) -(* LC_HIGH_BIT_POS_PROBE_OUT81 = "16'b0000000001110000" *) (* LC_HIGH_BIT_POS_PROBE_OUT82 = "16'b0000000001110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT83 = "16'b0000000001110010" *) -(* LC_HIGH_BIT_POS_PROBE_OUT84 = "16'b0000000001110011" *) (* LC_HIGH_BIT_POS_PROBE_OUT85 = "16'b0000000001110100" *) (* LC_HIGH_BIT_POS_PROBE_OUT86 = "16'b0000000001110101" *) -(* LC_HIGH_BIT_POS_PROBE_OUT87 = "16'b0000000001110110" *) (* LC_HIGH_BIT_POS_PROBE_OUT88 = "16'b0000000001110111" *) (* LC_HIGH_BIT_POS_PROBE_OUT89 = "16'b0000000001111000" *) -(* LC_HIGH_BIT_POS_PROBE_OUT9 = "16'b0000000000101000" *) (* LC_HIGH_BIT_POS_PROBE_OUT90 = "16'b0000000001111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT91 = "16'b0000000001111010" *) -(* LC_HIGH_BIT_POS_PROBE_OUT92 = "16'b0000000001111011" *) (* LC_HIGH_BIT_POS_PROBE_OUT93 = "16'b0000000001111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT94 = "16'b0000000001111101" *) -(* LC_HIGH_BIT_POS_PROBE_OUT95 = "16'b0000000001111110" *) (* LC_HIGH_BIT_POS_PROBE_OUT96 = "16'b0000000001111111" *) (* LC_HIGH_BIT_POS_PROBE_OUT97 = "16'b0000000010000000" *) -(* LC_HIGH_BIT_POS_PROBE_OUT98 = "16'b0000000010000001" *) (* LC_HIGH_BIT_POS_PROBE_OUT99 = "16'b0000000010000010" *) (* LC_LOW_BIT_POS_PROBE_OUT0 = "16'b0000000000000000" *) -(* LC_LOW_BIT_POS_PROBE_OUT1 = "16'b0000000000100000" *) (* LC_LOW_BIT_POS_PROBE_OUT10 = "16'b0000000000101001" *) (* LC_LOW_BIT_POS_PROBE_OUT100 = "16'b0000000010000011" *) -(* LC_LOW_BIT_POS_PROBE_OUT101 = "16'b0000000010000100" *) (* LC_LOW_BIT_POS_PROBE_OUT102 = "16'b0000000010000101" *) (* LC_LOW_BIT_POS_PROBE_OUT103 = "16'b0000000010000110" *) -(* LC_LOW_BIT_POS_PROBE_OUT104 = "16'b0000000010000111" *) (* LC_LOW_BIT_POS_PROBE_OUT105 = "16'b0000000010001000" *) (* LC_LOW_BIT_POS_PROBE_OUT106 = "16'b0000000010001001" *) -(* LC_LOW_BIT_POS_PROBE_OUT107 = "16'b0000000010001010" *) (* LC_LOW_BIT_POS_PROBE_OUT108 = "16'b0000000010001011" *) (* LC_LOW_BIT_POS_PROBE_OUT109 = "16'b0000000010001100" *) -(* LC_LOW_BIT_POS_PROBE_OUT11 = "16'b0000000000101010" *) (* LC_LOW_BIT_POS_PROBE_OUT110 = "16'b0000000010001101" *) (* LC_LOW_BIT_POS_PROBE_OUT111 = "16'b0000000010001110" *) -(* LC_LOW_BIT_POS_PROBE_OUT112 = "16'b0000000010001111" *) (* LC_LOW_BIT_POS_PROBE_OUT113 = "16'b0000000010010000" *) (* LC_LOW_BIT_POS_PROBE_OUT114 = "16'b0000000010010001" *) -(* LC_LOW_BIT_POS_PROBE_OUT115 = "16'b0000000010010010" *) (* LC_LOW_BIT_POS_PROBE_OUT116 = "16'b0000000010010011" *) (* LC_LOW_BIT_POS_PROBE_OUT117 = "16'b0000000010010100" *) -(* LC_LOW_BIT_POS_PROBE_OUT118 = "16'b0000000010010101" *) (* LC_LOW_BIT_POS_PROBE_OUT119 = "16'b0000000010010110" *) (* LC_LOW_BIT_POS_PROBE_OUT12 = "16'b0000000000101011" *) -(* LC_LOW_BIT_POS_PROBE_OUT120 = "16'b0000000010010111" *) (* LC_LOW_BIT_POS_PROBE_OUT121 = "16'b0000000010011000" *) (* LC_LOW_BIT_POS_PROBE_OUT122 = "16'b0000000010011001" *) -(* LC_LOW_BIT_POS_PROBE_OUT123 = "16'b0000000010011010" *) (* LC_LOW_BIT_POS_PROBE_OUT124 = "16'b0000000010011011" *) (* LC_LOW_BIT_POS_PROBE_OUT125 = "16'b0000000010011100" *) -(* LC_LOW_BIT_POS_PROBE_OUT126 = "16'b0000000010011101" *) (* LC_LOW_BIT_POS_PROBE_OUT127 = "16'b0000000010011110" *) (* LC_LOW_BIT_POS_PROBE_OUT128 = "16'b0000000010011111" *) -(* LC_LOW_BIT_POS_PROBE_OUT129 = "16'b0000000010100000" *) (* LC_LOW_BIT_POS_PROBE_OUT13 = "16'b0000000000101100" *) (* LC_LOW_BIT_POS_PROBE_OUT130 = "16'b0000000010100001" *) -(* LC_LOW_BIT_POS_PROBE_OUT131 = "16'b0000000010100010" *) (* LC_LOW_BIT_POS_PROBE_OUT132 = "16'b0000000010100011" *) (* LC_LOW_BIT_POS_PROBE_OUT133 = "16'b0000000010100100" *) -(* LC_LOW_BIT_POS_PROBE_OUT134 = "16'b0000000010100101" *) (* LC_LOW_BIT_POS_PROBE_OUT135 = "16'b0000000010100110" *) (* LC_LOW_BIT_POS_PROBE_OUT136 = "16'b0000000010100111" *) -(* LC_LOW_BIT_POS_PROBE_OUT137 = "16'b0000000010101000" *) (* LC_LOW_BIT_POS_PROBE_OUT138 = "16'b0000000010101001" *) (* LC_LOW_BIT_POS_PROBE_OUT139 = "16'b0000000010101010" *) -(* LC_LOW_BIT_POS_PROBE_OUT14 = "16'b0000000000101101" *) (* LC_LOW_BIT_POS_PROBE_OUT140 = "16'b0000000010101011" *) (* LC_LOW_BIT_POS_PROBE_OUT141 = "16'b0000000010101100" *) -(* LC_LOW_BIT_POS_PROBE_OUT142 = "16'b0000000010101101" *) (* LC_LOW_BIT_POS_PROBE_OUT143 = "16'b0000000010101110" *) (* LC_LOW_BIT_POS_PROBE_OUT144 = "16'b0000000010101111" *) -(* LC_LOW_BIT_POS_PROBE_OUT145 = "16'b0000000010110000" *) (* LC_LOW_BIT_POS_PROBE_OUT146 = "16'b0000000010110001" *) (* LC_LOW_BIT_POS_PROBE_OUT147 = "16'b0000000010110010" *) -(* LC_LOW_BIT_POS_PROBE_OUT148 = "16'b0000000010110011" *) (* LC_LOW_BIT_POS_PROBE_OUT149 = "16'b0000000010110100" *) (* LC_LOW_BIT_POS_PROBE_OUT15 = "16'b0000000000101110" *) -(* LC_LOW_BIT_POS_PROBE_OUT150 = "16'b0000000010110101" *) (* LC_LOW_BIT_POS_PROBE_OUT151 = "16'b0000000010110110" *) (* LC_LOW_BIT_POS_PROBE_OUT152 = "16'b0000000010110111" *) -(* LC_LOW_BIT_POS_PROBE_OUT153 = "16'b0000000010111000" *) (* LC_LOW_BIT_POS_PROBE_OUT154 = "16'b0000000010111001" *) (* LC_LOW_BIT_POS_PROBE_OUT155 = "16'b0000000010111010" *) -(* LC_LOW_BIT_POS_PROBE_OUT156 = "16'b0000000010111011" *) (* LC_LOW_BIT_POS_PROBE_OUT157 = "16'b0000000010111100" *) (* LC_LOW_BIT_POS_PROBE_OUT158 = "16'b0000000010111101" *) -(* LC_LOW_BIT_POS_PROBE_OUT159 = "16'b0000000010111110" *) (* LC_LOW_BIT_POS_PROBE_OUT16 = "16'b0000000000101111" *) (* LC_LOW_BIT_POS_PROBE_OUT160 = "16'b0000000010111111" *) -(* LC_LOW_BIT_POS_PROBE_OUT161 = "16'b0000000011000000" *) (* LC_LOW_BIT_POS_PROBE_OUT162 = "16'b0000000011000001" *) (* LC_LOW_BIT_POS_PROBE_OUT163 = "16'b0000000011000010" *) -(* LC_LOW_BIT_POS_PROBE_OUT164 = "16'b0000000011000011" *) (* LC_LOW_BIT_POS_PROBE_OUT165 = "16'b0000000011000100" *) (* LC_LOW_BIT_POS_PROBE_OUT166 = "16'b0000000011000101" *) -(* LC_LOW_BIT_POS_PROBE_OUT167 = "16'b0000000011000110" *) (* LC_LOW_BIT_POS_PROBE_OUT168 = "16'b0000000011000111" *) (* LC_LOW_BIT_POS_PROBE_OUT169 = "16'b0000000011001000" *) -(* LC_LOW_BIT_POS_PROBE_OUT17 = "16'b0000000000110000" *) (* LC_LOW_BIT_POS_PROBE_OUT170 = "16'b0000000011001001" *) (* LC_LOW_BIT_POS_PROBE_OUT171 = "16'b0000000011001010" *) -(* LC_LOW_BIT_POS_PROBE_OUT172 = "16'b0000000011001011" *) (* LC_LOW_BIT_POS_PROBE_OUT173 = "16'b0000000011001100" *) (* LC_LOW_BIT_POS_PROBE_OUT174 = "16'b0000000011001101" *) -(* LC_LOW_BIT_POS_PROBE_OUT175 = "16'b0000000011001110" *) (* LC_LOW_BIT_POS_PROBE_OUT176 = "16'b0000000011001111" *) (* LC_LOW_BIT_POS_PROBE_OUT177 = "16'b0000000011010000" *) -(* LC_LOW_BIT_POS_PROBE_OUT178 = "16'b0000000011010001" *) (* LC_LOW_BIT_POS_PROBE_OUT179 = "16'b0000000011010010" *) (* LC_LOW_BIT_POS_PROBE_OUT18 = "16'b0000000000110001" *) -(* LC_LOW_BIT_POS_PROBE_OUT180 = "16'b0000000011010011" *) (* LC_LOW_BIT_POS_PROBE_OUT181 = "16'b0000000011010100" *) (* LC_LOW_BIT_POS_PROBE_OUT182 = "16'b0000000011010101" *) -(* LC_LOW_BIT_POS_PROBE_OUT183 = "16'b0000000011010110" *) (* LC_LOW_BIT_POS_PROBE_OUT184 = "16'b0000000011010111" *) (* LC_LOW_BIT_POS_PROBE_OUT185 = "16'b0000000011011000" *) -(* LC_LOW_BIT_POS_PROBE_OUT186 = "16'b0000000011011001" *) (* LC_LOW_BIT_POS_PROBE_OUT187 = "16'b0000000011011010" *) (* LC_LOW_BIT_POS_PROBE_OUT188 = "16'b0000000011011011" *) -(* LC_LOW_BIT_POS_PROBE_OUT189 = "16'b0000000011011100" *) (* LC_LOW_BIT_POS_PROBE_OUT19 = "16'b0000000000110010" *) (* LC_LOW_BIT_POS_PROBE_OUT190 = "16'b0000000011011101" *) -(* LC_LOW_BIT_POS_PROBE_OUT191 = "16'b0000000011011110" *) (* LC_LOW_BIT_POS_PROBE_OUT192 = "16'b0000000011011111" *) (* LC_LOW_BIT_POS_PROBE_OUT193 = "16'b0000000011100000" *) -(* LC_LOW_BIT_POS_PROBE_OUT194 = "16'b0000000011100001" *) (* LC_LOW_BIT_POS_PROBE_OUT195 = "16'b0000000011100010" *) (* LC_LOW_BIT_POS_PROBE_OUT196 = "16'b0000000011100011" *) -(* LC_LOW_BIT_POS_PROBE_OUT197 = "16'b0000000011100100" *) (* LC_LOW_BIT_POS_PROBE_OUT198 = "16'b0000000011100101" *) (* LC_LOW_BIT_POS_PROBE_OUT199 = "16'b0000000011100110" *) -(* LC_LOW_BIT_POS_PROBE_OUT2 = "16'b0000000000100001" *) (* LC_LOW_BIT_POS_PROBE_OUT20 = "16'b0000000000110011" *) (* LC_LOW_BIT_POS_PROBE_OUT200 = "16'b0000000011100111" *) -(* LC_LOW_BIT_POS_PROBE_OUT201 = "16'b0000000011101000" *) (* LC_LOW_BIT_POS_PROBE_OUT202 = "16'b0000000011101001" *) (* LC_LOW_BIT_POS_PROBE_OUT203 = "16'b0000000011101010" *) -(* LC_LOW_BIT_POS_PROBE_OUT204 = "16'b0000000011101011" *) (* LC_LOW_BIT_POS_PROBE_OUT205 = "16'b0000000011101100" *) (* LC_LOW_BIT_POS_PROBE_OUT206 = "16'b0000000011101101" *) -(* LC_LOW_BIT_POS_PROBE_OUT207 = "16'b0000000011101110" *) (* LC_LOW_BIT_POS_PROBE_OUT208 = "16'b0000000011101111" *) (* LC_LOW_BIT_POS_PROBE_OUT209 = "16'b0000000011110000" *) -(* LC_LOW_BIT_POS_PROBE_OUT21 = "16'b0000000000110100" *) (* LC_LOW_BIT_POS_PROBE_OUT210 = "16'b0000000011110001" *) (* LC_LOW_BIT_POS_PROBE_OUT211 = "16'b0000000011110010" *) -(* LC_LOW_BIT_POS_PROBE_OUT212 = "16'b0000000011110011" *) (* LC_LOW_BIT_POS_PROBE_OUT213 = "16'b0000000011110100" *) (* LC_LOW_BIT_POS_PROBE_OUT214 = "16'b0000000011110101" *) -(* LC_LOW_BIT_POS_PROBE_OUT215 = "16'b0000000011110110" *) (* LC_LOW_BIT_POS_PROBE_OUT216 = "16'b0000000011110111" *) (* LC_LOW_BIT_POS_PROBE_OUT217 = "16'b0000000011111000" *) -(* LC_LOW_BIT_POS_PROBE_OUT218 = "16'b0000000011111001" *) (* LC_LOW_BIT_POS_PROBE_OUT219 = "16'b0000000011111010" *) (* LC_LOW_BIT_POS_PROBE_OUT22 = "16'b0000000000110101" *) -(* LC_LOW_BIT_POS_PROBE_OUT220 = "16'b0000000011111011" *) (* LC_LOW_BIT_POS_PROBE_OUT221 = "16'b0000000011111100" *) (* LC_LOW_BIT_POS_PROBE_OUT222 = "16'b0000000011111101" *) -(* LC_LOW_BIT_POS_PROBE_OUT223 = "16'b0000000011111110" *) (* LC_LOW_BIT_POS_PROBE_OUT224 = "16'b0000000011111111" *) (* LC_LOW_BIT_POS_PROBE_OUT225 = "16'b0000000100000000" *) -(* LC_LOW_BIT_POS_PROBE_OUT226 = "16'b0000000100000001" *) (* LC_LOW_BIT_POS_PROBE_OUT227 = "16'b0000000100000010" *) (* LC_LOW_BIT_POS_PROBE_OUT228 = "16'b0000000100000011" *) -(* LC_LOW_BIT_POS_PROBE_OUT229 = "16'b0000000100000100" *) (* LC_LOW_BIT_POS_PROBE_OUT23 = "16'b0000000000110110" *) (* LC_LOW_BIT_POS_PROBE_OUT230 = "16'b0000000100000101" *) -(* LC_LOW_BIT_POS_PROBE_OUT231 = "16'b0000000100000110" *) (* LC_LOW_BIT_POS_PROBE_OUT232 = "16'b0000000100000111" *) (* LC_LOW_BIT_POS_PROBE_OUT233 = "16'b0000000100001000" *) -(* LC_LOW_BIT_POS_PROBE_OUT234 = "16'b0000000100001001" *) (* LC_LOW_BIT_POS_PROBE_OUT235 = "16'b0000000100001010" *) (* LC_LOW_BIT_POS_PROBE_OUT236 = "16'b0000000100001011" *) -(* LC_LOW_BIT_POS_PROBE_OUT237 = "16'b0000000100001100" *) (* LC_LOW_BIT_POS_PROBE_OUT238 = "16'b0000000100001101" *) (* LC_LOW_BIT_POS_PROBE_OUT239 = "16'b0000000100001110" *) -(* LC_LOW_BIT_POS_PROBE_OUT24 = "16'b0000000000110111" *) (* LC_LOW_BIT_POS_PROBE_OUT240 = "16'b0000000100001111" *) (* LC_LOW_BIT_POS_PROBE_OUT241 = "16'b0000000100010000" *) -(* LC_LOW_BIT_POS_PROBE_OUT242 = "16'b0000000100010001" *) (* LC_LOW_BIT_POS_PROBE_OUT243 = "16'b0000000100010010" *) (* LC_LOW_BIT_POS_PROBE_OUT244 = "16'b0000000100010011" *) -(* LC_LOW_BIT_POS_PROBE_OUT245 = "16'b0000000100010100" *) (* LC_LOW_BIT_POS_PROBE_OUT246 = "16'b0000000100010101" *) (* LC_LOW_BIT_POS_PROBE_OUT247 = "16'b0000000100010110" *) -(* LC_LOW_BIT_POS_PROBE_OUT248 = "16'b0000000100010111" *) (* LC_LOW_BIT_POS_PROBE_OUT249 = "16'b0000000100011000" *) (* LC_LOW_BIT_POS_PROBE_OUT25 = "16'b0000000000111000" *) -(* LC_LOW_BIT_POS_PROBE_OUT250 = "16'b0000000100011001" *) (* LC_LOW_BIT_POS_PROBE_OUT251 = "16'b0000000100011010" *) (* LC_LOW_BIT_POS_PROBE_OUT252 = "16'b0000000100011011" *) -(* LC_LOW_BIT_POS_PROBE_OUT253 = "16'b0000000100011100" *) (* LC_LOW_BIT_POS_PROBE_OUT254 = "16'b0000000100011101" *) (* LC_LOW_BIT_POS_PROBE_OUT255 = "16'b0000000100011110" *) -(* LC_LOW_BIT_POS_PROBE_OUT26 = "16'b0000000000111001" *) (* LC_LOW_BIT_POS_PROBE_OUT27 = "16'b0000000000111010" *) (* LC_LOW_BIT_POS_PROBE_OUT28 = "16'b0000000000111011" *) -(* LC_LOW_BIT_POS_PROBE_OUT29 = "16'b0000000000111100" *) (* LC_LOW_BIT_POS_PROBE_OUT3 = "16'b0000000000100010" *) (* LC_LOW_BIT_POS_PROBE_OUT30 = "16'b0000000000111101" *) -(* LC_LOW_BIT_POS_PROBE_OUT31 = "16'b0000000000111110" *) (* LC_LOW_BIT_POS_PROBE_OUT32 = "16'b0000000000111111" *) (* LC_LOW_BIT_POS_PROBE_OUT33 = "16'b0000000001000000" *) -(* LC_LOW_BIT_POS_PROBE_OUT34 = "16'b0000000001000001" *) (* LC_LOW_BIT_POS_PROBE_OUT35 = "16'b0000000001000010" *) (* LC_LOW_BIT_POS_PROBE_OUT36 = "16'b0000000001000011" *) -(* LC_LOW_BIT_POS_PROBE_OUT37 = "16'b0000000001000100" *) (* LC_LOW_BIT_POS_PROBE_OUT38 = "16'b0000000001000101" *) (* LC_LOW_BIT_POS_PROBE_OUT39 = "16'b0000000001000110" *) -(* LC_LOW_BIT_POS_PROBE_OUT4 = "16'b0000000000100011" *) (* LC_LOW_BIT_POS_PROBE_OUT40 = "16'b0000000001000111" *) (* LC_LOW_BIT_POS_PROBE_OUT41 = "16'b0000000001001000" *) -(* LC_LOW_BIT_POS_PROBE_OUT42 = "16'b0000000001001001" *) (* LC_LOW_BIT_POS_PROBE_OUT43 = "16'b0000000001001010" *) (* LC_LOW_BIT_POS_PROBE_OUT44 = "16'b0000000001001011" *) -(* LC_LOW_BIT_POS_PROBE_OUT45 = "16'b0000000001001100" *) (* LC_LOW_BIT_POS_PROBE_OUT46 = "16'b0000000001001101" *) (* LC_LOW_BIT_POS_PROBE_OUT47 = "16'b0000000001001110" *) -(* LC_LOW_BIT_POS_PROBE_OUT48 = "16'b0000000001001111" *) (* LC_LOW_BIT_POS_PROBE_OUT49 = "16'b0000000001010000" *) (* LC_LOW_BIT_POS_PROBE_OUT5 = "16'b0000000000100100" *) -(* LC_LOW_BIT_POS_PROBE_OUT50 = "16'b0000000001010001" *) (* LC_LOW_BIT_POS_PROBE_OUT51 = "16'b0000000001010010" *) (* LC_LOW_BIT_POS_PROBE_OUT52 = "16'b0000000001010011" *) -(* LC_LOW_BIT_POS_PROBE_OUT53 = "16'b0000000001010100" *) (* LC_LOW_BIT_POS_PROBE_OUT54 = "16'b0000000001010101" *) (* LC_LOW_BIT_POS_PROBE_OUT55 = "16'b0000000001010110" *) -(* LC_LOW_BIT_POS_PROBE_OUT56 = "16'b0000000001010111" *) (* LC_LOW_BIT_POS_PROBE_OUT57 = "16'b0000000001011000" *) (* LC_LOW_BIT_POS_PROBE_OUT58 = "16'b0000000001011001" *) -(* LC_LOW_BIT_POS_PROBE_OUT59 = "16'b0000000001011010" *) (* LC_LOW_BIT_POS_PROBE_OUT6 = "16'b0000000000100101" *) (* LC_LOW_BIT_POS_PROBE_OUT60 = "16'b0000000001011011" *) -(* LC_LOW_BIT_POS_PROBE_OUT61 = "16'b0000000001011100" *) (* LC_LOW_BIT_POS_PROBE_OUT62 = "16'b0000000001011101" *) (* LC_LOW_BIT_POS_PROBE_OUT63 = "16'b0000000001011110" *) -(* LC_LOW_BIT_POS_PROBE_OUT64 = "16'b0000000001011111" *) (* LC_LOW_BIT_POS_PROBE_OUT65 = "16'b0000000001100000" *) (* LC_LOW_BIT_POS_PROBE_OUT66 = "16'b0000000001100001" *) -(* LC_LOW_BIT_POS_PROBE_OUT67 = "16'b0000000001100010" *) (* LC_LOW_BIT_POS_PROBE_OUT68 = "16'b0000000001100011" *) (* LC_LOW_BIT_POS_PROBE_OUT69 = "16'b0000000001100100" *) -(* LC_LOW_BIT_POS_PROBE_OUT7 = "16'b0000000000100110" *) (* LC_LOW_BIT_POS_PROBE_OUT70 = "16'b0000000001100101" *) (* LC_LOW_BIT_POS_PROBE_OUT71 = "16'b0000000001100110" *) -(* LC_LOW_BIT_POS_PROBE_OUT72 = "16'b0000000001100111" *) (* LC_LOW_BIT_POS_PROBE_OUT73 = "16'b0000000001101000" *) (* LC_LOW_BIT_POS_PROBE_OUT74 = "16'b0000000001101001" *) -(* LC_LOW_BIT_POS_PROBE_OUT75 = "16'b0000000001101010" *) (* LC_LOW_BIT_POS_PROBE_OUT76 = "16'b0000000001101011" *) (* LC_LOW_BIT_POS_PROBE_OUT77 = "16'b0000000001101100" *) -(* LC_LOW_BIT_POS_PROBE_OUT78 = "16'b0000000001101101" *) (* LC_LOW_BIT_POS_PROBE_OUT79 = "16'b0000000001101110" *) (* LC_LOW_BIT_POS_PROBE_OUT8 = "16'b0000000000100111" *) -(* LC_LOW_BIT_POS_PROBE_OUT80 = "16'b0000000001101111" *) (* LC_LOW_BIT_POS_PROBE_OUT81 = "16'b0000000001110000" *) (* LC_LOW_BIT_POS_PROBE_OUT82 = "16'b0000000001110001" *) -(* LC_LOW_BIT_POS_PROBE_OUT83 = "16'b0000000001110010" *) (* LC_LOW_BIT_POS_PROBE_OUT84 = "16'b0000000001110011" *) (* LC_LOW_BIT_POS_PROBE_OUT85 = "16'b0000000001110100" *) -(* LC_LOW_BIT_POS_PROBE_OUT86 = "16'b0000000001110101" *) (* LC_LOW_BIT_POS_PROBE_OUT87 = "16'b0000000001110110" *) (* LC_LOW_BIT_POS_PROBE_OUT88 = "16'b0000000001110111" *) -(* LC_LOW_BIT_POS_PROBE_OUT89 = "16'b0000000001111000" *) (* LC_LOW_BIT_POS_PROBE_OUT9 = "16'b0000000000101000" *) (* LC_LOW_BIT_POS_PROBE_OUT90 = "16'b0000000001111001" *) -(* LC_LOW_BIT_POS_PROBE_OUT91 = "16'b0000000001111010" *) (* LC_LOW_BIT_POS_PROBE_OUT92 = "16'b0000000001111011" *) (* LC_LOW_BIT_POS_PROBE_OUT93 = "16'b0000000001111100" *) -(* LC_LOW_BIT_POS_PROBE_OUT94 = "16'b0000000001111101" *) (* LC_LOW_BIT_POS_PROBE_OUT95 = "16'b0000000001111110" *) (* LC_LOW_BIT_POS_PROBE_OUT96 = "16'b0000000001111111" *) -(* LC_LOW_BIT_POS_PROBE_OUT97 = "16'b0000000010000000" *) (* LC_LOW_BIT_POS_PROBE_OUT98 = "16'b0000000010000001" *) (* LC_LOW_BIT_POS_PROBE_OUT99 = "16'b0000000010000010" *) -(* LC_PROBE_IN_WIDTH_STRING = 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*) (* LC_PROBE_OUT_HIGH_BIT_POS_STRING = "4096'b0000000100011110000000010001110100000001000111000000000100011011000000010001101000000001000110010000000100011000000000010001011100000001000101100000000100010101000000010001010000000001000100110000000100010010000000010001000100000001000100000000000100001111000000010000111000000001000011010000000100001100000000010000101100000001000010100000000100001001000000010000100000000001000001110000000100000110000000010000010100000001000001000000000100000011000000010000001000000001000000010000000100000000000000001111111100000000111111100000000011111101000000001111110000000000111110110000000011111010000000001111100100000000111110000000000011110111000000001111011000000000111101010000000011110100000000001111001100000000111100100000000011110001000000001111000000000000111011110000000011101110000000001110110100000000111011000000000011101011000000001110101000000000111010010000000011101000000000001110011100000000111001100000000011100101000000001110010000000000111000110000000011100010000000001110000100000000111000000000000011011111000000001101111000000000110111010000000011011100000000001101101100000000110110100000000011011001000000001101100000000000110101110000000011010110000000001101010100000000110101000000000011010011000000001101001000000000110100010000000011010000000000001100111100000000110011100000000011001101000000001100110000000000110010110000000011001010000000001100100100000000110010000000000011000111000000001100011000000000110001010000000011000100000000001100001100000000110000100000000011000001000000001100000000000000101111110000000010111110000000001011110100000000101111000000000010111011000000001011101000000000101110010000000010111000000000001011011100000000101101100000000010110101000000001011010000000000101100110000000010110010000000001011000100000000101100000000000010101111000000001010111000000000101011010000000010101100000000001010101100000000101010100000000010101001000000001010100000000000101001110000000010100110000000001010010100000000101001000000000010100011000000001010001000000000101000010000000010100000000000001001111100000000100111100000000010011101000000001001110000000000100110110000000010011010000000001001100100000000100110000000000010010111000000001001011000000000100101010000000010010100000000001001001100000000100100100000000010010001000000001001000000000000100011110000000010001110000000001000110100000000100011000000000010001011000000001000101000000000100010010000000010001000000000001000011100000000100001100000000010000101000000001000010000000000100000110000000010000010000000001000000100000000100000000000000001111111000000000111111000000000011111010000000001111100000000000111101100000000011110100000000001111001000000000111100000000000011101110000000001110110000000000111010100000000011101000000000001110011000000000111001000000000011100010000000001110000000000000110111100000000011011100000000001101101000000000110110000000000011010110000000001101010000000000110100100000000011010000000000001100111000000000110011000000000011001010000000001100100000000000110001100000000011000100000000001100001000000000110000000000000010111110000000001011110000000000101110100000000010111000000000001011011000000000101101000000000010110010000000001011000000000000101011100000000010101100000000001010101000000000101010000000000010100110000000001010010000000000101000100000000010100000000000001001111000000000100111000000000010011010000000001001100000000000100101100000000010010100000000001001001000000000100100000000000010001110000000001000110000000000100010100000000010001000000000001000011000000000100001000000000010000010000000001000000000000000011111100000000001111100000000000111101000000000011110000000000001110110000000000111010000000000011100100000000001110000000000000110111000000000011011000000000001101010000000000110100000000000011001100000000001100100000000000110001000000000011000000000000001011110000000000101110000000000010110100000000001011000000000000101011000000000010101000000000001010010000000000101000000000000010011100000000001001100000000000100101000000000010010000000000001000110000000000100010000000000010000100000000001000000000000000011111" *) (* LC_PROBE_OUT_INIT_VAL_STRING = "287'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) -(* LC_PROBE_OUT_LOW_BIT_POS_STRING = "4096'b0000000100011110000000010001110100000001000111000000000100011011000000010001101000000001000110010000000100011000000000010001011100000001000101100000000100010101000000010001010000000001000100110000000100010010000000010001000100000001000100000000000100001111000000010000111000000001000011010000000100001100000000010000101100000001000010100000000100001001000000010000100000000001000001110000000100000110000000010000010100000001000001000000000100000011000000010000001000000001000000010000000100000000000000001111111100000000111111100000000011111101000000001111110000000000111110110000000011111010000000001111100100000000111110000000000011110111000000001111011000000000111101010000000011110100000000001111001100000000111100100000000011110001000000001111000000000000111011110000000011101110000000001110110100000000111011000000000011101011000000001110101000000000111010010000000011101000000000001110011100000000111001100000000011100101000000001110010000000000111000110000000011100010000000001110000100000000111000000000000011011111000000001101111000000000110111010000000011011100000000001101101100000000110110100000000011011001000000001101100000000000110101110000000011010110000000001101010100000000110101000000000011010011000000001101001000000000110100010000000011010000000000001100111100000000110011100000000011001101000000001100110000000000110010110000000011001010000000001100100100000000110010000000000011000111000000001100011000000000110001010000000011000100000000001100001100000000110000100000000011000001000000001100000000000000101111110000000010111110000000001011110100000000101111000000000010111011000000001011101000000000101110010000000010111000000000001011011100000000101101100000000010110101000000001011010000000000101100110000000010110010000000001011000100000000101100000000000010101111000000001010111000000000101011010000000010101100000000001010101100000000101010100000000010101001000000001010100000000000101001110000000010100110000000001010010100000000101001000000000010100011000000001010001000000000101000010000000010100000000000001001111100000000100111100000000010011101000000001001110000000000100110110000000010011010000000001001100100000000100110000000000010010111000000001001011000000000100101010000000010010100000000001001001100000000100100100000000010010001000000001001000000000000100011110000000010001110000000001000110100000000100011000000000010001011000000001000101000000000100010010000000010001000000000001000011100000000100001100000000010000101000000001000010000000000100000110000000010000010000000001000000100000000100000000000000001111111000000000111111000000000011111010000000001111100000000000111101100000000011110100000000001111001000000000111100000000000011101110000000001110110000000000111010100000000011101000000000001110011000000000111001000000000011100010000000001110000000000000110111100000000011011100000000001101101000000000110110000000000011010110000000001101010000000000110100100000000011010000000000001100111000000000110011000000000011001010000000001100100000000000110001100000000011000100000000001100001000000000110000000000000010111110000000001011110000000000101110100000000010111000000000001011011000000000101101000000000010110010000000001011000000000000101011100000000010101100000000001010101000000000101010000000000010100110000000001010010000000000101000100000000010100000000000001001111000000000100111000000000010011010000000001001100000000000100101100000000010010100000000001001001000000000100100000000000010001110000000001000110000000000100010100000000010001000000000001000011000000000100001000000000010000010000000001000000000000000011111100000000001111100000000000111101000000000011110000000000001110110000000000111010000000000011100100000000001110000000000000110111000000000011011000000000001101010000000000110100000000000011001100000000001100100000000000110001000000000011000000000000001011110000000000101110000000000010110100000000001011000000000000101011000000000010101000000000001010010000000000101000000000000010011100000000001001100000000000100101000000000010010000000000001000110000000000100010000000000010000100000000001000000000000000000000" *) (* LC_PROBE_OUT_WIDTH_STRING = "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111" *) (* LC_TOTAL_PROBE_IN_WIDTH = "64" *) -(* LC_TOTAL_PROBE_OUT_WIDTH = "32" *) (* ORIG_REF_NAME = "vio_v3_0_19_vio" *) (* dont_touch = "true" *) -module vio_0_vio_v3_0_19_vio - (clk, - probe_in0, - probe_in1, - probe_in2, - probe_in3, - probe_in4, - probe_in5, - probe_in6, - probe_in7, - probe_in8, - probe_in9, - probe_in10, - probe_in11, - probe_in12, - probe_in13, - probe_in14, - probe_in15, - probe_in16, - probe_in17, - probe_in18, - probe_in19, - probe_in20, - probe_in21, - probe_in22, - probe_in23, - probe_in24, - probe_in25, - probe_in26, - probe_in27, - probe_in28, - probe_in29, - probe_in30, - probe_in31, - probe_in32, - probe_in33, - probe_in34, - probe_in35, - probe_in36, - probe_in37, - probe_in38, - probe_in39, - probe_in40, - probe_in41, - probe_in42, - probe_in43, - probe_in44, - probe_in45, - probe_in46, - probe_in47, - probe_in48, - probe_in49, - probe_in50, - probe_in51, - probe_in52, - probe_in53, - probe_in54, - probe_in55, - probe_in56, - probe_in57, - probe_in58, - probe_in59, - probe_in60, - probe_in61, - probe_in62, - probe_in63, - probe_in64, - probe_in65, - probe_in66, - probe_in67, - probe_in68, - probe_in69, - probe_in70, - probe_in71, - probe_in72, - probe_in73, - probe_in74, - probe_in75, - probe_in76, - probe_in77, - probe_in78, - probe_in79, - probe_in80, - probe_in81, - probe_in82, - probe_in83, - probe_in84, - probe_in85, - probe_in86, - probe_in87, - probe_in88, - probe_in89, - probe_in90, - probe_in91, - probe_in92, - probe_in93, - probe_in94, - probe_in95, - probe_in96, - probe_in97, - probe_in98, - probe_in99, - probe_in100, - probe_in101, - probe_in102, - probe_in103, - probe_in104, - probe_in105, - probe_in106, - probe_in107, - probe_in108, - probe_in109, - probe_in110, - probe_in111, - probe_in112, - probe_in113, - probe_in114, - probe_in115, - probe_in116, - probe_in117, - probe_in118, - probe_in119, - probe_in120, - probe_in121, - probe_in122, - probe_in123, - probe_in124, - probe_in125, - probe_in126, - probe_in127, - probe_in128, - probe_in129, - probe_in130, - probe_in131, - probe_in132, - probe_in133, - probe_in134, - probe_in135, - probe_in136, - probe_in137, - probe_in138, - probe_in139, - probe_in140, - probe_in141, - probe_in142, - probe_in143, - probe_in144, - probe_in145, - probe_in146, - probe_in147, - probe_in148, - probe_in149, - probe_in150, - probe_in151, - probe_in152, - probe_in153, - probe_in154, - probe_in155, - probe_in156, - probe_in157, - probe_in158, - probe_in159, - probe_in160, - probe_in161, - probe_in162, - probe_in163, - probe_in164, - probe_in165, - probe_in166, - probe_in167, - probe_in168, - probe_in169, - probe_in170, - probe_in171, - probe_in172, - probe_in173, - probe_in174, - probe_in175, - probe_in176, - probe_in177, - probe_in178, - probe_in179, - probe_in180, - probe_in181, - probe_in182, - probe_in183, - probe_in184, - probe_in185, - probe_in186, - probe_in187, - probe_in188, - probe_in189, - probe_in190, - probe_in191, - probe_in192, - probe_in193, - probe_in194, - probe_in195, - probe_in196, - probe_in197, - probe_in198, - probe_in199, - probe_in200, - probe_in201, - probe_in202, - probe_in203, - probe_in204, - probe_in205, - probe_in206, - probe_in207, - probe_in208, - probe_in209, - probe_in210, - probe_in211, - probe_in212, - probe_in213, - probe_in214, - probe_in215, - probe_in216, - probe_in217, - probe_in218, - probe_in219, - probe_in220, - probe_in221, - probe_in222, - probe_in223, - probe_in224, - probe_in225, - probe_in226, - probe_in227, - probe_in228, - probe_in229, - probe_in230, - probe_in231, - probe_in232, - probe_in233, - probe_in234, - probe_in235, - probe_in236, - probe_in237, - probe_in238, - probe_in239, - probe_in240, - probe_in241, - probe_in242, - probe_in243, - probe_in244, - probe_in245, - probe_in246, - probe_in247, - probe_in248, - probe_in249, - probe_in250, - probe_in251, - probe_in252, - probe_in253, - probe_in254, - probe_in255, - sl_iport0, - sl_oport0, - probe_out0, - probe_out1, - probe_out2, - probe_out3, - probe_out4, - probe_out5, - probe_out6, - probe_out7, - probe_out8, - probe_out9, - probe_out10, - probe_out11, - probe_out12, - probe_out13, - probe_out14, - probe_out15, - probe_out16, - probe_out17, - probe_out18, - probe_out19, - probe_out20, - probe_out21, - probe_out22, - probe_out23, - probe_out24, - probe_out25, - probe_out26, - probe_out27, - probe_out28, - probe_out29, - probe_out30, - probe_out31, - probe_out32, - probe_out33, - probe_out34, - probe_out35, - probe_out36, - probe_out37, - probe_out38, - probe_out39, - probe_out40, - probe_out41, - probe_out42, - probe_out43, - probe_out44, - probe_out45, - probe_out46, - probe_out47, - probe_out48, - probe_out49, - probe_out50, - probe_out51, - probe_out52, - probe_out53, - probe_out54, - probe_out55, - probe_out56, - probe_out57, - probe_out58, - probe_out59, - probe_out60, - probe_out61, - probe_out62, - probe_out63, - probe_out64, - probe_out65, - probe_out66, - probe_out67, - probe_out68, - probe_out69, - probe_out70, - probe_out71, - probe_out72, - probe_out73, - probe_out74, - probe_out75, - probe_out76, - probe_out77, - probe_out78, - probe_out79, - probe_out80, - probe_out81, - probe_out82, - probe_out83, - probe_out84, - probe_out85, - probe_out86, - probe_out87, - probe_out88, - probe_out89, - probe_out90, - probe_out91, - probe_out92, - probe_out93, - probe_out94, - probe_out95, - probe_out96, - probe_out97, - probe_out98, - probe_out99, - probe_out100, - probe_out101, - probe_out102, - probe_out103, - probe_out104, - probe_out105, - probe_out106, - probe_out107, - probe_out108, - probe_out109, - probe_out110, - probe_out111, - probe_out112, - probe_out113, - probe_out114, - probe_out115, - probe_out116, - probe_out117, - probe_out118, - probe_out119, - probe_out120, - probe_out121, - probe_out122, - probe_out123, - probe_out124, - probe_out125, - probe_out126, - probe_out127, - probe_out128, - probe_out129, - probe_out130, - probe_out131, - probe_out132, - probe_out133, - probe_out134, - probe_out135, - probe_out136, - probe_out137, - probe_out138, - probe_out139, - probe_out140, - probe_out141, - probe_out142, - probe_out143, - probe_out144, - probe_out145, - probe_out146, - probe_out147, - probe_out148, - probe_out149, - probe_out150, - probe_out151, - probe_out152, - probe_out153, - probe_out154, - probe_out155, - probe_out156, - probe_out157, - probe_out158, - probe_out159, - probe_out160, - probe_out161, - probe_out162, - probe_out163, - probe_out164, - probe_out165, - probe_out166, - probe_out167, - probe_out168, - probe_out169, - probe_out170, - probe_out171, - probe_out172, - probe_out173, - probe_out174, - probe_out175, - probe_out176, - probe_out177, - probe_out178, - probe_out179, - probe_out180, - probe_out181, - probe_out182, - probe_out183, - probe_out184, - probe_out185, - probe_out186, - probe_out187, - probe_out188, - probe_out189, - probe_out190, - probe_out191, - probe_out192, - probe_out193, - probe_out194, - probe_out195, - probe_out196, - probe_out197, - probe_out198, - probe_out199, - probe_out200, - probe_out201, - probe_out202, - probe_out203, - probe_out204, - probe_out205, - probe_out206, - probe_out207, - probe_out208, - probe_out209, - probe_out210, - probe_out211, - probe_out212, - probe_out213, - probe_out214, - probe_out215, - probe_out216, - probe_out217, - probe_out218, - probe_out219, - probe_out220, - probe_out221, - probe_out222, - probe_out223, - probe_out224, - probe_out225, - probe_out226, - probe_out227, - probe_out228, - probe_out229, - probe_out230, - probe_out231, - probe_out232, - probe_out233, - probe_out234, - probe_out235, - probe_out236, - probe_out237, - probe_out238, - probe_out239, - probe_out240, - probe_out241, - probe_out242, - probe_out243, - probe_out244, - probe_out245, - probe_out246, - probe_out247, - probe_out248, - probe_out249, - probe_out250, - probe_out251, - probe_out252, - probe_out253, - probe_out254, - probe_out255); - input clk; - input [31:0]probe_in0; - input [31:0]probe_in1; - input [0:0]probe_in2; - input [0:0]probe_in3; - input [0:0]probe_in4; - input [0:0]probe_in5; - input [0:0]probe_in6; - input [0:0]probe_in7; - input [0:0]probe_in8; - input [0:0]probe_in9; - input [0:0]probe_in10; - input [0:0]probe_in11; - input [0:0]probe_in12; - input [0:0]probe_in13; - input [0:0]probe_in14; - input [0:0]probe_in15; - input [0:0]probe_in16; - input [0:0]probe_in17; - input [0:0]probe_in18; - input [0:0]probe_in19; - input [0:0]probe_in20; - input [0:0]probe_in21; - input [0:0]probe_in22; - input [0:0]probe_in23; - input [0:0]probe_in24; - input [0:0]probe_in25; - input [0:0]probe_in26; - input [0:0]probe_in27; - input [0:0]probe_in28; - input [0:0]probe_in29; - input [0:0]probe_in30; - input [0:0]probe_in31; - input [0:0]probe_in32; - input [0:0]probe_in33; - input [0:0]probe_in34; - input [0:0]probe_in35; - input [0:0]probe_in36; - input [0:0]probe_in37; - input [0:0]probe_in38; - input [0:0]probe_in39; - input [0:0]probe_in40; - input [0:0]probe_in41; - input [0:0]probe_in42; - input [0:0]probe_in43; - input [0:0]probe_in44; - input [0:0]probe_in45; - input [0:0]probe_in46; - input [0:0]probe_in47; - input [0:0]probe_in48; - input [0:0]probe_in49; - input [0:0]probe_in50; - input [0:0]probe_in51; - input [0:0]probe_in52; - input [0:0]probe_in53; - input [0:0]probe_in54; - input [0:0]probe_in55; - input [0:0]probe_in56; - input [0:0]probe_in57; - input [0:0]probe_in58; - input [0:0]probe_in59; - input [0:0]probe_in60; - input [0:0]probe_in61; - input [0:0]probe_in62; - input [0:0]probe_in63; - input [0:0]probe_in64; - input [0:0]probe_in65; - input [0:0]probe_in66; - input [0:0]probe_in67; - input [0:0]probe_in68; - input [0:0]probe_in69; - input [0:0]probe_in70; - input [0:0]probe_in71; - input [0:0]probe_in72; - input [0:0]probe_in73; - input [0:0]probe_in74; - input [0:0]probe_in75; - input [0:0]probe_in76; - input [0:0]probe_in77; - input [0:0]probe_in78; - input [0:0]probe_in79; - input [0:0]probe_in80; - input [0:0]probe_in81; - input [0:0]probe_in82; - input [0:0]probe_in83; - input [0:0]probe_in84; - input [0:0]probe_in85; - input [0:0]probe_in86; - input [0:0]probe_in87; - input [0:0]probe_in88; - input [0:0]probe_in89; - input [0:0]probe_in90; - input [0:0]probe_in91; - input [0:0]probe_in92; - input [0:0]probe_in93; - input [0:0]probe_in94; - input [0:0]probe_in95; - input [0:0]probe_in96; - input [0:0]probe_in97; - input [0:0]probe_in98; - input [0:0]probe_in99; - input [0:0]probe_in100; - input [0:0]probe_in101; - input [0:0]probe_in102; - input [0:0]probe_in103; - input [0:0]probe_in104; - input [0:0]probe_in105; - input [0:0]probe_in106; - input [0:0]probe_in107; - input [0:0]probe_in108; - input [0:0]probe_in109; - input [0:0]probe_in110; - input [0:0]probe_in111; - input [0:0]probe_in112; - input [0:0]probe_in113; - input [0:0]probe_in114; - input [0:0]probe_in115; - input [0:0]probe_in116; - input [0:0]probe_in117; - input [0:0]probe_in118; - input [0:0]probe_in119; - input [0:0]probe_in120; - input [0:0]probe_in121; - input [0:0]probe_in122; - input [0:0]probe_in123; - input [0:0]probe_in124; - input [0:0]probe_in125; - input [0:0]probe_in126; - input [0:0]probe_in127; - input [0:0]probe_in128; - input [0:0]probe_in129; - input [0:0]probe_in130; - input [0:0]probe_in131; - input [0:0]probe_in132; - input [0:0]probe_in133; - input [0:0]probe_in134; - input [0:0]probe_in135; - input [0:0]probe_in136; - input [0:0]probe_in137; - input [0:0]probe_in138; - input [0:0]probe_in139; - input [0:0]probe_in140; - input [0:0]probe_in141; - input [0:0]probe_in142; - input [0:0]probe_in143; - input [0:0]probe_in144; - input [0:0]probe_in145; - input [0:0]probe_in146; - input [0:0]probe_in147; - input [0:0]probe_in148; - input [0:0]probe_in149; - input [0:0]probe_in150; - input [0:0]probe_in151; - input [0:0]probe_in152; - input [0:0]probe_in153; - input [0:0]probe_in154; - input [0:0]probe_in155; - input [0:0]probe_in156; - input [0:0]probe_in157; - input [0:0]probe_in158; - input [0:0]probe_in159; - input [0:0]probe_in160; - input [0:0]probe_in161; - input [0:0]probe_in162; - input [0:0]probe_in163; - input [0:0]probe_in164; - input [0:0]probe_in165; - input [0:0]probe_in166; - input [0:0]probe_in167; - input [0:0]probe_in168; - input [0:0]probe_in169; - input [0:0]probe_in170; - input [0:0]probe_in171; - input [0:0]probe_in172; - input [0:0]probe_in173; - input [0:0]probe_in174; - input [0:0]probe_in175; - input [0:0]probe_in176; - input [0:0]probe_in177; - input [0:0]probe_in178; - input [0:0]probe_in179; - input [0:0]probe_in180; - input [0:0]probe_in181; - input [0:0]probe_in182; - input [0:0]probe_in183; - input [0:0]probe_in184; - input [0:0]probe_in185; - input [0:0]probe_in186; - input [0:0]probe_in187; - input [0:0]probe_in188; - input [0:0]probe_in189; - input [0:0]probe_in190; - input [0:0]probe_in191; - input [0:0]probe_in192; - input [0:0]probe_in193; - input [0:0]probe_in194; - input [0:0]probe_in195; - input [0:0]probe_in196; - input [0:0]probe_in197; - input [0:0]probe_in198; - input [0:0]probe_in199; - input [0:0]probe_in200; - input [0:0]probe_in201; - input [0:0]probe_in202; - input [0:0]probe_in203; - input [0:0]probe_in204; - input [0:0]probe_in205; - input [0:0]probe_in206; - input [0:0]probe_in207; - input [0:0]probe_in208; - input [0:0]probe_in209; - input [0:0]probe_in210; - input [0:0]probe_in211; - input [0:0]probe_in212; - input [0:0]probe_in213; - input [0:0]probe_in214; - input [0:0]probe_in215; - input [0:0]probe_in216; - input [0:0]probe_in217; - input [0:0]probe_in218; - input [0:0]probe_in219; - input [0:0]probe_in220; - input [0:0]probe_in221; - input [0:0]probe_in222; - input [0:0]probe_in223; - input [0:0]probe_in224; - input [0:0]probe_in225; - input [0:0]probe_in226; - input [0:0]probe_in227; - input [0:0]probe_in228; - input [0:0]probe_in229; - input [0:0]probe_in230; - input [0:0]probe_in231; - input [0:0]probe_in232; - input [0:0]probe_in233; - input [0:0]probe_in234; - input [0:0]probe_in235; - input [0:0]probe_in236; - input [0:0]probe_in237; - input [0:0]probe_in238; - input [0:0]probe_in239; - input [0:0]probe_in240; - input [0:0]probe_in241; - input [0:0]probe_in242; - input [0:0]probe_in243; - input [0:0]probe_in244; - input [0:0]probe_in245; - input [0:0]probe_in246; - input [0:0]probe_in247; - input [0:0]probe_in248; - input [0:0]probe_in249; - input [0:0]probe_in250; - input [0:0]probe_in251; - input [0:0]probe_in252; - input [0:0]probe_in253; - input [0:0]probe_in254; - input [0:0]probe_in255; - (* dont_touch = "true" *) input [36:0]sl_iport0; - (* dont_touch = "true" *) output [16:0]sl_oport0; - output [31:0]probe_out0; - output [0:0]probe_out1; - output [0:0]probe_out2; - output [0:0]probe_out3; - output [0:0]probe_out4; - output [0:0]probe_out5; - output [0:0]probe_out6; - output [0:0]probe_out7; - output [0:0]probe_out8; - output [0:0]probe_out9; - output [0:0]probe_out10; - output [0:0]probe_out11; - output [0:0]probe_out12; - output [0:0]probe_out13; - output [0:0]probe_out14; - output [0:0]probe_out15; - output [0:0]probe_out16; - output [0:0]probe_out17; - output [0:0]probe_out18; - output [0:0]probe_out19; - output [0:0]probe_out20; - output [0:0]probe_out21; - output [0:0]probe_out22; - output [0:0]probe_out23; - output [0:0]probe_out24; - output [0:0]probe_out25; - output [0:0]probe_out26; - output [0:0]probe_out27; - output [0:0]probe_out28; - output [0:0]probe_out29; - output [0:0]probe_out30; - output [0:0]probe_out31; - output [0:0]probe_out32; - output [0:0]probe_out33; - output [0:0]probe_out34; - output [0:0]probe_out35; - output [0:0]probe_out36; - output [0:0]probe_out37; - output [0:0]probe_out38; - output [0:0]probe_out39; - output [0:0]probe_out40; - output [0:0]probe_out41; - output [0:0]probe_out42; - output [0:0]probe_out43; - output [0:0]probe_out44; - output [0:0]probe_out45; - output [0:0]probe_out46; - output [0:0]probe_out47; - output [0:0]probe_out48; - output [0:0]probe_out49; - output [0:0]probe_out50; - output [0:0]probe_out51; - output [0:0]probe_out52; - output [0:0]probe_out53; - output [0:0]probe_out54; - output [0:0]probe_out55; - output [0:0]probe_out56; - output [0:0]probe_out57; - output [0:0]probe_out58; - output [0:0]probe_out59; - output [0:0]probe_out60; - output [0:0]probe_out61; - output [0:0]probe_out62; - output [0:0]probe_out63; - output [0:0]probe_out64; - output [0:0]probe_out65; - output [0:0]probe_out66; - output [0:0]probe_out67; - output [0:0]probe_out68; - output [0:0]probe_out69; - output [0:0]probe_out70; - output [0:0]probe_out71; - output [0:0]probe_out72; - output [0:0]probe_out73; - output [0:0]probe_out74; - output [0:0]probe_out75; - output [0:0]probe_out76; - output [0:0]probe_out77; - output [0:0]probe_out78; - output [0:0]probe_out79; - output [0:0]probe_out80; - output [0:0]probe_out81; - output [0:0]probe_out82; - output [0:0]probe_out83; - output [0:0]probe_out84; - output [0:0]probe_out85; - output [0:0]probe_out86; - output [0:0]probe_out87; - output [0:0]probe_out88; - output [0:0]probe_out89; - output [0:0]probe_out90; - output [0:0]probe_out91; - output [0:0]probe_out92; - output [0:0]probe_out93; - output [0:0]probe_out94; - output [0:0]probe_out95; - output [0:0]probe_out96; - output [0:0]probe_out97; - output [0:0]probe_out98; - output [0:0]probe_out99; - output [0:0]probe_out100; - output [0:0]probe_out101; - output [0:0]probe_out102; - output [0:0]probe_out103; - output [0:0]probe_out104; - output [0:0]probe_out105; - output [0:0]probe_out106; - output [0:0]probe_out107; - output [0:0]probe_out108; - output [0:0]probe_out109; - output [0:0]probe_out110; - output [0:0]probe_out111; - output [0:0]probe_out112; - output [0:0]probe_out113; - output [0:0]probe_out114; - output [0:0]probe_out115; - output [0:0]probe_out116; - output [0:0]probe_out117; - output [0:0]probe_out118; - output [0:0]probe_out119; - output [0:0]probe_out120; - output [0:0]probe_out121; - output [0:0]probe_out122; - output [0:0]probe_out123; - output [0:0]probe_out124; - output [0:0]probe_out125; - output [0:0]probe_out126; - output [0:0]probe_out127; - output [0:0]probe_out128; - output [0:0]probe_out129; - output [0:0]probe_out130; - output [0:0]probe_out131; - output [0:0]probe_out132; - output [0:0]probe_out133; - output [0:0]probe_out134; - output [0:0]probe_out135; - output [0:0]probe_out136; - output [0:0]probe_out137; - output [0:0]probe_out138; - output [0:0]probe_out139; - output [0:0]probe_out140; - output [0:0]probe_out141; - output [0:0]probe_out142; - output [0:0]probe_out143; - output [0:0]probe_out144; - output [0:0]probe_out145; - output [0:0]probe_out146; - output [0:0]probe_out147; - output [0:0]probe_out148; - output [0:0]probe_out149; - output [0:0]probe_out150; - output [0:0]probe_out151; - output [0:0]probe_out152; - output [0:0]probe_out153; - output [0:0]probe_out154; - output [0:0]probe_out155; - output [0:0]probe_out156; - output [0:0]probe_out157; - output [0:0]probe_out158; - output [0:0]probe_out159; - output [0:0]probe_out160; - output [0:0]probe_out161; - output [0:0]probe_out162; - output [0:0]probe_out163; - output [0:0]probe_out164; - output [0:0]probe_out165; - output [0:0]probe_out166; - output [0:0]probe_out167; - output [0:0]probe_out168; - output [0:0]probe_out169; - output [0:0]probe_out170; - output [0:0]probe_out171; - output [0:0]probe_out172; - output [0:0]probe_out173; - output [0:0]probe_out174; - output [0:0]probe_out175; - output [0:0]probe_out176; - output [0:0]probe_out177; - output [0:0]probe_out178; - output [0:0]probe_out179; - output [0:0]probe_out180; - output [0:0]probe_out181; - output [0:0]probe_out182; - output [0:0]probe_out183; - output [0:0]probe_out184; - output [0:0]probe_out185; - output [0:0]probe_out186; - output [0:0]probe_out187; - output [0:0]probe_out188; - output [0:0]probe_out189; - output [0:0]probe_out190; - output [0:0]probe_out191; - output [0:0]probe_out192; - output [0:0]probe_out193; - output [0:0]probe_out194; - output [0:0]probe_out195; - output [0:0]probe_out196; - output [0:0]probe_out197; - output [0:0]probe_out198; - output [0:0]probe_out199; - output [0:0]probe_out200; - output [0:0]probe_out201; - output [0:0]probe_out202; - output [0:0]probe_out203; - output [0:0]probe_out204; - output [0:0]probe_out205; - output [0:0]probe_out206; - output [0:0]probe_out207; - output [0:0]probe_out208; - output [0:0]probe_out209; - output [0:0]probe_out210; - output [0:0]probe_out211; - output [0:0]probe_out212; - output [0:0]probe_out213; - output [0:0]probe_out214; - output [0:0]probe_out215; - output [0:0]probe_out216; - output [0:0]probe_out217; - output [0:0]probe_out218; - output [0:0]probe_out219; - output [0:0]probe_out220; - output [0:0]probe_out221; - output [0:0]probe_out222; - output [0:0]probe_out223; - output [0:0]probe_out224; - output [0:0]probe_out225; - output [0:0]probe_out226; - output [0:0]probe_out227; - output [0:0]probe_out228; - output [0:0]probe_out229; - output [0:0]probe_out230; - output [0:0]probe_out231; - output [0:0]probe_out232; - output [0:0]probe_out233; - output [0:0]probe_out234; - output [0:0]probe_out235; - output [0:0]probe_out236; - output [0:0]probe_out237; - output [0:0]probe_out238; - output [0:0]probe_out239; - output [0:0]probe_out240; - output [0:0]probe_out241; - output [0:0]probe_out242; - output [0:0]probe_out243; - output [0:0]probe_out244; - output [0:0]probe_out245; - output [0:0]probe_out246; - output [0:0]probe_out247; - output [0:0]probe_out248; - output [0:0]probe_out249; - output [0:0]probe_out250; - output [0:0]probe_out251; - output [0:0]probe_out252; - output [0:0]probe_out253; - output [0:0]probe_out254; - output [0:0]probe_out255; - - wire \ ; - wire [15:0]Bus_Data_out; - wire DECODER_INST_n_10; - wire DECODER_INST_n_4; - wire DECODER_INST_n_6; - wire DECODER_INST_n_7; - wire DECODER_INST_n_8; - wire PROBE_OUT_ALL_INST_n_32; - wire PROBE_OUT_ALL_INST_n_33; - wire PROBE_OUT_ALL_INST_n_34; - wire PROBE_OUT_ALL_INST_n_35; - wire PROBE_OUT_ALL_INST_n_36; - wire PROBE_OUT_ALL_INST_n_37; - wire PROBE_OUT_ALL_INST_n_38; - wire PROBE_OUT_ALL_INST_n_39; - wire PROBE_OUT_ALL_INST_n_40; - wire PROBE_OUT_ALL_INST_n_41; - wire PROBE_OUT_ALL_INST_n_42; - wire PROBE_OUT_ALL_INST_n_43; - wire PROBE_OUT_ALL_INST_n_44; - wire PROBE_OUT_ALL_INST_n_45; - wire PROBE_OUT_ALL_INST_n_46; - wire PROBE_OUT_ALL_INST_n_47; - wire addr_count_reg0; - wire addr_count_reg1; - wire [16:0]bus_addr; - (* DONT_TOUCH *) wire bus_clk; - wire \bus_data_int_reg_n_0_[0] ; - wire \bus_data_int_reg_n_0_[10] ; - wire \bus_data_int_reg_n_0_[11] ; - wire \bus_data_int_reg_n_0_[12] ; - wire \bus_data_int_reg_n_0_[13] ; - wire \bus_data_int_reg_n_0_[14] ; - wire \bus_data_int_reg_n_0_[15] ; - wire \bus_data_int_reg_n_0_[2] ; - wire \bus_data_int_reg_n_0_[3] ; - wire \bus_data_int_reg_n_0_[4] ; - wire \bus_data_int_reg_n_0_[5] ; - wire \bus_data_int_reg_n_0_[6] ; - wire \bus_data_int_reg_n_0_[7] ; - wire \bus_data_int_reg_n_0_[8] ; - wire \bus_data_int_reg_n_0_[9] ; - wire bus_den; - wire [15:0]bus_di; - wire [15:0]bus_do; - wire bus_drdy; - wire bus_dwe; - wire bus_rst; - wire clear; - wire clk; - wire committ; - wire internal_cnt_rst; - wire p_0_in; - wire [31:0]probe_in0; - wire [31:0]probe_in1; - wire [31:0]probe_out0; - (* DONT_TOUCH *) wire [36:0]sl_iport0; - (* DONT_TOUCH *) wire [16:0]sl_oport0; - wire xsdb_rd; - wire xsdb_wr__0; - - assign probe_out1[0] = \ ; - assign probe_out10[0] = \ ; - assign probe_out100[0] = \ ; - assign probe_out101[0] = \ ; - assign probe_out102[0] = \ ; - assign probe_out103[0] = \ ; - assign probe_out104[0] = \ ; - assign probe_out105[0] = \ ; - assign probe_out106[0] = \ ; - assign probe_out107[0] = \ ; - assign probe_out108[0] = \ ; - assign probe_out109[0] = \ ; - assign probe_out11[0] = \ ; - assign probe_out110[0] = \ ; - assign probe_out111[0] = \ ; - assign probe_out112[0] = \ ; - assign probe_out113[0] = \ ; - assign probe_out114[0] = \ ; - assign probe_out115[0] = \ ; - assign probe_out116[0] = \ ; - assign probe_out117[0] = \ ; - assign probe_out118[0] = \ ; - assign probe_out119[0] = \ ; - assign probe_out12[0] = \ ; - assign probe_out120[0] = \ ; - assign probe_out121[0] = \ ; - assign probe_out122[0] = \ ; - assign probe_out123[0] = \ ; - assign probe_out124[0] = \ ; - assign probe_out125[0] = \ ; - assign probe_out126[0] = \ ; - assign probe_out127[0] = \ ; - assign probe_out128[0] = \ ; - assign probe_out129[0] = \ ; - assign probe_out13[0] = \ ; - assign probe_out130[0] = \ ; - assign probe_out131[0] = \ ; - assign probe_out132[0] = \ ; - assign probe_out133[0] = \ ; - assign probe_out134[0] = \ ; - assign probe_out135[0] = \ ; - assign probe_out136[0] = \ ; - assign probe_out137[0] = \ ; - assign probe_out138[0] = \ ; - assign probe_out139[0] = \ ; - assign probe_out14[0] = \ ; - assign probe_out140[0] = \ ; - assign probe_out141[0] = \ ; - assign probe_out142[0] = \ ; - assign probe_out143[0] = \ ; - assign probe_out144[0] = \ ; - assign probe_out145[0] = \ ; - assign probe_out146[0] = \ ; - assign probe_out147[0] = \ ; - assign probe_out148[0] = \ ; - assign probe_out149[0] = \ ; - assign probe_out15[0] = \ ; - assign probe_out150[0] = \ ; - assign probe_out151[0] = \ ; - assign probe_out152[0] = \ ; - assign probe_out153[0] = \ ; - assign probe_out154[0] = \ ; - assign probe_out155[0] = \ ; - assign probe_out156[0] = \ ; - assign probe_out157[0] = \ ; - assign probe_out158[0] = \ ; - assign probe_out159[0] = \ ; - assign probe_out16[0] = \ ; - assign probe_out160[0] = \ ; - assign probe_out161[0] = \ ; - assign probe_out162[0] = \ ; - assign probe_out163[0] = \ ; - assign probe_out164[0] = \ ; - assign probe_out165[0] = \ ; - assign probe_out166[0] = \ ; - assign probe_out167[0] = \ ; - assign probe_out168[0] = \ ; - assign probe_out169[0] = \ ; - assign probe_out17[0] = \ ; - assign probe_out170[0] = \ ; - assign probe_out171[0] = \ ; - assign probe_out172[0] = \ ; - assign probe_out173[0] = \ ; - assign probe_out174[0] = \ ; - assign probe_out175[0] = \ ; - assign probe_out176[0] = \ ; - assign probe_out177[0] = \ ; - assign probe_out178[0] = \ ; - assign probe_out179[0] = \ ; - assign probe_out18[0] = \ ; - assign probe_out180[0] = \ ; - assign probe_out181[0] = \ ; - assign probe_out182[0] = \ ; - assign probe_out183[0] = \ ; - assign probe_out184[0] = \ ; - assign probe_out185[0] = \ ; - assign probe_out186[0] = \ ; - assign probe_out187[0] = \ ; - assign probe_out188[0] = \ ; - assign probe_out189[0] = \ ; - assign probe_out19[0] = \ ; - assign probe_out190[0] = \ ; - assign probe_out191[0] = \ ; - assign probe_out192[0] = \ ; - assign probe_out193[0] = \ ; - assign probe_out194[0] = \ ; - assign probe_out195[0] = \ ; - assign probe_out196[0] = \ ; - assign probe_out197[0] = \ ; - assign probe_out198[0] = \ ; - assign probe_out199[0] = \ ; - assign probe_out2[0] = \ ; - assign probe_out20[0] = \ ; - assign probe_out200[0] = \ ; - assign probe_out201[0] = \ ; - assign probe_out202[0] = \ ; - assign probe_out203[0] = \ ; - assign probe_out204[0] = \ ; - assign probe_out205[0] = \ ; - assign probe_out206[0] = \ ; - assign probe_out207[0] = \ ; - assign probe_out208[0] = \ ; - assign probe_out209[0] = \ ; - assign probe_out21[0] = \ ; - assign probe_out210[0] = \ ; - assign probe_out211[0] = \ ; - assign probe_out212[0] = \ ; - assign probe_out213[0] = \ ; - assign probe_out214[0] = \ ; - assign probe_out215[0] = \ ; - assign probe_out216[0] = \ ; - assign probe_out217[0] = \ ; - assign probe_out218[0] = \ ; - assign probe_out219[0] = \ ; - assign probe_out22[0] = \ ; - assign probe_out220[0] = \ ; - assign probe_out221[0] = \ ; - assign probe_out222[0] = \ ; - assign probe_out223[0] = \ ; - assign probe_out224[0] = \ ; - assign probe_out225[0] = \ ; - assign probe_out226[0] = \ ; - assign probe_out227[0] = \ ; - assign probe_out228[0] = \ ; - assign probe_out229[0] = \ ; - assign probe_out23[0] = \ ; - assign probe_out230[0] = \ ; - assign probe_out231[0] = \ ; - assign probe_out232[0] = \ ; - assign probe_out233[0] = \ ; - assign probe_out234[0] = \ ; - assign probe_out235[0] = \ ; - assign probe_out236[0] = \ ; - assign probe_out237[0] = \ ; - assign probe_out238[0] = \ ; - assign probe_out239[0] = \ ; - assign probe_out24[0] = \ ; - assign probe_out240[0] = \ ; - assign probe_out241[0] = \ ; - assign probe_out242[0] = \ ; - assign probe_out243[0] = \ ; - assign probe_out244[0] = \ ; - assign probe_out245[0] = \ ; - assign probe_out246[0] = \ ; - assign probe_out247[0] = \ ; - assign probe_out248[0] = \ ; - assign probe_out249[0] = \ ; - assign probe_out25[0] = \ ; - assign probe_out250[0] = \ ; - assign probe_out251[0] = \ ; - assign probe_out252[0] = \ ; - assign probe_out253[0] = \ ; - assign probe_out254[0] = \ ; - assign probe_out255[0] = \ ; - assign probe_out26[0] = \ ; - assign probe_out27[0] = \ ; - assign probe_out28[0] = \ ; - assign probe_out29[0] = \ ; - assign probe_out3[0] = \ ; - assign probe_out30[0] = \ ; - assign probe_out31[0] = \ ; - assign probe_out32[0] = \ ; - assign probe_out33[0] = \ ; - assign probe_out34[0] = \ ; - assign probe_out35[0] = \ ; - assign probe_out36[0] = \ ; - assign probe_out37[0] = \ ; - assign probe_out38[0] = \ ; - assign probe_out39[0] = \ ; - assign probe_out4[0] = \ ; - assign probe_out40[0] = \ ; - assign probe_out41[0] = \ ; - assign probe_out42[0] = \ ; - assign probe_out43[0] = \ ; - assign probe_out44[0] = \ ; - assign probe_out45[0] = \ ; - assign probe_out46[0] = \ ; - assign probe_out47[0] = \ ; - assign probe_out48[0] = \ ; - assign probe_out49[0] = \ ; - assign probe_out5[0] = \ ; - assign probe_out50[0] = \ ; - assign probe_out51[0] = \ ; - assign probe_out52[0] = \ ; - assign probe_out53[0] = \ ; - assign probe_out54[0] = \ ; - assign probe_out55[0] = \ ; - assign probe_out56[0] = \ ; - assign probe_out57[0] = \ ; - assign probe_out58[0] = \ ; - assign probe_out59[0] = \ ; - assign probe_out6[0] = \ ; - assign probe_out60[0] = \ ; - assign probe_out61[0] = \ ; - assign probe_out62[0] = \ ; - assign probe_out63[0] = \ ; - assign probe_out64[0] = \ ; - assign probe_out65[0] = \ ; - assign probe_out66[0] = \ ; - assign probe_out67[0] = \ ; - assign probe_out68[0] = \ ; - assign probe_out69[0] = \ ; - assign probe_out7[0] = \ ; - assign probe_out70[0] = \ ; - assign probe_out71[0] = \ ; - assign probe_out72[0] = \ ; - assign probe_out73[0] = \ ; - assign probe_out74[0] = \ ; - assign probe_out75[0] = \ ; - assign probe_out76[0] = \ ; - assign probe_out77[0] = \ ; - assign probe_out78[0] = \ ; - assign probe_out79[0] = \ ; - assign probe_out8[0] = \ ; - assign probe_out80[0] = \ ; - assign probe_out81[0] = \ ; - assign probe_out82[0] = \ ; - assign probe_out83[0] = \ ; - assign probe_out84[0] = \ ; - assign probe_out85[0] = \ ; - assign probe_out86[0] = \ ; - assign probe_out87[0] = \ ; - assign probe_out88[0] = \ ; - assign probe_out89[0] = \ ; - assign probe_out9[0] = \ ; - assign probe_out90[0] = \ ; - assign probe_out91[0] = \ ; - assign probe_out92[0] = \ ; - assign probe_out93[0] = \ ; - assign probe_out94[0] = \ ; - assign probe_out95[0] = \ ; - assign probe_out96[0] = \ ; - assign probe_out97[0] = \ ; - assign probe_out98[0] = \ ; - assign probe_out99[0] = \ ; - vio_0_vio_v3_0_19_decoder DECODER_INST - (.\Bus_data_out_reg[15]_0 (bus_do), - .\Bus_data_out_reg[15]_1 (Bus_Data_out), - .\Bus_data_out_reg[15]_2 ({PROBE_OUT_ALL_INST_n_32,PROBE_OUT_ALL_INST_n_33,PROBE_OUT_ALL_INST_n_34,PROBE_OUT_ALL_INST_n_35,PROBE_OUT_ALL_INST_n_36,PROBE_OUT_ALL_INST_n_37,PROBE_OUT_ALL_INST_n_38,PROBE_OUT_ALL_INST_n_39,PROBE_OUT_ALL_INST_n_40,PROBE_OUT_ALL_INST_n_41,PROBE_OUT_ALL_INST_n_42,PROBE_OUT_ALL_INST_n_43,PROBE_OUT_ALL_INST_n_44,PROBE_OUT_ALL_INST_n_45,PROBE_OUT_ALL_INST_n_46,PROBE_OUT_ALL_INST_n_47}), - .CLK(bus_clk), - .E(DECODER_INST_n_10), - .Q({\bus_data_int_reg_n_0_[15] ,\bus_data_int_reg_n_0_[14] ,\bus_data_int_reg_n_0_[13] ,\bus_data_int_reg_n_0_[12] ,\bus_data_int_reg_n_0_[11] ,\bus_data_int_reg_n_0_[10] ,\bus_data_int_reg_n_0_[9] ,\bus_data_int_reg_n_0_[8] ,\bus_data_int_reg_n_0_[7] ,\bus_data_int_reg_n_0_[6] ,\bus_data_int_reg_n_0_[5] ,\bus_data_int_reg_n_0_[4] ,\bus_data_int_reg_n_0_[3] ,\bus_data_int_reg_n_0_[2] ,p_0_in,\bus_data_int_reg_n_0_[0] }), - .Read_int_i_7_0(DECODER_INST_n_7), - .Read_int_i_7_1(DECODER_INST_n_8), - .SR(clear), - .addr_count_reg1(addr_count_reg1), - .in0(committ), - .int_cnt_rst_reg_0(addr_count_reg0), - .internal_cnt_rst(internal_cnt_rst), - .s_daddr_o(bus_addr), - .s_den_o(bus_den), - .s_drdy_i(bus_drdy), - .s_dwe_o(bus_dwe), - .s_rst_o(bus_rst), - .\wr_en[2]_i_2_0 (DECODER_INST_n_4), - .\wr_en[2]_i_4_0 (DECODER_INST_n_6), - .xsdb_rd(xsdb_rd), - .xsdb_wr__0(xsdb_wr__0)); - GND GND - (.G(\ )); - vio_0_vio_v3_0_19_probe_in_one PROBE_IN_INST - (.CLK(bus_clk), - .D({probe_in1,probe_in0}), - .E(DECODER_INST_n_10), - .Q(Bus_Data_out), - .Read_int_reg_0(DECODER_INST_n_8), - .SR(addr_count_reg0), - .addr_count_reg1(addr_count_reg1), - .clk(clk), - .s_daddr_o(bus_addr), - .s_den_o(bus_den), - .s_dwe_o(bus_dwe), - .xsdb_rd(xsdb_rd)); - vio_0_vio_v3_0_19_probe_out_all PROBE_OUT_ALL_INST - (.CLK(bus_clk), - .\G_PROBE_OUT[0].wr_probe_out_reg[0]_0 (DECODER_INST_n_4), - .\G_PROBE_OUT[0].wr_probe_out_reg[0]_1 (DECODER_INST_n_7), - .\G_PROBE_OUT[0].wr_probe_out_reg[0]_2 (DECODER_INST_n_6), - .\Probe_out_reg_int_reg[15]_0 ({PROBE_OUT_ALL_INST_n_32,PROBE_OUT_ALL_INST_n_33,PROBE_OUT_ALL_INST_n_34,PROBE_OUT_ALL_INST_n_35,PROBE_OUT_ALL_INST_n_36,PROBE_OUT_ALL_INST_n_37,PROBE_OUT_ALL_INST_n_38,PROBE_OUT_ALL_INST_n_39,PROBE_OUT_ALL_INST_n_40,PROBE_OUT_ALL_INST_n_41,PROBE_OUT_ALL_INST_n_42,PROBE_OUT_ALL_INST_n_43,PROBE_OUT_ALL_INST_n_44,PROBE_OUT_ALL_INST_n_45,PROBE_OUT_ALL_INST_n_46,PROBE_OUT_ALL_INST_n_47}), - .Q({\bus_data_int_reg_n_0_[15] ,\bus_data_int_reg_n_0_[14] ,\bus_data_int_reg_n_0_[13] ,\bus_data_int_reg_n_0_[12] ,\bus_data_int_reg_n_0_[11] ,\bus_data_int_reg_n_0_[10] ,\bus_data_int_reg_n_0_[9] ,\bus_data_int_reg_n_0_[8] ,\bus_data_int_reg_n_0_[7] ,\bus_data_int_reg_n_0_[6] ,\bus_data_int_reg_n_0_[5] ,\bus_data_int_reg_n_0_[4] ,\bus_data_int_reg_n_0_[3] ,\bus_data_int_reg_n_0_[2] ,p_0_in,\bus_data_int_reg_n_0_[0] }), - .SR(clear), - .clk(clk), - .in0(committ), - .internal_cnt_rst(internal_cnt_rst), - .probe_out0(probe_out0), - .s_daddr_o({bus_addr[15:8],bus_addr[3:1]}), - .s_den_o(bus_den), - .s_dwe_o(bus_dwe), - .xsdb_wr__0(xsdb_wr__0)); - (* C_BUILD_REVISION = "0" *) - (* C_CORE_INFO1 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) - (* C_CORE_INFO2 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) - (* C_CORE_MAJOR_VER = "2" *) - (* C_CORE_MINOR_VER = "0" *) - (* C_CORE_TYPE = "2" *) - (* C_CSE_DRV_VER = "1" *) - (* C_MAJOR_VERSION = "2013" *) - (* C_MINOR_VERSION = "1" *) - (* C_NEXT_SLAVE = "0" *) - (* C_PIPE_IFACE = "0" *) - (* C_USE_TEST_REG = "1" *) - (* C_XDEVICEFAMILY = "zynq" *) - (* C_XSDB_SLAVE_TYPE = "33" *) - (* DONT_TOUCH *) - vio_0_xsdbs_v1_0_2_xsdbs U_XSDB_SLAVE - (.s_daddr_o(bus_addr), - .s_dclk_o(bus_clk), - .s_den_o(bus_den), - .s_di_o(bus_di), - .s_do_i(bus_do), - .s_drdy_i(bus_drdy), - .s_dwe_o(bus_dwe), - .s_rst_o(bus_rst), - .sl_iport_i(sl_iport0), - .sl_oport_o(sl_oport0)); - FDRE \bus_data_int_reg[0] - (.C(bus_clk), - .CE(1'b1), - .D(bus_di[0]), - .Q(\bus_data_int_reg_n_0_[0] ), - .R(1'b0)); - FDRE \bus_data_int_reg[10] - (.C(bus_clk), - .CE(1'b1), - .D(bus_di[10]), - .Q(\bus_data_int_reg_n_0_[10] ), - .R(1'b0)); - FDRE \bus_data_int_reg[11] - (.C(bus_clk), - .CE(1'b1), - .D(bus_di[11]), - .Q(\bus_data_int_reg_n_0_[11] ), - .R(1'b0)); - FDRE \bus_data_int_reg[12] - (.C(bus_clk), - .CE(1'b1), - .D(bus_di[12]), - .Q(\bus_data_int_reg_n_0_[12] ), - .R(1'b0)); - FDRE \bus_data_int_reg[13] - (.C(bus_clk), - .CE(1'b1), - .D(bus_di[13]), - .Q(\bus_data_int_reg_n_0_[13] ), - .R(1'b0)); - FDRE \bus_data_int_reg[14] - (.C(bus_clk), - .CE(1'b1), - .D(bus_di[14]), - .Q(\bus_data_int_reg_n_0_[14] ), - .R(1'b0)); - FDRE \bus_data_int_reg[15] - (.C(bus_clk), - .CE(1'b1), - .D(bus_di[15]), - .Q(\bus_data_int_reg_n_0_[15] ), - .R(1'b0)); - FDRE \bus_data_int_reg[1] - (.C(bus_clk), - .CE(1'b1), - .D(bus_di[1]), - .Q(p_0_in), - .R(1'b0)); - FDRE \bus_data_int_reg[2] - (.C(bus_clk), - .CE(1'b1), - .D(bus_di[2]), - .Q(\bus_data_int_reg_n_0_[2] ), - .R(1'b0)); - FDRE \bus_data_int_reg[3] - (.C(bus_clk), - .CE(1'b1), - .D(bus_di[3]), - .Q(\bus_data_int_reg_n_0_[3] ), - .R(1'b0)); - FDRE \bus_data_int_reg[4] - (.C(bus_clk), - .CE(1'b1), - .D(bus_di[4]), - .Q(\bus_data_int_reg_n_0_[4] ), - .R(1'b0)); - FDRE \bus_data_int_reg[5] - (.C(bus_clk), - .CE(1'b1), - .D(bus_di[5]), - .Q(\bus_data_int_reg_n_0_[5] ), - .R(1'b0)); - FDRE \bus_data_int_reg[6] - (.C(bus_clk), - .CE(1'b1), - .D(bus_di[6]), - .Q(\bus_data_int_reg_n_0_[6] ), - .R(1'b0)); - FDRE \bus_data_int_reg[7] - (.C(bus_clk), - .CE(1'b1), - .D(bus_di[7]), - .Q(\bus_data_int_reg_n_0_[7] ), - .R(1'b0)); - FDRE \bus_data_int_reg[8] - (.C(bus_clk), - .CE(1'b1), - .D(bus_di[8]), - .Q(\bus_data_int_reg_n_0_[8] ), - .R(1'b0)); - FDRE \bus_data_int_reg[9] - (.C(bus_clk), - .CE(1'b1), - .D(bus_di[9]), - .Q(\bus_data_int_reg_n_0_[9] ), - .R(1'b0)); -endmodule - -(* C_BUILD_REVISION = "0" *) (* C_CORE_INFO1 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_CORE_INFO2 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) -(* C_CORE_MAJOR_VER = "2" *) (* C_CORE_MINOR_VER = "0" *) (* C_CORE_TYPE = "2" *) -(* C_CSE_DRV_VER = "1" *) (* C_MAJOR_VERSION = "2013" *) (* C_MINOR_VERSION = "1" *) -(* C_NEXT_SLAVE = "0" *) (* C_PIPE_IFACE = "0" *) (* C_USE_TEST_REG = "1" *) -(* C_XDEVICEFAMILY = "zynq" *) (* C_XSDB_SLAVE_TYPE = "33" *) (* ORIG_REF_NAME = "xsdbs_v1_0_2_xsdbs" *) -(* dont_touch = "true" *) -module vio_0_xsdbs_v1_0_2_xsdbs - (s_rst_o, - s_dclk_o, - s_den_o, - s_dwe_o, - s_daddr_o, - s_di_o, - sl_oport_o, - s_do_i, - sl_iport_i, - s_drdy_i); - output s_rst_o; - output s_dclk_o; - output s_den_o; - output s_dwe_o; - output [16:0]s_daddr_o; - output [15:0]s_di_o; - output [16:0]sl_oport_o; - input [15:0]s_do_i; - input [36:0]sl_iport_i; - input s_drdy_i; - - wire [15:0]reg_do; - wire \reg_do[0]_i_2_n_0 ; - wire \reg_do[0]_i_3_n_0 ; - wire \reg_do[0]_i_4_n_0 ; - wire \reg_do[10]_i_2_n_0 ; - wire \reg_do[10]_i_3_n_0 ; - wire \reg_do[10]_i_4_n_0 ; - wire \reg_do[10]_i_5_n_0 ; - wire \reg_do[11]_i_2_n_0 ; - wire \reg_do[11]_i_3_n_0 ; - wire \reg_do[12]_i_2_n_0 ; - wire \reg_do[12]_i_3_n_0 ; - wire \reg_do[13]_i_2_n_0 ; - wire \reg_do[13]_i_3_n_0 ; - wire \reg_do[14]_i_2_n_0 ; - wire \reg_do[14]_i_3_n_0 ; - wire \reg_do[15]_i_2_n_0 ; - wire \reg_do[15]_i_3_n_0 ; - wire \reg_do[15]_i_4_n_0 ; - wire \reg_do[15]_i_5_n_0 ; - wire \reg_do[15]_i_6_n_0 ; - wire \reg_do[1]_i_2_n_0 ; - wire \reg_do[1]_i_3_n_0 ; - wire \reg_do[1]_i_4_n_0 ; - wire \reg_do[2]_i_2_n_0 ; - wire \reg_do[2]_i_3_n_0 ; - wire \reg_do[2]_i_4_n_0 ; - wire \reg_do[3]_i_2_n_0 ; - wire \reg_do[3]_i_3_n_0 ; - wire \reg_do[3]_i_4_n_0 ; - wire \reg_do[4]_i_2_n_0 ; - wire \reg_do[4]_i_3_n_0 ; - wire \reg_do[4]_i_4_n_0 ; - wire \reg_do[5]_i_2_n_0 ; - wire \reg_do[5]_i_3_n_0 ; - wire \reg_do[5]_i_4_n_0 ; - wire \reg_do[5]_i_5_n_0 ; - wire \reg_do[6]_i_2_n_0 ; - wire \reg_do[6]_i_3_n_0 ; - wire \reg_do[6]_i_4_n_0 ; - wire \reg_do[7]_i_2_n_0 ; - wire \reg_do[7]_i_3_n_0 ; - wire \reg_do[7]_i_4_n_0 ; - wire \reg_do[8]_i_2_n_0 ; - wire \reg_do[8]_i_3_n_0 ; - wire \reg_do[8]_i_4_n_0 ; - wire \reg_do[9]_i_2_n_0 ; - wire \reg_do[9]_i_3_n_0 ; - wire \reg_do[9]_i_4_n_0 ; - wire \reg_do[9]_i_5_n_0 ; - wire \reg_do[9]_i_6_n_0 ; - wire \reg_do_reg_n_0_[0] ; - wire \reg_do_reg_n_0_[10] ; - wire \reg_do_reg_n_0_[11] ; - wire \reg_do_reg_n_0_[12] ; - wire \reg_do_reg_n_0_[13] ; - wire \reg_do_reg_n_0_[14] ; - wire \reg_do_reg_n_0_[15] ; - wire \reg_do_reg_n_0_[1] ; - wire \reg_do_reg_n_0_[2] ; - wire \reg_do_reg_n_0_[3] ; - wire \reg_do_reg_n_0_[4] ; - wire \reg_do_reg_n_0_[5] ; - wire \reg_do_reg_n_0_[6] ; - wire \reg_do_reg_n_0_[7] ; - wire \reg_do_reg_n_0_[8] ; - wire \reg_do_reg_n_0_[9] ; - wire reg_drdy; - wire reg_drdy_i_1_n_0; - wire [15:0]reg_test; - wire reg_test0; - wire s_den_o; - wire s_den_o_INST_0_i_1_n_0; - wire [15:0]s_do_i; - wire s_drdy_i; - wire [36:0]sl_iport_i; - wire [16:0]sl_oport_o; - (* DONT_TOUCH *) (* UUID = "1" *) wire [127:0]uuid_stamp; - - assign s_daddr_o[16:0] = sl_iport_i[20:4]; - assign s_dclk_o = sl_iport_i[1]; - assign s_di_o[15:0] = sl_iport_i[36:21]; - assign s_dwe_o = sl_iport_i[3]; - assign s_rst_o = sl_iport_i[0]; - LUT6 #( - .INIT(64'hAAAAAAAA0020AAAA)) - \reg_do[0]_i_1 - (.I0(\reg_do[0]_i_2_n_0 ), - .I1(\reg_do[9]_i_3_n_0 ), - .I2(reg_test[0]), - .I3(sl_iport_i[4]), - .I4(sl_iport_i[5]), - .I5(\reg_do[9]_i_2_n_0 ), - .O(reg_do[0])); - LUT6 #( - .INIT(64'hABABABAAAAAAABAA)) - \reg_do[0]_i_2 - (.I0(\reg_do[5]_i_3_n_0 ), - .I1(sl_iport_i[8]), - .I2(sl_iport_i[7]), - .I3(\reg_do[0]_i_3_n_0 ), - .I4(sl_iport_i[6]), - .I5(\reg_do[0]_i_4_n_0 ), - .O(\reg_do[0]_i_2_n_0 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \reg_do[0]_i_3 - (.I0(uuid_stamp[48]), - .I1(uuid_stamp[32]), - .I2(sl_iport_i[5]), - .I3(uuid_stamp[16]), - .I4(sl_iport_i[4]), - .I5(uuid_stamp[0]), - .O(\reg_do[0]_i_3_n_0 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \reg_do[0]_i_4 - (.I0(uuid_stamp[112]), - .I1(uuid_stamp[96]), - .I2(sl_iport_i[5]), - .I3(uuid_stamp[80]), - .I4(sl_iport_i[4]), - .I5(uuid_stamp[64]), - .O(\reg_do[0]_i_4_n_0 )); - LUT5 #( - .INIT(32'hFFFF2808)) - \reg_do[10]_i_1 - (.I0(\reg_do[10]_i_2_n_0 ), - .I1(sl_iport_i[4]), - .I2(sl_iport_i[5]), - .I3(reg_test[10]), - .I4(\reg_do[10]_i_3_n_0 ), - .O(reg_do[10])); - LUT6 #( - .INIT(64'h0800000000000000)) - \reg_do[10]_i_2 - (.I0(sl_iport_i[6]), - .I1(sl_iport_i[9]), - .I2(sl_iport_i[7]), - .I3(sl_iport_i[8]), - .I4(sl_iport_i[11]), - .I5(sl_iport_i[10]), - .O(\reg_do[10]_i_2_n_0 )); - LUT6 #( - .INIT(64'h00000000AAFBAA08)) - \reg_do[10]_i_3 - (.I0(\reg_do[10]_i_4_n_0 ), - .I1(sl_iport_i[6]), - .I2(sl_iport_i[7]), - .I3(sl_iport_i[8]), - .I4(\reg_do[10]_i_5_n_0 ), - .I5(\reg_do[15]_i_4_n_0 ), - .O(\reg_do[10]_i_3_n_0 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \reg_do[10]_i_4 - (.I0(uuid_stamp[122]), - .I1(uuid_stamp[106]), - .I2(sl_iport_i[5]), - .I3(uuid_stamp[90]), - .I4(sl_iport_i[4]), - .I5(uuid_stamp[74]), - .O(\reg_do[10]_i_4_n_0 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \reg_do[10]_i_5 - (.I0(uuid_stamp[58]), - .I1(uuid_stamp[42]), - .I2(sl_iport_i[5]), - .I3(uuid_stamp[26]), - .I4(sl_iport_i[4]), - .I5(uuid_stamp[10]), - .O(\reg_do[10]_i_5_n_0 )); - LUT6 #( - .INIT(64'h4540FFFF45404540)) - \reg_do[11]_i_1 - (.I0(\reg_do[15]_i_4_n_0 ), - .I1(\reg_do[11]_i_2_n_0 ), - .I2(\reg_do[15]_i_2_n_0 ), - .I3(\reg_do[11]_i_3_n_0 ), - .I4(\reg_do[15]_i_6_n_0 ), - .I5(reg_test[11]), - .O(reg_do[11])); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \reg_do[11]_i_2 - (.I0(uuid_stamp[59]), - .I1(uuid_stamp[43]), - .I2(sl_iport_i[5]), - .I3(uuid_stamp[27]), - .I4(sl_iport_i[4]), - .I5(uuid_stamp[11]), - .O(\reg_do[11]_i_2_n_0 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \reg_do[11]_i_3 - (.I0(uuid_stamp[123]), - .I1(uuid_stamp[107]), - .I2(sl_iport_i[5]), - .I3(uuid_stamp[91]), - .I4(sl_iport_i[4]), - .I5(uuid_stamp[75]), - .O(\reg_do[11]_i_3_n_0 )); - LUT6 #( - .INIT(64'h5404FFFF54045404)) - \reg_do[12]_i_1 - (.I0(\reg_do[15]_i_4_n_0 ), - .I1(\reg_do[12]_i_2_n_0 ), - .I2(\reg_do[15]_i_2_n_0 ), - .I3(\reg_do[12]_i_3_n_0 ), - .I4(\reg_do[15]_i_6_n_0 ), - .I5(reg_test[12]), - .O(reg_do[12])); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \reg_do[12]_i_2 - (.I0(uuid_stamp[124]), - .I1(uuid_stamp[108]), - .I2(sl_iport_i[5]), - .I3(uuid_stamp[92]), - .I4(sl_iport_i[4]), - .I5(uuid_stamp[76]), - .O(\reg_do[12]_i_2_n_0 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \reg_do[12]_i_3 - (.I0(uuid_stamp[60]), - .I1(uuid_stamp[44]), - .I2(sl_iport_i[5]), - .I3(uuid_stamp[28]), - .I4(sl_iport_i[4]), - .I5(uuid_stamp[12]), - .O(\reg_do[12]_i_3_n_0 )); - LUT6 #( - .INIT(64'h4540FFFF45404540)) - \reg_do[13]_i_1 - (.I0(\reg_do[15]_i_4_n_0 ), - .I1(\reg_do[13]_i_2_n_0 ), - .I2(\reg_do[15]_i_2_n_0 ), - .I3(\reg_do[13]_i_3_n_0 ), - .I4(\reg_do[15]_i_6_n_0 ), - .I5(reg_test[13]), - .O(reg_do[13])); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \reg_do[13]_i_2 - (.I0(uuid_stamp[61]), - .I1(uuid_stamp[45]), - .I2(sl_iport_i[5]), - .I3(uuid_stamp[29]), - .I4(sl_iport_i[4]), - .I5(uuid_stamp[13]), - .O(\reg_do[13]_i_2_n_0 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \reg_do[13]_i_3 - (.I0(uuid_stamp[125]), - .I1(uuid_stamp[109]), - .I2(sl_iport_i[5]), - .I3(uuid_stamp[93]), - .I4(sl_iport_i[4]), - .I5(uuid_stamp[77]), - .O(\reg_do[13]_i_3_n_0 )); - LUT6 #( - .INIT(64'h4540FFFF45404540)) - \reg_do[14]_i_1 - (.I0(\reg_do[15]_i_4_n_0 ), - .I1(\reg_do[14]_i_2_n_0 ), - .I2(\reg_do[15]_i_2_n_0 ), - .I3(\reg_do[14]_i_3_n_0 ), - .I4(\reg_do[15]_i_6_n_0 ), - .I5(reg_test[14]), - .O(reg_do[14])); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \reg_do[14]_i_2 - (.I0(uuid_stamp[62]), - .I1(uuid_stamp[46]), - .I2(sl_iport_i[5]), - .I3(uuid_stamp[30]), - .I4(sl_iport_i[4]), - .I5(uuid_stamp[14]), - .O(\reg_do[14]_i_2_n_0 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \reg_do[14]_i_3 - (.I0(uuid_stamp[126]), - .I1(uuid_stamp[110]), - .I2(sl_iport_i[5]), - .I3(uuid_stamp[94]), - .I4(sl_iport_i[4]), - .I5(uuid_stamp[78]), - .O(\reg_do[14]_i_3_n_0 )); - LUT6 #( - .INIT(64'h0B01FFFF0B010B01)) - \reg_do[15]_i_1 - (.I0(\reg_do[15]_i_2_n_0 ), - .I1(\reg_do[15]_i_3_n_0 ), - .I2(\reg_do[15]_i_4_n_0 ), - .I3(\reg_do[15]_i_5_n_0 ), - .I4(\reg_do[15]_i_6_n_0 ), - .I5(reg_test[15]), - .O(reg_do[15])); - (* SOFT_HLUTNM = "soft_lutpair9" *) - LUT3 #( - .INIT(8'h45)) - \reg_do[15]_i_2 - (.I0(sl_iport_i[8]), - .I1(sl_iport_i[7]), - .I2(sl_iport_i[6]), - .O(\reg_do[15]_i_2_n_0 )); - LUT6 #( - .INIT(64'h505F3030505F3F3F)) - \reg_do[15]_i_3 - (.I0(uuid_stamp[127]), - .I1(uuid_stamp[111]), - .I2(sl_iport_i[5]), - .I3(uuid_stamp[95]), - .I4(sl_iport_i[4]), - .I5(uuid_stamp[79]), - .O(\reg_do[15]_i_3_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair0" *) - LUT5 #( - .INIT(32'hFFFFFFFE)) - \reg_do[15]_i_4 - (.I0(sl_iport_i[7]), - .I1(sl_iport_i[8]), - .I2(sl_iport_i[9]), - .I3(sl_iport_i[11]), - .I4(sl_iport_i[10]), - .O(\reg_do[15]_i_4_n_0 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \reg_do[15]_i_5 - (.I0(uuid_stamp[63]), - .I1(uuid_stamp[47]), - .I2(sl_iport_i[5]), - .I3(uuid_stamp[31]), - .I4(sl_iport_i[4]), - .I5(uuid_stamp[15]), - .O(\reg_do[15]_i_5_n_0 )); - LUT6 #( - .INIT(64'hFFFFFFD0FFFFFFFF)) - \reg_do[15]_i_6 - (.I0(sl_iport_i[6]), - .I1(sl_iport_i[7]), - .I2(sl_iport_i[8]), - .I3(\reg_do[9]_i_2_n_0 ), - .I4(sl_iport_i[4]), - .I5(sl_iport_i[5]), - .O(\reg_do[15]_i_6_n_0 )); - LUT6 #( - .INIT(64'hAAAAAAAAAAAAFEAA)) - \reg_do[1]_i_1 - (.I0(\reg_do[1]_i_2_n_0 ), - .I1(reg_test[1]), - .I2(\reg_do[9]_i_3_n_0 ), - .I3(sl_iport_i[5]), - .I4(sl_iport_i[4]), - .I5(\reg_do[9]_i_2_n_0 ), - .O(reg_do[1])); - LUT6 #( - .INIT(64'h00000000FFAE00A2)) - \reg_do[1]_i_2 - (.I0(\reg_do[1]_i_3_n_0 ), - .I1(sl_iport_i[6]), - .I2(sl_iport_i[7]), - .I3(sl_iport_i[8]), - .I4(\reg_do[1]_i_4_n_0 ), - .I5(\reg_do[15]_i_4_n_0 ), - .O(\reg_do[1]_i_2_n_0 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \reg_do[1]_i_3 - (.I0(uuid_stamp[49]), - .I1(uuid_stamp[33]), - .I2(sl_iport_i[5]), - .I3(uuid_stamp[17]), - .I4(sl_iport_i[4]), - .I5(uuid_stamp[1]), - .O(\reg_do[1]_i_3_n_0 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \reg_do[1]_i_4 - (.I0(uuid_stamp[113]), - .I1(uuid_stamp[97]), - .I2(sl_iport_i[5]), - .I3(uuid_stamp[81]), - .I4(sl_iport_i[4]), - .I5(uuid_stamp[65]), - .O(\reg_do[1]_i_4_n_0 )); - LUT5 #( - .INIT(32'hFFFF6200)) - \reg_do[2]_i_1 - (.I0(sl_iport_i[4]), - .I1(sl_iport_i[5]), - .I2(reg_test[2]), - .I3(\reg_do[10]_i_2_n_0 ), - .I4(\reg_do[2]_i_2_n_0 ), - .O(reg_do[2])); - LUT6 #( - .INIT(64'h00000000AAFBAA08)) - \reg_do[2]_i_2 - (.I0(\reg_do[2]_i_3_n_0 ), - .I1(sl_iport_i[6]), - .I2(sl_iport_i[7]), - .I3(sl_iport_i[8]), - .I4(\reg_do[2]_i_4_n_0 ), - .I5(\reg_do[15]_i_4_n_0 ), - .O(\reg_do[2]_i_2_n_0 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \reg_do[2]_i_3 - (.I0(uuid_stamp[114]), - .I1(uuid_stamp[98]), - .I2(sl_iport_i[5]), - .I3(uuid_stamp[82]), - .I4(sl_iport_i[4]), - .I5(uuid_stamp[66]), - .O(\reg_do[2]_i_3_n_0 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \reg_do[2]_i_4 - (.I0(uuid_stamp[50]), - .I1(uuid_stamp[34]), - .I2(sl_iport_i[5]), - .I3(uuid_stamp[18]), - .I4(sl_iport_i[4]), - .I5(uuid_stamp[2]), - .O(\reg_do[2]_i_4_n_0 )); - LUT5 #( - .INIT(32'hFFFF6200)) - \reg_do[3]_i_1 - (.I0(sl_iport_i[4]), - .I1(sl_iport_i[5]), - .I2(reg_test[3]), - .I3(\reg_do[10]_i_2_n_0 ), - .I4(\reg_do[3]_i_2_n_0 ), - .O(reg_do[3])); - LUT6 #( - .INIT(64'h000000003333AA3A)) - \reg_do[3]_i_2 - (.I0(\reg_do[3]_i_3_n_0 ), - .I1(\reg_do[3]_i_4_n_0 ), - .I2(sl_iport_i[6]), - .I3(sl_iport_i[7]), - .I4(sl_iport_i[8]), - .I5(\reg_do[15]_i_4_n_0 ), - .O(\reg_do[3]_i_2_n_0 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \reg_do[3]_i_3 - (.I0(uuid_stamp[51]), - .I1(uuid_stamp[35]), - .I2(sl_iport_i[5]), - .I3(uuid_stamp[19]), - .I4(sl_iport_i[4]), - .I5(uuid_stamp[3]), - .O(\reg_do[3]_i_3_n_0 )); - LUT6 #( - .INIT(64'h05F5030305F5F3F3)) - \reg_do[3]_i_4 - (.I0(uuid_stamp[83]), - .I1(uuid_stamp[67]), - .I2(sl_iport_i[5]), - .I3(uuid_stamp[115]), - .I4(sl_iport_i[4]), - .I5(uuid_stamp[99]), - .O(\reg_do[3]_i_4_n_0 )); - LUT5 #( - .INIT(32'hFFFF6200)) - \reg_do[4]_i_1 - (.I0(sl_iport_i[4]), - .I1(sl_iport_i[5]), - .I2(reg_test[4]), - .I3(\reg_do[10]_i_2_n_0 ), - .I4(\reg_do[4]_i_2_n_0 ), - .O(reg_do[4])); - LUT6 #( - .INIT(64'h00000000FFAE00A2)) - \reg_do[4]_i_2 - (.I0(\reg_do[4]_i_3_n_0 ), - .I1(sl_iport_i[6]), - .I2(sl_iport_i[7]), - .I3(sl_iport_i[8]), - .I4(\reg_do[4]_i_4_n_0 ), - .I5(\reg_do[15]_i_4_n_0 ), - .O(\reg_do[4]_i_2_n_0 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \reg_do[4]_i_3 - (.I0(uuid_stamp[52]), - .I1(uuid_stamp[36]), - .I2(sl_iport_i[5]), - .I3(uuid_stamp[20]), - .I4(sl_iport_i[4]), - .I5(uuid_stamp[4]), - .O(\reg_do[4]_i_3_n_0 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \reg_do[4]_i_4 - (.I0(uuid_stamp[116]), - .I1(uuid_stamp[100]), - .I2(sl_iport_i[5]), - .I3(uuid_stamp[84]), - .I4(sl_iport_i[4]), - .I5(uuid_stamp[68]), - .O(\reg_do[4]_i_4_n_0 )); - LUT6 #( - .INIT(64'h888888888A88A8A8)) - \reg_do[5]_i_1 - (.I0(\reg_do[5]_i_2_n_0 ), - .I1(\reg_do[9]_i_2_n_0 ), - .I2(\reg_do[9]_i_3_n_0 ), - .I3(reg_test[5]), - .I4(sl_iport_i[5]), - .I5(sl_iport_i[4]), - .O(reg_do[5])); - LUT6 #( - .INIT(64'hABABABAAAAAAABAA)) - \reg_do[5]_i_2 - (.I0(\reg_do[5]_i_3_n_0 ), - .I1(sl_iport_i[8]), - .I2(sl_iport_i[7]), - .I3(\reg_do[5]_i_4_n_0 ), - .I4(sl_iport_i[6]), - .I5(\reg_do[5]_i_5_n_0 ), - .O(\reg_do[5]_i_2_n_0 )); - LUT4 #( - .INIT(16'hFFFE)) - \reg_do[5]_i_3 - (.I0(sl_iport_i[10]), - .I1(sl_iport_i[11]), - .I2(sl_iport_i[9]), - .I3(sl_iport_i[8]), - .O(\reg_do[5]_i_3_n_0 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \reg_do[5]_i_4 - (.I0(uuid_stamp[53]), - .I1(uuid_stamp[37]), - .I2(sl_iport_i[5]), - .I3(uuid_stamp[21]), - .I4(sl_iport_i[4]), - .I5(uuid_stamp[5]), - .O(\reg_do[5]_i_4_n_0 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \reg_do[5]_i_5 - (.I0(uuid_stamp[117]), - .I1(uuid_stamp[101]), - .I2(sl_iport_i[5]), - .I3(uuid_stamp[85]), - .I4(sl_iport_i[4]), - .I5(uuid_stamp[69]), - .O(\reg_do[5]_i_5_n_0 )); - LUT5 #( - .INIT(32'hFFFF6200)) - \reg_do[6]_i_1 - (.I0(sl_iport_i[4]), - .I1(sl_iport_i[5]), - .I2(reg_test[6]), - .I3(\reg_do[10]_i_2_n_0 ), - .I4(\reg_do[6]_i_2_n_0 ), - .O(reg_do[6])); - LUT6 #( - .INIT(64'h00000000AAFBAA08)) - \reg_do[6]_i_2 - (.I0(\reg_do[6]_i_3_n_0 ), - .I1(sl_iport_i[6]), - .I2(sl_iport_i[7]), - .I3(sl_iport_i[8]), - .I4(\reg_do[6]_i_4_n_0 ), - .I5(\reg_do[15]_i_4_n_0 ), - .O(\reg_do[6]_i_2_n_0 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \reg_do[6]_i_3 - (.I0(uuid_stamp[118]), - .I1(uuid_stamp[102]), - .I2(sl_iport_i[5]), - .I3(uuid_stamp[86]), - .I4(sl_iport_i[4]), - .I5(uuid_stamp[70]), - .O(\reg_do[6]_i_3_n_0 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \reg_do[6]_i_4 - (.I0(uuid_stamp[54]), - .I1(uuid_stamp[38]), - .I2(sl_iport_i[5]), - .I3(uuid_stamp[22]), - .I4(sl_iport_i[4]), - .I5(uuid_stamp[6]), - .O(\reg_do[6]_i_4_n_0 )); - LUT5 #( - .INIT(32'hFFFF6200)) - \reg_do[7]_i_1 - (.I0(sl_iport_i[4]), - .I1(sl_iport_i[5]), - .I2(reg_test[7]), - .I3(\reg_do[10]_i_2_n_0 ), - .I4(\reg_do[7]_i_2_n_0 ), - .O(reg_do[7])); - LUT6 #( - .INIT(64'h00000000AAFBAA08)) - \reg_do[7]_i_2 - (.I0(\reg_do[7]_i_3_n_0 ), - .I1(sl_iport_i[6]), - .I2(sl_iport_i[7]), - .I3(sl_iport_i[8]), - .I4(\reg_do[7]_i_4_n_0 ), - .I5(\reg_do[15]_i_4_n_0 ), - .O(\reg_do[7]_i_2_n_0 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \reg_do[7]_i_3 - (.I0(uuid_stamp[119]), - .I1(uuid_stamp[103]), - .I2(sl_iport_i[5]), - .I3(uuid_stamp[87]), - .I4(sl_iport_i[4]), - .I5(uuid_stamp[71]), - .O(\reg_do[7]_i_3_n_0 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \reg_do[7]_i_4 - (.I0(uuid_stamp[55]), - .I1(uuid_stamp[39]), - .I2(sl_iport_i[5]), - .I3(uuid_stamp[23]), - .I4(sl_iport_i[4]), - .I5(uuid_stamp[7]), - .O(\reg_do[7]_i_4_n_0 )); - LUT5 #( - .INIT(32'hFFFF7500)) - \reg_do[8]_i_1 - (.I0(sl_iport_i[5]), - .I1(sl_iport_i[4]), - .I2(reg_test[8]), - .I3(\reg_do[10]_i_2_n_0 ), - .I4(\reg_do[8]_i_2_n_0 ), - .O(reg_do[8])); - LUT6 #( - .INIT(64'h00000000AAFBAA08)) - \reg_do[8]_i_2 - (.I0(\reg_do[8]_i_3_n_0 ), - .I1(sl_iport_i[6]), - .I2(sl_iport_i[7]), - .I3(sl_iport_i[8]), - .I4(\reg_do[8]_i_4_n_0 ), - .I5(\reg_do[15]_i_4_n_0 ), - .O(\reg_do[8]_i_2_n_0 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \reg_do[8]_i_3 - (.I0(uuid_stamp[120]), - .I1(uuid_stamp[104]), - .I2(sl_iport_i[5]), - .I3(uuid_stamp[88]), - .I4(sl_iport_i[4]), - .I5(uuid_stamp[72]), - .O(\reg_do[8]_i_3_n_0 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \reg_do[8]_i_4 - (.I0(uuid_stamp[56]), - .I1(uuid_stamp[40]), - .I2(sl_iport_i[5]), - .I3(uuid_stamp[24]), - .I4(sl_iport_i[4]), - .I5(uuid_stamp[8]), - .O(\reg_do[8]_i_4_n_0 )); - LUT6 #( - .INIT(64'hFFFFFFFF40144010)) - \reg_do[9]_i_1 - (.I0(\reg_do[9]_i_2_n_0 ), - .I1(sl_iport_i[5]), - .I2(sl_iport_i[4]), - .I3(\reg_do[9]_i_3_n_0 ), - .I4(reg_test[9]), - .I5(\reg_do[9]_i_4_n_0 ), - .O(reg_do[9])); - (* SOFT_HLUTNM = "soft_lutpair0" *) - LUT5 #( - .INIT(32'hFF7FFFFF)) - \reg_do[9]_i_2 - (.I0(sl_iport_i[10]), - .I1(sl_iport_i[11]), - .I2(sl_iport_i[8]), - .I3(sl_iport_i[7]), - .I4(sl_iport_i[9]), - .O(\reg_do[9]_i_2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair9" *) - LUT3 #( - .INIT(8'h8A)) - \reg_do[9]_i_3 - (.I0(sl_iport_i[8]), - .I1(sl_iport_i[7]), - .I2(sl_iport_i[6]), - .O(\reg_do[9]_i_3_n_0 )); - LUT6 #( - .INIT(64'h00000000AAFBAA08)) - \reg_do[9]_i_4 - (.I0(\reg_do[9]_i_5_n_0 ), - .I1(sl_iport_i[6]), - .I2(sl_iport_i[7]), - .I3(sl_iport_i[8]), - .I4(\reg_do[9]_i_6_n_0 ), - .I5(\reg_do[15]_i_4_n_0 ), - .O(\reg_do[9]_i_4_n_0 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \reg_do[9]_i_5 - (.I0(uuid_stamp[121]), - .I1(uuid_stamp[105]), - .I2(sl_iport_i[5]), - .I3(uuid_stamp[89]), - .I4(sl_iport_i[4]), - .I5(uuid_stamp[73]), - .O(\reg_do[9]_i_5_n_0 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \reg_do[9]_i_6 - (.I0(uuid_stamp[57]), - .I1(uuid_stamp[41]), - .I2(sl_iport_i[5]), - .I3(uuid_stamp[25]), - .I4(sl_iport_i[4]), - .I5(uuid_stamp[9]), - .O(\reg_do[9]_i_6_n_0 )); - FDRE #( - .INIT(1'b0)) - \reg_do_reg[0] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(reg_do[0]), - .Q(\reg_do_reg_n_0_[0] ), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \reg_do_reg[10] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(reg_do[10]), - .Q(\reg_do_reg_n_0_[10] ), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \reg_do_reg[11] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(reg_do[11]), - .Q(\reg_do_reg_n_0_[11] ), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \reg_do_reg[12] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(reg_do[12]), - .Q(\reg_do_reg_n_0_[12] ), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \reg_do_reg[13] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(reg_do[13]), - .Q(\reg_do_reg_n_0_[13] ), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \reg_do_reg[14] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(reg_do[14]), - .Q(\reg_do_reg_n_0_[14] ), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \reg_do_reg[15] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(reg_do[15]), - .Q(\reg_do_reg_n_0_[15] ), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \reg_do_reg[1] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(reg_do[1]), - .Q(\reg_do_reg_n_0_[1] ), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \reg_do_reg[2] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(reg_do[2]), - .Q(\reg_do_reg_n_0_[2] ), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \reg_do_reg[3] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(reg_do[3]), - .Q(\reg_do_reg_n_0_[3] ), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \reg_do_reg[4] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(reg_do[4]), - .Q(\reg_do_reg_n_0_[4] ), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \reg_do_reg[5] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(reg_do[5]), - .Q(\reg_do_reg_n_0_[5] ), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \reg_do_reg[6] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(reg_do[6]), - .Q(\reg_do_reg_n_0_[6] ), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \reg_do_reg[7] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(reg_do[7]), - .Q(\reg_do_reg_n_0_[7] ), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \reg_do_reg[8] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(reg_do[8]), - .Q(\reg_do_reg_n_0_[8] ), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \reg_do_reg[9] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(reg_do[9]), - .Q(\reg_do_reg_n_0_[9] ), - .R(1'b0)); - LUT6 #( - .INIT(64'h0000800000000000)) - reg_drdy_i_1 - (.I0(s_den_o_INST_0_i_1_n_0), - .I1(sl_iport_i[12]), - .I2(sl_iport_i[13]), - .I3(sl_iport_i[14]), - .I4(sl_iport_i[0]), - .I5(sl_iport_i[2]), - .O(reg_drdy_i_1_n_0)); - FDRE #( - .INIT(1'b0)) - reg_drdy_reg - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(reg_drdy_i_1_n_0), - .Q(reg_drdy), - .R(1'b0)); - LUT6 #( - .INIT(64'h8000000000000000)) - \reg_test[15]_i_1 - (.I0(s_den_o_INST_0_i_1_n_0), - .I1(sl_iport_i[12]), - .I2(sl_iport_i[13]), - .I3(sl_iport_i[14]), - .I4(sl_iport_i[3]), - .I5(sl_iport_i[2]), - .O(reg_test0)); - FDRE #( - .INIT(1'b0)) - \reg_test_reg[0] - (.C(sl_iport_i[1]), - .CE(reg_test0), - .D(sl_iport_i[21]), - .Q(reg_test[0]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \reg_test_reg[10] - (.C(sl_iport_i[1]), - .CE(reg_test0), - .D(sl_iport_i[31]), - .Q(reg_test[10]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \reg_test_reg[11] - (.C(sl_iport_i[1]), - .CE(reg_test0), - .D(sl_iport_i[32]), - .Q(reg_test[11]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \reg_test_reg[12] - (.C(sl_iport_i[1]), - .CE(reg_test0), - .D(sl_iport_i[33]), - .Q(reg_test[12]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \reg_test_reg[13] - (.C(sl_iport_i[1]), - .CE(reg_test0), - .D(sl_iport_i[34]), - .Q(reg_test[13]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \reg_test_reg[14] - (.C(sl_iport_i[1]), - .CE(reg_test0), - .D(sl_iport_i[35]), - .Q(reg_test[14]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \reg_test_reg[15] - (.C(sl_iport_i[1]), - .CE(reg_test0), - .D(sl_iport_i[36]), - .Q(reg_test[15]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \reg_test_reg[1] - (.C(sl_iport_i[1]), - .CE(reg_test0), - .D(sl_iport_i[22]), - .Q(reg_test[1]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \reg_test_reg[2] - (.C(sl_iport_i[1]), - .CE(reg_test0), - .D(sl_iport_i[23]), - .Q(reg_test[2]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \reg_test_reg[3] - (.C(sl_iport_i[1]), - .CE(reg_test0), - .D(sl_iport_i[24]), - .Q(reg_test[3]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \reg_test_reg[4] - (.C(sl_iport_i[1]), - .CE(reg_test0), - .D(sl_iport_i[25]), - .Q(reg_test[4]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \reg_test_reg[5] - (.C(sl_iport_i[1]), - .CE(reg_test0), - .D(sl_iport_i[26]), - .Q(reg_test[5]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \reg_test_reg[6] - (.C(sl_iport_i[1]), - .CE(reg_test0), - .D(sl_iport_i[27]), - .Q(reg_test[6]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \reg_test_reg[7] - (.C(sl_iport_i[1]), - .CE(reg_test0), - .D(sl_iport_i[28]), - .Q(reg_test[7]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \reg_test_reg[8] - (.C(sl_iport_i[1]), - .CE(reg_test0), - .D(sl_iport_i[29]), - .Q(reg_test[8]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \reg_test_reg[9] - (.C(sl_iport_i[1]), - .CE(reg_test0), - .D(sl_iport_i[30]), - .Q(reg_test[9]), - .R(1'b0)); - LUT5 #( - .INIT(32'h7FFF0000)) - s_den_o_INST_0 - (.I0(s_den_o_INST_0_i_1_n_0), - .I1(sl_iport_i[12]), - .I2(sl_iport_i[13]), - .I3(sl_iport_i[14]), - .I4(sl_iport_i[2]), - .O(s_den_o)); - LUT6 #( - .INIT(64'h8000000000000000)) - s_den_o_INST_0_i_1 - (.I0(sl_iport_i[15]), - .I1(sl_iport_i[16]), - .I2(sl_iport_i[17]), - .I3(sl_iport_i[18]), - .I4(sl_iport_i[20]), - .I5(sl_iport_i[19]), - .O(s_den_o_INST_0_i_1_n_0)); - (* SOFT_HLUTNM = "soft_lutpair1" *) - LUT2 #( - .INIT(4'hE)) - \sl_oport_o[0]_INST_0 - (.I0(reg_drdy), - .I1(s_drdy_i), - .O(sl_oport_o[0])); - (* SOFT_HLUTNM = "soft_lutpair6" *) - LUT3 #( - .INIT(8'hB8)) - \sl_oport_o[10]_INST_0 - (.I0(\reg_do_reg_n_0_[9] ), - .I1(reg_drdy), - .I2(s_do_i[9]), - .O(sl_oport_o[10])); - (* SOFT_HLUTNM = "soft_lutpair6" *) - LUT3 #( - .INIT(8'hB8)) - \sl_oport_o[11]_INST_0 - (.I0(\reg_do_reg_n_0_[10] ), - .I1(reg_drdy), - .I2(s_do_i[10]), - .O(sl_oport_o[11])); - (* SOFT_HLUTNM = "soft_lutpair7" *) - LUT3 #( - .INIT(8'hB8)) - \sl_oport_o[12]_INST_0 - (.I0(\reg_do_reg_n_0_[11] ), - .I1(reg_drdy), - .I2(s_do_i[11]), - .O(sl_oport_o[12])); - (* SOFT_HLUTNM = "soft_lutpair7" *) - LUT3 #( - .INIT(8'hB8)) - \sl_oport_o[13]_INST_0 - (.I0(\reg_do_reg_n_0_[12] ), - .I1(reg_drdy), - .I2(s_do_i[12]), - .O(sl_oport_o[13])); - (* SOFT_HLUTNM = "soft_lutpair8" *) - LUT3 #( - .INIT(8'hB8)) - \sl_oport_o[14]_INST_0 - (.I0(\reg_do_reg_n_0_[13] ), - .I1(reg_drdy), - .I2(s_do_i[13]), - .O(sl_oport_o[14])); - (* SOFT_HLUTNM = "soft_lutpair8" *) - LUT3 #( - .INIT(8'hB8)) - \sl_oport_o[15]_INST_0 - (.I0(\reg_do_reg_n_0_[14] ), - .I1(reg_drdy), - .I2(s_do_i[14]), - .O(sl_oport_o[15])); - LUT3 #( - .INIT(8'hB8)) - \sl_oport_o[16]_INST_0 - (.I0(\reg_do_reg_n_0_[15] ), - .I1(reg_drdy), - .I2(s_do_i[15]), - .O(sl_oport_o[16])); - (* SOFT_HLUTNM = "soft_lutpair2" *) - LUT3 #( - .INIT(8'hB8)) - \sl_oport_o[1]_INST_0 - (.I0(\reg_do_reg_n_0_[0] ), - .I1(reg_drdy), - .I2(s_do_i[0]), - .O(sl_oport_o[1])); - (* SOFT_HLUTNM = "soft_lutpair1" *) - LUT3 #( - .INIT(8'hB8)) - \sl_oport_o[2]_INST_0 - (.I0(\reg_do_reg_n_0_[1] ), - .I1(reg_drdy), - .I2(s_do_i[1]), - .O(sl_oport_o[2])); - (* SOFT_HLUTNM = "soft_lutpair3" *) - LUT3 #( - .INIT(8'hB8)) - \sl_oport_o[3]_INST_0 - (.I0(\reg_do_reg_n_0_[2] ), - .I1(reg_drdy), - .I2(s_do_i[2]), - .O(sl_oport_o[3])); - (* SOFT_HLUTNM = "soft_lutpair2" *) - LUT3 #( - .INIT(8'hB8)) - \sl_oport_o[4]_INST_0 - (.I0(\reg_do_reg_n_0_[3] ), - .I1(reg_drdy), - .I2(s_do_i[3]), - .O(sl_oport_o[4])); - (* SOFT_HLUTNM = "soft_lutpair3" *) - LUT3 #( - .INIT(8'hB8)) - \sl_oport_o[5]_INST_0 - (.I0(\reg_do_reg_n_0_[4] ), - .I1(reg_drdy), - .I2(s_do_i[4]), - .O(sl_oport_o[5])); - (* SOFT_HLUTNM = "soft_lutpair4" *) - LUT3 #( - .INIT(8'hB8)) - \sl_oport_o[6]_INST_0 - (.I0(\reg_do_reg_n_0_[5] ), - .I1(reg_drdy), - .I2(s_do_i[5]), - .O(sl_oport_o[6])); - (* SOFT_HLUTNM = "soft_lutpair4" *) - LUT3 #( - .INIT(8'hB8)) - \sl_oport_o[7]_INST_0 - (.I0(\reg_do_reg_n_0_[6] ), - .I1(reg_drdy), - .I2(s_do_i[6]), - .O(sl_oport_o[7])); - (* SOFT_HLUTNM = "soft_lutpair5" *) - LUT3 #( - .INIT(8'hB8)) - \sl_oport_o[8]_INST_0 - (.I0(\reg_do_reg_n_0_[7] ), - .I1(reg_drdy), - .I2(s_do_i[7]), - .O(sl_oport_o[8])); - (* SOFT_HLUTNM = "soft_lutpair5" *) - LUT3 #( - .INIT(8'hB8)) - \sl_oport_o[9]_INST_0 - (.I0(\reg_do_reg_n_0_[8] ), - .I1(reg_drdy), - .I2(s_do_i[8]), - .O(sl_oport_o[9])); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[0] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[0]), - .Q(uuid_stamp[0]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[100] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[100]), - .Q(uuid_stamp[100]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[101] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[101]), - .Q(uuid_stamp[101]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[102] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[102]), - .Q(uuid_stamp[102]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[103] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[103]), - .Q(uuid_stamp[103]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[104] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[104]), - .Q(uuid_stamp[104]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[105] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[105]), - .Q(uuid_stamp[105]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[106] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[106]), - .Q(uuid_stamp[106]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[107] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[107]), - .Q(uuid_stamp[107]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[108] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[108]), - .Q(uuid_stamp[108]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[109] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[109]), - .Q(uuid_stamp[109]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[10] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[10]), - .Q(uuid_stamp[10]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[110] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[110]), - .Q(uuid_stamp[110]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[111] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[111]), - .Q(uuid_stamp[111]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[112] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[112]), - .Q(uuid_stamp[112]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[113] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[113]), - .Q(uuid_stamp[113]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[114] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[114]), - .Q(uuid_stamp[114]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[115] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[115]), - .Q(uuid_stamp[115]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[116] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[116]), - .Q(uuid_stamp[116]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[117] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[117]), - .Q(uuid_stamp[117]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[118] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[118]), - .Q(uuid_stamp[118]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[119] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[119]), - .Q(uuid_stamp[119]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[11] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[11]), - .Q(uuid_stamp[11]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[120] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[120]), - .Q(uuid_stamp[120]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[121] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[121]), - .Q(uuid_stamp[121]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[122] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[122]), - .Q(uuid_stamp[122]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[123] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[123]), - .Q(uuid_stamp[123]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[124] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[124]), - .Q(uuid_stamp[124]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[125] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[125]), - .Q(uuid_stamp[125]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[126] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[126]), - .Q(uuid_stamp[126]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[127] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[127]), - .Q(uuid_stamp[127]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[12] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[12]), - .Q(uuid_stamp[12]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[13] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[13]), - .Q(uuid_stamp[13]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[14] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[14]), - .Q(uuid_stamp[14]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[15] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[15]), - .Q(uuid_stamp[15]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[16] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[16]), - .Q(uuid_stamp[16]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[17] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[17]), - .Q(uuid_stamp[17]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[18] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[18]), - .Q(uuid_stamp[18]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[19] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[19]), - .Q(uuid_stamp[19]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[1] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[1]), - .Q(uuid_stamp[1]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[20] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[20]), - .Q(uuid_stamp[20]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[21] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[21]), - .Q(uuid_stamp[21]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[22] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[22]), - .Q(uuid_stamp[22]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[23] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[23]), - .Q(uuid_stamp[23]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[24] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[24]), - .Q(uuid_stamp[24]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[25] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[25]), - .Q(uuid_stamp[25]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[26] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[26]), - .Q(uuid_stamp[26]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[27] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[27]), - .Q(uuid_stamp[27]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[28] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[28]), - .Q(uuid_stamp[28]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[29] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[29]), - .Q(uuid_stamp[29]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[2] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[2]), - .Q(uuid_stamp[2]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[30] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[30]), - .Q(uuid_stamp[30]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[31] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[31]), - .Q(uuid_stamp[31]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[32] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[32]), - .Q(uuid_stamp[32]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[33] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[33]), - .Q(uuid_stamp[33]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[34] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[34]), - .Q(uuid_stamp[34]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[35] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[35]), - .Q(uuid_stamp[35]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[36] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[36]), - .Q(uuid_stamp[36]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[37] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[37]), - .Q(uuid_stamp[37]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[38] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[38]), - .Q(uuid_stamp[38]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[39] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[39]), - .Q(uuid_stamp[39]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[3] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[3]), - .Q(uuid_stamp[3]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[40] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[40]), - .Q(uuid_stamp[40]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[41] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[41]), - .Q(uuid_stamp[41]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[42] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[42]), - .Q(uuid_stamp[42]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[43] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[43]), - .Q(uuid_stamp[43]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[44] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[44]), - .Q(uuid_stamp[44]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[45] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[45]), - .Q(uuid_stamp[45]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[46] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[46]), - .Q(uuid_stamp[46]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[47] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[47]), - .Q(uuid_stamp[47]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[48] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[48]), - .Q(uuid_stamp[48]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[49] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[49]), - .Q(uuid_stamp[49]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[4] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[4]), - .Q(uuid_stamp[4]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[50] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[50]), - .Q(uuid_stamp[50]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[51] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[51]), - .Q(uuid_stamp[51]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[52] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[52]), - .Q(uuid_stamp[52]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[53] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[53]), - .Q(uuid_stamp[53]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[54] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[54]), - .Q(uuid_stamp[54]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[55] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[55]), - .Q(uuid_stamp[55]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[56] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[56]), - .Q(uuid_stamp[56]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[57] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[57]), - .Q(uuid_stamp[57]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[58] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[58]), - .Q(uuid_stamp[58]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[59] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[59]), - .Q(uuid_stamp[59]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[5] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[5]), - .Q(uuid_stamp[5]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[60] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[60]), - .Q(uuid_stamp[60]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[61] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[61]), - .Q(uuid_stamp[61]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[62] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[62]), - .Q(uuid_stamp[62]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[63] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[63]), - .Q(uuid_stamp[63]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[64] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[64]), - .Q(uuid_stamp[64]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[65] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[65]), - .Q(uuid_stamp[65]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[66] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[66]), - .Q(uuid_stamp[66]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[67] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[67]), - .Q(uuid_stamp[67]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[68] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[68]), - .Q(uuid_stamp[68]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[69] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[69]), - .Q(uuid_stamp[69]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[6] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[6]), - .Q(uuid_stamp[6]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[70] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[70]), - .Q(uuid_stamp[70]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[71] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[71]), - .Q(uuid_stamp[71]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[72] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[72]), - .Q(uuid_stamp[72]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[73] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[73]), - .Q(uuid_stamp[73]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[74] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[74]), - .Q(uuid_stamp[74]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[75] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[75]), - .Q(uuid_stamp[75]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[76] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[76]), - .Q(uuid_stamp[76]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[77] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[77]), - .Q(uuid_stamp[77]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[78] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[78]), - .Q(uuid_stamp[78]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[79] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[79]), - .Q(uuid_stamp[79]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[7] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[7]), - .Q(uuid_stamp[7]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[80] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[80]), - .Q(uuid_stamp[80]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[81] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[81]), - .Q(uuid_stamp[81]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[82] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[82]), - .Q(uuid_stamp[82]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[83] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[83]), - .Q(uuid_stamp[83]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[84] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[84]), - .Q(uuid_stamp[84]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[85] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[85]), - .Q(uuid_stamp[85]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[86] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[86]), - .Q(uuid_stamp[86]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[87] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[87]), - .Q(uuid_stamp[87]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[88] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[88]), - .Q(uuid_stamp[88]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[89] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[89]), - .Q(uuid_stamp[89]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[8] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[8]), - .Q(uuid_stamp[8]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[90] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[90]), - .Q(uuid_stamp[90]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[91] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[91]), - .Q(uuid_stamp[91]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[92] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[92]), - .Q(uuid_stamp[92]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[93] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[93]), - .Q(uuid_stamp[93]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[94] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[94]), - .Q(uuid_stamp[94]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[95] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[95]), - .Q(uuid_stamp[95]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[96] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[96]), - .Q(uuid_stamp[96]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[97] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[97]), - .Q(uuid_stamp[97]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[98] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[98]), - .Q(uuid_stamp[98]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[99] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[99]), - .Q(uuid_stamp[99]), - .R(1'b0)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* UUID = "1" *) - FDRE \uuid_stamp_reg[9] - (.C(sl_iport_i[1]), - .CE(1'b1), - .D(uuid_stamp[9]), - .Q(uuid_stamp[9]), - .R(1'b0)); -endmodule -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/vio_0_sim_netlist.vhdl b/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/vio_0_sim_netlist.vhdl deleted file mode 100755 index 1597560..0000000 --- a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/vio_0_sim_netlist.vhdl +++ /dev/null @@ -1,19070 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.2 (win64) Build 2700185 Thu Oct 24 18:46:05 MDT 2019 --- Date : Fri Apr 1 15:55:35 2022 --- Host : PAVLOV running 64-bit Service Pack 1 (build 7601) --- Command : write_vhdl -force -mode funcsim --- J:/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/vio_0_sim_netlist.vhdl --- Design : vio_0 --- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or --- synthesized. This netlist cannot be used for SDF annotated simulation. --- Device : xc7z020clg400-1 --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity vio_0_vio_v3_0_19_decoder is - port ( - s_drdy_i : out STD_LOGIC; - in0 : out STD_LOGIC; - SR : out STD_LOGIC_VECTOR ( 0 to 0 ); - internal_cnt_rst : out STD_LOGIC; - \wr_en[2]_i_2_0\ : out STD_LOGIC; - \xsdb_wr__0\ : out STD_LOGIC; - \wr_en[2]_i_4_0\ : out STD_LOGIC; - Read_int_i_7_0 : out STD_LOGIC; - Read_int_i_7_1 : out STD_LOGIC; - int_cnt_rst_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 ); - E : out STD_LOGIC_VECTOR ( 0 to 0 ); - \Bus_data_out_reg[15]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); - s_rst_o : in STD_LOGIC; - Q : in STD_LOGIC_VECTOR ( 15 downto 0 ); - CLK : in STD_LOGIC; - xsdb_rd : in STD_LOGIC; - s_daddr_o : in STD_LOGIC_VECTOR ( 16 downto 0 ); - s_den_o : in STD_LOGIC; - s_dwe_o : in STD_LOGIC; - addr_count_reg1 : in STD_LOGIC; - \Bus_data_out_reg[15]_1\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); - \Bus_data_out_reg[15]_2\ : in STD_LOGIC_VECTOR ( 15 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of vio_0_vio_v3_0_19_decoder : entity is "vio_v3_0_19_decoder"; -end vio_0_vio_v3_0_19_decoder; - -architecture STRUCTURE of vio_0_vio_v3_0_19_decoder is - signal \Bus_data_out[0]_i_1_n_0\ : STD_LOGIC; - signal \Bus_data_out[10]_i_1_n_0\ : STD_LOGIC; - signal \Bus_data_out[10]_i_2_n_0\ : STD_LOGIC; - signal \Bus_data_out[11]_i_1_n_0\ : STD_LOGIC; - signal \Bus_data_out[11]_i_2_n_0\ : STD_LOGIC; - signal \Bus_data_out[12]_i_1_n_0\ : STD_LOGIC; - signal \Bus_data_out[12]_i_2_n_0\ : STD_LOGIC; - signal \Bus_data_out[13]_i_1_n_0\ : STD_LOGIC; - signal \Bus_data_out[14]_i_1_n_0\ : STD_LOGIC; - signal \Bus_data_out[15]_i_1_n_0\ : STD_LOGIC; - signal \Bus_data_out[15]_i_2_n_0\ : STD_LOGIC; - signal \Bus_data_out[15]_i_3_n_0\ : STD_LOGIC; - signal \Bus_data_out[1]_i_1_n_0\ : STD_LOGIC; - signal \Bus_data_out[2]_i_1_n_0\ : STD_LOGIC; - signal \Bus_data_out[2]_i_2_n_0\ : STD_LOGIC; - signal \Bus_data_out[3]_i_1_n_0\ : STD_LOGIC; - signal \Bus_data_out[3]_i_2_n_0\ : STD_LOGIC; - signal \Bus_data_out[4]_i_1_n_0\ : STD_LOGIC; - signal \Bus_data_out[4]_i_2_n_0\ : STD_LOGIC; - signal \Bus_data_out[5]_i_1_n_0\ : STD_LOGIC; - signal \Bus_data_out[6]_i_1_n_0\ : STD_LOGIC; - signal \Bus_data_out[7]_i_1_n_0\ : STD_LOGIC; - signal \Bus_data_out[8]_i_1_n_0\ : STD_LOGIC; - signal \Bus_data_out[8]_i_2_n_0\ : STD_LOGIC; - signal \Bus_data_out[9]_i_1_n_0\ : STD_LOGIC; - signal \Bus_data_out[9]_i_2_n_0\ : STD_LOGIC; - signal Hold_probe_in : STD_LOGIC; - signal \^read_int_i_7_0\ : STD_LOGIC; - signal \^read_int_i_7_1\ : STD_LOGIC; - signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal data_info_probe_in : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal \^in0\ : STD_LOGIC; - signal \^internal_cnt_rst\ : STD_LOGIC; - signal probe_out_modified : STD_LOGIC_VECTOR ( 15 downto 0 ); - signal rd_en_p1 : STD_LOGIC; - signal rd_en_p2 : STD_LOGIC; - signal wr_control_reg : STD_LOGIC; - signal \wr_en[2]_i_1_n_0\ : STD_LOGIC; - signal \^wr_en[2]_i_2_0\ : STD_LOGIC; - signal \^wr_en[2]_i_4_0\ : STD_LOGIC; - signal \wr_en[4]_i_1_n_0\ : STD_LOGIC; - signal \wr_en[4]_i_2_n_0\ : STD_LOGIC; - signal wr_probe_out_modified : STD_LOGIC; - signal xsdb_addr_2_0_p1 : STD_LOGIC_VECTOR ( 2 downto 0 ); - signal xsdb_addr_2_0_p2 : STD_LOGIC_VECTOR ( 2 downto 0 ); - signal xsdb_addr_8_p1 : STD_LOGIC; - signal xsdb_addr_8_p2 : STD_LOGIC; - signal xsdb_drdy_i_1_n_0 : STD_LOGIC; - signal \^xsdb_wr__0\ : STD_LOGIC; - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \Bus_data_out[10]_i_1\ : label is "soft_lutpair11"; - attribute SOFT_HLUTNM of \Bus_data_out[11]_i_1\ : label is "soft_lutpair14"; - attribute SOFT_HLUTNM of \Bus_data_out[12]_i_1\ : label is "soft_lutpair12"; - attribute SOFT_HLUTNM of \Bus_data_out[15]_i_2\ : label is "soft_lutpair10"; - attribute SOFT_HLUTNM of \Bus_data_out[15]_i_3\ : label is "soft_lutpair10"; - attribute SOFT_HLUTNM of \Bus_data_out[1]_i_1\ : label is "soft_lutpair14"; - attribute SOFT_HLUTNM of \Bus_data_out[3]_i_1\ : label is "soft_lutpair11"; - attribute SOFT_HLUTNM of \Bus_data_out[4]_i_1\ : label is "soft_lutpair12"; - attribute SOFT_HLUTNM of \Bus_data_out[8]_i_1\ : label is "soft_lutpair13"; - attribute SOFT_HLUTNM of \Bus_data_out[9]_i_1\ : label is "soft_lutpair13"; - attribute SOFT_HLUTNM of \wr_en[2]_i_3\ : label is "soft_lutpair15"; - attribute SOFT_HLUTNM of xsdb_drdy_i_1 : label is "soft_lutpair15"; -begin - Read_int_i_7_0 <= \^read_int_i_7_0\; - Read_int_i_7_1 <= \^read_int_i_7_1\; - SR(0) <= \^sr\(0); - in0 <= \^in0\; - internal_cnt_rst <= \^internal_cnt_rst\; - \wr_en[2]_i_2_0\ <= \^wr_en[2]_i_2_0\; - \wr_en[2]_i_4_0\ <= \^wr_en[2]_i_4_0\; - \xsdb_wr__0\ <= \^xsdb_wr__0\; -\Bus_data_out[0]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => \Bus_data_out_reg[15]_2\(0), - I1 => xsdb_addr_8_p2, - I2 => data_info_probe_in(0), - O => \Bus_data_out[0]_i_1_n_0\ - ); -\Bus_data_out[0]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFFACFFAFFF0F0F0" - ) - port map ( - I0 => probe_out_modified(0), - I1 => \Bus_data_out_reg[15]_1\(0), - I2 => xsdb_addr_2_0_p2(0), - I3 => xsdb_addr_2_0_p2(1), - I4 => \^in0\, - I5 => xsdb_addr_2_0_p2(2), - O => data_info_probe_in(0) - ); -\Bus_data_out[10]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"F8" - ) - port map ( - I0 => xsdb_addr_8_p2, - I1 => \Bus_data_out_reg[15]_2\(10), - I2 => \Bus_data_out[10]_i_2_n_0\, - O => \Bus_data_out[10]_i_1_n_0\ - ); -\Bus_data_out[10]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"4000400044444400" - ) - port map ( - I0 => xsdb_addr_8_p2, - I1 => xsdb_addr_2_0_p2(2), - I2 => \Bus_data_out_reg[15]_1\(10), - I3 => xsdb_addr_2_0_p2(0), - I4 => probe_out_modified(10), - I5 => xsdb_addr_2_0_p2(1), - O => \Bus_data_out[10]_i_2_n_0\ - ); -\Bus_data_out[11]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"F8" - ) - port map ( - I0 => xsdb_addr_8_p2, - I1 => \Bus_data_out_reg[15]_2\(11), - I2 => \Bus_data_out[11]_i_2_n_0\, - O => \Bus_data_out[11]_i_1_n_0\ - ); -\Bus_data_out[11]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"4000400044444400" - ) - port map ( - I0 => xsdb_addr_8_p2, - I1 => xsdb_addr_2_0_p2(2), - I2 => \Bus_data_out_reg[15]_1\(11), - I3 => xsdb_addr_2_0_p2(0), - I4 => probe_out_modified(11), - I5 => xsdb_addr_2_0_p2(1), - O => \Bus_data_out[11]_i_2_n_0\ - ); -\Bus_data_out[12]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"F8" - ) - port map ( - I0 => xsdb_addr_8_p2, - I1 => \Bus_data_out_reg[15]_2\(12), - I2 => \Bus_data_out[12]_i_2_n_0\, - O => \Bus_data_out[12]_i_1_n_0\ - ); -\Bus_data_out[12]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"4000400044444400" - ) - port map ( - I0 => xsdb_addr_8_p2, - I1 => xsdb_addr_2_0_p2(2), - I2 => \Bus_data_out_reg[15]_1\(12), - I3 => xsdb_addr_2_0_p2(0), - I4 => probe_out_modified(12), - I5 => xsdb_addr_2_0_p2(1), - O => \Bus_data_out[12]_i_2_n_0\ - ); -\Bus_data_out[13]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"FFFFF888F888F888" - ) - port map ( - I0 => \Bus_data_out[15]_i_2_n_0\, - I1 => probe_out_modified(13), - I2 => \Bus_data_out[15]_i_3_n_0\, - I3 => \Bus_data_out_reg[15]_1\(13), - I4 => xsdb_addr_8_p2, - I5 => \Bus_data_out_reg[15]_2\(13), - O => \Bus_data_out[13]_i_1_n_0\ - ); -\Bus_data_out[14]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"FFFFF888F888F888" - ) - port map ( - I0 => \Bus_data_out[15]_i_2_n_0\, - I1 => probe_out_modified(14), - I2 => \Bus_data_out[15]_i_3_n_0\, - I3 => \Bus_data_out_reg[15]_1\(14), - I4 => xsdb_addr_8_p2, - I5 => \Bus_data_out_reg[15]_2\(14), - O => \Bus_data_out[14]_i_1_n_0\ - ); -\Bus_data_out[15]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"FFFFF888F888F888" - ) - port map ( - I0 => \Bus_data_out[15]_i_2_n_0\, - I1 => probe_out_modified(15), - I2 => \Bus_data_out[15]_i_3_n_0\, - I3 => \Bus_data_out_reg[15]_1\(15), - I4 => xsdb_addr_8_p2, - I5 => \Bus_data_out_reg[15]_2\(15), - O => \Bus_data_out[15]_i_1_n_0\ - ); -\Bus_data_out[15]_i_2\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0100" - ) - port map ( - I0 => xsdb_addr_2_0_p2(1), - I1 => xsdb_addr_2_0_p2(0), - I2 => xsdb_addr_8_p2, - I3 => xsdb_addr_2_0_p2(2), - O => \Bus_data_out[15]_i_2_n_0\ - ); -\Bus_data_out[15]_i_3\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0800" - ) - port map ( - I0 => xsdb_addr_2_0_p2(1), - I1 => xsdb_addr_2_0_p2(0), - I2 => xsdb_addr_8_p2, - I3 => xsdb_addr_2_0_p2(2), - O => \Bus_data_out[15]_i_3_n_0\ - ); -\Bus_data_out[1]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => \Bus_data_out_reg[15]_2\(1), - I1 => xsdb_addr_8_p2, - I2 => data_info_probe_in(1), - O => \Bus_data_out[1]_i_1_n_0\ - ); -\Bus_data_out[1]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"B0B0FFF3B0B0CFC3" - ) - port map ( - I0 => \Bus_data_out_reg[15]_1\(1), - I1 => xsdb_addr_2_0_p2(1), - I2 => xsdb_addr_2_0_p2(2), - I3 => \^sr\(0), - I4 => xsdb_addr_2_0_p2(0), - I5 => probe_out_modified(1), - O => data_info_probe_in(1) - ); -\Bus_data_out[2]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"FFFFBAAAAAAABAAA" - ) - port map ( - I0 => \Bus_data_out[2]_i_2_n_0\, - I1 => xsdb_addr_2_0_p2(0), - I2 => \^internal_cnt_rst\, - I3 => xsdb_addr_2_0_p2(1), - I4 => xsdb_addr_8_p2, - I5 => \Bus_data_out_reg[15]_2\(2), - O => \Bus_data_out[2]_i_1_n_0\ - ); -\Bus_data_out[2]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"4044404444444400" - ) - port map ( - I0 => xsdb_addr_8_p2, - I1 => xsdb_addr_2_0_p2(2), - I2 => \Bus_data_out_reg[15]_1\(2), - I3 => xsdb_addr_2_0_p2(1), - I4 => probe_out_modified(2), - I5 => xsdb_addr_2_0_p2(0), - O => \Bus_data_out[2]_i_2_n_0\ - ); -\Bus_data_out[3]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"F8" - ) - port map ( - I0 => xsdb_addr_8_p2, - I1 => \Bus_data_out_reg[15]_2\(3), - I2 => \Bus_data_out[3]_i_2_n_0\, - O => \Bus_data_out[3]_i_1_n_0\ - ); -\Bus_data_out[3]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"4044404444444400" - ) - port map ( - I0 => xsdb_addr_8_p2, - I1 => xsdb_addr_2_0_p2(2), - I2 => \Bus_data_out_reg[15]_1\(3), - I3 => xsdb_addr_2_0_p2(1), - I4 => probe_out_modified(3), - I5 => xsdb_addr_2_0_p2(0), - O => \Bus_data_out[3]_i_2_n_0\ - ); -\Bus_data_out[4]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"F8" - ) - port map ( - I0 => xsdb_addr_8_p2, - I1 => \Bus_data_out_reg[15]_2\(4), - I2 => \Bus_data_out[4]_i_2_n_0\, - O => \Bus_data_out[4]_i_1_n_0\ - ); -\Bus_data_out[4]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"4044404444444400" - ) - port map ( - I0 => xsdb_addr_8_p2, - I1 => xsdb_addr_2_0_p2(2), - I2 => \Bus_data_out_reg[15]_1\(4), - I3 => xsdb_addr_2_0_p2(1), - I4 => probe_out_modified(4), - I5 => xsdb_addr_2_0_p2(0), - O => \Bus_data_out[4]_i_2_n_0\ - ); -\Bus_data_out[5]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"FFFFF888F888F888" - ) - port map ( - I0 => \Bus_data_out[15]_i_2_n_0\, - I1 => probe_out_modified(5), - I2 => \Bus_data_out[15]_i_3_n_0\, - I3 => \Bus_data_out_reg[15]_1\(5), - I4 => xsdb_addr_8_p2, - I5 => \Bus_data_out_reg[15]_2\(5), - O => \Bus_data_out[5]_i_1_n_0\ - ); -\Bus_data_out[6]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"FFFFF888F888F888" - ) - port map ( - I0 => \Bus_data_out[15]_i_2_n_0\, - I1 => probe_out_modified(6), - I2 => \Bus_data_out[15]_i_3_n_0\, - I3 => \Bus_data_out_reg[15]_1\(6), - I4 => xsdb_addr_8_p2, - I5 => \Bus_data_out_reg[15]_2\(6), - O => \Bus_data_out[6]_i_1_n_0\ - ); -\Bus_data_out[7]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"FFFFF888F888F888" - ) - port map ( - I0 => \Bus_data_out[15]_i_2_n_0\, - I1 => probe_out_modified(7), - I2 => \Bus_data_out[15]_i_3_n_0\, - I3 => \Bus_data_out_reg[15]_1\(7), - I4 => xsdb_addr_8_p2, - I5 => \Bus_data_out_reg[15]_2\(7), - O => \Bus_data_out[7]_i_1_n_0\ - ); -\Bus_data_out[8]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"F8" - ) - port map ( - I0 => xsdb_addr_8_p2, - I1 => \Bus_data_out_reg[15]_2\(8), - I2 => \Bus_data_out[8]_i_2_n_0\, - O => \Bus_data_out[8]_i_1_n_0\ - ); -\Bus_data_out[8]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"4000400044444400" - ) - port map ( - I0 => xsdb_addr_8_p2, - I1 => xsdb_addr_2_0_p2(2), - I2 => \Bus_data_out_reg[15]_1\(8), - I3 => xsdb_addr_2_0_p2(0), - I4 => probe_out_modified(8), - I5 => xsdb_addr_2_0_p2(1), - O => \Bus_data_out[8]_i_2_n_0\ - ); -\Bus_data_out[9]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"F8" - ) - port map ( - I0 => xsdb_addr_8_p2, - I1 => \Bus_data_out_reg[15]_2\(9), - I2 => \Bus_data_out[9]_i_2_n_0\, - O => \Bus_data_out[9]_i_1_n_0\ - ); -\Bus_data_out[9]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"4000400044444400" - ) - port map ( - I0 => xsdb_addr_8_p2, - I1 => xsdb_addr_2_0_p2(2), - I2 => \Bus_data_out_reg[15]_1\(9), - I3 => xsdb_addr_2_0_p2(0), - I4 => probe_out_modified(9), - I5 => xsdb_addr_2_0_p2(1), - O => \Bus_data_out[9]_i_2_n_0\ - ); -\Bus_data_out_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => \Bus_data_out[0]_i_1_n_0\, - Q => \Bus_data_out_reg[15]_0\(0), - R => '0' - ); -\Bus_data_out_reg[10]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => \Bus_data_out[10]_i_1_n_0\, - Q => \Bus_data_out_reg[15]_0\(10), - R => '0' - ); -\Bus_data_out_reg[11]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => \Bus_data_out[11]_i_1_n_0\, - Q => \Bus_data_out_reg[15]_0\(11), - R => '0' - ); -\Bus_data_out_reg[12]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => \Bus_data_out[12]_i_1_n_0\, - Q => \Bus_data_out_reg[15]_0\(12), - R => '0' - ); -\Bus_data_out_reg[13]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => \Bus_data_out[13]_i_1_n_0\, - Q => \Bus_data_out_reg[15]_0\(13), - R => '0' - ); -\Bus_data_out_reg[14]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => \Bus_data_out[14]_i_1_n_0\, - Q => \Bus_data_out_reg[15]_0\(14), - R => '0' - ); -\Bus_data_out_reg[15]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => \Bus_data_out[15]_i_1_n_0\, - Q => \Bus_data_out_reg[15]_0\(15), - R => '0' - ); -\Bus_data_out_reg[1]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => \Bus_data_out[1]_i_1_n_0\, - Q => \Bus_data_out_reg[15]_0\(1), - R => '0' - ); -\Bus_data_out_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => \Bus_data_out[2]_i_1_n_0\, - Q => \Bus_data_out_reg[15]_0\(2), - R => '0' - ); -\Bus_data_out_reg[3]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => \Bus_data_out[3]_i_1_n_0\, - Q => \Bus_data_out_reg[15]_0\(3), - R => '0' - ); -\Bus_data_out_reg[4]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => \Bus_data_out[4]_i_1_n_0\, - Q => \Bus_data_out_reg[15]_0\(4), - R => '0' - ); -\Bus_data_out_reg[5]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => \Bus_data_out[5]_i_1_n_0\, - Q => \Bus_data_out_reg[15]_0\(5), - R => '0' - ); -\Bus_data_out_reg[6]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => \Bus_data_out[6]_i_1_n_0\, - Q => \Bus_data_out_reg[15]_0\(6), - R => '0' - ); -\Bus_data_out_reg[7]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => \Bus_data_out[7]_i_1_n_0\, - Q => \Bus_data_out_reg[15]_0\(7), - R => '0' - ); -\Bus_data_out_reg[8]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => \Bus_data_out[8]_i_1_n_0\, - Q => \Bus_data_out_reg[15]_0\(8), - R => '0' - ); -\Bus_data_out_reg[9]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => \Bus_data_out[9]_i_1_n_0\, - Q => \Bus_data_out_reg[15]_0\(9), - R => '0' - ); -Hold_probe_in_reg: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => wr_control_reg, - D => Q(3), - Q => Hold_probe_in, - R => s_rst_o - ); -Read_int_i_7: unisim.vcomponents.LUT2 - generic map( - INIT => X"E" - ) - port map ( - I0 => s_daddr_o(11), - I1 => s_daddr_o(10), - O => \^read_int_i_7_1\ - ); -\addr_count[4]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"FE" - ) - port map ( - I0 => \^internal_cnt_rst\, - I1 => s_rst_o, - I2 => addr_count_reg1, - O => int_cnt_rst_reg_0(0) - ); -clear_int_reg: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => wr_control_reg, - D => Q(1), - Q => \^sr\(0), - R => s_rst_o - ); -committ_int_reg: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => wr_control_reg, - D => Q(0), - Q => \^in0\, - R => s_rst_o - ); -int_cnt_rst_reg: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => wr_control_reg, - D => Q(2), - Q => \^internal_cnt_rst\, - R => s_rst_o - ); -\probe_in_reg[63]_i_1\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => Hold_probe_in, - O => E(0) - ); -\probe_out_modified_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => wr_probe_out_modified, - D => Q(0), - Q => probe_out_modified(0), - R => \^sr\(0) - ); -\probe_out_modified_reg[10]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => wr_probe_out_modified, - D => Q(10), - Q => probe_out_modified(10), - R => \^sr\(0) - ); -\probe_out_modified_reg[11]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => wr_probe_out_modified, - D => Q(11), - Q => probe_out_modified(11), - R => \^sr\(0) - ); -\probe_out_modified_reg[12]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => wr_probe_out_modified, - D => Q(12), - Q => probe_out_modified(12), - R => \^sr\(0) - ); -\probe_out_modified_reg[13]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => wr_probe_out_modified, - D => Q(13), - Q => probe_out_modified(13), - R => \^sr\(0) - ); -\probe_out_modified_reg[14]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => wr_probe_out_modified, - D => Q(14), - Q => probe_out_modified(14), - R => \^sr\(0) - ); -\probe_out_modified_reg[15]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => wr_probe_out_modified, - D => Q(15), - Q => probe_out_modified(15), - R => \^sr\(0) - ); -\probe_out_modified_reg[1]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => wr_probe_out_modified, - D => Q(1), - Q => probe_out_modified(1), - R => \^sr\(0) - ); -\probe_out_modified_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => wr_probe_out_modified, - D => Q(2), - Q => probe_out_modified(2), - R => \^sr\(0) - ); -\probe_out_modified_reg[3]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => wr_probe_out_modified, - D => Q(3), - Q => probe_out_modified(3), - R => \^sr\(0) - ); -\probe_out_modified_reg[4]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => wr_probe_out_modified, - D => Q(4), - Q => probe_out_modified(4), - R => \^sr\(0) - ); -\probe_out_modified_reg[5]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => wr_probe_out_modified, - D => Q(5), - Q => probe_out_modified(5), - R => \^sr\(0) - ); -\probe_out_modified_reg[6]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => wr_probe_out_modified, - D => Q(6), - Q => probe_out_modified(6), - R => \^sr\(0) - ); -\probe_out_modified_reg[7]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => wr_probe_out_modified, - D => Q(7), - Q => probe_out_modified(7), - R => \^sr\(0) - ); -\probe_out_modified_reg[8]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => wr_probe_out_modified, - D => Q(8), - Q => probe_out_modified(8), - R => \^sr\(0) - ); -\probe_out_modified_reg[9]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => wr_probe_out_modified, - D => Q(9), - Q => probe_out_modified(9), - R => \^sr\(0) - ); -rd_en_p1_reg: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => xsdb_rd, - Q => rd_en_p1, - R => s_rst_o - ); -rd_en_p2_reg: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => rd_en_p1, - Q => rd_en_p2, - R => s_rst_o - ); -\wr_en[2]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0000000000000080" - ) - port map ( - I0 => \^wr_en[2]_i_2_0\, - I1 => s_daddr_o(1), - I2 => \^xsdb_wr__0\, - I3 => \^wr_en[2]_i_4_0\, - I4 => s_daddr_o(8), - I5 => \^read_int_i_7_0\, - O => \wr_en[2]_i_1_n_0\ - ); -\wr_en[2]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0000000000000001" - ) - port map ( - I0 => s_daddr_o(0), - I1 => s_daddr_o(4), - I2 => s_daddr_o(5), - I3 => s_daddr_o(6), - I4 => s_daddr_o(7), - I5 => s_daddr_o(16), - O => \^wr_en[2]_i_2_0\ - ); -\wr_en[2]_i_3\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => s_den_o, - I1 => s_dwe_o, - O => \^xsdb_wr__0\ - ); -\wr_en[2]_i_4\: unisim.vcomponents.LUT2 - generic map( - INIT => X"E" - ) - port map ( - I0 => s_daddr_o(3), - I1 => s_daddr_o(2), - O => \^wr_en[2]_i_4_0\ - ); -\wr_en[4]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"02" - ) - port map ( - I0 => \wr_en[4]_i_2_n_0\, - I1 => s_daddr_o(8), - I2 => \^read_int_i_7_0\, - O => \wr_en[4]_i_1_n_0\ - ); -\wr_en[4]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0000080000000000" - ) - port map ( - I0 => s_den_o, - I1 => s_dwe_o, - I2 => s_daddr_o(3), - I3 => s_daddr_o(2), - I4 => s_daddr_o(1), - I5 => \^wr_en[2]_i_2_0\, - O => \wr_en[4]_i_2_n_0\ - ); -\wr_en[4]_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"FFFFFFFFFFFFFFFE" - ) - port map ( - I0 => s_daddr_o(9), - I1 => \^read_int_i_7_1\, - I2 => s_daddr_o(15), - I3 => s_daddr_o(14), - I4 => s_daddr_o(13), - I5 => s_daddr_o(12), - O => \^read_int_i_7_0\ - ); -\wr_en_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => \wr_en[2]_i_1_n_0\, - Q => wr_control_reg, - R => '0' - ); -\wr_en_reg[4]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => \wr_en[4]_i_1_n_0\, - Q => wr_probe_out_modified, - R => '0' - ); -\xsdb_addr_2_0_p1_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => s_daddr_o(0), - Q => xsdb_addr_2_0_p1(0), - R => '0' - ); -\xsdb_addr_2_0_p1_reg[1]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => s_daddr_o(1), - Q => xsdb_addr_2_0_p1(1), - R => '0' - ); -\xsdb_addr_2_0_p1_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => s_daddr_o(2), - Q => xsdb_addr_2_0_p1(2), - R => '0' - ); -\xsdb_addr_2_0_p2_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => xsdb_addr_2_0_p1(0), - Q => xsdb_addr_2_0_p2(0), - R => '0' - ); -\xsdb_addr_2_0_p2_reg[1]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => xsdb_addr_2_0_p1(1), - Q => xsdb_addr_2_0_p2(1), - R => '0' - ); -\xsdb_addr_2_0_p2_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => xsdb_addr_2_0_p1(2), - Q => xsdb_addr_2_0_p2(2), - R => '0' - ); -xsdb_addr_8_p1_reg: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => s_daddr_o(8), - Q => xsdb_addr_8_p1, - R => '0' - ); -xsdb_addr_8_p2_reg: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => xsdb_addr_8_p1, - Q => xsdb_addr_8_p2, - R => '0' - ); -xsdb_drdy_i_1: unisim.vcomponents.LUT3 - generic map( - INIT => X"F8" - ) - port map ( - I0 => s_dwe_o, - I1 => s_den_o, - I2 => rd_en_p2, - O => xsdb_drdy_i_1_n_0 - ); -xsdb_drdy_reg: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => xsdb_drdy_i_1_n_0, - Q => s_drdy_i, - R => s_rst_o - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity vio_0_vio_v3_0_19_probe_in_one is - port ( - addr_count_reg1 : out STD_LOGIC; - xsdb_rd : out STD_LOGIC; - Q : out STD_LOGIC_VECTOR ( 15 downto 0 ); - CLK : in STD_LOGIC; - s_daddr_o : in STD_LOGIC_VECTOR ( 16 downto 0 ); - Read_int_reg_0 : in STD_LOGIC; - s_den_o : in STD_LOGIC; - s_dwe_o : in STD_LOGIC; - E : in STD_LOGIC_VECTOR ( 0 to 0 ); - D : in STD_LOGIC_VECTOR ( 63 downto 0 ); - \^clk\ : in STD_LOGIC; - SR : in STD_LOGIC_VECTOR ( 0 to 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of vio_0_vio_v3_0_19_probe_in_one : entity is "vio_v3_0_19_probe_in_one"; -end vio_0_vio_v3_0_19_probe_in_one; - -architecture STRUCTURE of vio_0_vio_v3_0_19_probe_in_one is - signal \Bus_Data_out[0]_i_2_n_0\ : STD_LOGIC; - signal \Bus_Data_out[0]_i_3_n_0\ : STD_LOGIC; - signal \Bus_Data_out[0]_i_4_n_0\ : STD_LOGIC; - signal \Bus_Data_out[10]_i_2_n_0\ : STD_LOGIC; - signal \Bus_Data_out[10]_i_3_n_0\ : STD_LOGIC; - signal \Bus_Data_out[10]_i_4_n_0\ : STD_LOGIC; - signal \Bus_Data_out[11]_i_2_n_0\ : STD_LOGIC; - signal \Bus_Data_out[11]_i_3_n_0\ : STD_LOGIC; - signal \Bus_Data_out[11]_i_4_n_0\ : STD_LOGIC; - signal \Bus_Data_out[12]_i_2_n_0\ : STD_LOGIC; - signal \Bus_Data_out[12]_i_3_n_0\ : STD_LOGIC; - signal \Bus_Data_out[12]_i_4_n_0\ : STD_LOGIC; - signal \Bus_Data_out[13]_i_2_n_0\ : STD_LOGIC; - signal \Bus_Data_out[13]_i_3_n_0\ : STD_LOGIC; - signal \Bus_Data_out[13]_i_4_n_0\ : STD_LOGIC; - signal \Bus_Data_out[14]_i_2_n_0\ : STD_LOGIC; - signal \Bus_Data_out[14]_i_3_n_0\ : STD_LOGIC; - signal \Bus_Data_out[14]_i_4_n_0\ : STD_LOGIC; - signal \Bus_Data_out[15]_i_2_n_0\ : STD_LOGIC; - signal \Bus_Data_out[15]_i_3_n_0\ : STD_LOGIC; - signal \Bus_Data_out[15]_i_4_n_0\ : STD_LOGIC; - signal \Bus_Data_out[1]_i_2_n_0\ : STD_LOGIC; - signal \Bus_Data_out[1]_i_3_n_0\ : STD_LOGIC; - signal \Bus_Data_out[1]_i_4_n_0\ : STD_LOGIC; - signal \Bus_Data_out[2]_i_2_n_0\ : STD_LOGIC; - signal \Bus_Data_out[2]_i_3_n_0\ : STD_LOGIC; - signal \Bus_Data_out[2]_i_4_n_0\ : STD_LOGIC; - signal \Bus_Data_out[3]_i_2_n_0\ : STD_LOGIC; - signal \Bus_Data_out[3]_i_3_n_0\ : STD_LOGIC; - signal \Bus_Data_out[3]_i_4_n_0\ : STD_LOGIC; - signal \Bus_Data_out[4]_i_2_n_0\ : STD_LOGIC; - signal \Bus_Data_out[4]_i_3_n_0\ : STD_LOGIC; - signal \Bus_Data_out[4]_i_4_n_0\ : STD_LOGIC; - signal \Bus_Data_out[5]_i_2_n_0\ : STD_LOGIC; - signal \Bus_Data_out[5]_i_3_n_0\ : STD_LOGIC; - signal \Bus_Data_out[5]_i_4_n_0\ : STD_LOGIC; - signal \Bus_Data_out[6]_i_2_n_0\ : STD_LOGIC; - signal \Bus_Data_out[6]_i_3_n_0\ : STD_LOGIC; - signal \Bus_Data_out[6]_i_4_n_0\ : STD_LOGIC; - signal \Bus_Data_out[7]_i_2_n_0\ : STD_LOGIC; - signal \Bus_Data_out[7]_i_3_n_0\ : STD_LOGIC; - signal \Bus_Data_out[7]_i_4_n_0\ : STD_LOGIC; - signal \Bus_Data_out[8]_i_2_n_0\ : STD_LOGIC; - signal \Bus_Data_out[8]_i_3_n_0\ : STD_LOGIC; - signal \Bus_Data_out[8]_i_4_n_0\ : STD_LOGIC; - signal \Bus_Data_out[9]_i_2_n_0\ : STD_LOGIC; - signal \Bus_Data_out[9]_i_3_n_0\ : STD_LOGIC; - signal \Bus_Data_out[9]_i_4_n_0\ : STD_LOGIC; - signal \DECODER_INST/rd_en_int_7\ : STD_LOGIC; - signal Read_int : STD_LOGIC; - signal Read_int_i_2_n_0 : STD_LOGIC; - signal Read_int_i_3_n_0 : STD_LOGIC; - signal Read_int_i_4_n_0 : STD_LOGIC; - signal Read_int_i_5_n_0 : STD_LOGIC; - signal Read_int_i_6_n_0 : STD_LOGIC; - signal addr_count : STD_LOGIC_VECTOR ( 4 downto 0 ); - signal \addr_count[0]_i_1_n_0\ : STD_LOGIC; - signal \addr_count[1]_i_1_n_0\ : STD_LOGIC; - signal \addr_count[2]_i_1_n_0\ : STD_LOGIC; - signal \addr_count[3]_i_1_n_0\ : STD_LOGIC; - signal \addr_count[4]_i_2_n_0\ : STD_LOGIC; - signal \^addr_count_reg1\ : STD_LOGIC; - signal data_int_sync1 : STD_LOGIC_VECTOR ( 63 downto 0 ); - attribute async_reg : string; - attribute async_reg of data_int_sync1 : signal is "true"; - signal data_int_sync2 : STD_LOGIC_VECTOR ( 63 downto 0 ); - attribute async_reg of data_int_sync2 : signal is "true"; - signal dn_activity0 : STD_LOGIC; - signal dn_activity0102_out : STD_LOGIC; - signal dn_activity0106_out : STD_LOGIC; - signal dn_activity010_out : STD_LOGIC; - signal dn_activity0110_out : STD_LOGIC; - signal dn_activity0114_out : STD_LOGIC; - signal dn_activity0118_out : STD_LOGIC; - signal dn_activity0122_out : STD_LOGIC; - signal dn_activity0126_out : STD_LOGIC; - signal dn_activity0130_out : STD_LOGIC; - signal dn_activity0134_out : STD_LOGIC; - signal dn_activity0138_out : STD_LOGIC; - signal dn_activity0142_out : STD_LOGIC; - signal dn_activity0146_out : STD_LOGIC; - signal dn_activity014_out : STD_LOGIC; - signal dn_activity0150_out : STD_LOGIC; - signal dn_activity0154_out : STD_LOGIC; - signal dn_activity0158_out : STD_LOGIC; - signal dn_activity0162_out : STD_LOGIC; - signal dn_activity0166_out : STD_LOGIC; - signal dn_activity0170_out : STD_LOGIC; - signal dn_activity0174_out : STD_LOGIC; - signal dn_activity0178_out : STD_LOGIC; - signal dn_activity0182_out : STD_LOGIC; - signal dn_activity0186_out : STD_LOGIC; - signal dn_activity018_out : STD_LOGIC; - signal dn_activity0190_out : STD_LOGIC; - signal dn_activity0194_out : STD_LOGIC; - signal dn_activity0198_out : STD_LOGIC; - signal dn_activity0202_out : STD_LOGIC; - signal dn_activity0206_out : STD_LOGIC; - signal dn_activity0210_out : STD_LOGIC; - signal dn_activity0214_out : STD_LOGIC; - signal dn_activity0218_out : STD_LOGIC; - signal dn_activity0222_out : STD_LOGIC; - signal dn_activity0226_out : STD_LOGIC; - signal dn_activity022_out : STD_LOGIC; - signal dn_activity0230_out : STD_LOGIC; - signal dn_activity0234_out : STD_LOGIC; - signal dn_activity0238_out : STD_LOGIC; - signal dn_activity0242_out : STD_LOGIC; - signal dn_activity0246_out : STD_LOGIC; - signal dn_activity0250_out : STD_LOGIC; - signal dn_activity026_out : STD_LOGIC; - signal dn_activity02_out : STD_LOGIC; - signal dn_activity030_out : STD_LOGIC; - signal dn_activity034_out : STD_LOGIC; - signal dn_activity038_out : STD_LOGIC; - signal dn_activity042_out : STD_LOGIC; - signal dn_activity046_out : STD_LOGIC; - signal dn_activity050_out : STD_LOGIC; - signal dn_activity054_out : STD_LOGIC; - signal dn_activity058_out : STD_LOGIC; - signal dn_activity062_out : STD_LOGIC; - signal dn_activity066_out : STD_LOGIC; - signal dn_activity06_out : STD_LOGIC; - signal dn_activity070_out : STD_LOGIC; - signal dn_activity074_out : STD_LOGIC; - signal dn_activity078_out : STD_LOGIC; - signal dn_activity082_out : STD_LOGIC; - signal dn_activity086_out : STD_LOGIC; - signal dn_activity090_out : STD_LOGIC; - signal dn_activity094_out : STD_LOGIC; - signal dn_activity098_out : STD_LOGIC; - signal mem_probe_in : STD_LOGIC_VECTOR ( 15 downto 0 ); - signal \mem_probe_in[10]__0\ : STD_LOGIC_VECTOR ( 15 downto 0 ); - signal \mem_probe_in[11]__0\ : STD_LOGIC_VECTOR ( 15 downto 0 ); - signal \mem_probe_in[4]__0\ : STD_LOGIC_VECTOR ( 15 downto 0 ); - signal \mem_probe_in[5]__0\ : STD_LOGIC_VECTOR ( 15 downto 0 ); - signal \mem_probe_in[6]__0\ : STD_LOGIC_VECTOR ( 15 downto 0 ); - signal \mem_probe_in[7]__0\ : STD_LOGIC_VECTOR ( 15 downto 0 ); - signal \mem_probe_in[8]__0\ : STD_LOGIC_VECTOR ( 15 downto 0 ); - signal \mem_probe_in[9]__0\ : STD_LOGIC_VECTOR ( 15 downto 0 ); - signal probe_in_reg : STD_LOGIC_VECTOR ( 63 downto 0 ); - attribute DONT_TOUCH : boolean; - attribute DONT_TOUCH of probe_in_reg : signal is std.standard.true; - signal read_done : STD_LOGIC; - attribute MAX_FANOUT : string; - attribute MAX_FANOUT of read_done : signal is "200"; - attribute RTL_MAX_FANOUT : string; - attribute RTL_MAX_FANOUT of read_done : signal is "found"; - signal up_activity0 : STD_LOGIC; - signal up_activity0256_out : STD_LOGIC; - signal up_activity0260_out : STD_LOGIC; - signal up_activity0264_out : STD_LOGIC; - signal up_activity0268_out : STD_LOGIC; - signal up_activity0272_out : STD_LOGIC; - signal up_activity0276_out : STD_LOGIC; - signal up_activity0280_out : STD_LOGIC; - signal up_activity0284_out : STD_LOGIC; - signal up_activity0288_out : STD_LOGIC; - signal up_activity0292_out : STD_LOGIC; - signal up_activity0296_out : STD_LOGIC; - signal up_activity0300_out : STD_LOGIC; - signal up_activity0304_out : STD_LOGIC; - signal up_activity0308_out : STD_LOGIC; - signal up_activity0312_out : STD_LOGIC; - signal up_activity0316_out : STD_LOGIC; - signal up_activity0320_out : STD_LOGIC; - signal up_activity0324_out : STD_LOGIC; - signal up_activity0328_out : STD_LOGIC; - signal up_activity0332_out : STD_LOGIC; - signal up_activity0336_out : STD_LOGIC; - signal up_activity0340_out : STD_LOGIC; - signal up_activity0344_out : STD_LOGIC; - signal up_activity0348_out : STD_LOGIC; - signal up_activity0352_out : STD_LOGIC; - signal up_activity0356_out : STD_LOGIC; - signal up_activity0360_out : STD_LOGIC; - signal up_activity0364_out : STD_LOGIC; - signal up_activity0368_out : STD_LOGIC; - signal up_activity0372_out : STD_LOGIC; - signal up_activity0376_out : STD_LOGIC; - signal up_activity0380_out : STD_LOGIC; - signal up_activity0384_out : STD_LOGIC; - signal up_activity0388_out : STD_LOGIC; - signal up_activity0392_out : STD_LOGIC; - signal up_activity0396_out : STD_LOGIC; - signal up_activity0400_out : STD_LOGIC; - signal up_activity0404_out : STD_LOGIC; - signal up_activity0408_out : STD_LOGIC; - signal up_activity0412_out : STD_LOGIC; - signal up_activity0416_out : STD_LOGIC; - signal up_activity0420_out : STD_LOGIC; - signal up_activity0424_out : STD_LOGIC; - signal up_activity0428_out : STD_LOGIC; - signal up_activity0432_out : STD_LOGIC; - signal up_activity0436_out : STD_LOGIC; - signal up_activity0440_out : STD_LOGIC; - signal up_activity0444_out : STD_LOGIC; - signal up_activity0448_out : STD_LOGIC; - signal up_activity0452_out : STD_LOGIC; - signal up_activity0456_out : STD_LOGIC; - signal up_activity0460_out : STD_LOGIC; - signal up_activity0464_out : STD_LOGIC; - signal up_activity0468_out : STD_LOGIC; - signal up_activity0472_out : STD_LOGIC; - signal up_activity0476_out : STD_LOGIC; - signal up_activity0480_out : STD_LOGIC; - signal up_activity0484_out : STD_LOGIC; - signal up_activity0488_out : STD_LOGIC; - signal up_activity0492_out : STD_LOGIC; - signal up_activity0496_out : STD_LOGIC; - signal up_activity0500_out : STD_LOGIC; - signal up_activity0504_out : STD_LOGIC; - signal \^xsdb_rd\ : STD_LOGIC; - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \addr_count[1]_i_1\ : label is "soft_lutpair17"; - attribute SOFT_HLUTNM of \addr_count[2]_i_1\ : label is "soft_lutpair17"; - attribute SOFT_HLUTNM of \addr_count[3]_i_1\ : label is "soft_lutpair16"; - attribute SOFT_HLUTNM of \addr_count[4]_i_2\ : label is "soft_lutpair16"; - attribute MAX_FANOUT of \addr_count_reg[0]\ : label is "100"; - attribute MAX_FANOUT of \addr_count_reg[1]\ : label is "100"; - attribute MAX_FANOUT of \addr_count_reg[2]\ : label is "100"; - attribute MAX_FANOUT of \addr_count_reg[3]\ : label is "100"; - attribute MAX_FANOUT of \addr_count_reg[4]\ : label is "100"; - attribute ASYNC_REG_boolean : boolean; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[0]\ : label is std.standard.true; - attribute KEEP : string; - attribute KEEP of \data_int_sync1_reg[0]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[10]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[10]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[11]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[11]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[12]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[12]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[13]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[13]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[14]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[14]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[15]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[15]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[16]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[16]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[17]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[17]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[18]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[18]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[19]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[19]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[1]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[1]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[20]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[20]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[21]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[21]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[22]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[22]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[23]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[23]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[24]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[24]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[25]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[25]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[26]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[26]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[27]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[27]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[28]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[28]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[29]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[29]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[2]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[2]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[30]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[30]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[31]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[31]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[32]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[32]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[33]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[33]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[34]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[34]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[35]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[35]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[36]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[36]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[37]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[37]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[38]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[38]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[39]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[39]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[3]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[3]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[40]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[40]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[41]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[41]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[42]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[42]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[43]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[43]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[44]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[44]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[45]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[45]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[46]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[46]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[47]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[47]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[48]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[48]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[49]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[49]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[4]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[4]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[50]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[50]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[51]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[51]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[52]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[52]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[53]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[53]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[54]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[54]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[55]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[55]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[56]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[56]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[57]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[57]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[58]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[58]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[59]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[59]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[5]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[5]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[60]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[60]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[61]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[61]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[62]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[62]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[63]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[63]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[6]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[6]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[7]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[7]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[8]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[8]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync1_reg[9]\ : label is std.standard.true; - attribute KEEP of \data_int_sync1_reg[9]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[0]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[0]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[10]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[10]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[11]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[11]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[12]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[12]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[13]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[13]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[14]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[14]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[15]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[15]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[16]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[16]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[17]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[17]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[18]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[18]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[19]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[19]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[1]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[1]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[20]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[20]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[21]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[21]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[22]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[22]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[23]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[23]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[24]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[24]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[25]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[25]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[26]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[26]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[27]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[27]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[28]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[28]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[29]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[29]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[2]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[2]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[30]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[30]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[31]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[31]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[32]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[32]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[33]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[33]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[34]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[34]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[35]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[35]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[36]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[36]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[37]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[37]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[38]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[38]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[39]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[39]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[3]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[3]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[40]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[40]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[41]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[41]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[42]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[42]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[43]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[43]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[44]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[44]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[45]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[45]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[46]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[46]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[47]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[47]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[48]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[48]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[49]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[49]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[4]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[4]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[50]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[50]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[51]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[51]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[52]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[52]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[53]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[53]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[54]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[54]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[55]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[55]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[56]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[56]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[57]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[57]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[58]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[58]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[59]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[59]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[5]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[5]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[60]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[60]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[61]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[61]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[62]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[62]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[63]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[63]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[6]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[6]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[7]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[7]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[8]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[8]\ : label is "yes"; - attribute ASYNC_REG_boolean of \data_int_sync2_reg[9]\ : label is std.standard.true; - attribute KEEP of \data_int_sync2_reg[9]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[0]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[0]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[10]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[10]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[11]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[11]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[12]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[12]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[13]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[13]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[14]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[14]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[15]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[15]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[16]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[16]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[17]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[17]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[18]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[18]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[19]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[19]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[1]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[1]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[20]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[20]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[21]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[21]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[22]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[22]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[23]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[23]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[24]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[24]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[25]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[25]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[26]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[26]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[27]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[27]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[28]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[28]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[29]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[29]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[2]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[2]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[30]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[30]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[31]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[31]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[32]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[32]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[33]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[33]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[34]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[34]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[35]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[35]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[36]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[36]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[37]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[37]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[38]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[38]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[39]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[39]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[3]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[3]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[40]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[40]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[41]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[41]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[42]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[42]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[43]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[43]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[44]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[44]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[45]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[45]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[46]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[46]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[47]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[47]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[48]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[48]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[49]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[49]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[4]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[4]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[50]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[50]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[51]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[51]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[52]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[52]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[53]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[53]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[54]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[54]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[55]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[55]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[56]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[56]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[57]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[57]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[58]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[58]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[59]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[59]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[5]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[5]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[60]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[60]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[61]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[61]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[62]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[62]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[63]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[63]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[6]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[6]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[7]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[7]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[8]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[8]\ : label is "yes"; - attribute DONT_TOUCH of \probe_in_reg_reg[9]\ : label is std.standard.true; - attribute KEEP of \probe_in_reg_reg[9]\ : label is "yes"; - attribute RTL_MAX_FANOUT of read_done_reg : label is "found"; -begin - addr_count_reg1 <= \^addr_count_reg1\; - xsdb_rd <= \^xsdb_rd\; -\Bus_Data_out[0]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"FFE400E4" - ) - port map ( - I0 => addr_count(2), - I1 => \Bus_Data_out[0]_i_2_n_0\, - I2 => \Bus_Data_out[0]_i_3_n_0\, - I3 => addr_count(3), - I4 => \Bus_Data_out[0]_i_4_n_0\, - O => mem_probe_in(0) - ); -\Bus_Data_out[0]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => data_int_sync2(16), - I1 => data_int_sync2(48), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => data_int_sync2(0), - I5 => data_int_sync2(32), - O => \Bus_Data_out[0]_i_2_n_0\ - ); -\Bus_Data_out[0]_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => \mem_probe_in[5]__0\(0), - I1 => \mem_probe_in[7]__0\(0), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => \mem_probe_in[4]__0\(0), - I5 => \mem_probe_in[6]__0\(0), - O => \Bus_Data_out[0]_i_3_n_0\ - ); -\Bus_Data_out[0]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => \mem_probe_in[9]__0\(0), - I1 => \mem_probe_in[11]__0\(0), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => \mem_probe_in[8]__0\(0), - I5 => \mem_probe_in[10]__0\(0), - O => \Bus_Data_out[0]_i_4_n_0\ - ); -\Bus_Data_out[10]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"FFE400E4" - ) - port map ( - I0 => addr_count(2), - I1 => \Bus_Data_out[10]_i_2_n_0\, - I2 => \Bus_Data_out[10]_i_3_n_0\, - I3 => addr_count(3), - I4 => \Bus_Data_out[10]_i_4_n_0\, - O => mem_probe_in(10) - ); -\Bus_Data_out[10]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => data_int_sync2(26), - I1 => data_int_sync2(58), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => data_int_sync2(10), - I5 => data_int_sync2(42), - O => \Bus_Data_out[10]_i_2_n_0\ - ); -\Bus_Data_out[10]_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => \mem_probe_in[5]__0\(10), - I1 => \mem_probe_in[7]__0\(10), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => \mem_probe_in[4]__0\(10), - I5 => \mem_probe_in[6]__0\(10), - O => \Bus_Data_out[10]_i_3_n_0\ - ); -\Bus_Data_out[10]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => \mem_probe_in[9]__0\(10), - I1 => \mem_probe_in[11]__0\(10), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => \mem_probe_in[8]__0\(10), - I5 => \mem_probe_in[10]__0\(10), - O => \Bus_Data_out[10]_i_4_n_0\ - ); -\Bus_Data_out[11]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"FFE400E4" - ) - port map ( - I0 => addr_count(2), - I1 => \Bus_Data_out[11]_i_2_n_0\, - I2 => \Bus_Data_out[11]_i_3_n_0\, - I3 => addr_count(3), - I4 => \Bus_Data_out[11]_i_4_n_0\, - O => mem_probe_in(11) - ); -\Bus_Data_out[11]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => data_int_sync2(27), - I1 => data_int_sync2(59), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => data_int_sync2(11), - I5 => data_int_sync2(43), - O => \Bus_Data_out[11]_i_2_n_0\ - ); -\Bus_Data_out[11]_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => \mem_probe_in[5]__0\(11), - I1 => \mem_probe_in[7]__0\(11), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => \mem_probe_in[4]__0\(11), - I5 => \mem_probe_in[6]__0\(11), - O => \Bus_Data_out[11]_i_3_n_0\ - ); -\Bus_Data_out[11]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => \mem_probe_in[9]__0\(11), - I1 => \mem_probe_in[11]__0\(11), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => \mem_probe_in[8]__0\(11), - I5 => \mem_probe_in[10]__0\(11), - O => \Bus_Data_out[11]_i_4_n_0\ - ); -\Bus_Data_out[12]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"FFE400E4" - ) - port map ( - I0 => addr_count(2), - I1 => \Bus_Data_out[12]_i_2_n_0\, - I2 => \Bus_Data_out[12]_i_3_n_0\, - I3 => addr_count(3), - I4 => \Bus_Data_out[12]_i_4_n_0\, - O => mem_probe_in(12) - ); -\Bus_Data_out[12]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => data_int_sync2(28), - I1 => data_int_sync2(60), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => data_int_sync2(12), - I5 => data_int_sync2(44), - O => \Bus_Data_out[12]_i_2_n_0\ - ); -\Bus_Data_out[12]_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => \mem_probe_in[5]__0\(12), - I1 => \mem_probe_in[7]__0\(12), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => \mem_probe_in[4]__0\(12), - I5 => \mem_probe_in[6]__0\(12), - O => \Bus_Data_out[12]_i_3_n_0\ - ); -\Bus_Data_out[12]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => \mem_probe_in[9]__0\(12), - I1 => \mem_probe_in[11]__0\(12), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => \mem_probe_in[8]__0\(12), - I5 => \mem_probe_in[10]__0\(12), - O => \Bus_Data_out[12]_i_4_n_0\ - ); -\Bus_Data_out[13]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"FFE400E4" - ) - port map ( - I0 => addr_count(2), - I1 => \Bus_Data_out[13]_i_2_n_0\, - I2 => \Bus_Data_out[13]_i_3_n_0\, - I3 => addr_count(3), - I4 => \Bus_Data_out[13]_i_4_n_0\, - O => mem_probe_in(13) - ); -\Bus_Data_out[13]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => data_int_sync2(29), - I1 => data_int_sync2(61), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => data_int_sync2(13), - I5 => data_int_sync2(45), - O => \Bus_Data_out[13]_i_2_n_0\ - ); -\Bus_Data_out[13]_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => \mem_probe_in[5]__0\(13), - I1 => \mem_probe_in[7]__0\(13), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => \mem_probe_in[4]__0\(13), - I5 => \mem_probe_in[6]__0\(13), - O => \Bus_Data_out[13]_i_3_n_0\ - ); -\Bus_Data_out[13]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => \mem_probe_in[9]__0\(13), - I1 => \mem_probe_in[11]__0\(13), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => \mem_probe_in[8]__0\(13), - I5 => \mem_probe_in[10]__0\(13), - O => \Bus_Data_out[13]_i_4_n_0\ - ); -\Bus_Data_out[14]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"FFE400E4" - ) - port map ( - I0 => addr_count(2), - I1 => \Bus_Data_out[14]_i_2_n_0\, - I2 => \Bus_Data_out[14]_i_3_n_0\, - I3 => addr_count(3), - I4 => \Bus_Data_out[14]_i_4_n_0\, - O => mem_probe_in(14) - ); -\Bus_Data_out[14]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => data_int_sync2(30), - I1 => data_int_sync2(62), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => data_int_sync2(14), - I5 => data_int_sync2(46), - O => \Bus_Data_out[14]_i_2_n_0\ - ); -\Bus_Data_out[14]_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => \mem_probe_in[5]__0\(14), - I1 => \mem_probe_in[7]__0\(14), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => \mem_probe_in[4]__0\(14), - I5 => \mem_probe_in[6]__0\(14), - O => \Bus_Data_out[14]_i_3_n_0\ - ); -\Bus_Data_out[14]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => \mem_probe_in[9]__0\(14), - I1 => \mem_probe_in[11]__0\(14), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => \mem_probe_in[8]__0\(14), - I5 => \mem_probe_in[10]__0\(14), - O => \Bus_Data_out[14]_i_4_n_0\ - ); -\Bus_Data_out[15]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"FFE400E4" - ) - port map ( - I0 => addr_count(2), - I1 => \Bus_Data_out[15]_i_2_n_0\, - I2 => \Bus_Data_out[15]_i_3_n_0\, - I3 => addr_count(3), - I4 => \Bus_Data_out[15]_i_4_n_0\, - O => mem_probe_in(15) - ); -\Bus_Data_out[15]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => data_int_sync2(31), - I1 => data_int_sync2(63), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => data_int_sync2(15), - I5 => data_int_sync2(47), - O => \Bus_Data_out[15]_i_2_n_0\ - ); -\Bus_Data_out[15]_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => \mem_probe_in[5]__0\(15), - I1 => \mem_probe_in[7]__0\(15), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => \mem_probe_in[4]__0\(15), - I5 => \mem_probe_in[6]__0\(15), - O => \Bus_Data_out[15]_i_3_n_0\ - ); -\Bus_Data_out[15]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => \mem_probe_in[9]__0\(15), - I1 => \mem_probe_in[11]__0\(15), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => \mem_probe_in[8]__0\(15), - I5 => \mem_probe_in[10]__0\(15), - O => \Bus_Data_out[15]_i_4_n_0\ - ); -\Bus_Data_out[1]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"FFE400E4" - ) - port map ( - I0 => addr_count(2), - I1 => \Bus_Data_out[1]_i_2_n_0\, - I2 => \Bus_Data_out[1]_i_3_n_0\, - I3 => addr_count(3), - I4 => \Bus_Data_out[1]_i_4_n_0\, - O => mem_probe_in(1) - ); -\Bus_Data_out[1]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => data_int_sync2(17), - I1 => data_int_sync2(49), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => data_int_sync2(1), - I5 => data_int_sync2(33), - O => \Bus_Data_out[1]_i_2_n_0\ - ); -\Bus_Data_out[1]_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => \mem_probe_in[5]__0\(1), - I1 => \mem_probe_in[7]__0\(1), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => \mem_probe_in[4]__0\(1), - I5 => \mem_probe_in[6]__0\(1), - O => \Bus_Data_out[1]_i_3_n_0\ - ); -\Bus_Data_out[1]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => \mem_probe_in[9]__0\(1), - I1 => \mem_probe_in[11]__0\(1), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => \mem_probe_in[8]__0\(1), - I5 => \mem_probe_in[10]__0\(1), - O => \Bus_Data_out[1]_i_4_n_0\ - ); -\Bus_Data_out[2]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"FFE400E4" - ) - port map ( - I0 => addr_count(2), - I1 => \Bus_Data_out[2]_i_2_n_0\, - I2 => \Bus_Data_out[2]_i_3_n_0\, - I3 => addr_count(3), - I4 => \Bus_Data_out[2]_i_4_n_0\, - O => mem_probe_in(2) - ); -\Bus_Data_out[2]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => data_int_sync2(18), - I1 => data_int_sync2(50), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => data_int_sync2(2), - I5 => data_int_sync2(34), - O => \Bus_Data_out[2]_i_2_n_0\ - ); -\Bus_Data_out[2]_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => \mem_probe_in[5]__0\(2), - I1 => \mem_probe_in[7]__0\(2), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => \mem_probe_in[4]__0\(2), - I5 => \mem_probe_in[6]__0\(2), - O => \Bus_Data_out[2]_i_3_n_0\ - ); -\Bus_Data_out[2]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => \mem_probe_in[9]__0\(2), - I1 => \mem_probe_in[11]__0\(2), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => \mem_probe_in[8]__0\(2), - I5 => \mem_probe_in[10]__0\(2), - O => \Bus_Data_out[2]_i_4_n_0\ - ); -\Bus_Data_out[3]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"FFE400E4" - ) - port map ( - I0 => addr_count(2), - I1 => \Bus_Data_out[3]_i_2_n_0\, - I2 => \Bus_Data_out[3]_i_3_n_0\, - I3 => addr_count(3), - I4 => \Bus_Data_out[3]_i_4_n_0\, - O => mem_probe_in(3) - ); -\Bus_Data_out[3]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => data_int_sync2(19), - I1 => data_int_sync2(51), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => data_int_sync2(3), - I5 => data_int_sync2(35), - O => \Bus_Data_out[3]_i_2_n_0\ - ); -\Bus_Data_out[3]_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => \mem_probe_in[5]__0\(3), - I1 => \mem_probe_in[7]__0\(3), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => \mem_probe_in[4]__0\(3), - I5 => \mem_probe_in[6]__0\(3), - O => \Bus_Data_out[3]_i_3_n_0\ - ); -\Bus_Data_out[3]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => \mem_probe_in[9]__0\(3), - I1 => \mem_probe_in[11]__0\(3), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => \mem_probe_in[8]__0\(3), - I5 => \mem_probe_in[10]__0\(3), - O => \Bus_Data_out[3]_i_4_n_0\ - ); -\Bus_Data_out[4]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"FFE400E4" - ) - port map ( - I0 => addr_count(2), - I1 => \Bus_Data_out[4]_i_2_n_0\, - I2 => \Bus_Data_out[4]_i_3_n_0\, - I3 => addr_count(3), - I4 => \Bus_Data_out[4]_i_4_n_0\, - O => mem_probe_in(4) - ); -\Bus_Data_out[4]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => data_int_sync2(20), - I1 => data_int_sync2(52), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => data_int_sync2(4), - I5 => data_int_sync2(36), - O => \Bus_Data_out[4]_i_2_n_0\ - ); -\Bus_Data_out[4]_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => \mem_probe_in[5]__0\(4), - I1 => \mem_probe_in[7]__0\(4), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => \mem_probe_in[4]__0\(4), - I5 => \mem_probe_in[6]__0\(4), - O => \Bus_Data_out[4]_i_3_n_0\ - ); -\Bus_Data_out[4]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => \mem_probe_in[9]__0\(4), - I1 => \mem_probe_in[11]__0\(4), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => \mem_probe_in[8]__0\(4), - I5 => \mem_probe_in[10]__0\(4), - O => \Bus_Data_out[4]_i_4_n_0\ - ); -\Bus_Data_out[5]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"FFE400E4" - ) - port map ( - I0 => addr_count(2), - I1 => \Bus_Data_out[5]_i_2_n_0\, - I2 => \Bus_Data_out[5]_i_3_n_0\, - I3 => addr_count(3), - I4 => \Bus_Data_out[5]_i_4_n_0\, - O => mem_probe_in(5) - ); -\Bus_Data_out[5]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => data_int_sync2(21), - I1 => data_int_sync2(53), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => data_int_sync2(5), - I5 => data_int_sync2(37), - O => \Bus_Data_out[5]_i_2_n_0\ - ); -\Bus_Data_out[5]_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => \mem_probe_in[5]__0\(5), - I1 => \mem_probe_in[7]__0\(5), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => \mem_probe_in[4]__0\(5), - I5 => \mem_probe_in[6]__0\(5), - O => \Bus_Data_out[5]_i_3_n_0\ - ); -\Bus_Data_out[5]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => \mem_probe_in[9]__0\(5), - I1 => \mem_probe_in[11]__0\(5), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => \mem_probe_in[8]__0\(5), - I5 => \mem_probe_in[10]__0\(5), - O => \Bus_Data_out[5]_i_4_n_0\ - ); -\Bus_Data_out[6]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"FFE400E4" - ) - port map ( - I0 => addr_count(2), - I1 => \Bus_Data_out[6]_i_2_n_0\, - I2 => \Bus_Data_out[6]_i_3_n_0\, - I3 => addr_count(3), - I4 => \Bus_Data_out[6]_i_4_n_0\, - O => mem_probe_in(6) - ); -\Bus_Data_out[6]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => data_int_sync2(22), - I1 => data_int_sync2(54), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => data_int_sync2(6), - I5 => data_int_sync2(38), - O => \Bus_Data_out[6]_i_2_n_0\ - ); -\Bus_Data_out[6]_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => \mem_probe_in[5]__0\(6), - I1 => \mem_probe_in[7]__0\(6), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => \mem_probe_in[4]__0\(6), - I5 => \mem_probe_in[6]__0\(6), - O => \Bus_Data_out[6]_i_3_n_0\ - ); -\Bus_Data_out[6]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => \mem_probe_in[9]__0\(6), - I1 => \mem_probe_in[11]__0\(6), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => \mem_probe_in[8]__0\(6), - I5 => \mem_probe_in[10]__0\(6), - O => \Bus_Data_out[6]_i_4_n_0\ - ); -\Bus_Data_out[7]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"FFE400E4" - ) - port map ( - I0 => addr_count(2), - I1 => \Bus_Data_out[7]_i_2_n_0\, - I2 => \Bus_Data_out[7]_i_3_n_0\, - I3 => addr_count(3), - I4 => \Bus_Data_out[7]_i_4_n_0\, - O => mem_probe_in(7) - ); -\Bus_Data_out[7]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => data_int_sync2(23), - I1 => data_int_sync2(55), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => data_int_sync2(7), - I5 => data_int_sync2(39), - O => \Bus_Data_out[7]_i_2_n_0\ - ); -\Bus_Data_out[7]_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => \mem_probe_in[5]__0\(7), - I1 => \mem_probe_in[7]__0\(7), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => \mem_probe_in[4]__0\(7), - I5 => \mem_probe_in[6]__0\(7), - O => \Bus_Data_out[7]_i_3_n_0\ - ); -\Bus_Data_out[7]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => \mem_probe_in[9]__0\(7), - I1 => \mem_probe_in[11]__0\(7), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => \mem_probe_in[8]__0\(7), - I5 => \mem_probe_in[10]__0\(7), - O => \Bus_Data_out[7]_i_4_n_0\ - ); -\Bus_Data_out[8]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"FFE400E4" - ) - port map ( - I0 => addr_count(2), - I1 => \Bus_Data_out[8]_i_2_n_0\, - I2 => \Bus_Data_out[8]_i_3_n_0\, - I3 => addr_count(3), - I4 => \Bus_Data_out[8]_i_4_n_0\, - O => mem_probe_in(8) - ); -\Bus_Data_out[8]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => data_int_sync2(24), - I1 => data_int_sync2(56), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => data_int_sync2(8), - I5 => data_int_sync2(40), - O => \Bus_Data_out[8]_i_2_n_0\ - ); -\Bus_Data_out[8]_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => \mem_probe_in[5]__0\(8), - I1 => \mem_probe_in[7]__0\(8), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => \mem_probe_in[4]__0\(8), - I5 => \mem_probe_in[6]__0\(8), - O => \Bus_Data_out[8]_i_3_n_0\ - ); -\Bus_Data_out[8]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => \mem_probe_in[9]__0\(8), - I1 => \mem_probe_in[11]__0\(8), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => \mem_probe_in[8]__0\(8), - I5 => \mem_probe_in[10]__0\(8), - O => \Bus_Data_out[8]_i_4_n_0\ - ); -\Bus_Data_out[9]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"FFE400E4" - ) - port map ( - I0 => addr_count(2), - I1 => \Bus_Data_out[9]_i_2_n_0\, - I2 => \Bus_Data_out[9]_i_3_n_0\, - I3 => addr_count(3), - I4 => \Bus_Data_out[9]_i_4_n_0\, - O => mem_probe_in(9) - ); -\Bus_Data_out[9]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => data_int_sync2(25), - I1 => data_int_sync2(57), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => data_int_sync2(9), - I5 => data_int_sync2(41), - O => \Bus_Data_out[9]_i_2_n_0\ - ); -\Bus_Data_out[9]_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => \mem_probe_in[5]__0\(9), - I1 => \mem_probe_in[7]__0\(9), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => \mem_probe_in[4]__0\(9), - I5 => \mem_probe_in[6]__0\(9), - O => \Bus_Data_out[9]_i_3_n_0\ - ); -\Bus_Data_out[9]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"CFAFCFA0C0AFC0A0" - ) - port map ( - I0 => \mem_probe_in[9]__0\(9), - I1 => \mem_probe_in[11]__0\(9), - I2 => addr_count(0), - I3 => addr_count(1), - I4 => \mem_probe_in[8]__0\(9), - I5 => \mem_probe_in[10]__0\(9), - O => \Bus_Data_out[9]_i_4_n_0\ - ); -\Bus_Data_out_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => mem_probe_in(0), - Q => Q(0), - R => '0' - ); -\Bus_Data_out_reg[10]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => mem_probe_in(10), - Q => Q(10), - R => '0' - ); -\Bus_Data_out_reg[11]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => mem_probe_in(11), - Q => Q(11), - R => '0' - ); -\Bus_Data_out_reg[12]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => mem_probe_in(12), - Q => Q(12), - R => '0' - ); -\Bus_Data_out_reg[13]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => mem_probe_in(13), - Q => Q(13), - R => '0' - ); -\Bus_Data_out_reg[14]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => mem_probe_in(14), - Q => Q(14), - R => '0' - ); -\Bus_Data_out_reg[15]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => mem_probe_in(15), - Q => Q(15), - R => '0' - ); -\Bus_Data_out_reg[1]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => mem_probe_in(1), - Q => Q(1), - R => '0' - ); -\Bus_Data_out_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => mem_probe_in(2), - Q => Q(2), - R => '0' - ); -\Bus_Data_out_reg[3]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => mem_probe_in(3), - Q => Q(3), - R => '0' - ); -\Bus_Data_out_reg[4]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => mem_probe_in(4), - Q => Q(4), - R => '0' - ); -\Bus_Data_out_reg[5]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => mem_probe_in(5), - Q => Q(5), - R => '0' - ); -\Bus_Data_out_reg[6]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => mem_probe_in(6), - Q => Q(6), - R => '0' - ); -\Bus_Data_out_reg[7]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => mem_probe_in(7), - Q => Q(7), - R => '0' - ); -\Bus_Data_out_reg[8]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => mem_probe_in(8), - Q => Q(8), - R => '0' - ); -\Bus_Data_out_reg[9]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => mem_probe_in(9), - Q => Q(9), - R => '0' - ); -Read_int_i_1: unisim.vcomponents.LUT4 - generic map( - INIT => X"8000" - ) - port map ( - I0 => Read_int_i_2_n_0, - I1 => Read_int_i_3_n_0, - I2 => Read_int_i_4_n_0, - I3 => Read_int_i_5_n_0, - O => \DECODER_INST/rd_en_int_7\ - ); -Read_int_i_2: unisim.vcomponents.LUT6 - generic map( - INIT => X"0000000000000080" - ) - port map ( - I0 => s_daddr_o(0), - I1 => s_daddr_o(1), - I2 => s_daddr_o(2), - I3 => Read_int_i_6_n_0, - I4 => s_daddr_o(7), - I5 => s_daddr_o(8), - O => Read_int_i_2_n_0 - ); -Read_int_i_3: unisim.vcomponents.LUT6 - generic map( - INIT => X"0000000000000010" - ) - port map ( - I0 => s_daddr_o(15), - I1 => s_daddr_o(16), - I2 => \^xsdb_rd\, - I3 => Read_int_reg_0, - I4 => s_daddr_o(13), - I5 => s_daddr_o(14), - O => Read_int_i_3_n_0 - ); -Read_int_i_4: unisim.vcomponents.LUT6 - generic map( - INIT => X"0000230000002323" - ) - port map ( - I0 => s_daddr_o(7), - I1 => s_daddr_o(8), - I2 => s_daddr_o(6), - I3 => s_daddr_o(4), - I4 => s_daddr_o(5), - I5 => s_daddr_o(3), - O => Read_int_i_4_n_0 - ); -Read_int_i_5: unisim.vcomponents.LUT6 - generic map( - INIT => X"0000230000002323" - ) - port map ( - I0 => s_daddr_o(13), - I1 => s_daddr_o(14), - I2 => s_daddr_o(12), - I3 => s_daddr_o(10), - I4 => s_daddr_o(11), - I5 => s_daddr_o(9), - O => Read_int_i_5_n_0 - ); -Read_int_i_6: unisim.vcomponents.LUT2 - generic map( - INIT => X"E" - ) - port map ( - I0 => s_daddr_o(5), - I1 => s_daddr_o(4), - O => Read_int_i_6_n_0 - ); -Read_int_reg: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => \DECODER_INST/rd_en_int_7\, - Q => Read_int, - R => '0' - ); -\addr_count[0]_i_1\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => addr_count(0), - O => \addr_count[0]_i_1_n_0\ - ); -\addr_count[1]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => addr_count(1), - I1 => addr_count(0), - O => \addr_count[1]_i_1_n_0\ - ); -\addr_count[2]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"78" - ) - port map ( - I0 => addr_count(0), - I1 => addr_count(1), - I2 => addr_count(2), - O => \addr_count[2]_i_1_n_0\ - ); -\addr_count[3]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"7F80" - ) - port map ( - I0 => addr_count(1), - I1 => addr_count(0), - I2 => addr_count(2), - I3 => addr_count(3), - O => \addr_count[3]_i_1_n_0\ - ); -\addr_count[4]_i_2\: unisim.vcomponents.LUT5 - generic map( - INIT => X"7FFF8000" - ) - port map ( - I0 => addr_count(2), - I1 => addr_count(0), - I2 => addr_count(1), - I3 => addr_count(3), - I4 => addr_count(4), - O => \addr_count[4]_i_2_n_0\ - ); -\addr_count_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => Read_int, - D => \addr_count[0]_i_1_n_0\, - Q => addr_count(0), - R => SR(0) - ); -\addr_count_reg[1]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => Read_int, - D => \addr_count[1]_i_1_n_0\, - Q => addr_count(1), - R => SR(0) - ); -\addr_count_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => Read_int, - D => \addr_count[2]_i_1_n_0\, - Q => addr_count(2), - R => SR(0) - ); -\addr_count_reg[3]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => Read_int, - D => \addr_count[3]_i_1_n_0\, - Q => addr_count(3), - R => SR(0) - ); -\addr_count_reg[4]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => Read_int, - D => \addr_count[4]_i_2_n_0\, - Q => addr_count(4), - R => SR(0) - ); -\data_int_sync1_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(0), - Q => data_int_sync1(0), - R => '0' - ); -\data_int_sync1_reg[10]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(10), - Q => data_int_sync1(10), - R => '0' - ); -\data_int_sync1_reg[11]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(11), - Q => data_int_sync1(11), - R => '0' - ); -\data_int_sync1_reg[12]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(12), - Q => data_int_sync1(12), - R => '0' - ); -\data_int_sync1_reg[13]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(13), - Q => data_int_sync1(13), - R => '0' - ); -\data_int_sync1_reg[14]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(14), - Q => data_int_sync1(14), - R => '0' - ); -\data_int_sync1_reg[15]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(15), - Q => data_int_sync1(15), - R => '0' - ); -\data_int_sync1_reg[16]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(16), - Q => data_int_sync1(16), - R => '0' - ); -\data_int_sync1_reg[17]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(17), - Q => data_int_sync1(17), - R => '0' - ); -\data_int_sync1_reg[18]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(18), - Q => data_int_sync1(18), - R => '0' - ); -\data_int_sync1_reg[19]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(19), - Q => data_int_sync1(19), - R => '0' - ); -\data_int_sync1_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(1), - Q => data_int_sync1(1), - R => '0' - ); -\data_int_sync1_reg[20]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(20), - Q => data_int_sync1(20), - R => '0' - ); -\data_int_sync1_reg[21]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(21), - Q => data_int_sync1(21), - R => '0' - ); -\data_int_sync1_reg[22]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(22), - Q => data_int_sync1(22), - R => '0' - ); -\data_int_sync1_reg[23]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(23), - Q => data_int_sync1(23), - R => '0' - ); -\data_int_sync1_reg[24]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(24), - Q => data_int_sync1(24), - R => '0' - ); -\data_int_sync1_reg[25]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(25), - Q => data_int_sync1(25), - R => '0' - ); -\data_int_sync1_reg[26]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(26), - Q => data_int_sync1(26), - R => '0' - ); -\data_int_sync1_reg[27]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(27), - Q => data_int_sync1(27), - R => '0' - ); -\data_int_sync1_reg[28]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(28), - Q => data_int_sync1(28), - R => '0' - ); -\data_int_sync1_reg[29]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(29), - Q => data_int_sync1(29), - R => '0' - ); -\data_int_sync1_reg[2]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(2), - Q => data_int_sync1(2), - R => '0' - ); -\data_int_sync1_reg[30]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(30), - Q => data_int_sync1(30), - R => '0' - ); -\data_int_sync1_reg[31]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(31), - Q => data_int_sync1(31), - R => '0' - ); -\data_int_sync1_reg[32]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(32), - Q => data_int_sync1(32), - R => '0' - ); -\data_int_sync1_reg[33]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(33), - Q => data_int_sync1(33), - R => '0' - ); -\data_int_sync1_reg[34]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(34), - Q => data_int_sync1(34), - R => '0' - ); -\data_int_sync1_reg[35]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(35), - Q => data_int_sync1(35), - R => '0' - ); -\data_int_sync1_reg[36]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(36), - Q => data_int_sync1(36), - R => '0' - ); -\data_int_sync1_reg[37]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(37), - Q => data_int_sync1(37), - R => '0' - ); -\data_int_sync1_reg[38]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(38), - Q => data_int_sync1(38), - R => '0' - ); -\data_int_sync1_reg[39]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(39), - Q => data_int_sync1(39), - R => '0' - ); -\data_int_sync1_reg[3]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(3), - Q => data_int_sync1(3), - R => '0' - ); -\data_int_sync1_reg[40]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(40), - Q => data_int_sync1(40), - R => '0' - ); -\data_int_sync1_reg[41]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(41), - Q => data_int_sync1(41), - R => '0' - ); -\data_int_sync1_reg[42]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(42), - Q => data_int_sync1(42), - R => '0' - ); -\data_int_sync1_reg[43]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(43), - Q => data_int_sync1(43), - R => '0' - ); -\data_int_sync1_reg[44]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(44), - Q => data_int_sync1(44), - R => '0' - ); -\data_int_sync1_reg[45]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(45), - Q => data_int_sync1(45), - R => '0' - ); -\data_int_sync1_reg[46]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(46), - Q => data_int_sync1(46), - R => '0' - ); -\data_int_sync1_reg[47]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(47), - Q => data_int_sync1(47), - R => '0' - ); -\data_int_sync1_reg[48]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(48), - Q => data_int_sync1(48), - R => '0' - ); -\data_int_sync1_reg[49]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(49), - Q => data_int_sync1(49), - R => '0' - ); -\data_int_sync1_reg[4]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(4), - Q => data_int_sync1(4), - R => '0' - ); -\data_int_sync1_reg[50]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(50), - Q => data_int_sync1(50), - R => '0' - ); -\data_int_sync1_reg[51]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(51), - Q => data_int_sync1(51), - R => '0' - ); -\data_int_sync1_reg[52]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(52), - Q => data_int_sync1(52), - R => '0' - ); -\data_int_sync1_reg[53]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(53), - Q => data_int_sync1(53), - R => '0' - ); -\data_int_sync1_reg[54]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(54), - Q => data_int_sync1(54), - R => '0' - ); -\data_int_sync1_reg[55]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(55), - Q => data_int_sync1(55), - R => '0' - ); -\data_int_sync1_reg[56]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(56), - Q => data_int_sync1(56), - R => '0' - ); -\data_int_sync1_reg[57]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(57), - Q => data_int_sync1(57), - R => '0' - ); -\data_int_sync1_reg[58]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(58), - Q => data_int_sync1(58), - R => '0' - ); -\data_int_sync1_reg[59]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(59), - Q => data_int_sync1(59), - R => '0' - ); -\data_int_sync1_reg[5]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(5), - Q => data_int_sync1(5), - R => '0' - ); -\data_int_sync1_reg[60]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(60), - Q => data_int_sync1(60), - R => '0' - ); -\data_int_sync1_reg[61]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(61), - Q => data_int_sync1(61), - R => '0' - ); -\data_int_sync1_reg[62]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(62), - Q => data_int_sync1(62), - R => '0' - ); -\data_int_sync1_reg[63]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(63), - Q => data_int_sync1(63), - R => '0' - ); -\data_int_sync1_reg[6]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(6), - Q => data_int_sync1(6), - R => '0' - ); -\data_int_sync1_reg[7]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(7), - Q => data_int_sync1(7), - R => '0' - ); -\data_int_sync1_reg[8]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(8), - Q => data_int_sync1(8), - R => '0' - ); -\data_int_sync1_reg[9]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => probe_in_reg(9), - Q => data_int_sync1(9), - R => '0' - ); -\data_int_sync2_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(0), - Q => data_int_sync2(0), - R => '0' - ); -\data_int_sync2_reg[10]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(10), - Q => data_int_sync2(10), - R => '0' - ); -\data_int_sync2_reg[11]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(11), - Q => data_int_sync2(11), - R => '0' - ); -\data_int_sync2_reg[12]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(12), - Q => data_int_sync2(12), - R => '0' - ); -\data_int_sync2_reg[13]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(13), - Q => data_int_sync2(13), - R => '0' - ); -\data_int_sync2_reg[14]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(14), - Q => data_int_sync2(14), - R => '0' - ); -\data_int_sync2_reg[15]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(15), - Q => data_int_sync2(15), - R => '0' - ); -\data_int_sync2_reg[16]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(16), - Q => data_int_sync2(16), - R => '0' - ); -\data_int_sync2_reg[17]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(17), - Q => data_int_sync2(17), - R => '0' - ); -\data_int_sync2_reg[18]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(18), - Q => data_int_sync2(18), - R => '0' - ); -\data_int_sync2_reg[19]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(19), - Q => data_int_sync2(19), - R => '0' - ); -\data_int_sync2_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(1), - Q => data_int_sync2(1), - R => '0' - ); -\data_int_sync2_reg[20]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(20), - Q => data_int_sync2(20), - R => '0' - ); -\data_int_sync2_reg[21]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(21), - Q => data_int_sync2(21), - R => '0' - ); -\data_int_sync2_reg[22]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(22), - Q => data_int_sync2(22), - R => '0' - ); -\data_int_sync2_reg[23]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(23), - Q => data_int_sync2(23), - R => '0' - ); -\data_int_sync2_reg[24]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(24), - Q => data_int_sync2(24), - R => '0' - ); -\data_int_sync2_reg[25]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(25), - Q => data_int_sync2(25), - R => '0' - ); -\data_int_sync2_reg[26]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(26), - Q => data_int_sync2(26), - R => '0' - ); -\data_int_sync2_reg[27]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(27), - Q => data_int_sync2(27), - R => '0' - ); -\data_int_sync2_reg[28]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(28), - Q => data_int_sync2(28), - R => '0' - ); -\data_int_sync2_reg[29]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(29), - Q => data_int_sync2(29), - R => '0' - ); -\data_int_sync2_reg[2]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(2), - Q => data_int_sync2(2), - R => '0' - ); -\data_int_sync2_reg[30]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(30), - Q => data_int_sync2(30), - R => '0' - ); -\data_int_sync2_reg[31]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(31), - Q => data_int_sync2(31), - R => '0' - ); -\data_int_sync2_reg[32]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(32), - Q => data_int_sync2(32), - R => '0' - ); -\data_int_sync2_reg[33]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(33), - Q => data_int_sync2(33), - R => '0' - ); -\data_int_sync2_reg[34]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(34), - Q => data_int_sync2(34), - R => '0' - ); -\data_int_sync2_reg[35]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(35), - Q => data_int_sync2(35), - R => '0' - ); -\data_int_sync2_reg[36]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(36), - Q => data_int_sync2(36), - R => '0' - ); -\data_int_sync2_reg[37]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(37), - Q => data_int_sync2(37), - R => '0' - ); -\data_int_sync2_reg[38]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(38), - Q => data_int_sync2(38), - R => '0' - ); -\data_int_sync2_reg[39]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(39), - Q => data_int_sync2(39), - R => '0' - ); -\data_int_sync2_reg[3]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(3), - Q => data_int_sync2(3), - R => '0' - ); -\data_int_sync2_reg[40]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(40), - Q => data_int_sync2(40), - R => '0' - ); -\data_int_sync2_reg[41]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(41), - Q => data_int_sync2(41), - R => '0' - ); -\data_int_sync2_reg[42]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(42), - Q => data_int_sync2(42), - R => '0' - ); -\data_int_sync2_reg[43]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(43), - Q => data_int_sync2(43), - R => '0' - ); -\data_int_sync2_reg[44]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(44), - Q => data_int_sync2(44), - R => '0' - ); -\data_int_sync2_reg[45]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(45), - Q => data_int_sync2(45), - R => '0' - ); -\data_int_sync2_reg[46]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(46), - Q => data_int_sync2(46), - R => '0' - ); -\data_int_sync2_reg[47]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(47), - Q => data_int_sync2(47), - R => '0' - ); -\data_int_sync2_reg[48]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(48), - Q => data_int_sync2(48), - R => '0' - ); -\data_int_sync2_reg[49]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(49), - Q => data_int_sync2(49), - R => '0' - ); -\data_int_sync2_reg[4]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(4), - Q => data_int_sync2(4), - R => '0' - ); -\data_int_sync2_reg[50]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(50), - Q => data_int_sync2(50), - R => '0' - ); -\data_int_sync2_reg[51]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(51), - Q => data_int_sync2(51), - R => '0' - ); -\data_int_sync2_reg[52]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(52), - Q => data_int_sync2(52), - R => '0' - ); -\data_int_sync2_reg[53]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(53), - Q => data_int_sync2(53), - R => '0' - ); -\data_int_sync2_reg[54]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(54), - Q => data_int_sync2(54), - R => '0' - ); -\data_int_sync2_reg[55]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(55), - Q => data_int_sync2(55), - R => '0' - ); -\data_int_sync2_reg[56]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(56), - Q => data_int_sync2(56), - R => '0' - ); -\data_int_sync2_reg[57]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(57), - Q => data_int_sync2(57), - R => '0' - ); -\data_int_sync2_reg[58]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(58), - Q => data_int_sync2(58), - R => '0' - ); -\data_int_sync2_reg[59]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(59), - Q => data_int_sync2(59), - R => '0' - ); -\data_int_sync2_reg[5]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(5), - Q => data_int_sync2(5), - R => '0' - ); -\data_int_sync2_reg[60]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(60), - Q => data_int_sync2(60), - R => '0' - ); -\data_int_sync2_reg[61]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(61), - Q => data_int_sync2(61), - R => '0' - ); -\data_int_sync2_reg[62]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(62), - Q => data_int_sync2(62), - R => '0' - ); -\data_int_sync2_reg[63]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(63), - Q => data_int_sync2(63), - R => '0' - ); -\data_int_sync2_reg[6]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(6), - Q => data_int_sync2(6), - R => '0' - ); -\data_int_sync2_reg[7]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(7), - Q => data_int_sync2(7), - R => '0' - ); -\data_int_sync2_reg[8]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(8), - Q => data_int_sync2(8), - R => '0' - ); -\data_int_sync2_reg[9]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => data_int_sync1(9), - Q => data_int_sync2(9), - R => '0' - ); -\dn_activity[0]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(0), - I1 => data_int_sync1(0), - I2 => read_done, - I3 => \mem_probe_in[8]__0\(0), - O => dn_activity0 - ); -\dn_activity[10]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(10), - I1 => data_int_sync1(10), - I2 => read_done, - I3 => \mem_probe_in[8]__0\(10), - O => dn_activity038_out - ); -\dn_activity[11]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(11), - I1 => data_int_sync1(11), - I2 => read_done, - I3 => \mem_probe_in[8]__0\(11), - O => dn_activity042_out - ); -\dn_activity[12]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(12), - I1 => data_int_sync1(12), - I2 => read_done, - I3 => \mem_probe_in[8]__0\(12), - O => dn_activity046_out - ); -\dn_activity[13]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(13), - I1 => data_int_sync1(13), - I2 => read_done, - I3 => \mem_probe_in[8]__0\(13), - O => dn_activity050_out - ); -\dn_activity[14]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(14), - I1 => data_int_sync1(14), - I2 => read_done, - I3 => \mem_probe_in[8]__0\(14), - O => dn_activity054_out - ); -\dn_activity[15]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(15), - I1 => data_int_sync1(15), - I2 => read_done, - I3 => \mem_probe_in[8]__0\(15), - O => dn_activity058_out - ); -\dn_activity[16]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(16), - I1 => data_int_sync1(16), - I2 => read_done, - I3 => \mem_probe_in[9]__0\(0), - O => dn_activity062_out - ); -\dn_activity[17]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(17), - I1 => data_int_sync1(17), - I2 => read_done, - I3 => \mem_probe_in[9]__0\(1), - O => dn_activity066_out - ); -\dn_activity[18]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(18), - I1 => data_int_sync1(18), - I2 => read_done, - I3 => \mem_probe_in[9]__0\(2), - O => dn_activity070_out - ); -\dn_activity[19]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(19), - I1 => data_int_sync1(19), - I2 => read_done, - I3 => \mem_probe_in[9]__0\(3), - O => dn_activity074_out - ); -\dn_activity[1]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(1), - I1 => data_int_sync1(1), - I2 => read_done, - I3 => \mem_probe_in[8]__0\(1), - O => dn_activity02_out - ); -\dn_activity[20]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(20), - I1 => data_int_sync1(20), - I2 => read_done, - I3 => \mem_probe_in[9]__0\(4), - O => dn_activity078_out - ); -\dn_activity[21]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(21), - I1 => data_int_sync1(21), - I2 => read_done, - I3 => \mem_probe_in[9]__0\(5), - O => dn_activity082_out - ); -\dn_activity[22]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(22), - I1 => data_int_sync1(22), - I2 => read_done, - I3 => \mem_probe_in[9]__0\(6), - O => dn_activity086_out - ); -\dn_activity[23]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(23), - I1 => data_int_sync1(23), - I2 => read_done, - I3 => \mem_probe_in[9]__0\(7), - O => dn_activity090_out - ); -\dn_activity[24]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(24), - I1 => data_int_sync1(24), - I2 => read_done, - I3 => \mem_probe_in[9]__0\(8), - O => dn_activity094_out - ); -\dn_activity[25]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(25), - I1 => data_int_sync1(25), - I2 => read_done, - I3 => \mem_probe_in[9]__0\(9), - O => dn_activity098_out - ); -\dn_activity[26]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(26), - I1 => data_int_sync1(26), - I2 => read_done, - I3 => \mem_probe_in[9]__0\(10), - O => dn_activity0102_out - ); -\dn_activity[27]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(27), - I1 => data_int_sync1(27), - I2 => read_done, - I3 => \mem_probe_in[9]__0\(11), - O => dn_activity0106_out - ); -\dn_activity[28]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(28), - I1 => data_int_sync1(28), - I2 => read_done, - I3 => \mem_probe_in[9]__0\(12), - O => dn_activity0110_out - ); -\dn_activity[29]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(29), - I1 => data_int_sync1(29), - I2 => read_done, - I3 => \mem_probe_in[9]__0\(13), - O => dn_activity0114_out - ); -\dn_activity[2]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(2), - I1 => data_int_sync1(2), - I2 => read_done, - I3 => \mem_probe_in[8]__0\(2), - O => dn_activity06_out - ); -\dn_activity[30]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(30), - I1 => data_int_sync1(30), - I2 => read_done, - I3 => \mem_probe_in[9]__0\(14), - O => dn_activity0118_out - ); -\dn_activity[31]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(31), - I1 => data_int_sync1(31), - I2 => read_done, - I3 => \mem_probe_in[9]__0\(15), - O => dn_activity0122_out - ); -\dn_activity[32]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(32), - I1 => data_int_sync1(32), - I2 => read_done, - I3 => \mem_probe_in[10]__0\(0), - O => dn_activity0126_out - ); -\dn_activity[33]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(33), - I1 => data_int_sync1(33), - I2 => read_done, - I3 => \mem_probe_in[10]__0\(1), - O => dn_activity0130_out - ); -\dn_activity[34]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(34), - I1 => data_int_sync1(34), - I2 => read_done, - I3 => \mem_probe_in[10]__0\(2), - O => dn_activity0134_out - ); -\dn_activity[35]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(35), - I1 => data_int_sync1(35), - I2 => read_done, - I3 => \mem_probe_in[10]__0\(3), - O => dn_activity0138_out - ); -\dn_activity[36]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(36), - I1 => data_int_sync1(36), - I2 => read_done, - I3 => \mem_probe_in[10]__0\(4), - O => dn_activity0142_out - ); -\dn_activity[37]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(37), - I1 => data_int_sync1(37), - I2 => read_done, - I3 => \mem_probe_in[10]__0\(5), - O => dn_activity0146_out - ); -\dn_activity[38]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(38), - I1 => data_int_sync1(38), - I2 => read_done, - I3 => \mem_probe_in[10]__0\(6), - O => dn_activity0150_out - ); -\dn_activity[39]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(39), - I1 => data_int_sync1(39), - I2 => read_done, - I3 => \mem_probe_in[10]__0\(7), - O => dn_activity0154_out - ); -\dn_activity[3]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(3), - I1 => data_int_sync1(3), - I2 => read_done, - I3 => \mem_probe_in[8]__0\(3), - O => dn_activity010_out - ); -\dn_activity[40]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(40), - I1 => data_int_sync1(40), - I2 => read_done, - I3 => \mem_probe_in[10]__0\(8), - O => dn_activity0158_out - ); -\dn_activity[41]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(41), - I1 => data_int_sync1(41), - I2 => read_done, - I3 => \mem_probe_in[10]__0\(9), - O => dn_activity0162_out - ); -\dn_activity[42]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(42), - I1 => data_int_sync1(42), - I2 => read_done, - I3 => \mem_probe_in[10]__0\(10), - O => dn_activity0166_out - ); -\dn_activity[43]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(43), - I1 => data_int_sync1(43), - I2 => read_done, - I3 => \mem_probe_in[10]__0\(11), - O => dn_activity0170_out - ); -\dn_activity[44]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(44), - I1 => data_int_sync1(44), - I2 => read_done, - I3 => \mem_probe_in[10]__0\(12), - O => dn_activity0174_out - ); -\dn_activity[45]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(45), - I1 => data_int_sync1(45), - I2 => read_done, - I3 => \mem_probe_in[10]__0\(13), - O => dn_activity0178_out - ); -\dn_activity[46]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(46), - I1 => data_int_sync1(46), - I2 => read_done, - I3 => \mem_probe_in[10]__0\(14), - O => dn_activity0182_out - ); -\dn_activity[47]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(47), - I1 => data_int_sync1(47), - I2 => read_done, - I3 => \mem_probe_in[10]__0\(15), - O => dn_activity0186_out - ); -\dn_activity[48]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(48), - I1 => data_int_sync1(48), - I2 => read_done, - I3 => \mem_probe_in[11]__0\(0), - O => dn_activity0190_out - ); -\dn_activity[49]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(49), - I1 => data_int_sync1(49), - I2 => read_done, - I3 => \mem_probe_in[11]__0\(1), - O => dn_activity0194_out - ); -\dn_activity[4]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(4), - I1 => data_int_sync1(4), - I2 => read_done, - I3 => \mem_probe_in[8]__0\(4), - O => dn_activity014_out - ); -\dn_activity[50]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(50), - I1 => data_int_sync1(50), - I2 => read_done, - I3 => \mem_probe_in[11]__0\(2), - O => dn_activity0198_out - ); -\dn_activity[51]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(51), - I1 => data_int_sync1(51), - I2 => read_done, - I3 => \mem_probe_in[11]__0\(3), - O => dn_activity0202_out - ); -\dn_activity[52]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(52), - I1 => data_int_sync1(52), - I2 => read_done, - I3 => \mem_probe_in[11]__0\(4), - O => dn_activity0206_out - ); -\dn_activity[53]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(53), - I1 => data_int_sync1(53), - I2 => read_done, - I3 => \mem_probe_in[11]__0\(5), - O => dn_activity0210_out - ); -\dn_activity[54]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(54), - I1 => data_int_sync1(54), - I2 => read_done, - I3 => \mem_probe_in[11]__0\(6), - O => dn_activity0214_out - ); -\dn_activity[55]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(55), - I1 => data_int_sync1(55), - I2 => read_done, - I3 => \mem_probe_in[11]__0\(7), - O => dn_activity0218_out - ); -\dn_activity[56]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(56), - I1 => data_int_sync1(56), - I2 => read_done, - I3 => \mem_probe_in[11]__0\(8), - O => dn_activity0222_out - ); -\dn_activity[57]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(57), - I1 => data_int_sync1(57), - I2 => read_done, - I3 => \mem_probe_in[11]__0\(9), - O => dn_activity0226_out - ); -\dn_activity[58]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(58), - I1 => data_int_sync1(58), - I2 => read_done, - I3 => \mem_probe_in[11]__0\(10), - O => dn_activity0230_out - ); -\dn_activity[59]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(59), - I1 => data_int_sync1(59), - I2 => read_done, - I3 => \mem_probe_in[11]__0\(11), - O => dn_activity0234_out - ); -\dn_activity[5]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(5), - I1 => data_int_sync1(5), - I2 => read_done, - I3 => \mem_probe_in[8]__0\(5), - O => dn_activity018_out - ); -\dn_activity[60]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(60), - I1 => data_int_sync1(60), - I2 => read_done, - I3 => \mem_probe_in[11]__0\(12), - O => dn_activity0238_out - ); -\dn_activity[61]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(61), - I1 => data_int_sync1(61), - I2 => read_done, - I3 => \mem_probe_in[11]__0\(13), - O => dn_activity0242_out - ); -\dn_activity[62]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(62), - I1 => data_int_sync1(62), - I2 => read_done, - I3 => \mem_probe_in[11]__0\(14), - O => dn_activity0246_out - ); -\dn_activity[63]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(63), - I1 => data_int_sync1(63), - I2 => read_done, - I3 => \mem_probe_in[11]__0\(15), - O => dn_activity0250_out - ); -\dn_activity[6]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(6), - I1 => data_int_sync1(6), - I2 => read_done, - I3 => \mem_probe_in[8]__0\(6), - O => dn_activity022_out - ); -\dn_activity[7]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(7), - I1 => data_int_sync1(7), - I2 => read_done, - I3 => \mem_probe_in[8]__0\(7), - O => dn_activity026_out - ); -\dn_activity[8]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(8), - I1 => data_int_sync1(8), - I2 => read_done, - I3 => \mem_probe_in[8]__0\(8), - O => dn_activity030_out - ); -\dn_activity[9]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync2(9), - I1 => data_int_sync1(9), - I2 => read_done, - I3 => \mem_probe_in[8]__0\(9), - O => dn_activity034_out - ); -\dn_activity_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity0, - Q => \mem_probe_in[8]__0\(0), - R => '0' - ); -\dn_activity_reg[10]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity038_out, - Q => \mem_probe_in[8]__0\(10), - R => '0' - ); -\dn_activity_reg[11]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity042_out, - Q => \mem_probe_in[8]__0\(11), - R => '0' - ); -\dn_activity_reg[12]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity046_out, - Q => \mem_probe_in[8]__0\(12), - R => '0' - ); -\dn_activity_reg[13]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity050_out, - Q => \mem_probe_in[8]__0\(13), - R => '0' - ); -\dn_activity_reg[14]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity054_out, - Q => \mem_probe_in[8]__0\(14), - R => '0' - ); -\dn_activity_reg[15]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity058_out, - Q => \mem_probe_in[8]__0\(15), - R => '0' - ); -\dn_activity_reg[16]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity062_out, - Q => \mem_probe_in[9]__0\(0), - R => '0' - ); -\dn_activity_reg[17]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity066_out, - Q => \mem_probe_in[9]__0\(1), - R => '0' - ); -\dn_activity_reg[18]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity070_out, - Q => \mem_probe_in[9]__0\(2), - R => '0' - ); -\dn_activity_reg[19]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity074_out, - Q => \mem_probe_in[9]__0\(3), - R => '0' - ); -\dn_activity_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity02_out, - Q => \mem_probe_in[8]__0\(1), - R => '0' - ); -\dn_activity_reg[20]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity078_out, - Q => \mem_probe_in[9]__0\(4), - R => '0' - ); -\dn_activity_reg[21]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity082_out, - Q => \mem_probe_in[9]__0\(5), - R => '0' - ); -\dn_activity_reg[22]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity086_out, - Q => \mem_probe_in[9]__0\(6), - R => '0' - ); -\dn_activity_reg[23]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity090_out, - Q => \mem_probe_in[9]__0\(7), - R => '0' - ); -\dn_activity_reg[24]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity094_out, - Q => \mem_probe_in[9]__0\(8), - R => '0' - ); -\dn_activity_reg[25]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity098_out, - Q => \mem_probe_in[9]__0\(9), - R => '0' - ); -\dn_activity_reg[26]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity0102_out, - Q => \mem_probe_in[9]__0\(10), - R => '0' - ); -\dn_activity_reg[27]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity0106_out, - Q => \mem_probe_in[9]__0\(11), - R => '0' - ); -\dn_activity_reg[28]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity0110_out, - Q => \mem_probe_in[9]__0\(12), - R => '0' - ); -\dn_activity_reg[29]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity0114_out, - Q => \mem_probe_in[9]__0\(13), - R => '0' - ); -\dn_activity_reg[2]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity06_out, - Q => \mem_probe_in[8]__0\(2), - R => '0' - ); -\dn_activity_reg[30]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity0118_out, - Q => \mem_probe_in[9]__0\(14), - R => '0' - ); -\dn_activity_reg[31]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity0122_out, - Q => \mem_probe_in[9]__0\(15), - R => '0' - ); -\dn_activity_reg[32]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity0126_out, - Q => \mem_probe_in[10]__0\(0), - R => '0' - ); -\dn_activity_reg[33]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity0130_out, - Q => \mem_probe_in[10]__0\(1), - R => '0' - ); -\dn_activity_reg[34]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity0134_out, - Q => \mem_probe_in[10]__0\(2), - R => '0' - ); -\dn_activity_reg[35]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity0138_out, - Q => \mem_probe_in[10]__0\(3), - R => '0' - ); -\dn_activity_reg[36]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity0142_out, - Q => \mem_probe_in[10]__0\(4), - R => '0' - ); -\dn_activity_reg[37]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity0146_out, - Q => \mem_probe_in[10]__0\(5), - R => '0' - ); -\dn_activity_reg[38]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity0150_out, - Q => \mem_probe_in[10]__0\(6), - R => '0' - ); -\dn_activity_reg[39]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity0154_out, - Q => \mem_probe_in[10]__0\(7), - R => '0' - ); -\dn_activity_reg[3]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity010_out, - Q => \mem_probe_in[8]__0\(3), - R => '0' - ); -\dn_activity_reg[40]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity0158_out, - Q => \mem_probe_in[10]__0\(8), - R => '0' - ); -\dn_activity_reg[41]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity0162_out, - Q => \mem_probe_in[10]__0\(9), - R => '0' - ); -\dn_activity_reg[42]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity0166_out, - Q => \mem_probe_in[10]__0\(10), - R => '0' - ); -\dn_activity_reg[43]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity0170_out, - Q => \mem_probe_in[10]__0\(11), - R => '0' - ); -\dn_activity_reg[44]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity0174_out, - Q => \mem_probe_in[10]__0\(12), - R => '0' - ); -\dn_activity_reg[45]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity0178_out, - Q => \mem_probe_in[10]__0\(13), - R => '0' - ); -\dn_activity_reg[46]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity0182_out, - Q => \mem_probe_in[10]__0\(14), - R => '0' - ); -\dn_activity_reg[47]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity0186_out, - Q => \mem_probe_in[10]__0\(15), - R => '0' - ); -\dn_activity_reg[48]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity0190_out, - Q => \mem_probe_in[11]__0\(0), - R => '0' - ); -\dn_activity_reg[49]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity0194_out, - Q => \mem_probe_in[11]__0\(1), - R => '0' - ); -\dn_activity_reg[4]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity014_out, - Q => \mem_probe_in[8]__0\(4), - R => '0' - ); -\dn_activity_reg[50]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity0198_out, - Q => \mem_probe_in[11]__0\(2), - R => '0' - ); -\dn_activity_reg[51]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity0202_out, - Q => \mem_probe_in[11]__0\(3), - R => '0' - ); -\dn_activity_reg[52]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity0206_out, - Q => \mem_probe_in[11]__0\(4), - R => '0' - ); -\dn_activity_reg[53]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity0210_out, - Q => \mem_probe_in[11]__0\(5), - R => '0' - ); -\dn_activity_reg[54]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity0214_out, - Q => \mem_probe_in[11]__0\(6), - R => '0' - ); -\dn_activity_reg[55]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity0218_out, - Q => \mem_probe_in[11]__0\(7), - R => '0' - ); -\dn_activity_reg[56]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity0222_out, - Q => \mem_probe_in[11]__0\(8), - R => '0' - ); -\dn_activity_reg[57]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity0226_out, - Q => \mem_probe_in[11]__0\(9), - R => '0' - ); -\dn_activity_reg[58]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity0230_out, - Q => \mem_probe_in[11]__0\(10), - R => '0' - ); -\dn_activity_reg[59]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity0234_out, - Q => \mem_probe_in[11]__0\(11), - R => '0' - ); -\dn_activity_reg[5]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity018_out, - Q => \mem_probe_in[8]__0\(5), - R => '0' - ); -\dn_activity_reg[60]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity0238_out, - Q => \mem_probe_in[11]__0\(12), - R => '0' - ); -\dn_activity_reg[61]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity0242_out, - Q => \mem_probe_in[11]__0\(13), - R => '0' - ); -\dn_activity_reg[62]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity0246_out, - Q => \mem_probe_in[11]__0\(14), - R => '0' - ); -\dn_activity_reg[63]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity0250_out, - Q => \mem_probe_in[11]__0\(15), - R => '0' - ); -\dn_activity_reg[6]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity022_out, - Q => \mem_probe_in[8]__0\(6), - R => '0' - ); -\dn_activity_reg[7]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity026_out, - Q => \mem_probe_in[8]__0\(7), - R => '0' - ); -\dn_activity_reg[8]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity030_out, - Q => \mem_probe_in[8]__0\(8), - R => '0' - ); -\dn_activity_reg[9]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => dn_activity034_out, - Q => \mem_probe_in[8]__0\(9), - R => '0' - ); -\probe_in_reg_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(0), - Q => probe_in_reg(0), - R => '0' - ); -\probe_in_reg_reg[10]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(10), - Q => probe_in_reg(10), - R => '0' - ); -\probe_in_reg_reg[11]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(11), - Q => probe_in_reg(11), - R => '0' - ); -\probe_in_reg_reg[12]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(12), - Q => probe_in_reg(12), - R => '0' - ); -\probe_in_reg_reg[13]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(13), - Q => probe_in_reg(13), - R => '0' - ); -\probe_in_reg_reg[14]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(14), - Q => probe_in_reg(14), - R => '0' - ); -\probe_in_reg_reg[15]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(15), - Q => probe_in_reg(15), - R => '0' - ); -\probe_in_reg_reg[16]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(16), - Q => probe_in_reg(16), - R => '0' - ); -\probe_in_reg_reg[17]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(17), - Q => probe_in_reg(17), - R => '0' - ); -\probe_in_reg_reg[18]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(18), - Q => probe_in_reg(18), - R => '0' - ); -\probe_in_reg_reg[19]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(19), - Q => probe_in_reg(19), - R => '0' - ); -\probe_in_reg_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(1), - Q => probe_in_reg(1), - R => '0' - ); -\probe_in_reg_reg[20]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(20), - Q => probe_in_reg(20), - R => '0' - ); -\probe_in_reg_reg[21]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(21), - Q => probe_in_reg(21), - R => '0' - ); -\probe_in_reg_reg[22]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(22), - Q => probe_in_reg(22), - R => '0' - ); -\probe_in_reg_reg[23]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(23), - Q => probe_in_reg(23), - R => '0' - ); -\probe_in_reg_reg[24]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(24), - Q => probe_in_reg(24), - R => '0' - ); -\probe_in_reg_reg[25]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(25), - Q => probe_in_reg(25), - R => '0' - ); -\probe_in_reg_reg[26]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(26), - Q => probe_in_reg(26), - R => '0' - ); -\probe_in_reg_reg[27]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(27), - Q => probe_in_reg(27), - R => '0' - ); -\probe_in_reg_reg[28]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(28), - Q => probe_in_reg(28), - R => '0' - ); -\probe_in_reg_reg[29]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(29), - Q => probe_in_reg(29), - R => '0' - ); -\probe_in_reg_reg[2]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(2), - Q => probe_in_reg(2), - R => '0' - ); -\probe_in_reg_reg[30]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(30), - Q => probe_in_reg(30), - R => '0' - ); -\probe_in_reg_reg[31]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(31), - Q => probe_in_reg(31), - R => '0' - ); -\probe_in_reg_reg[32]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(32), - Q => probe_in_reg(32), - R => '0' - ); -\probe_in_reg_reg[33]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(33), - Q => probe_in_reg(33), - R => '0' - ); -\probe_in_reg_reg[34]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(34), - Q => probe_in_reg(34), - R => '0' - ); -\probe_in_reg_reg[35]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(35), - Q => probe_in_reg(35), - R => '0' - ); -\probe_in_reg_reg[36]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(36), - Q => probe_in_reg(36), - R => '0' - ); -\probe_in_reg_reg[37]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(37), - Q => probe_in_reg(37), - R => '0' - ); -\probe_in_reg_reg[38]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(38), - Q => probe_in_reg(38), - R => '0' - ); -\probe_in_reg_reg[39]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(39), - Q => probe_in_reg(39), - R => '0' - ); -\probe_in_reg_reg[3]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(3), - Q => probe_in_reg(3), - R => '0' - ); -\probe_in_reg_reg[40]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(40), - Q => probe_in_reg(40), - R => '0' - ); -\probe_in_reg_reg[41]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(41), - Q => probe_in_reg(41), - R => '0' - ); -\probe_in_reg_reg[42]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(42), - Q => probe_in_reg(42), - R => '0' - ); -\probe_in_reg_reg[43]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(43), - Q => probe_in_reg(43), - R => '0' - ); -\probe_in_reg_reg[44]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(44), - Q => probe_in_reg(44), - R => '0' - ); -\probe_in_reg_reg[45]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(45), - Q => probe_in_reg(45), - R => '0' - ); -\probe_in_reg_reg[46]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(46), - Q => probe_in_reg(46), - R => '0' - ); -\probe_in_reg_reg[47]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(47), - Q => probe_in_reg(47), - R => '0' - ); -\probe_in_reg_reg[48]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(48), - Q => probe_in_reg(48), - R => '0' - ); -\probe_in_reg_reg[49]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(49), - Q => probe_in_reg(49), - R => '0' - ); -\probe_in_reg_reg[4]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(4), - Q => probe_in_reg(4), - R => '0' - ); -\probe_in_reg_reg[50]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(50), - Q => probe_in_reg(50), - R => '0' - ); -\probe_in_reg_reg[51]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(51), - Q => probe_in_reg(51), - R => '0' - ); -\probe_in_reg_reg[52]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(52), - Q => probe_in_reg(52), - R => '0' - ); -\probe_in_reg_reg[53]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(53), - Q => probe_in_reg(53), - R => '0' - ); -\probe_in_reg_reg[54]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(54), - Q => probe_in_reg(54), - R => '0' - ); -\probe_in_reg_reg[55]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(55), - Q => probe_in_reg(55), - R => '0' - ); -\probe_in_reg_reg[56]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(56), - Q => probe_in_reg(56), - R => '0' - ); -\probe_in_reg_reg[57]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(57), - Q => probe_in_reg(57), - R => '0' - ); -\probe_in_reg_reg[58]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(58), - Q => probe_in_reg(58), - R => '0' - ); -\probe_in_reg_reg[59]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(59), - Q => probe_in_reg(59), - R => '0' - ); -\probe_in_reg_reg[5]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(5), - Q => probe_in_reg(5), - R => '0' - ); -\probe_in_reg_reg[60]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(60), - Q => probe_in_reg(60), - R => '0' - ); -\probe_in_reg_reg[61]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(61), - Q => probe_in_reg(61), - R => '0' - ); -\probe_in_reg_reg[62]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(62), - Q => probe_in_reg(62), - R => '0' - ); -\probe_in_reg_reg[63]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(63), - Q => probe_in_reg(63), - R => '0' - ); -\probe_in_reg_reg[6]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(6), - Q => probe_in_reg(6), - R => '0' - ); -\probe_in_reg_reg[7]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(7), - Q => probe_in_reg(7), - R => '0' - ); -\probe_in_reg_reg[8]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(8), - Q => probe_in_reg(8), - R => '0' - ); -\probe_in_reg_reg[9]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^clk\, - CE => E(0), - D => D(9), - Q => probe_in_reg(9), - R => '0' - ); -rd_en_p1_i_1: unisim.vcomponents.LUT2 - generic map( - INIT => X"2" - ) - port map ( - I0 => s_den_o, - I1 => s_dwe_o, - O => \^xsdb_rd\ - ); -read_done_i_1: unisim.vcomponents.LUT6 - generic map( - INIT => X"0020000000000000" - ) - port map ( - I0 => addr_count(3), - I1 => addr_count(4), - I2 => Read_int, - I3 => addr_count(2), - I4 => addr_count(0), - I5 => addr_count(1), - O => \^addr_count_reg1\ - ); -read_done_reg: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => \^addr_count_reg1\, - Q => read_done, - R => '0' - ); -\up_activity[0]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(0), - I1 => data_int_sync2(0), - I2 => read_done, - I3 => \mem_probe_in[4]__0\(0), - O => up_activity0 - ); -\up_activity[10]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(10), - I1 => data_int_sync2(10), - I2 => read_done, - I3 => \mem_probe_in[4]__0\(10), - O => up_activity0292_out - ); -\up_activity[11]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(11), - I1 => data_int_sync2(11), - I2 => read_done, - I3 => \mem_probe_in[4]__0\(11), - O => up_activity0296_out - ); -\up_activity[12]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(12), - I1 => data_int_sync2(12), - I2 => read_done, - I3 => \mem_probe_in[4]__0\(12), - O => up_activity0300_out - ); -\up_activity[13]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(13), - I1 => data_int_sync2(13), - I2 => read_done, - I3 => \mem_probe_in[4]__0\(13), - O => up_activity0304_out - ); -\up_activity[14]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(14), - I1 => data_int_sync2(14), - I2 => read_done, - I3 => \mem_probe_in[4]__0\(14), - O => up_activity0308_out - ); -\up_activity[15]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(15), - I1 => data_int_sync2(15), - I2 => read_done, - I3 => \mem_probe_in[4]__0\(15), - O => up_activity0312_out - ); -\up_activity[16]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(16), - I1 => data_int_sync2(16), - I2 => read_done, - I3 => \mem_probe_in[5]__0\(0), - O => up_activity0316_out - ); -\up_activity[17]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(17), - I1 => data_int_sync2(17), - I2 => read_done, - I3 => \mem_probe_in[5]__0\(1), - O => up_activity0320_out - ); -\up_activity[18]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(18), - I1 => data_int_sync2(18), - I2 => read_done, - I3 => \mem_probe_in[5]__0\(2), - O => up_activity0324_out - ); -\up_activity[19]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(19), - I1 => data_int_sync2(19), - I2 => read_done, - I3 => \mem_probe_in[5]__0\(3), - O => up_activity0328_out - ); -\up_activity[1]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(1), - I1 => data_int_sync2(1), - I2 => read_done, - I3 => \mem_probe_in[4]__0\(1), - O => up_activity0256_out - ); -\up_activity[20]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(20), - I1 => data_int_sync2(20), - I2 => read_done, - I3 => \mem_probe_in[5]__0\(4), - O => up_activity0332_out - ); -\up_activity[21]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(21), - I1 => data_int_sync2(21), - I2 => read_done, - I3 => \mem_probe_in[5]__0\(5), - O => up_activity0336_out - ); -\up_activity[22]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(22), - I1 => data_int_sync2(22), - I2 => read_done, - I3 => \mem_probe_in[5]__0\(6), - O => up_activity0340_out - ); -\up_activity[23]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(23), - I1 => data_int_sync2(23), - I2 => read_done, - I3 => \mem_probe_in[5]__0\(7), - O => up_activity0344_out - ); -\up_activity[24]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(24), - I1 => data_int_sync2(24), - I2 => read_done, - I3 => \mem_probe_in[5]__0\(8), - O => up_activity0348_out - ); -\up_activity[25]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(25), - I1 => data_int_sync2(25), - I2 => read_done, - I3 => \mem_probe_in[5]__0\(9), - O => up_activity0352_out - ); -\up_activity[26]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(26), - I1 => data_int_sync2(26), - I2 => read_done, - I3 => \mem_probe_in[5]__0\(10), - O => up_activity0356_out - ); -\up_activity[27]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(27), - I1 => data_int_sync2(27), - I2 => read_done, - I3 => \mem_probe_in[5]__0\(11), - O => up_activity0360_out - ); -\up_activity[28]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(28), - I1 => data_int_sync2(28), - I2 => read_done, - I3 => \mem_probe_in[5]__0\(12), - O => up_activity0364_out - ); -\up_activity[29]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(29), - I1 => data_int_sync2(29), - I2 => read_done, - I3 => \mem_probe_in[5]__0\(13), - O => up_activity0368_out - ); -\up_activity[2]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(2), - I1 => data_int_sync2(2), - I2 => read_done, - I3 => \mem_probe_in[4]__0\(2), - O => up_activity0260_out - ); -\up_activity[30]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(30), - I1 => data_int_sync2(30), - I2 => read_done, - I3 => \mem_probe_in[5]__0\(14), - O => up_activity0372_out - ); -\up_activity[31]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(31), - I1 => data_int_sync2(31), - I2 => read_done, - I3 => \mem_probe_in[5]__0\(15), - O => up_activity0376_out - ); -\up_activity[32]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(32), - I1 => data_int_sync2(32), - I2 => read_done, - I3 => \mem_probe_in[6]__0\(0), - O => up_activity0380_out - ); -\up_activity[33]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(33), - I1 => data_int_sync2(33), - I2 => read_done, - I3 => \mem_probe_in[6]__0\(1), - O => up_activity0384_out - ); -\up_activity[34]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(34), - I1 => data_int_sync2(34), - I2 => read_done, - I3 => \mem_probe_in[6]__0\(2), - O => up_activity0388_out - ); -\up_activity[35]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(35), - I1 => data_int_sync2(35), - I2 => read_done, - I3 => \mem_probe_in[6]__0\(3), - O => up_activity0392_out - ); -\up_activity[36]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(36), - I1 => data_int_sync2(36), - I2 => read_done, - I3 => \mem_probe_in[6]__0\(4), - O => up_activity0396_out - ); -\up_activity[37]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(37), - I1 => data_int_sync2(37), - I2 => read_done, - I3 => \mem_probe_in[6]__0\(5), - O => up_activity0400_out - ); -\up_activity[38]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(38), - I1 => data_int_sync2(38), - I2 => read_done, - I3 => \mem_probe_in[6]__0\(6), - O => up_activity0404_out - ); -\up_activity[39]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(39), - I1 => data_int_sync2(39), - I2 => read_done, - I3 => \mem_probe_in[6]__0\(7), - O => up_activity0408_out - ); -\up_activity[3]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(3), - I1 => data_int_sync2(3), - I2 => read_done, - I3 => \mem_probe_in[4]__0\(3), - O => up_activity0264_out - ); -\up_activity[40]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(40), - I1 => data_int_sync2(40), - I2 => read_done, - I3 => \mem_probe_in[6]__0\(8), - O => up_activity0412_out - ); -\up_activity[41]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(41), - I1 => data_int_sync2(41), - I2 => read_done, - I3 => \mem_probe_in[6]__0\(9), - O => up_activity0416_out - ); -\up_activity[42]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(42), - I1 => data_int_sync2(42), - I2 => read_done, - I3 => \mem_probe_in[6]__0\(10), - O => up_activity0420_out - ); -\up_activity[43]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(43), - I1 => data_int_sync2(43), - I2 => read_done, - I3 => \mem_probe_in[6]__0\(11), - O => up_activity0424_out - ); -\up_activity[44]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(44), - I1 => data_int_sync2(44), - I2 => read_done, - I3 => \mem_probe_in[6]__0\(12), - O => up_activity0428_out - ); -\up_activity[45]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(45), - I1 => data_int_sync2(45), - I2 => read_done, - I3 => \mem_probe_in[6]__0\(13), - O => up_activity0432_out - ); -\up_activity[46]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(46), - I1 => data_int_sync2(46), - I2 => read_done, - I3 => \mem_probe_in[6]__0\(14), - O => up_activity0436_out - ); -\up_activity[47]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(47), - I1 => data_int_sync2(47), - I2 => read_done, - I3 => \mem_probe_in[6]__0\(15), - O => up_activity0440_out - ); -\up_activity[48]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(48), - I1 => data_int_sync2(48), - I2 => read_done, - I3 => \mem_probe_in[7]__0\(0), - O => up_activity0444_out - ); -\up_activity[49]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(49), - I1 => data_int_sync2(49), - I2 => read_done, - I3 => \mem_probe_in[7]__0\(1), - O => up_activity0448_out - ); -\up_activity[4]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(4), - I1 => data_int_sync2(4), - I2 => read_done, - I3 => \mem_probe_in[4]__0\(4), - O => up_activity0268_out - ); -\up_activity[50]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(50), - I1 => data_int_sync2(50), - I2 => read_done, - I3 => \mem_probe_in[7]__0\(2), - O => up_activity0452_out - ); -\up_activity[51]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(51), - I1 => data_int_sync2(51), - I2 => read_done, - I3 => \mem_probe_in[7]__0\(3), - O => up_activity0456_out - ); -\up_activity[52]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(52), - I1 => data_int_sync2(52), - I2 => read_done, - I3 => \mem_probe_in[7]__0\(4), - O => up_activity0460_out - ); -\up_activity[53]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(53), - I1 => data_int_sync2(53), - I2 => read_done, - I3 => \mem_probe_in[7]__0\(5), - O => up_activity0464_out - ); -\up_activity[54]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(54), - I1 => data_int_sync2(54), - I2 => read_done, - I3 => \mem_probe_in[7]__0\(6), - O => up_activity0468_out - ); -\up_activity[55]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(55), - I1 => data_int_sync2(55), - I2 => read_done, - I3 => \mem_probe_in[7]__0\(7), - O => up_activity0472_out - ); -\up_activity[56]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(56), - I1 => data_int_sync2(56), - I2 => read_done, - I3 => \mem_probe_in[7]__0\(8), - O => up_activity0476_out - ); -\up_activity[57]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(57), - I1 => data_int_sync2(57), - I2 => read_done, - I3 => \mem_probe_in[7]__0\(9), - O => up_activity0480_out - ); -\up_activity[58]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(58), - I1 => data_int_sync2(58), - I2 => read_done, - I3 => \mem_probe_in[7]__0\(10), - O => up_activity0484_out - ); -\up_activity[59]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(59), - I1 => data_int_sync2(59), - I2 => read_done, - I3 => \mem_probe_in[7]__0\(11), - O => up_activity0488_out - ); -\up_activity[5]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(5), - I1 => data_int_sync2(5), - I2 => read_done, - I3 => \mem_probe_in[4]__0\(5), - O => up_activity0272_out - ); -\up_activity[60]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(60), - I1 => data_int_sync2(60), - I2 => read_done, - I3 => \mem_probe_in[7]__0\(12), - O => up_activity0492_out - ); -\up_activity[61]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(61), - I1 => data_int_sync2(61), - I2 => read_done, - I3 => \mem_probe_in[7]__0\(13), - O => up_activity0496_out - ); -\up_activity[62]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(62), - I1 => data_int_sync2(62), - I2 => read_done, - I3 => \mem_probe_in[7]__0\(14), - O => up_activity0500_out - ); -\up_activity[63]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(63), - I1 => data_int_sync2(63), - I2 => read_done, - I3 => \mem_probe_in[7]__0\(15), - O => up_activity0504_out - ); -\up_activity[6]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(6), - I1 => data_int_sync2(6), - I2 => read_done, - I3 => \mem_probe_in[4]__0\(6), - O => up_activity0276_out - ); -\up_activity[7]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(7), - I1 => data_int_sync2(7), - I2 => read_done, - I3 => \mem_probe_in[4]__0\(7), - O => up_activity0280_out - ); -\up_activity[8]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(8), - I1 => data_int_sync2(8), - I2 => read_done, - I3 => \mem_probe_in[4]__0\(8), - O => up_activity0284_out - ); -\up_activity[9]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0F02" - ) - port map ( - I0 => data_int_sync1(9), - I1 => data_int_sync2(9), - I2 => read_done, - I3 => \mem_probe_in[4]__0\(9), - O => up_activity0288_out - ); -\up_activity_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0, - Q => \mem_probe_in[4]__0\(0), - R => '0' - ); -\up_activity_reg[10]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0292_out, - Q => \mem_probe_in[4]__0\(10), - R => '0' - ); -\up_activity_reg[11]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0296_out, - Q => \mem_probe_in[4]__0\(11), - R => '0' - ); -\up_activity_reg[12]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0300_out, - Q => \mem_probe_in[4]__0\(12), - R => '0' - ); -\up_activity_reg[13]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0304_out, - Q => \mem_probe_in[4]__0\(13), - R => '0' - ); -\up_activity_reg[14]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0308_out, - Q => \mem_probe_in[4]__0\(14), - R => '0' - ); -\up_activity_reg[15]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0312_out, - Q => \mem_probe_in[4]__0\(15), - R => '0' - ); -\up_activity_reg[16]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0316_out, - Q => \mem_probe_in[5]__0\(0), - R => '0' - ); -\up_activity_reg[17]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0320_out, - Q => \mem_probe_in[5]__0\(1), - R => '0' - ); -\up_activity_reg[18]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0324_out, - Q => \mem_probe_in[5]__0\(2), - R => '0' - ); -\up_activity_reg[19]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0328_out, - Q => \mem_probe_in[5]__0\(3), - R => '0' - ); -\up_activity_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0256_out, - Q => \mem_probe_in[4]__0\(1), - R => '0' - ); -\up_activity_reg[20]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0332_out, - Q => \mem_probe_in[5]__0\(4), - R => '0' - ); -\up_activity_reg[21]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0336_out, - Q => \mem_probe_in[5]__0\(5), - R => '0' - ); -\up_activity_reg[22]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0340_out, - Q => \mem_probe_in[5]__0\(6), - R => '0' - ); -\up_activity_reg[23]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0344_out, - Q => \mem_probe_in[5]__0\(7), - R => '0' - ); -\up_activity_reg[24]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0348_out, - Q => \mem_probe_in[5]__0\(8), - R => '0' - ); -\up_activity_reg[25]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0352_out, - Q => \mem_probe_in[5]__0\(9), - R => '0' - ); -\up_activity_reg[26]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0356_out, - Q => \mem_probe_in[5]__0\(10), - R => '0' - ); -\up_activity_reg[27]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0360_out, - Q => \mem_probe_in[5]__0\(11), - R => '0' - ); -\up_activity_reg[28]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0364_out, - Q => \mem_probe_in[5]__0\(12), - R => '0' - ); -\up_activity_reg[29]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0368_out, - Q => \mem_probe_in[5]__0\(13), - R => '0' - ); -\up_activity_reg[2]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0260_out, - Q => \mem_probe_in[4]__0\(2), - R => '0' - ); -\up_activity_reg[30]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0372_out, - Q => \mem_probe_in[5]__0\(14), - R => '0' - ); -\up_activity_reg[31]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0376_out, - Q => \mem_probe_in[5]__0\(15), - R => '0' - ); -\up_activity_reg[32]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0380_out, - Q => \mem_probe_in[6]__0\(0), - R => '0' - ); -\up_activity_reg[33]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0384_out, - Q => \mem_probe_in[6]__0\(1), - R => '0' - ); -\up_activity_reg[34]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0388_out, - Q => \mem_probe_in[6]__0\(2), - R => '0' - ); -\up_activity_reg[35]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0392_out, - Q => \mem_probe_in[6]__0\(3), - R => '0' - ); -\up_activity_reg[36]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0396_out, - Q => \mem_probe_in[6]__0\(4), - R => '0' - ); -\up_activity_reg[37]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0400_out, - Q => \mem_probe_in[6]__0\(5), - R => '0' - ); -\up_activity_reg[38]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0404_out, - Q => \mem_probe_in[6]__0\(6), - R => '0' - ); -\up_activity_reg[39]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0408_out, - Q => \mem_probe_in[6]__0\(7), - R => '0' - ); -\up_activity_reg[3]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0264_out, - Q => \mem_probe_in[4]__0\(3), - R => '0' - ); -\up_activity_reg[40]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0412_out, - Q => \mem_probe_in[6]__0\(8), - R => '0' - ); -\up_activity_reg[41]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0416_out, - Q => \mem_probe_in[6]__0\(9), - R => '0' - ); -\up_activity_reg[42]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0420_out, - Q => \mem_probe_in[6]__0\(10), - R => '0' - ); -\up_activity_reg[43]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0424_out, - Q => \mem_probe_in[6]__0\(11), - R => '0' - ); -\up_activity_reg[44]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0428_out, - Q => \mem_probe_in[6]__0\(12), - R => '0' - ); -\up_activity_reg[45]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0432_out, - Q => \mem_probe_in[6]__0\(13), - R => '0' - ); -\up_activity_reg[46]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0436_out, - Q => \mem_probe_in[6]__0\(14), - R => '0' - ); -\up_activity_reg[47]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0440_out, - Q => \mem_probe_in[6]__0\(15), - R => '0' - ); -\up_activity_reg[48]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0444_out, - Q => \mem_probe_in[7]__0\(0), - R => '0' - ); -\up_activity_reg[49]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0448_out, - Q => \mem_probe_in[7]__0\(1), - R => '0' - ); -\up_activity_reg[4]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0268_out, - Q => \mem_probe_in[4]__0\(4), - R => '0' - ); -\up_activity_reg[50]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0452_out, - Q => \mem_probe_in[7]__0\(2), - R => '0' - ); -\up_activity_reg[51]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0456_out, - Q => \mem_probe_in[7]__0\(3), - R => '0' - ); -\up_activity_reg[52]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0460_out, - Q => \mem_probe_in[7]__0\(4), - R => '0' - ); -\up_activity_reg[53]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0464_out, - Q => \mem_probe_in[7]__0\(5), - R => '0' - ); -\up_activity_reg[54]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0468_out, - Q => \mem_probe_in[7]__0\(6), - R => '0' - ); -\up_activity_reg[55]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0472_out, - Q => \mem_probe_in[7]__0\(7), - R => '0' - ); -\up_activity_reg[56]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0476_out, - Q => \mem_probe_in[7]__0\(8), - R => '0' - ); -\up_activity_reg[57]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0480_out, - Q => \mem_probe_in[7]__0\(9), - R => '0' - ); -\up_activity_reg[58]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0484_out, - Q => \mem_probe_in[7]__0\(10), - R => '0' - ); -\up_activity_reg[59]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0488_out, - Q => \mem_probe_in[7]__0\(11), - R => '0' - ); -\up_activity_reg[5]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0272_out, - Q => \mem_probe_in[4]__0\(5), - R => '0' - ); -\up_activity_reg[60]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0492_out, - Q => \mem_probe_in[7]__0\(12), - R => '0' - ); -\up_activity_reg[61]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0496_out, - Q => \mem_probe_in[7]__0\(13), - R => '0' - ); -\up_activity_reg[62]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0500_out, - Q => \mem_probe_in[7]__0\(14), - R => '0' - ); -\up_activity_reg[63]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0504_out, - Q => \mem_probe_in[7]__0\(15), - R => '0' - ); -\up_activity_reg[6]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0276_out, - Q => \mem_probe_in[4]__0\(6), - R => '0' - ); -\up_activity_reg[7]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0280_out, - Q => \mem_probe_in[4]__0\(7), - R => '0' - ); -\up_activity_reg[8]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0284_out, - Q => \mem_probe_in[4]__0\(8), - R => '0' - ); -\up_activity_reg[9]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => CLK, - CE => '1', - D => up_activity0288_out, - Q => \mem_probe_in[4]__0\(9), - R => '0' - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity vio_0_vio_v3_0_19_probe_out_one is - port ( - probe_out0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); - \Bus_Data_out_int_reg[15]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); - SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - s_daddr_o : in STD_LOGIC_VECTOR ( 10 downto 0 ); - \addr_count_reg[0]_0\ : in STD_LOGIC; - s_den_o : in STD_LOGIC; - s_dwe_o : in STD_LOGIC; - internal_cnt_rst : in STD_LOGIC; - CLK : in STD_LOGIC; - E : in STD_LOGIC_VECTOR ( 0 to 0 ); - Q : in STD_LOGIC_VECTOR ( 15 downto 0 ); - \Probe_out_reg[31]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - \^clk\ : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of vio_0_vio_v3_0_19_probe_out_one : entity is "vio_v3_0_19_probe_out_one"; -end vio_0_vio_v3_0_19_probe_out_one; - -architecture STRUCTURE of vio_0_vio_v3_0_19_probe_out_one is - signal \Bus_Data_out_int[0]_i_1_n_0\ : STD_LOGIC; - signal \Bus_Data_out_int[10]_i_1_n_0\ : STD_LOGIC; - signal \Bus_Data_out_int[11]_i_1_n_0\ : STD_LOGIC; - signal \Bus_Data_out_int[12]_i_1_n_0\ : STD_LOGIC; - signal \Bus_Data_out_int[13]_i_1_n_0\ : STD_LOGIC; - signal \Bus_Data_out_int[14]_i_1_n_0\ : STD_LOGIC; - signal \Bus_Data_out_int[15]_i_1_n_0\ : STD_LOGIC; - signal \Bus_Data_out_int[1]_i_1_n_0\ : STD_LOGIC; - signal \Bus_Data_out_int[2]_i_1_n_0\ : STD_LOGIC; - signal \Bus_Data_out_int[3]_i_1_n_0\ : STD_LOGIC; - signal \Bus_Data_out_int[4]_i_1_n_0\ : STD_LOGIC; - signal \Bus_Data_out_int[5]_i_1_n_0\ : STD_LOGIC; - signal \Bus_Data_out_int[6]_i_1_n_0\ : STD_LOGIC; - signal \Bus_Data_out_int[7]_i_1_n_0\ : STD_LOGIC; - signal \Bus_Data_out_int[8]_i_1_n_0\ : STD_LOGIC; - signal \Bus_Data_out_int[9]_i_1_n_0\ : STD_LOGIC; - signal addr_count : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal \addr_count[0]_i_1_n_0\ : STD_LOGIC; - signal \addr_count[1]_i_1_n_0\ : STD_LOGIC; - signal \addr_count[1]_i_3_n_0\ : STD_LOGIC; - signal \addr_count[1]_i_4_n_0\ : STD_LOGIC; - signal \mem_probe_out[0]\ : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal rd_probe_out : STD_LOGIC; - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \Bus_Data_out_int[0]_i_1\ : label is "soft_lutpair25"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[10]_i_1\ : label is "soft_lutpair20"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[11]_i_1\ : label is "soft_lutpair20"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[12]_i_1\ : label is "soft_lutpair19"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[13]_i_1\ : label is "soft_lutpair19"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[14]_i_1\ : label is "soft_lutpair18"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[15]_i_1\ : label is "soft_lutpair18"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[1]_i_1\ : label is "soft_lutpair25"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[2]_i_1\ : label is "soft_lutpair24"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[3]_i_1\ : label is "soft_lutpair24"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[4]_i_1\ : label is "soft_lutpair23"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[5]_i_1\ : label is "soft_lutpair23"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[6]_i_1\ : label is "soft_lutpair22"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[7]_i_1\ : label is "soft_lutpair22"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[8]_i_1\ : label is "soft_lutpair21"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[9]_i_1\ : label is "soft_lutpair21"; - attribute DONT_TOUCH : boolean; - attribute DONT_TOUCH of \Probe_out_reg[0]\ : label is std.standard.true; - attribute KEEP : string; - attribute KEEP of \Probe_out_reg[0]\ : label is "yes"; - attribute DONT_TOUCH of \Probe_out_reg[10]\ : label is std.standard.true; - attribute KEEP of \Probe_out_reg[10]\ : label is "yes"; - attribute DONT_TOUCH of \Probe_out_reg[11]\ : label is std.standard.true; - attribute KEEP of \Probe_out_reg[11]\ : label is "yes"; - attribute DONT_TOUCH of \Probe_out_reg[12]\ : label is std.standard.true; - attribute KEEP of \Probe_out_reg[12]\ : label is "yes"; - attribute DONT_TOUCH of \Probe_out_reg[13]\ : label is std.standard.true; - attribute KEEP of \Probe_out_reg[13]\ : label is "yes"; - attribute DONT_TOUCH of \Probe_out_reg[14]\ : label is std.standard.true; - attribute KEEP of \Probe_out_reg[14]\ : label is "yes"; - attribute DONT_TOUCH of \Probe_out_reg[15]\ : label is std.standard.true; - attribute KEEP of \Probe_out_reg[15]\ : label is "yes"; - attribute DONT_TOUCH of \Probe_out_reg[16]\ : label is std.standard.true; - attribute KEEP of \Probe_out_reg[16]\ : label is "yes"; - attribute DONT_TOUCH of \Probe_out_reg[17]\ : label is std.standard.true; - attribute KEEP of \Probe_out_reg[17]\ : label is "yes"; - attribute DONT_TOUCH of \Probe_out_reg[18]\ : label is std.standard.true; - attribute KEEP of \Probe_out_reg[18]\ : label is "yes"; - attribute DONT_TOUCH of \Probe_out_reg[19]\ : label is std.standard.true; - attribute KEEP of \Probe_out_reg[19]\ : label is "yes"; - attribute DONT_TOUCH of \Probe_out_reg[1]\ : label is std.standard.true; - attribute KEEP of \Probe_out_reg[1]\ : label is "yes"; - attribute DONT_TOUCH of \Probe_out_reg[20]\ : label is std.standard.true; - attribute KEEP of \Probe_out_reg[20]\ : label is "yes"; - attribute DONT_TOUCH of \Probe_out_reg[21]\ : label is std.standard.true; - attribute KEEP of \Probe_out_reg[21]\ : label is "yes"; - attribute DONT_TOUCH of \Probe_out_reg[22]\ : label is std.standard.true; - attribute KEEP of \Probe_out_reg[22]\ : label is "yes"; - attribute DONT_TOUCH of \Probe_out_reg[23]\ : label is std.standard.true; - attribute KEEP of \Probe_out_reg[23]\ : label is "yes"; - attribute DONT_TOUCH of \Probe_out_reg[24]\ : label is std.standard.true; - attribute KEEP of \Probe_out_reg[24]\ : label is "yes"; - attribute DONT_TOUCH of \Probe_out_reg[25]\ : label is std.standard.true; - attribute KEEP of \Probe_out_reg[25]\ : label is "yes"; - attribute DONT_TOUCH of \Probe_out_reg[26]\ : label is std.standard.true; - attribute KEEP of \Probe_out_reg[26]\ : label is "yes"; - attribute DONT_TOUCH of \Probe_out_reg[27]\ : label is std.standard.true; - attribute KEEP of \Probe_out_reg[27]\ : label is "yes"; - attribute DONT_TOUCH of \Probe_out_reg[28]\ : label is std.standard.true; - attribute KEEP of \Probe_out_reg[28]\ : label is "yes"; - attribute DONT_TOUCH of \Probe_out_reg[29]\ : label is std.standard.true; - attribute KEEP of \Probe_out_reg[29]\ : label is "yes"; - attribute DONT_TOUCH of \Probe_out_reg[2]\ : label is std.standard.true; - attribute KEEP of \Probe_out_reg[2]\ : label is "yes"; - attribute DONT_TOUCH of \Probe_out_reg[30]\ : label is std.standard.true; - attribute KEEP of \Probe_out_reg[30]\ : label is "yes"; - attribute DONT_TOUCH of \Probe_out_reg[31]\ : label is std.standard.true; - attribute KEEP of \Probe_out_reg[31]\ : label is "yes"; - attribute DONT_TOUCH of \Probe_out_reg[3]\ : label is std.standard.true; - attribute KEEP of \Probe_out_reg[3]\ : label is "yes"; - attribute DONT_TOUCH of \Probe_out_reg[4]\ : label is std.standard.true; - attribute KEEP of \Probe_out_reg[4]\ : label is "yes"; - attribute DONT_TOUCH of \Probe_out_reg[5]\ : label is std.standard.true; - attribute KEEP of \Probe_out_reg[5]\ : label is "yes"; - attribute DONT_TOUCH of \Probe_out_reg[6]\ : label is std.standard.true; - attribute KEEP of \Probe_out_reg[6]\ : label is "yes"; - attribute DONT_TOUCH of \Probe_out_reg[7]\ : label is std.standard.true; - attribute KEEP of \Probe_out_reg[7]\ : label is "yes"; - attribute DONT_TOUCH of \Probe_out_reg[8]\ : label is std.standard.true; - attribute KEEP of \Probe_out_reg[8]\ : label is "yes"; - attribute DONT_TOUCH of \Probe_out_reg[9]\ : label is std.standard.true; - attribute KEEP of \Probe_out_reg[9]\ : label is "yes"; - attribute MAX_FANOUT : string; - attribute MAX_FANOUT of \addr_count_reg[0]\ : label is "200"; - attribute MAX_FANOUT of \addr_count_reg[1]\ : label is "200"; -begin -\Bus_Data_out_int[0]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => \mem_probe_out[0]\(16), - I1 => addr_count(0), - I2 => \mem_probe_out[0]\(0), - O => \Bus_Data_out_int[0]_i_1_n_0\ - ); -\Bus_Data_out_int[10]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => \mem_probe_out[0]\(26), - I1 => addr_count(0), - I2 => \mem_probe_out[0]\(10), - O => \Bus_Data_out_int[10]_i_1_n_0\ - ); -\Bus_Data_out_int[11]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => \mem_probe_out[0]\(27), - I1 => addr_count(0), - I2 => \mem_probe_out[0]\(11), - O => \Bus_Data_out_int[11]_i_1_n_0\ - ); -\Bus_Data_out_int[12]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => \mem_probe_out[0]\(28), - I1 => addr_count(0), - I2 => \mem_probe_out[0]\(12), - O => \Bus_Data_out_int[12]_i_1_n_0\ - ); -\Bus_Data_out_int[13]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => \mem_probe_out[0]\(29), - I1 => addr_count(0), - I2 => \mem_probe_out[0]\(13), - O => \Bus_Data_out_int[13]_i_1_n_0\ - ); -\Bus_Data_out_int[14]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => \mem_probe_out[0]\(30), - I1 => addr_count(0), - I2 => \mem_probe_out[0]\(14), - O => \Bus_Data_out_int[14]_i_1_n_0\ - ); -\Bus_Data_out_int[15]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => \mem_probe_out[0]\(31), - I1 => addr_count(0), - I2 => \mem_probe_out[0]\(15), - O => \Bus_Data_out_int[15]_i_1_n_0\ - ); -\Bus_Data_out_int[1]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => \mem_probe_out[0]\(17), - I1 => addr_count(0), - I2 => \mem_probe_out[0]\(1), - O => \Bus_Data_out_int[1]_i_1_n_0\ - ); -\Bus_Data_out_int[2]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => \mem_probe_out[0]\(18), - I1 => addr_count(0), - I2 => \mem_probe_out[0]\(2), - O => \Bus_Data_out_int[2]_i_1_n_0\ - ); -\Bus_Data_out_int[3]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => \mem_probe_out[0]\(19), - I1 => addr_count(0), - I2 => \mem_probe_out[0]\(3), - O => \Bus_Data_out_int[3]_i_1_n_0\ - ); -\Bus_Data_out_int[4]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => \mem_probe_out[0]\(20), - I1 => addr_count(0), - I2 => \mem_probe_out[0]\(4), - O => \Bus_Data_out_int[4]_i_1_n_0\ - ); -\Bus_Data_out_int[5]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => \mem_probe_out[0]\(21), - I1 => addr_count(0), - I2 => \mem_probe_out[0]\(5), - O => \Bus_Data_out_int[5]_i_1_n_0\ - ); -\Bus_Data_out_int[6]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => \mem_probe_out[0]\(22), - I1 => addr_count(0), - I2 => \mem_probe_out[0]\(6), - O => \Bus_Data_out_int[6]_i_1_n_0\ - ); -\Bus_Data_out_int[7]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => \mem_probe_out[0]\(23), - I1 => addr_count(0), - I2 => \mem_probe_out[0]\(7), - O => \Bus_Data_out_int[7]_i_1_n_0\ - ); -\Bus_Data_out_int[8]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => \mem_probe_out[0]\(24), - I1 => addr_count(0), - I2 => \mem_probe_out[0]\(8), - O => \Bus_Data_out_int[8]_i_1_n_0\ - ); -\Bus_Data_out_int[9]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => \mem_probe_out[0]\(25), - I1 => addr_count(0), - I2 => \mem_probe_out[0]\(9), - O => \Bus_Data_out_int[9]_i_1_n_0\ - ); -\Bus_Data_out_int_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => \Bus_Data_out_int[0]_i_1_n_0\, - Q => \Bus_Data_out_int_reg[15]_0\(0), - R => '0' - ); -\Bus_Data_out_int_reg[10]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => \Bus_Data_out_int[10]_i_1_n_0\, - Q => \Bus_Data_out_int_reg[15]_0\(10), - R => '0' - ); -\Bus_Data_out_int_reg[11]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => \Bus_Data_out_int[11]_i_1_n_0\, - Q => \Bus_Data_out_int_reg[15]_0\(11), - R => '0' - ); -\Bus_Data_out_int_reg[12]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => \Bus_Data_out_int[12]_i_1_n_0\, - Q => \Bus_Data_out_int_reg[15]_0\(12), - R => '0' - ); -\Bus_Data_out_int_reg[13]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => \Bus_Data_out_int[13]_i_1_n_0\, - Q => \Bus_Data_out_int_reg[15]_0\(13), - R => '0' - ); -\Bus_Data_out_int_reg[14]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => \Bus_Data_out_int[14]_i_1_n_0\, - Q => \Bus_Data_out_int_reg[15]_0\(14), - R => '0' - ); -\Bus_Data_out_int_reg[15]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => \Bus_Data_out_int[15]_i_1_n_0\, - Q => \Bus_Data_out_int_reg[15]_0\(15), - R => '0' - ); -\Bus_Data_out_int_reg[1]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => \Bus_Data_out_int[1]_i_1_n_0\, - Q => \Bus_Data_out_int_reg[15]_0\(1), - R => '0' - ); -\Bus_Data_out_int_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => \Bus_Data_out_int[2]_i_1_n_0\, - Q => \Bus_Data_out_int_reg[15]_0\(2), - R => '0' - ); -\Bus_Data_out_int_reg[3]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => \Bus_Data_out_int[3]_i_1_n_0\, - Q => \Bus_Data_out_int_reg[15]_0\(3), - R => '0' - ); -\Bus_Data_out_int_reg[4]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => \Bus_Data_out_int[4]_i_1_n_0\, - Q => \Bus_Data_out_int_reg[15]_0\(4), - R => '0' - ); -\Bus_Data_out_int_reg[5]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => \Bus_Data_out_int[5]_i_1_n_0\, - Q => \Bus_Data_out_int_reg[15]_0\(5), - R => '0' - ); -\Bus_Data_out_int_reg[6]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => \Bus_Data_out_int[6]_i_1_n_0\, - Q => \Bus_Data_out_int_reg[15]_0\(6), - R => '0' - ); -\Bus_Data_out_int_reg[7]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => \Bus_Data_out_int[7]_i_1_n_0\, - Q => \Bus_Data_out_int_reg[15]_0\(7), - R => '0' - ); -\Bus_Data_out_int_reg[8]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => \Bus_Data_out_int[8]_i_1_n_0\, - Q => \Bus_Data_out_int_reg[15]_0\(8), - R => '0' - ); -\Bus_Data_out_int_reg[9]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => \Bus_Data_out_int[9]_i_1_n_0\, - Q => \Bus_Data_out_int_reg[15]_0\(9), - R => '0' - ); -\LOOP_I[1].data_int_reg[16]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => E(0), - D => \mem_probe_out[0]\(0), - Q => \mem_probe_out[0]\(16), - R => SR(0) - ); -\LOOP_I[1].data_int_reg[17]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => E(0), - D => \mem_probe_out[0]\(1), - Q => \mem_probe_out[0]\(17), - R => SR(0) - ); -\LOOP_I[1].data_int_reg[18]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => E(0), - D => \mem_probe_out[0]\(2), - Q => \mem_probe_out[0]\(18), - R => SR(0) - ); -\LOOP_I[1].data_int_reg[19]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => E(0), - D => \mem_probe_out[0]\(3), - Q => \mem_probe_out[0]\(19), - R => SR(0) - ); -\LOOP_I[1].data_int_reg[20]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => E(0), - D => \mem_probe_out[0]\(4), - Q => \mem_probe_out[0]\(20), - R => SR(0) - ); -\LOOP_I[1].data_int_reg[21]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => E(0), - D => \mem_probe_out[0]\(5), - Q => \mem_probe_out[0]\(21), - R => SR(0) - ); -\LOOP_I[1].data_int_reg[22]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => E(0), - D => \mem_probe_out[0]\(6), - Q => \mem_probe_out[0]\(22), - R => SR(0) - ); -\LOOP_I[1].data_int_reg[23]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => E(0), - D => \mem_probe_out[0]\(7), - Q => \mem_probe_out[0]\(23), - R => SR(0) - ); -\LOOP_I[1].data_int_reg[24]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => E(0), - D => \mem_probe_out[0]\(8), - Q => \mem_probe_out[0]\(24), - R => SR(0) - ); -\LOOP_I[1].data_int_reg[25]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => E(0), - D => \mem_probe_out[0]\(9), - Q => \mem_probe_out[0]\(25), - R => SR(0) - ); -\LOOP_I[1].data_int_reg[26]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => E(0), - D => \mem_probe_out[0]\(10), - Q => \mem_probe_out[0]\(26), - R => SR(0) - ); -\LOOP_I[1].data_int_reg[27]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => E(0), - D => \mem_probe_out[0]\(11), - Q => \mem_probe_out[0]\(27), - R => SR(0) - ); -\LOOP_I[1].data_int_reg[28]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => E(0), - D => \mem_probe_out[0]\(12), - Q => \mem_probe_out[0]\(28), - R => SR(0) - ); -\LOOP_I[1].data_int_reg[29]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => E(0), - D => \mem_probe_out[0]\(13), - Q => \mem_probe_out[0]\(29), - R => SR(0) - ); -\LOOP_I[1].data_int_reg[30]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => E(0), - D => \mem_probe_out[0]\(14), - Q => \mem_probe_out[0]\(30), - R => SR(0) - ); -\LOOP_I[1].data_int_reg[31]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => E(0), - D => \mem_probe_out[0]\(15), - Q => \mem_probe_out[0]\(31), - R => SR(0) - ); -\Probe_out_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => \^clk\, - CE => \Probe_out_reg[31]_0\(0), - D => \mem_probe_out[0]\(0), - Q => probe_out0(0), - R => SR(0) - ); -\Probe_out_reg[10]\: unisim.vcomponents.FDRE - port map ( - C => \^clk\, - CE => \Probe_out_reg[31]_0\(0), - D => \mem_probe_out[0]\(10), - Q => probe_out0(10), - R => SR(0) - ); -\Probe_out_reg[11]\: unisim.vcomponents.FDRE - port map ( - C => \^clk\, - CE => \Probe_out_reg[31]_0\(0), - D => \mem_probe_out[0]\(11), - Q => probe_out0(11), - R => SR(0) - ); -\Probe_out_reg[12]\: unisim.vcomponents.FDRE - port map ( - C => \^clk\, - CE => \Probe_out_reg[31]_0\(0), - D => \mem_probe_out[0]\(12), - Q => probe_out0(12), - R => SR(0) - ); -\Probe_out_reg[13]\: unisim.vcomponents.FDRE - port map ( - C => \^clk\, - CE => \Probe_out_reg[31]_0\(0), - D => \mem_probe_out[0]\(13), - Q => probe_out0(13), - R => SR(0) - ); -\Probe_out_reg[14]\: unisim.vcomponents.FDRE - port map ( - C => \^clk\, - CE => \Probe_out_reg[31]_0\(0), - D => \mem_probe_out[0]\(14), - Q => probe_out0(14), - R => SR(0) - ); -\Probe_out_reg[15]\: unisim.vcomponents.FDRE - port map ( - C => \^clk\, - CE => \Probe_out_reg[31]_0\(0), - D => \mem_probe_out[0]\(15), - Q => probe_out0(15), - R => SR(0) - ); -\Probe_out_reg[16]\: unisim.vcomponents.FDRE - port map ( - C => \^clk\, - CE => \Probe_out_reg[31]_0\(0), - D => \mem_probe_out[0]\(16), - Q => probe_out0(16), - R => SR(0) - ); -\Probe_out_reg[17]\: unisim.vcomponents.FDRE - port map ( - C => \^clk\, - CE => \Probe_out_reg[31]_0\(0), - D => \mem_probe_out[0]\(17), - Q => probe_out0(17), - R => SR(0) - ); -\Probe_out_reg[18]\: unisim.vcomponents.FDRE - port map ( - C => \^clk\, - CE => \Probe_out_reg[31]_0\(0), - D => \mem_probe_out[0]\(18), - Q => probe_out0(18), - R => SR(0) - ); -\Probe_out_reg[19]\: unisim.vcomponents.FDRE - port map ( - C => \^clk\, - CE => \Probe_out_reg[31]_0\(0), - D => \mem_probe_out[0]\(19), - Q => probe_out0(19), - R => SR(0) - ); -\Probe_out_reg[1]\: unisim.vcomponents.FDRE - port map ( - C => \^clk\, - CE => \Probe_out_reg[31]_0\(0), - D => \mem_probe_out[0]\(1), - Q => probe_out0(1), - R => SR(0) - ); -\Probe_out_reg[20]\: unisim.vcomponents.FDRE - port map ( - C => \^clk\, - CE => \Probe_out_reg[31]_0\(0), - D => \mem_probe_out[0]\(20), - Q => probe_out0(20), - R => SR(0) - ); -\Probe_out_reg[21]\: unisim.vcomponents.FDRE - port map ( - C => \^clk\, - CE => \Probe_out_reg[31]_0\(0), - D => \mem_probe_out[0]\(21), - Q => probe_out0(21), - R => SR(0) - ); -\Probe_out_reg[22]\: unisim.vcomponents.FDRE - port map ( - C => \^clk\, - CE => \Probe_out_reg[31]_0\(0), - D => \mem_probe_out[0]\(22), - Q => probe_out0(22), - R => SR(0) - ); -\Probe_out_reg[23]\: unisim.vcomponents.FDRE - port map ( - C => \^clk\, - CE => \Probe_out_reg[31]_0\(0), - D => \mem_probe_out[0]\(23), - Q => probe_out0(23), - R => SR(0) - ); -\Probe_out_reg[24]\: unisim.vcomponents.FDRE - port map ( - C => \^clk\, - CE => \Probe_out_reg[31]_0\(0), - D => \mem_probe_out[0]\(24), - Q => probe_out0(24), - R => SR(0) - ); -\Probe_out_reg[25]\: unisim.vcomponents.FDRE - port map ( - C => \^clk\, - CE => \Probe_out_reg[31]_0\(0), - D => \mem_probe_out[0]\(25), - Q => probe_out0(25), - R => SR(0) - ); -\Probe_out_reg[26]\: unisim.vcomponents.FDRE - port map ( - C => \^clk\, - CE => \Probe_out_reg[31]_0\(0), - D => \mem_probe_out[0]\(26), - Q => probe_out0(26), - R => SR(0) - ); -\Probe_out_reg[27]\: unisim.vcomponents.FDRE - port map ( - C => \^clk\, - CE => \Probe_out_reg[31]_0\(0), - D => \mem_probe_out[0]\(27), - Q => probe_out0(27), - R => SR(0) - ); -\Probe_out_reg[28]\: unisim.vcomponents.FDRE - port map ( - C => \^clk\, - CE => \Probe_out_reg[31]_0\(0), - D => \mem_probe_out[0]\(28), - Q => probe_out0(28), - R => SR(0) - ); -\Probe_out_reg[29]\: unisim.vcomponents.FDRE - port map ( - C => \^clk\, - CE => \Probe_out_reg[31]_0\(0), - D => \mem_probe_out[0]\(29), - Q => probe_out0(29), - R => SR(0) - ); -\Probe_out_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => \^clk\, - CE => \Probe_out_reg[31]_0\(0), - D => \mem_probe_out[0]\(2), - Q => probe_out0(2), - R => SR(0) - ); -\Probe_out_reg[30]\: unisim.vcomponents.FDRE - port map ( - C => \^clk\, - CE => \Probe_out_reg[31]_0\(0), - D => \mem_probe_out[0]\(30), - Q => probe_out0(30), - R => SR(0) - ); -\Probe_out_reg[31]\: unisim.vcomponents.FDRE - port map ( - C => \^clk\, - CE => \Probe_out_reg[31]_0\(0), - D => \mem_probe_out[0]\(31), - Q => probe_out0(31), - R => SR(0) - ); -\Probe_out_reg[3]\: unisim.vcomponents.FDRE - port map ( - C => \^clk\, - CE => \Probe_out_reg[31]_0\(0), - D => \mem_probe_out[0]\(3), - Q => probe_out0(3), - R => SR(0) - ); -\Probe_out_reg[4]\: unisim.vcomponents.FDRE - port map ( - C => \^clk\, - CE => \Probe_out_reg[31]_0\(0), - D => \mem_probe_out[0]\(4), - Q => probe_out0(4), - R => SR(0) - ); -\Probe_out_reg[5]\: unisim.vcomponents.FDRE - port map ( - C => \^clk\, - CE => \Probe_out_reg[31]_0\(0), - D => \mem_probe_out[0]\(5), - Q => probe_out0(5), - R => SR(0) - ); -\Probe_out_reg[6]\: unisim.vcomponents.FDRE - port map ( - C => \^clk\, - CE => \Probe_out_reg[31]_0\(0), - D => \mem_probe_out[0]\(6), - Q => probe_out0(6), - R => SR(0) - ); -\Probe_out_reg[7]\: unisim.vcomponents.FDRE - port map ( - C => \^clk\, - CE => \Probe_out_reg[31]_0\(0), - D => \mem_probe_out[0]\(7), - Q => probe_out0(7), - R => SR(0) - ); -\Probe_out_reg[8]\: unisim.vcomponents.FDRE - port map ( - C => \^clk\, - CE => \Probe_out_reg[31]_0\(0), - D => \mem_probe_out[0]\(8), - Q => probe_out0(8), - R => SR(0) - ); -\Probe_out_reg[9]\: unisim.vcomponents.FDRE - port map ( - C => \^clk\, - CE => \Probe_out_reg[31]_0\(0), - D => \mem_probe_out[0]\(9), - Q => probe_out0(9), - R => SR(0) - ); -\addr_count[0]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"0322" - ) - port map ( - I0 => addr_count(0), - I1 => internal_cnt_rst, - I2 => addr_count(0), - I3 => rd_probe_out, - O => \addr_count[0]_i_1_n_0\ - ); -\addr_count[1]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"00302222" - ) - port map ( - I0 => addr_count(1), - I1 => internal_cnt_rst, - I2 => addr_count(1), - I3 => addr_count(0), - I4 => rd_probe_out, - O => \addr_count[1]_i_1_n_0\ - ); -\addr_count[1]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0001000000000000" - ) - port map ( - I0 => s_daddr_o(4), - I1 => s_daddr_o(6), - I2 => s_daddr_o(5), - I3 => \addr_count[1]_i_3_n_0\, - I4 => \addr_count[1]_i_4_n_0\, - I5 => \addr_count_reg[0]_0\, - O => rd_probe_out - ); -\addr_count[1]_i_3\: unisim.vcomponents.LUT4 - generic map( - INIT => X"FFFE" - ) - port map ( - I0 => s_daddr_o(7), - I1 => s_daddr_o(8), - I2 => s_daddr_o(9), - I3 => s_daddr_o(10), - O => \addr_count[1]_i_3_n_0\ - ); -\addr_count[1]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0000000000000020" - ) - port map ( - I0 => s_den_o, - I1 => s_dwe_o, - I2 => s_daddr_o(3), - I3 => s_daddr_o(0), - I4 => s_daddr_o(1), - I5 => s_daddr_o(2), - O => \addr_count[1]_i_4_n_0\ - ); -\addr_count_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => \addr_count[0]_i_1_n_0\, - Q => addr_count(0), - R => '0' - ); -\addr_count_reg[1]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => \addr_count[1]_i_1_n_0\, - Q => addr_count(1), - R => '0' - ); -\data_int_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => E(0), - D => Q(0), - Q => \mem_probe_out[0]\(0), - R => SR(0) - ); -\data_int_reg[10]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => E(0), - D => Q(10), - Q => \mem_probe_out[0]\(10), - R => SR(0) - ); -\data_int_reg[11]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => E(0), - D => Q(11), - Q => \mem_probe_out[0]\(11), - R => SR(0) - ); -\data_int_reg[12]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => E(0), - D => Q(12), - Q => \mem_probe_out[0]\(12), - R => SR(0) - ); -\data_int_reg[13]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => E(0), - D => Q(13), - Q => \mem_probe_out[0]\(13), - R => SR(0) - ); -\data_int_reg[14]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => E(0), - D => Q(14), - Q => \mem_probe_out[0]\(14), - R => SR(0) - ); -\data_int_reg[15]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => E(0), - D => Q(15), - Q => \mem_probe_out[0]\(15), - R => SR(0) - ); -\data_int_reg[1]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => E(0), - D => Q(1), - Q => \mem_probe_out[0]\(1), - R => SR(0) - ); -\data_int_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => E(0), - D => Q(2), - Q => \mem_probe_out[0]\(2), - R => SR(0) - ); -\data_int_reg[3]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => E(0), - D => Q(3), - Q => \mem_probe_out[0]\(3), - R => SR(0) - ); -\data_int_reg[4]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => E(0), - D => Q(4), - Q => \mem_probe_out[0]\(4), - R => SR(0) - ); -\data_int_reg[5]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => E(0), - D => Q(5), - Q => \mem_probe_out[0]\(5), - R => SR(0) - ); -\data_int_reg[6]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => E(0), - D => Q(6), - Q => \mem_probe_out[0]\(6), - R => SR(0) - ); -\data_int_reg[7]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => E(0), - D => Q(7), - Q => \mem_probe_out[0]\(7), - R => SR(0) - ); -\data_int_reg[8]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => E(0), - D => Q(8), - Q => \mem_probe_out[0]\(8), - R => SR(0) - ); -\data_int_reg[9]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => E(0), - D => Q(9), - Q => \mem_probe_out[0]\(9), - R => SR(0) - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity vio_0_xsdbs_v1_0_2_xsdbs is - port ( - s_rst_o : out STD_LOGIC; - s_dclk_o : out STD_LOGIC; - s_den_o : out STD_LOGIC; - s_dwe_o : out STD_LOGIC; - s_daddr_o : out STD_LOGIC_VECTOR ( 16 downto 0 ); - s_di_o : out STD_LOGIC_VECTOR ( 15 downto 0 ); - sl_oport_o : out STD_LOGIC_VECTOR ( 16 downto 0 ); - s_do_i : in STD_LOGIC_VECTOR ( 15 downto 0 ); - sl_iport_i : in STD_LOGIC_VECTOR ( 36 downto 0 ); - s_drdy_i : in STD_LOGIC - ); - attribute C_BUILD_REVISION : integer; - attribute C_BUILD_REVISION of vio_0_xsdbs_v1_0_2_xsdbs : entity is 0; - attribute C_CORE_INFO1 : string; - attribute C_CORE_INFO1 of vio_0_xsdbs_v1_0_2_xsdbs : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute C_CORE_INFO2 : string; - attribute C_CORE_INFO2 of vio_0_xsdbs_v1_0_2_xsdbs : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute C_CORE_MAJOR_VER : integer; - attribute C_CORE_MAJOR_VER of vio_0_xsdbs_v1_0_2_xsdbs : entity is 2; - attribute C_CORE_MINOR_VER : integer; - attribute C_CORE_MINOR_VER of vio_0_xsdbs_v1_0_2_xsdbs : entity is 0; - attribute C_CORE_TYPE : integer; - attribute C_CORE_TYPE of vio_0_xsdbs_v1_0_2_xsdbs : entity is 2; - attribute C_CSE_DRV_VER : integer; - attribute C_CSE_DRV_VER of vio_0_xsdbs_v1_0_2_xsdbs : entity is 1; - attribute C_MAJOR_VERSION : integer; - attribute C_MAJOR_VERSION of vio_0_xsdbs_v1_0_2_xsdbs : entity is 2013; - attribute C_MINOR_VERSION : integer; - attribute C_MINOR_VERSION of vio_0_xsdbs_v1_0_2_xsdbs : entity is 1; - attribute C_NEXT_SLAVE : integer; - attribute C_NEXT_SLAVE of vio_0_xsdbs_v1_0_2_xsdbs : entity is 0; - attribute C_PIPE_IFACE : integer; - attribute C_PIPE_IFACE of vio_0_xsdbs_v1_0_2_xsdbs : entity is 0; - attribute C_USE_TEST_REG : integer; - attribute C_USE_TEST_REG of vio_0_xsdbs_v1_0_2_xsdbs : entity is 1; - attribute C_XDEVICEFAMILY : string; - attribute C_XDEVICEFAMILY of vio_0_xsdbs_v1_0_2_xsdbs : entity is "zynq"; - attribute C_XSDB_SLAVE_TYPE : integer; - attribute C_XSDB_SLAVE_TYPE of vio_0_xsdbs_v1_0_2_xsdbs : entity is 33; - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of vio_0_xsdbs_v1_0_2_xsdbs : entity is "xsdbs_v1_0_2_xsdbs"; - attribute dont_touch : string; - attribute dont_touch of vio_0_xsdbs_v1_0_2_xsdbs : entity is "true"; -end vio_0_xsdbs_v1_0_2_xsdbs; - -architecture STRUCTURE of vio_0_xsdbs_v1_0_2_xsdbs is - signal reg_do : STD_LOGIC_VECTOR ( 15 downto 0 ); - signal \reg_do[0]_i_2_n_0\ : STD_LOGIC; - signal \reg_do[0]_i_3_n_0\ : STD_LOGIC; - signal \reg_do[0]_i_4_n_0\ : STD_LOGIC; - signal \reg_do[10]_i_2_n_0\ : STD_LOGIC; - signal \reg_do[10]_i_3_n_0\ : STD_LOGIC; - signal \reg_do[10]_i_4_n_0\ : STD_LOGIC; - signal \reg_do[10]_i_5_n_0\ : STD_LOGIC; - signal \reg_do[11]_i_2_n_0\ : STD_LOGIC; - signal \reg_do[11]_i_3_n_0\ : STD_LOGIC; - signal \reg_do[12]_i_2_n_0\ : STD_LOGIC; - signal \reg_do[12]_i_3_n_0\ : STD_LOGIC; - signal \reg_do[13]_i_2_n_0\ : STD_LOGIC; - signal \reg_do[13]_i_3_n_0\ : STD_LOGIC; - signal \reg_do[14]_i_2_n_0\ : STD_LOGIC; - signal \reg_do[14]_i_3_n_0\ : STD_LOGIC; - signal \reg_do[15]_i_2_n_0\ : STD_LOGIC; - signal \reg_do[15]_i_3_n_0\ : STD_LOGIC; - signal \reg_do[15]_i_4_n_0\ : STD_LOGIC; - signal \reg_do[15]_i_5_n_0\ : STD_LOGIC; - signal \reg_do[15]_i_6_n_0\ : STD_LOGIC; - signal \reg_do[1]_i_2_n_0\ : STD_LOGIC; - signal \reg_do[1]_i_3_n_0\ : STD_LOGIC; - signal \reg_do[1]_i_4_n_0\ : STD_LOGIC; - signal \reg_do[2]_i_2_n_0\ : STD_LOGIC; - signal \reg_do[2]_i_3_n_0\ : STD_LOGIC; - signal \reg_do[2]_i_4_n_0\ : STD_LOGIC; - signal \reg_do[3]_i_2_n_0\ : STD_LOGIC; - signal \reg_do[3]_i_3_n_0\ : STD_LOGIC; - signal \reg_do[3]_i_4_n_0\ : STD_LOGIC; - signal \reg_do[4]_i_2_n_0\ : STD_LOGIC; - signal \reg_do[4]_i_3_n_0\ : STD_LOGIC; - signal \reg_do[4]_i_4_n_0\ : STD_LOGIC; - signal \reg_do[5]_i_2_n_0\ : STD_LOGIC; - signal \reg_do[5]_i_3_n_0\ : STD_LOGIC; - signal \reg_do[5]_i_4_n_0\ : STD_LOGIC; - signal \reg_do[5]_i_5_n_0\ : STD_LOGIC; - signal \reg_do[6]_i_2_n_0\ : STD_LOGIC; - signal \reg_do[6]_i_3_n_0\ : STD_LOGIC; - signal \reg_do[6]_i_4_n_0\ : STD_LOGIC; - signal \reg_do[7]_i_2_n_0\ : STD_LOGIC; - signal \reg_do[7]_i_3_n_0\ : STD_LOGIC; - signal \reg_do[7]_i_4_n_0\ : STD_LOGIC; - signal \reg_do[8]_i_2_n_0\ : STD_LOGIC; - signal \reg_do[8]_i_3_n_0\ : STD_LOGIC; - signal \reg_do[8]_i_4_n_0\ : STD_LOGIC; - signal \reg_do[9]_i_2_n_0\ : STD_LOGIC; - signal \reg_do[9]_i_3_n_0\ : STD_LOGIC; - signal \reg_do[9]_i_4_n_0\ : STD_LOGIC; - signal \reg_do[9]_i_5_n_0\ : STD_LOGIC; - signal \reg_do[9]_i_6_n_0\ : STD_LOGIC; - signal \reg_do_reg_n_0_[0]\ : STD_LOGIC; - signal \reg_do_reg_n_0_[10]\ : STD_LOGIC; - signal \reg_do_reg_n_0_[11]\ : STD_LOGIC; - signal \reg_do_reg_n_0_[12]\ : STD_LOGIC; - signal \reg_do_reg_n_0_[13]\ : STD_LOGIC; - signal \reg_do_reg_n_0_[14]\ : STD_LOGIC; - signal \reg_do_reg_n_0_[15]\ : STD_LOGIC; - signal \reg_do_reg_n_0_[1]\ : STD_LOGIC; - signal \reg_do_reg_n_0_[2]\ : STD_LOGIC; - signal \reg_do_reg_n_0_[3]\ : STD_LOGIC; - signal \reg_do_reg_n_0_[4]\ : STD_LOGIC; - signal \reg_do_reg_n_0_[5]\ : STD_LOGIC; - signal \reg_do_reg_n_0_[6]\ : STD_LOGIC; - signal \reg_do_reg_n_0_[7]\ : STD_LOGIC; - signal \reg_do_reg_n_0_[8]\ : STD_LOGIC; - signal \reg_do_reg_n_0_[9]\ : STD_LOGIC; - signal reg_drdy : STD_LOGIC; - signal reg_drdy_i_1_n_0 : STD_LOGIC; - signal reg_test : STD_LOGIC_VECTOR ( 15 downto 0 ); - signal reg_test0 : STD_LOGIC; - signal s_den_o_INST_0_i_1_n_0 : STD_LOGIC; - signal \^sl_iport_i\ : STD_LOGIC_VECTOR ( 36 downto 0 ); - signal uuid_stamp : STD_LOGIC_VECTOR ( 127 downto 0 ); - attribute DONT_TOUCH_boolean : boolean; - attribute DONT_TOUCH_boolean of uuid_stamp : signal is std.standard.true; - attribute UUID : string; - attribute UUID of uuid_stamp : signal is "1"; - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \reg_do[15]_i_2\ : label is "soft_lutpair9"; - attribute SOFT_HLUTNM of \reg_do[15]_i_4\ : label is "soft_lutpair0"; - attribute SOFT_HLUTNM of \reg_do[9]_i_2\ : label is "soft_lutpair0"; - attribute SOFT_HLUTNM of \reg_do[9]_i_3\ : label is "soft_lutpair9"; - attribute SOFT_HLUTNM of \sl_oport_o[0]_INST_0\ : label is "soft_lutpair1"; - attribute SOFT_HLUTNM of \sl_oport_o[10]_INST_0\ : label is "soft_lutpair6"; - attribute SOFT_HLUTNM of \sl_oport_o[11]_INST_0\ : label is "soft_lutpair6"; - attribute SOFT_HLUTNM of \sl_oport_o[12]_INST_0\ : label is "soft_lutpair7"; - attribute SOFT_HLUTNM of \sl_oport_o[13]_INST_0\ : label is "soft_lutpair7"; - attribute SOFT_HLUTNM of \sl_oport_o[14]_INST_0\ : label is "soft_lutpair8"; - attribute SOFT_HLUTNM of \sl_oport_o[15]_INST_0\ : label is "soft_lutpair8"; - attribute SOFT_HLUTNM of \sl_oport_o[1]_INST_0\ : label is "soft_lutpair2"; - attribute SOFT_HLUTNM of \sl_oport_o[2]_INST_0\ : label is "soft_lutpair1"; - attribute SOFT_HLUTNM of \sl_oport_o[3]_INST_0\ : label is "soft_lutpair3"; - attribute SOFT_HLUTNM of \sl_oport_o[4]_INST_0\ : label is "soft_lutpair2"; - attribute SOFT_HLUTNM of \sl_oport_o[5]_INST_0\ : label is "soft_lutpair3"; - attribute SOFT_HLUTNM of \sl_oport_o[6]_INST_0\ : label is "soft_lutpair4"; - attribute SOFT_HLUTNM of \sl_oport_o[7]_INST_0\ : label is "soft_lutpair4"; - attribute SOFT_HLUTNM of \sl_oport_o[8]_INST_0\ : label is "soft_lutpair5"; - attribute SOFT_HLUTNM of \sl_oport_o[9]_INST_0\ : label is "soft_lutpair5"; - attribute DONT_TOUCH_boolean of \uuid_stamp_reg[0]\ : label is std.standard.true; - attribute KEEP : string; - attribute KEEP of \uuid_stamp_reg[0]\ : label is "yes"; - attribute UUID of \uuid_stamp_reg[0]\ : label is "1"; - attribute DONT_TOUCH_boolean of \uuid_stamp_reg[100]\ : label is std.standard.true; - attribute KEEP of \uuid_stamp_reg[100]\ : label is "yes"; - attribute UUID of \uuid_stamp_reg[100]\ : label is "1"; - attribute DONT_TOUCH_boolean of \uuid_stamp_reg[101]\ : label is std.standard.true; - attribute KEEP of \uuid_stamp_reg[101]\ : label is "yes"; - attribute UUID of \uuid_stamp_reg[101]\ : label is "1"; - attribute DONT_TOUCH_boolean of \uuid_stamp_reg[102]\ : label is std.standard.true; - attribute KEEP of \uuid_stamp_reg[102]\ : label is "yes"; - attribute UUID of \uuid_stamp_reg[102]\ : label is "1"; - attribute DONT_TOUCH_boolean of \uuid_stamp_reg[103]\ : label is std.standard.true; - attribute KEEP of \uuid_stamp_reg[103]\ : label is "yes"; - attribute UUID of \uuid_stamp_reg[103]\ : label is "1"; - attribute DONT_TOUCH_boolean of \uuid_stamp_reg[104]\ : label is std.standard.true; - attribute KEEP of \uuid_stamp_reg[104]\ : label is "yes"; - attribute UUID of \uuid_stamp_reg[104]\ : label is "1"; - attribute DONT_TOUCH_boolean of \uuid_stamp_reg[105]\ : label is std.standard.true; - attribute KEEP of \uuid_stamp_reg[105]\ : label is "yes"; - attribute UUID of \uuid_stamp_reg[105]\ : label is "1"; - attribute DONT_TOUCH_boolean of \uuid_stamp_reg[106]\ : label is std.standard.true; - attribute KEEP of \uuid_stamp_reg[106]\ : label is "yes"; - attribute UUID of \uuid_stamp_reg[106]\ : label is "1"; - attribute DONT_TOUCH_boolean of \uuid_stamp_reg[107]\ : label is std.standard.true; - attribute KEEP of \uuid_stamp_reg[107]\ : label is "yes"; - attribute UUID of \uuid_stamp_reg[107]\ : label is "1"; - attribute DONT_TOUCH_boolean of \uuid_stamp_reg[108]\ : label is std.standard.true; - attribute KEEP of \uuid_stamp_reg[108]\ : label is "yes"; - attribute UUID of \uuid_stamp_reg[108]\ : label is "1"; - attribute DONT_TOUCH_boolean of \uuid_stamp_reg[109]\ : label is std.standard.true; - attribute KEEP of \uuid_stamp_reg[109]\ : label is "yes"; - attribute UUID of \uuid_stamp_reg[109]\ : label is "1"; - attribute DONT_TOUCH_boolean of \uuid_stamp_reg[10]\ : label is std.standard.true; - attribute KEEP of \uuid_stamp_reg[10]\ : label is "yes"; - attribute UUID of \uuid_stamp_reg[10]\ : label is "1"; - attribute DONT_TOUCH_boolean of \uuid_stamp_reg[110]\ : label is std.standard.true; - attribute KEEP of \uuid_stamp_reg[110]\ : label is "yes"; - attribute UUID of \uuid_stamp_reg[110]\ : label is "1"; - attribute DONT_TOUCH_boolean of \uuid_stamp_reg[111]\ : label is std.standard.true; - attribute KEEP of \uuid_stamp_reg[111]\ : label is "yes"; - attribute UUID of \uuid_stamp_reg[111]\ : label is "1"; - attribute DONT_TOUCH_boolean of \uuid_stamp_reg[112]\ : label is std.standard.true; - attribute KEEP of \uuid_stamp_reg[112]\ : label is "yes"; - attribute UUID of \uuid_stamp_reg[112]\ : label is "1"; - attribute DONT_TOUCH_boolean of \uuid_stamp_reg[113]\ : label is std.standard.true; - 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attribute KEEP of \uuid_stamp_reg[7]\ : label is "yes"; - attribute UUID of \uuid_stamp_reg[7]\ : label is "1"; - attribute DONT_TOUCH_boolean of \uuid_stamp_reg[80]\ : label is std.standard.true; - attribute KEEP of \uuid_stamp_reg[80]\ : label is "yes"; - attribute UUID of \uuid_stamp_reg[80]\ : label is "1"; - attribute DONT_TOUCH_boolean of \uuid_stamp_reg[81]\ : label is std.standard.true; - attribute KEEP of \uuid_stamp_reg[81]\ : label is "yes"; - attribute UUID of \uuid_stamp_reg[81]\ : label is "1"; - attribute DONT_TOUCH_boolean of \uuid_stamp_reg[82]\ : label is std.standard.true; - attribute KEEP of \uuid_stamp_reg[82]\ : label is "yes"; - attribute UUID of \uuid_stamp_reg[82]\ : label is "1"; - attribute DONT_TOUCH_boolean of \uuid_stamp_reg[83]\ : label is std.standard.true; - attribute KEEP of \uuid_stamp_reg[83]\ : label is "yes"; - attribute UUID of \uuid_stamp_reg[83]\ : label is "1"; - attribute DONT_TOUCH_boolean of \uuid_stamp_reg[84]\ : label is std.standard.true; - attribute KEEP of \uuid_stamp_reg[84]\ : label is "yes"; - attribute UUID of \uuid_stamp_reg[84]\ : label is "1"; - attribute DONT_TOUCH_boolean of \uuid_stamp_reg[85]\ : label is std.standard.true; - attribute KEEP of \uuid_stamp_reg[85]\ : label is "yes"; - attribute UUID of \uuid_stamp_reg[85]\ : label is "1"; - attribute DONT_TOUCH_boolean of \uuid_stamp_reg[86]\ : label is std.standard.true; - attribute KEEP of \uuid_stamp_reg[86]\ : label is "yes"; - attribute UUID of \uuid_stamp_reg[86]\ : label is "1"; - attribute DONT_TOUCH_boolean of \uuid_stamp_reg[87]\ : label is std.standard.true; - attribute KEEP of \uuid_stamp_reg[87]\ : label is "yes"; - attribute UUID of \uuid_stamp_reg[87]\ : label is "1"; - attribute DONT_TOUCH_boolean of \uuid_stamp_reg[88]\ : label is std.standard.true; - attribute KEEP of \uuid_stamp_reg[88]\ : label is "yes"; - attribute UUID of \uuid_stamp_reg[88]\ : label is "1"; - attribute DONT_TOUCH_boolean of \uuid_stamp_reg[89]\ : label is std.standard.true; - attribute KEEP of \uuid_stamp_reg[89]\ : label is "yes"; - attribute UUID of \uuid_stamp_reg[89]\ : label is "1"; - attribute DONT_TOUCH_boolean of \uuid_stamp_reg[8]\ : label is std.standard.true; - attribute KEEP of \uuid_stamp_reg[8]\ : label is "yes"; - attribute UUID of \uuid_stamp_reg[8]\ : label is "1"; - attribute DONT_TOUCH_boolean of \uuid_stamp_reg[90]\ : label is std.standard.true; - attribute KEEP of \uuid_stamp_reg[90]\ : label is "yes"; - attribute UUID of \uuid_stamp_reg[90]\ : label is "1"; - attribute DONT_TOUCH_boolean of \uuid_stamp_reg[91]\ : label is std.standard.true; - attribute KEEP of \uuid_stamp_reg[91]\ : label is "yes"; - attribute UUID of \uuid_stamp_reg[91]\ : label is "1"; - attribute DONT_TOUCH_boolean of \uuid_stamp_reg[92]\ : label is std.standard.true; - attribute KEEP of \uuid_stamp_reg[92]\ : label is "yes"; - attribute UUID of \uuid_stamp_reg[92]\ : label is "1"; - attribute DONT_TOUCH_boolean of \uuid_stamp_reg[93]\ : label is std.standard.true; - attribute KEEP of \uuid_stamp_reg[93]\ : label is "yes"; - attribute UUID of \uuid_stamp_reg[93]\ : label is "1"; - attribute DONT_TOUCH_boolean of \uuid_stamp_reg[94]\ : label is std.standard.true; - attribute KEEP of \uuid_stamp_reg[94]\ : label is "yes"; - attribute UUID of \uuid_stamp_reg[94]\ : label is "1"; - attribute DONT_TOUCH_boolean of \uuid_stamp_reg[95]\ : label is std.standard.true; - attribute KEEP of \uuid_stamp_reg[95]\ : label is "yes"; - attribute UUID of \uuid_stamp_reg[95]\ : label is "1"; - attribute DONT_TOUCH_boolean of \uuid_stamp_reg[96]\ : label is std.standard.true; - attribute KEEP of \uuid_stamp_reg[96]\ : label is "yes"; - attribute UUID of \uuid_stamp_reg[96]\ : label is "1"; - attribute DONT_TOUCH_boolean of \uuid_stamp_reg[97]\ : label is std.standard.true; - attribute KEEP of \uuid_stamp_reg[97]\ : label is "yes"; - attribute UUID of \uuid_stamp_reg[97]\ : label is "1"; - attribute DONT_TOUCH_boolean of \uuid_stamp_reg[98]\ : label is std.standard.true; - attribute KEEP of \uuid_stamp_reg[98]\ : label is "yes"; - attribute UUID of \uuid_stamp_reg[98]\ : label is "1"; - attribute DONT_TOUCH_boolean of \uuid_stamp_reg[99]\ : label is std.standard.true; - attribute KEEP of \uuid_stamp_reg[99]\ : label is "yes"; - attribute UUID of \uuid_stamp_reg[99]\ : label is "1"; - attribute DONT_TOUCH_boolean of \uuid_stamp_reg[9]\ : label is std.standard.true; - attribute KEEP of \uuid_stamp_reg[9]\ : label is "yes"; - attribute UUID of \uuid_stamp_reg[9]\ : label is "1"; -begin - \^sl_iport_i\(36 downto 0) <= sl_iport_i(36 downto 0); - s_daddr_o(16 downto 0) <= \^sl_iport_i\(20 downto 4); - s_dclk_o <= \^sl_iport_i\(1); - s_di_o(15 downto 0) <= \^sl_iport_i\(36 downto 21); - s_dwe_o <= \^sl_iport_i\(3); - s_rst_o <= \^sl_iport_i\(0); -\reg_do[0]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AAAAAAAA0020AAAA" - ) - port map ( - I0 => \reg_do[0]_i_2_n_0\, - I1 => \reg_do[9]_i_3_n_0\, - I2 => reg_test(0), - I3 => \^sl_iport_i\(4), - I4 => \^sl_iport_i\(5), - I5 => \reg_do[9]_i_2_n_0\, - O => reg_do(0) - ); -\reg_do[0]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"ABABABAAAAAAABAA" - ) - port map ( - I0 => \reg_do[5]_i_3_n_0\, - I1 => \^sl_iport_i\(8), - I2 => \^sl_iport_i\(7), - I3 => \reg_do[0]_i_3_n_0\, - I4 => \^sl_iport_i\(6), - I5 => \reg_do[0]_i_4_n_0\, - O => \reg_do[0]_i_2_n_0\ - ); -\reg_do[0]_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => uuid_stamp(48), - I1 => uuid_stamp(32), - I2 => \^sl_iport_i\(5), - I3 => uuid_stamp(16), - I4 => \^sl_iport_i\(4), - I5 => uuid_stamp(0), - O => \reg_do[0]_i_3_n_0\ - ); -\reg_do[0]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => uuid_stamp(112), - I1 => uuid_stamp(96), - I2 => \^sl_iport_i\(5), - I3 => uuid_stamp(80), - I4 => \^sl_iport_i\(4), - I5 => uuid_stamp(64), - O => \reg_do[0]_i_4_n_0\ - ); -\reg_do[10]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"FFFF2808" - ) - port map ( - I0 => \reg_do[10]_i_2_n_0\, - I1 => \^sl_iport_i\(4), - I2 => \^sl_iport_i\(5), - I3 => reg_test(10), - I4 => \reg_do[10]_i_3_n_0\, - O => reg_do(10) - ); -\reg_do[10]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0800000000000000" - ) - port map ( - I0 => \^sl_iport_i\(6), - I1 => \^sl_iport_i\(9), - I2 => \^sl_iport_i\(7), - I3 => \^sl_iport_i\(8), - I4 => \^sl_iport_i\(11), - I5 => \^sl_iport_i\(10), - O => \reg_do[10]_i_2_n_0\ - ); -\reg_do[10]_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"00000000AAFBAA08" - ) - port map ( - I0 => \reg_do[10]_i_4_n_0\, - I1 => \^sl_iport_i\(6), - I2 => \^sl_iport_i\(7), - I3 => \^sl_iport_i\(8), - I4 => \reg_do[10]_i_5_n_0\, - I5 => \reg_do[15]_i_4_n_0\, - O => \reg_do[10]_i_3_n_0\ - ); -\reg_do[10]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => uuid_stamp(122), - I1 => uuid_stamp(106), - I2 => \^sl_iport_i\(5), - I3 => uuid_stamp(90), - I4 => \^sl_iport_i\(4), - I5 => uuid_stamp(74), - O => \reg_do[10]_i_4_n_0\ - ); -\reg_do[10]_i_5\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => uuid_stamp(58), - I1 => uuid_stamp(42), - I2 => \^sl_iport_i\(5), - I3 => uuid_stamp(26), - I4 => \^sl_iport_i\(4), - I5 => uuid_stamp(10), - O => \reg_do[10]_i_5_n_0\ - ); -\reg_do[11]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"4540FFFF45404540" - ) - port map ( - I0 => \reg_do[15]_i_4_n_0\, - I1 => \reg_do[11]_i_2_n_0\, - I2 => \reg_do[15]_i_2_n_0\, - I3 => \reg_do[11]_i_3_n_0\, - I4 => \reg_do[15]_i_6_n_0\, - I5 => reg_test(11), - O => reg_do(11) - ); -\reg_do[11]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => uuid_stamp(59), - I1 => uuid_stamp(43), - I2 => \^sl_iport_i\(5), - I3 => uuid_stamp(27), - I4 => \^sl_iport_i\(4), - I5 => uuid_stamp(11), - O => \reg_do[11]_i_2_n_0\ - ); -\reg_do[11]_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => uuid_stamp(123), - I1 => uuid_stamp(107), - I2 => \^sl_iport_i\(5), - I3 => uuid_stamp(91), - I4 => \^sl_iport_i\(4), - I5 => uuid_stamp(75), - O => \reg_do[11]_i_3_n_0\ - ); -\reg_do[12]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"5404FFFF54045404" - ) - port map ( - I0 => \reg_do[15]_i_4_n_0\, - I1 => \reg_do[12]_i_2_n_0\, - I2 => \reg_do[15]_i_2_n_0\, - I3 => \reg_do[12]_i_3_n_0\, - I4 => \reg_do[15]_i_6_n_0\, - I5 => reg_test(12), - O => reg_do(12) - ); -\reg_do[12]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => uuid_stamp(124), - I1 => uuid_stamp(108), - I2 => \^sl_iport_i\(5), - I3 => uuid_stamp(92), - I4 => \^sl_iport_i\(4), - I5 => uuid_stamp(76), - O => \reg_do[12]_i_2_n_0\ - ); -\reg_do[12]_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => uuid_stamp(60), - I1 => uuid_stamp(44), - I2 => \^sl_iport_i\(5), - I3 => uuid_stamp(28), - I4 => \^sl_iport_i\(4), - I5 => uuid_stamp(12), - O => \reg_do[12]_i_3_n_0\ - ); -\reg_do[13]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"4540FFFF45404540" - ) - port map ( - I0 => \reg_do[15]_i_4_n_0\, - I1 => \reg_do[13]_i_2_n_0\, - I2 => \reg_do[15]_i_2_n_0\, - I3 => \reg_do[13]_i_3_n_0\, - I4 => \reg_do[15]_i_6_n_0\, - I5 => reg_test(13), - O => reg_do(13) - ); -\reg_do[13]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => uuid_stamp(61), - I1 => uuid_stamp(45), - I2 => \^sl_iport_i\(5), - I3 => uuid_stamp(29), - I4 => \^sl_iport_i\(4), - I5 => uuid_stamp(13), - O => \reg_do[13]_i_2_n_0\ - ); -\reg_do[13]_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => uuid_stamp(125), - I1 => uuid_stamp(109), - I2 => \^sl_iport_i\(5), - I3 => uuid_stamp(93), - I4 => \^sl_iport_i\(4), - I5 => uuid_stamp(77), - O => \reg_do[13]_i_3_n_0\ - ); -\reg_do[14]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"4540FFFF45404540" - ) - port map ( - I0 => \reg_do[15]_i_4_n_0\, - I1 => \reg_do[14]_i_2_n_0\, - I2 => \reg_do[15]_i_2_n_0\, - I3 => \reg_do[14]_i_3_n_0\, - I4 => \reg_do[15]_i_6_n_0\, - I5 => reg_test(14), - O => reg_do(14) - ); -\reg_do[14]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => uuid_stamp(62), - I1 => uuid_stamp(46), - I2 => \^sl_iport_i\(5), - I3 => uuid_stamp(30), - I4 => \^sl_iport_i\(4), - I5 => uuid_stamp(14), - O => \reg_do[14]_i_2_n_0\ - ); -\reg_do[14]_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => uuid_stamp(126), - I1 => uuid_stamp(110), - I2 => \^sl_iport_i\(5), - I3 => uuid_stamp(94), - I4 => \^sl_iport_i\(4), - I5 => uuid_stamp(78), - O => \reg_do[14]_i_3_n_0\ - ); -\reg_do[15]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0B01FFFF0B010B01" - ) - port map ( - I0 => \reg_do[15]_i_2_n_0\, - I1 => \reg_do[15]_i_3_n_0\, - I2 => \reg_do[15]_i_4_n_0\, - I3 => \reg_do[15]_i_5_n_0\, - I4 => \reg_do[15]_i_6_n_0\, - I5 => reg_test(15), - O => reg_do(15) - ); -\reg_do[15]_i_2\: unisim.vcomponents.LUT3 - generic map( - INIT => X"45" - ) - port map ( - I0 => \^sl_iport_i\(8), - I1 => \^sl_iport_i\(7), - I2 => \^sl_iport_i\(6), - O => \reg_do[15]_i_2_n_0\ - ); -\reg_do[15]_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"505F3030505F3F3F" - ) - port map ( - I0 => uuid_stamp(127), - I1 => uuid_stamp(111), - I2 => \^sl_iport_i\(5), - I3 => uuid_stamp(95), - I4 => \^sl_iport_i\(4), - I5 => uuid_stamp(79), - O => \reg_do[15]_i_3_n_0\ - ); -\reg_do[15]_i_4\: unisim.vcomponents.LUT5 - generic map( - INIT => X"FFFFFFFE" - ) - port map ( - I0 => \^sl_iport_i\(7), - I1 => \^sl_iport_i\(8), - I2 => \^sl_iport_i\(9), - I3 => \^sl_iport_i\(11), - I4 => \^sl_iport_i\(10), - O => \reg_do[15]_i_4_n_0\ - ); -\reg_do[15]_i_5\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => uuid_stamp(63), - I1 => uuid_stamp(47), - I2 => \^sl_iport_i\(5), - I3 => uuid_stamp(31), - I4 => \^sl_iport_i\(4), - I5 => uuid_stamp(15), - O => \reg_do[15]_i_5_n_0\ - ); -\reg_do[15]_i_6\: unisim.vcomponents.LUT6 - generic map( - INIT => X"FFFFFFD0FFFFFFFF" - ) - port map ( - I0 => \^sl_iport_i\(6), - I1 => \^sl_iport_i\(7), - I2 => \^sl_iport_i\(8), - I3 => \reg_do[9]_i_2_n_0\, - I4 => \^sl_iport_i\(4), - I5 => \^sl_iport_i\(5), - O => \reg_do[15]_i_6_n_0\ - ); -\reg_do[1]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AAAAAAAAAAAAFEAA" - ) - port map ( - I0 => \reg_do[1]_i_2_n_0\, - I1 => reg_test(1), - I2 => \reg_do[9]_i_3_n_0\, - I3 => \^sl_iport_i\(5), - I4 => \^sl_iport_i\(4), - I5 => \reg_do[9]_i_2_n_0\, - O => reg_do(1) - ); -\reg_do[1]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"00000000FFAE00A2" - ) - port map ( - I0 => \reg_do[1]_i_3_n_0\, - I1 => \^sl_iport_i\(6), - I2 => \^sl_iport_i\(7), - I3 => \^sl_iport_i\(8), - I4 => \reg_do[1]_i_4_n_0\, - I5 => \reg_do[15]_i_4_n_0\, - O => \reg_do[1]_i_2_n_0\ - ); -\reg_do[1]_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => uuid_stamp(49), - I1 => uuid_stamp(33), - I2 => \^sl_iport_i\(5), - I3 => uuid_stamp(17), - I4 => \^sl_iport_i\(4), - I5 => uuid_stamp(1), - O => \reg_do[1]_i_3_n_0\ - ); -\reg_do[1]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => uuid_stamp(113), - I1 => uuid_stamp(97), - I2 => \^sl_iport_i\(5), - I3 => uuid_stamp(81), - I4 => \^sl_iport_i\(4), - I5 => uuid_stamp(65), - O => \reg_do[1]_i_4_n_0\ - ); -\reg_do[2]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"FFFF6200" - ) - port map ( - I0 => \^sl_iport_i\(4), - I1 => \^sl_iport_i\(5), - I2 => reg_test(2), - I3 => \reg_do[10]_i_2_n_0\, - I4 => \reg_do[2]_i_2_n_0\, - O => reg_do(2) - ); -\reg_do[2]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"00000000AAFBAA08" - ) - port map ( - I0 => \reg_do[2]_i_3_n_0\, - I1 => \^sl_iport_i\(6), - I2 => \^sl_iport_i\(7), - I3 => \^sl_iport_i\(8), - I4 => \reg_do[2]_i_4_n_0\, - I5 => \reg_do[15]_i_4_n_0\, - O => \reg_do[2]_i_2_n_0\ - ); -\reg_do[2]_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => uuid_stamp(114), - I1 => uuid_stamp(98), - I2 => \^sl_iport_i\(5), - I3 => uuid_stamp(82), - I4 => \^sl_iport_i\(4), - I5 => uuid_stamp(66), - O => \reg_do[2]_i_3_n_0\ - ); -\reg_do[2]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => uuid_stamp(50), - I1 => uuid_stamp(34), - I2 => \^sl_iport_i\(5), - I3 => uuid_stamp(18), - I4 => \^sl_iport_i\(4), - I5 => uuid_stamp(2), - O => \reg_do[2]_i_4_n_0\ - ); -\reg_do[3]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"FFFF6200" - ) - port map ( - I0 => \^sl_iport_i\(4), - I1 => \^sl_iport_i\(5), - I2 => reg_test(3), - I3 => \reg_do[10]_i_2_n_0\, - I4 => \reg_do[3]_i_2_n_0\, - O => reg_do(3) - ); -\reg_do[3]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"000000003333AA3A" - ) - port map ( - I0 => \reg_do[3]_i_3_n_0\, - I1 => \reg_do[3]_i_4_n_0\, - I2 => \^sl_iport_i\(6), - I3 => \^sl_iport_i\(7), - I4 => \^sl_iport_i\(8), - I5 => \reg_do[15]_i_4_n_0\, - O => \reg_do[3]_i_2_n_0\ - ); -\reg_do[3]_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => uuid_stamp(51), - I1 => uuid_stamp(35), - I2 => \^sl_iport_i\(5), - I3 => uuid_stamp(19), - I4 => \^sl_iport_i\(4), - I5 => uuid_stamp(3), - O => \reg_do[3]_i_3_n_0\ - ); -\reg_do[3]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"05F5030305F5F3F3" - ) - port map ( - I0 => uuid_stamp(83), - I1 => uuid_stamp(67), - I2 => \^sl_iport_i\(5), - I3 => uuid_stamp(115), - I4 => \^sl_iport_i\(4), - I5 => uuid_stamp(99), - O => \reg_do[3]_i_4_n_0\ - ); -\reg_do[4]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"FFFF6200" - ) - port map ( - I0 => \^sl_iport_i\(4), - I1 => \^sl_iport_i\(5), - I2 => reg_test(4), - I3 => \reg_do[10]_i_2_n_0\, - I4 => \reg_do[4]_i_2_n_0\, - O => reg_do(4) - ); -\reg_do[4]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"00000000FFAE00A2" - ) - port map ( - I0 => \reg_do[4]_i_3_n_0\, - I1 => \^sl_iport_i\(6), - I2 => \^sl_iport_i\(7), - I3 => \^sl_iport_i\(8), - I4 => \reg_do[4]_i_4_n_0\, - I5 => \reg_do[15]_i_4_n_0\, - O => \reg_do[4]_i_2_n_0\ - ); -\reg_do[4]_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => uuid_stamp(52), - I1 => uuid_stamp(36), - I2 => \^sl_iport_i\(5), - I3 => uuid_stamp(20), - I4 => \^sl_iport_i\(4), - I5 => uuid_stamp(4), - O => \reg_do[4]_i_3_n_0\ - ); -\reg_do[4]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => uuid_stamp(116), - I1 => uuid_stamp(100), - I2 => \^sl_iport_i\(5), - I3 => uuid_stamp(84), - I4 => \^sl_iport_i\(4), - I5 => uuid_stamp(68), - O => \reg_do[4]_i_4_n_0\ - ); -\reg_do[5]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"888888888A88A8A8" - ) - port map ( - I0 => \reg_do[5]_i_2_n_0\, - I1 => \reg_do[9]_i_2_n_0\, - I2 => \reg_do[9]_i_3_n_0\, - I3 => reg_test(5), - I4 => \^sl_iport_i\(5), - I5 => \^sl_iport_i\(4), - O => reg_do(5) - ); -\reg_do[5]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"ABABABAAAAAAABAA" - ) - port map ( - I0 => \reg_do[5]_i_3_n_0\, - I1 => \^sl_iport_i\(8), - I2 => \^sl_iport_i\(7), - I3 => \reg_do[5]_i_4_n_0\, - I4 => \^sl_iport_i\(6), - I5 => \reg_do[5]_i_5_n_0\, - O => \reg_do[5]_i_2_n_0\ - ); -\reg_do[5]_i_3\: unisim.vcomponents.LUT4 - generic map( - INIT => X"FFFE" - ) - port map ( - I0 => \^sl_iport_i\(10), - I1 => \^sl_iport_i\(11), - I2 => \^sl_iport_i\(9), - I3 => \^sl_iport_i\(8), - O => \reg_do[5]_i_3_n_0\ - ); -\reg_do[5]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => uuid_stamp(53), - I1 => uuid_stamp(37), - I2 => \^sl_iport_i\(5), - I3 => uuid_stamp(21), - I4 => \^sl_iport_i\(4), - I5 => uuid_stamp(5), - O => \reg_do[5]_i_4_n_0\ - ); -\reg_do[5]_i_5\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => uuid_stamp(117), - I1 => uuid_stamp(101), - I2 => \^sl_iport_i\(5), - I3 => uuid_stamp(85), - I4 => \^sl_iport_i\(4), - I5 => uuid_stamp(69), - O => \reg_do[5]_i_5_n_0\ - ); -\reg_do[6]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"FFFF6200" - ) - port map ( - I0 => \^sl_iport_i\(4), - I1 => \^sl_iport_i\(5), - I2 => reg_test(6), - I3 => \reg_do[10]_i_2_n_0\, - I4 => \reg_do[6]_i_2_n_0\, - O => reg_do(6) - ); -\reg_do[6]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"00000000AAFBAA08" - ) - port map ( - I0 => \reg_do[6]_i_3_n_0\, - I1 => \^sl_iport_i\(6), - I2 => \^sl_iport_i\(7), - I3 => \^sl_iport_i\(8), - I4 => \reg_do[6]_i_4_n_0\, - I5 => \reg_do[15]_i_4_n_0\, - O => \reg_do[6]_i_2_n_0\ - ); -\reg_do[6]_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => uuid_stamp(118), - I1 => uuid_stamp(102), - I2 => \^sl_iport_i\(5), - I3 => uuid_stamp(86), - I4 => \^sl_iport_i\(4), - I5 => uuid_stamp(70), - O => \reg_do[6]_i_3_n_0\ - ); -\reg_do[6]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => uuid_stamp(54), - I1 => uuid_stamp(38), - I2 => \^sl_iport_i\(5), - I3 => uuid_stamp(22), - I4 => \^sl_iport_i\(4), - I5 => uuid_stamp(6), - O => \reg_do[6]_i_4_n_0\ - ); -\reg_do[7]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"FFFF6200" - ) - port map ( - I0 => \^sl_iport_i\(4), - I1 => \^sl_iport_i\(5), - I2 => reg_test(7), - I3 => \reg_do[10]_i_2_n_0\, - I4 => \reg_do[7]_i_2_n_0\, - O => reg_do(7) - ); -\reg_do[7]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"00000000AAFBAA08" - ) - port map ( - I0 => \reg_do[7]_i_3_n_0\, - I1 => \^sl_iport_i\(6), - I2 => \^sl_iport_i\(7), - I3 => \^sl_iport_i\(8), - I4 => \reg_do[7]_i_4_n_0\, - I5 => \reg_do[15]_i_4_n_0\, - O => \reg_do[7]_i_2_n_0\ - ); -\reg_do[7]_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => uuid_stamp(119), - I1 => uuid_stamp(103), - I2 => \^sl_iport_i\(5), - I3 => uuid_stamp(87), - I4 => \^sl_iport_i\(4), - I5 => uuid_stamp(71), - O => \reg_do[7]_i_3_n_0\ - ); -\reg_do[7]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => uuid_stamp(55), - I1 => uuid_stamp(39), - I2 => \^sl_iport_i\(5), - I3 => uuid_stamp(23), - I4 => \^sl_iport_i\(4), - I5 => uuid_stamp(7), - O => \reg_do[7]_i_4_n_0\ - ); -\reg_do[8]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"FFFF7500" - ) - port map ( - I0 => \^sl_iport_i\(5), - I1 => \^sl_iport_i\(4), - I2 => reg_test(8), - I3 => \reg_do[10]_i_2_n_0\, - I4 => \reg_do[8]_i_2_n_0\, - O => reg_do(8) - ); -\reg_do[8]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"00000000AAFBAA08" - ) - port map ( - I0 => \reg_do[8]_i_3_n_0\, - I1 => \^sl_iport_i\(6), - I2 => \^sl_iport_i\(7), - I3 => \^sl_iport_i\(8), - I4 => \reg_do[8]_i_4_n_0\, - I5 => \reg_do[15]_i_4_n_0\, - O => \reg_do[8]_i_2_n_0\ - ); -\reg_do[8]_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => uuid_stamp(120), - I1 => uuid_stamp(104), - I2 => \^sl_iport_i\(5), - I3 => uuid_stamp(88), - I4 => \^sl_iport_i\(4), - I5 => uuid_stamp(72), - O => \reg_do[8]_i_3_n_0\ - ); -\reg_do[8]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => uuid_stamp(56), - I1 => uuid_stamp(40), - I2 => \^sl_iport_i\(5), - I3 => uuid_stamp(24), - I4 => \^sl_iport_i\(4), - I5 => uuid_stamp(8), - O => \reg_do[8]_i_4_n_0\ - ); -\reg_do[9]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"FFFFFFFF40144010" - ) - port map ( - I0 => \reg_do[9]_i_2_n_0\, - I1 => \^sl_iport_i\(5), - I2 => \^sl_iport_i\(4), - I3 => \reg_do[9]_i_3_n_0\, - I4 => reg_test(9), - I5 => \reg_do[9]_i_4_n_0\, - O => reg_do(9) - ); -\reg_do[9]_i_2\: unisim.vcomponents.LUT5 - generic map( - INIT => X"FF7FFFFF" - ) - port map ( - I0 => \^sl_iport_i\(10), - I1 => \^sl_iport_i\(11), - I2 => \^sl_iport_i\(8), - I3 => \^sl_iport_i\(7), - I4 => \^sl_iport_i\(9), - O => \reg_do[9]_i_2_n_0\ - ); -\reg_do[9]_i_3\: unisim.vcomponents.LUT3 - generic map( - INIT => X"8A" - ) - port map ( - I0 => \^sl_iport_i\(8), - I1 => \^sl_iport_i\(7), - I2 => \^sl_iport_i\(6), - O => \reg_do[9]_i_3_n_0\ - ); -\reg_do[9]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"00000000AAFBAA08" - ) - port map ( - I0 => \reg_do[9]_i_5_n_0\, - I1 => \^sl_iport_i\(6), - I2 => \^sl_iport_i\(7), - I3 => \^sl_iport_i\(8), - I4 => \reg_do[9]_i_6_n_0\, - I5 => \reg_do[15]_i_4_n_0\, - O => \reg_do[9]_i_4_n_0\ - ); -\reg_do[9]_i_5\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => uuid_stamp(121), - I1 => uuid_stamp(105), - I2 => \^sl_iport_i\(5), - I3 => uuid_stamp(89), - I4 => \^sl_iport_i\(4), - I5 => uuid_stamp(73), - O => \reg_do[9]_i_5_n_0\ - ); -\reg_do[9]_i_6\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => uuid_stamp(57), - I1 => uuid_stamp(41), - I2 => \^sl_iport_i\(5), - I3 => uuid_stamp(25), - I4 => \^sl_iport_i\(4), - I5 => uuid_stamp(9), - O => \reg_do[9]_i_6_n_0\ - ); -\reg_do_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => reg_do(0), - Q => \reg_do_reg_n_0_[0]\, - R => '0' - ); -\reg_do_reg[10]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => reg_do(10), - Q => \reg_do_reg_n_0_[10]\, - R => '0' - ); -\reg_do_reg[11]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => reg_do(11), - Q => \reg_do_reg_n_0_[11]\, - R => '0' - ); -\reg_do_reg[12]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => reg_do(12), - Q => \reg_do_reg_n_0_[12]\, - R => '0' - ); -\reg_do_reg[13]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => reg_do(13), - Q => \reg_do_reg_n_0_[13]\, - R => '0' - ); -\reg_do_reg[14]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => reg_do(14), - Q => \reg_do_reg_n_0_[14]\, - R => '0' - ); -\reg_do_reg[15]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => reg_do(15), - Q => \reg_do_reg_n_0_[15]\, - R => '0' - ); -\reg_do_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => reg_do(1), - Q => \reg_do_reg_n_0_[1]\, - R => '0' - ); -\reg_do_reg[2]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => reg_do(2), - Q => \reg_do_reg_n_0_[2]\, - R => '0' - ); -\reg_do_reg[3]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => reg_do(3), - Q => \reg_do_reg_n_0_[3]\, - R => '0' - ); -\reg_do_reg[4]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => reg_do(4), - Q => \reg_do_reg_n_0_[4]\, - R => '0' - ); -\reg_do_reg[5]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => reg_do(5), - Q => \reg_do_reg_n_0_[5]\, - R => '0' - ); -\reg_do_reg[6]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => reg_do(6), - Q => \reg_do_reg_n_0_[6]\, - R => '0' - ); -\reg_do_reg[7]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => reg_do(7), - Q => \reg_do_reg_n_0_[7]\, - R => '0' - ); -\reg_do_reg[8]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => reg_do(8), - Q => \reg_do_reg_n_0_[8]\, - R => '0' - ); -\reg_do_reg[9]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => reg_do(9), - Q => \reg_do_reg_n_0_[9]\, - R => '0' - ); -reg_drdy_i_1: unisim.vcomponents.LUT6 - generic map( - INIT => X"0000800000000000" - ) - port map ( - I0 => s_den_o_INST_0_i_1_n_0, - I1 => \^sl_iport_i\(12), - I2 => \^sl_iport_i\(13), - I3 => \^sl_iport_i\(14), - I4 => \^sl_iport_i\(0), - I5 => \^sl_iport_i\(2), - O => reg_drdy_i_1_n_0 - ); -reg_drdy_reg: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => reg_drdy_i_1_n_0, - Q => reg_drdy, - R => '0' - ); -\reg_test[15]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"8000000000000000" - ) - port map ( - I0 => s_den_o_INST_0_i_1_n_0, - I1 => \^sl_iport_i\(12), - I2 => \^sl_iport_i\(13), - I3 => \^sl_iport_i\(14), - I4 => \^sl_iport_i\(3), - I5 => \^sl_iport_i\(2), - O => reg_test0 - ); -\reg_test_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^sl_iport_i\(1), - CE => reg_test0, - D => \^sl_iport_i\(21), - Q => reg_test(0), - R => '0' - ); -\reg_test_reg[10]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^sl_iport_i\(1), - CE => reg_test0, - D => \^sl_iport_i\(31), - Q => reg_test(10), - R => '0' - ); -\reg_test_reg[11]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^sl_iport_i\(1), - CE => reg_test0, - D => \^sl_iport_i\(32), - Q => reg_test(11), - R => '0' - ); -\reg_test_reg[12]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^sl_iport_i\(1), - CE => reg_test0, - D => \^sl_iport_i\(33), - Q => reg_test(12), - R => '0' - ); -\reg_test_reg[13]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^sl_iport_i\(1), - CE => reg_test0, - D => \^sl_iport_i\(34), - Q => reg_test(13), - R => '0' - ); -\reg_test_reg[14]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^sl_iport_i\(1), - CE => reg_test0, - D => \^sl_iport_i\(35), - Q => reg_test(14), - R => '0' - ); -\reg_test_reg[15]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^sl_iport_i\(1), - CE => reg_test0, - D => \^sl_iport_i\(36), - Q => reg_test(15), - R => '0' - ); -\reg_test_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^sl_iport_i\(1), - CE => reg_test0, - D => \^sl_iport_i\(22), - Q => reg_test(1), - R => '0' - ); -\reg_test_reg[2]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^sl_iport_i\(1), - CE => reg_test0, - D => \^sl_iport_i\(23), - Q => reg_test(2), - R => '0' - ); -\reg_test_reg[3]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^sl_iport_i\(1), - CE => reg_test0, - D => \^sl_iport_i\(24), - Q => reg_test(3), - R => '0' - ); -\reg_test_reg[4]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^sl_iport_i\(1), - CE => reg_test0, - D => \^sl_iport_i\(25), - Q => reg_test(4), - R => '0' - ); -\reg_test_reg[5]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^sl_iport_i\(1), - CE => reg_test0, - D => \^sl_iport_i\(26), - Q => reg_test(5), - R => '0' - ); -\reg_test_reg[6]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^sl_iport_i\(1), - CE => reg_test0, - D => \^sl_iport_i\(27), - Q => reg_test(6), - R => '0' - ); -\reg_test_reg[7]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^sl_iport_i\(1), - CE => reg_test0, - D => \^sl_iport_i\(28), - Q => reg_test(7), - R => '0' - ); -\reg_test_reg[8]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^sl_iport_i\(1), - CE => reg_test0, - D => \^sl_iport_i\(29), - Q => reg_test(8), - R => '0' - ); -\reg_test_reg[9]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => \^sl_iport_i\(1), - CE => reg_test0, - D => \^sl_iport_i\(30), - Q => reg_test(9), - R => '0' - ); -s_den_o_INST_0: unisim.vcomponents.LUT5 - generic map( - INIT => X"7FFF0000" - ) - port map ( - I0 => s_den_o_INST_0_i_1_n_0, - I1 => \^sl_iport_i\(12), - I2 => \^sl_iport_i\(13), - I3 => \^sl_iport_i\(14), - I4 => \^sl_iport_i\(2), - O => s_den_o - ); -s_den_o_INST_0_i_1: unisim.vcomponents.LUT6 - generic map( - INIT => X"8000000000000000" - ) - port map ( - I0 => \^sl_iport_i\(15), - I1 => \^sl_iport_i\(16), - I2 => \^sl_iport_i\(17), - I3 => \^sl_iport_i\(18), - I4 => \^sl_iport_i\(20), - I5 => \^sl_iport_i\(19), - O => s_den_o_INST_0_i_1_n_0 - ); -\sl_oport_o[0]_INST_0\: unisim.vcomponents.LUT2 - generic map( - INIT => X"E" - ) - port map ( - I0 => reg_drdy, - I1 => s_drdy_i, - O => sl_oport_o(0) - ); -\sl_oport_o[10]_INST_0\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => \reg_do_reg_n_0_[9]\, - I1 => reg_drdy, - I2 => s_do_i(9), - O => sl_oport_o(10) - ); -\sl_oport_o[11]_INST_0\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => \reg_do_reg_n_0_[10]\, - I1 => reg_drdy, - I2 => s_do_i(10), - O => sl_oport_o(11) - ); -\sl_oport_o[12]_INST_0\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => \reg_do_reg_n_0_[11]\, - I1 => reg_drdy, - I2 => s_do_i(11), - O => sl_oport_o(12) - ); -\sl_oport_o[13]_INST_0\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => \reg_do_reg_n_0_[12]\, - I1 => reg_drdy, - I2 => s_do_i(12), - O => sl_oport_o(13) - ); -\sl_oport_o[14]_INST_0\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => \reg_do_reg_n_0_[13]\, - I1 => reg_drdy, - I2 => s_do_i(13), - O => sl_oport_o(14) - ); -\sl_oport_o[15]_INST_0\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => \reg_do_reg_n_0_[14]\, - I1 => reg_drdy, - I2 => s_do_i(14), - O => sl_oport_o(15) - ); -\sl_oport_o[16]_INST_0\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => \reg_do_reg_n_0_[15]\, - I1 => reg_drdy, - I2 => s_do_i(15), - O => sl_oport_o(16) - ); -\sl_oport_o[1]_INST_0\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => \reg_do_reg_n_0_[0]\, - I1 => reg_drdy, - I2 => s_do_i(0), - O => sl_oport_o(1) - ); -\sl_oport_o[2]_INST_0\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => \reg_do_reg_n_0_[1]\, - I1 => reg_drdy, - I2 => s_do_i(1), - O => sl_oport_o(2) - ); -\sl_oport_o[3]_INST_0\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => \reg_do_reg_n_0_[2]\, - I1 => reg_drdy, - I2 => s_do_i(2), - O => sl_oport_o(3) - ); -\sl_oport_o[4]_INST_0\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => \reg_do_reg_n_0_[3]\, - I1 => reg_drdy, - I2 => s_do_i(3), - O => sl_oport_o(4) - ); -\sl_oport_o[5]_INST_0\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => \reg_do_reg_n_0_[4]\, - I1 => reg_drdy, - I2 => s_do_i(4), - O => sl_oport_o(5) - ); -\sl_oport_o[6]_INST_0\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => \reg_do_reg_n_0_[5]\, - I1 => reg_drdy, - I2 => s_do_i(5), - O => sl_oport_o(6) - ); -\sl_oport_o[7]_INST_0\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => \reg_do_reg_n_0_[6]\, - I1 => reg_drdy, - I2 => s_do_i(6), - O => sl_oport_o(7) - ); -\sl_oport_o[8]_INST_0\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => \reg_do_reg_n_0_[7]\, - I1 => reg_drdy, - I2 => s_do_i(7), - O => sl_oport_o(8) - ); -\sl_oport_o[9]_INST_0\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => \reg_do_reg_n_0_[8]\, - I1 => reg_drdy, - I2 => s_do_i(8), - O => sl_oport_o(9) - ); -\uuid_stamp_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(0), - Q => uuid_stamp(0), - R => '0' - ); -\uuid_stamp_reg[100]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(100), - Q => uuid_stamp(100), - R => '0' - ); -\uuid_stamp_reg[101]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(101), - Q => uuid_stamp(101), - R => '0' - ); -\uuid_stamp_reg[102]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(102), - Q => uuid_stamp(102), - R => '0' - ); -\uuid_stamp_reg[103]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(103), - Q => uuid_stamp(103), - R => '0' - ); -\uuid_stamp_reg[104]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(104), - Q => uuid_stamp(104), - R => '0' - ); -\uuid_stamp_reg[105]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(105), - Q => uuid_stamp(105), - R => '0' - ); -\uuid_stamp_reg[106]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(106), - Q => uuid_stamp(106), - R => '0' - ); -\uuid_stamp_reg[107]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(107), - Q => uuid_stamp(107), - R => '0' - ); -\uuid_stamp_reg[108]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(108), - Q => uuid_stamp(108), - R => '0' - ); -\uuid_stamp_reg[109]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(109), - Q => uuid_stamp(109), - R => '0' - ); -\uuid_stamp_reg[10]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(10), - Q => uuid_stamp(10), - R => '0' - ); -\uuid_stamp_reg[110]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(110), - Q => uuid_stamp(110), - R => '0' - ); -\uuid_stamp_reg[111]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(111), - Q => uuid_stamp(111), - R => '0' - ); -\uuid_stamp_reg[112]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(112), - Q => uuid_stamp(112), - R => '0' - ); -\uuid_stamp_reg[113]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(113), - Q => uuid_stamp(113), - R => '0' - ); -\uuid_stamp_reg[114]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(114), - Q => uuid_stamp(114), - R => '0' - ); -\uuid_stamp_reg[115]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(115), - Q => uuid_stamp(115), - R => '0' - ); -\uuid_stamp_reg[116]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(116), - Q => uuid_stamp(116), - R => '0' - ); -\uuid_stamp_reg[117]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(117), - Q => uuid_stamp(117), - R => '0' - ); -\uuid_stamp_reg[118]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(118), - Q => uuid_stamp(118), - R => '0' - ); -\uuid_stamp_reg[119]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(119), - Q => uuid_stamp(119), - R => '0' - ); -\uuid_stamp_reg[11]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(11), - Q => uuid_stamp(11), - R => '0' - ); -\uuid_stamp_reg[120]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(120), - Q => uuid_stamp(120), - R => '0' - ); -\uuid_stamp_reg[121]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(121), - Q => uuid_stamp(121), - R => '0' - ); -\uuid_stamp_reg[122]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(122), - Q => uuid_stamp(122), - R => '0' - ); -\uuid_stamp_reg[123]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(123), - Q => uuid_stamp(123), - R => '0' - ); -\uuid_stamp_reg[124]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(124), - Q => uuid_stamp(124), - R => '0' - ); -\uuid_stamp_reg[125]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(125), - Q => uuid_stamp(125), - R => '0' - ); -\uuid_stamp_reg[126]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(126), - Q => uuid_stamp(126), - R => '0' - ); -\uuid_stamp_reg[127]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(127), - Q => uuid_stamp(127), - R => '0' - ); -\uuid_stamp_reg[12]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(12), - Q => uuid_stamp(12), - R => '0' - ); -\uuid_stamp_reg[13]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(13), - Q => uuid_stamp(13), - R => '0' - ); -\uuid_stamp_reg[14]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(14), - Q => uuid_stamp(14), - R => '0' - ); -\uuid_stamp_reg[15]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(15), - Q => uuid_stamp(15), - R => '0' - ); -\uuid_stamp_reg[16]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(16), - Q => uuid_stamp(16), - R => '0' - ); -\uuid_stamp_reg[17]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(17), - Q => uuid_stamp(17), - R => '0' - ); -\uuid_stamp_reg[18]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(18), - Q => uuid_stamp(18), - R => '0' - ); -\uuid_stamp_reg[19]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(19), - Q => uuid_stamp(19), - R => '0' - ); -\uuid_stamp_reg[1]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(1), - Q => uuid_stamp(1), - R => '0' - ); -\uuid_stamp_reg[20]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(20), - Q => uuid_stamp(20), - R => '0' - ); -\uuid_stamp_reg[21]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(21), - Q => uuid_stamp(21), - R => '0' - ); -\uuid_stamp_reg[22]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(22), - Q => uuid_stamp(22), - R => '0' - ); -\uuid_stamp_reg[23]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(23), - Q => uuid_stamp(23), - R => '0' - ); -\uuid_stamp_reg[24]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(24), - Q => uuid_stamp(24), - R => '0' - ); -\uuid_stamp_reg[25]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(25), - Q => uuid_stamp(25), - R => '0' - ); -\uuid_stamp_reg[26]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(26), - Q => uuid_stamp(26), - R => '0' - ); -\uuid_stamp_reg[27]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(27), - Q => uuid_stamp(27), - R => '0' - ); -\uuid_stamp_reg[28]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(28), - Q => uuid_stamp(28), - R => '0' - ); -\uuid_stamp_reg[29]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(29), - Q => uuid_stamp(29), - R => '0' - ); -\uuid_stamp_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(2), - Q => uuid_stamp(2), - R => '0' - ); -\uuid_stamp_reg[30]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(30), - Q => uuid_stamp(30), - R => '0' - ); -\uuid_stamp_reg[31]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(31), - Q => uuid_stamp(31), - R => '0' - ); -\uuid_stamp_reg[32]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(32), - Q => uuid_stamp(32), - R => '0' - ); -\uuid_stamp_reg[33]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(33), - Q => uuid_stamp(33), - R => '0' - ); -\uuid_stamp_reg[34]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(34), - Q => uuid_stamp(34), - R => '0' - ); -\uuid_stamp_reg[35]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(35), - Q => uuid_stamp(35), - R => '0' - ); -\uuid_stamp_reg[36]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(36), - Q => uuid_stamp(36), - R => '0' - ); -\uuid_stamp_reg[37]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(37), - Q => uuid_stamp(37), - R => '0' - ); -\uuid_stamp_reg[38]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(38), - Q => uuid_stamp(38), - R => '0' - ); -\uuid_stamp_reg[39]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(39), - Q => uuid_stamp(39), - R => '0' - ); -\uuid_stamp_reg[3]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(3), - Q => uuid_stamp(3), - R => '0' - ); -\uuid_stamp_reg[40]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(40), - Q => uuid_stamp(40), - R => '0' - ); -\uuid_stamp_reg[41]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(41), - Q => uuid_stamp(41), - R => '0' - ); -\uuid_stamp_reg[42]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(42), - Q => uuid_stamp(42), - R => '0' - ); -\uuid_stamp_reg[43]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(43), - Q => uuid_stamp(43), - R => '0' - ); -\uuid_stamp_reg[44]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(44), - Q => uuid_stamp(44), - R => '0' - ); -\uuid_stamp_reg[45]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(45), - Q => uuid_stamp(45), - R => '0' - ); -\uuid_stamp_reg[46]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(46), - Q => uuid_stamp(46), - R => '0' - ); -\uuid_stamp_reg[47]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(47), - Q => uuid_stamp(47), - R => '0' - ); -\uuid_stamp_reg[48]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(48), - Q => uuid_stamp(48), - R => '0' - ); -\uuid_stamp_reg[49]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(49), - Q => uuid_stamp(49), - R => '0' - ); -\uuid_stamp_reg[4]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(4), - Q => uuid_stamp(4), - R => '0' - ); -\uuid_stamp_reg[50]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(50), - Q => uuid_stamp(50), - R => '0' - ); -\uuid_stamp_reg[51]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(51), - Q => uuid_stamp(51), - R => '0' - ); -\uuid_stamp_reg[52]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(52), - Q => uuid_stamp(52), - R => '0' - ); -\uuid_stamp_reg[53]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(53), - Q => uuid_stamp(53), - R => '0' - ); -\uuid_stamp_reg[54]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(54), - Q => uuid_stamp(54), - R => '0' - ); -\uuid_stamp_reg[55]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(55), - Q => uuid_stamp(55), - R => '0' - ); -\uuid_stamp_reg[56]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(56), - Q => uuid_stamp(56), - R => '0' - ); -\uuid_stamp_reg[57]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(57), - Q => uuid_stamp(57), - R => '0' - ); -\uuid_stamp_reg[58]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(58), - Q => uuid_stamp(58), - R => '0' - ); -\uuid_stamp_reg[59]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(59), - Q => uuid_stamp(59), - R => '0' - ); -\uuid_stamp_reg[5]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(5), - Q => uuid_stamp(5), - R => '0' - ); -\uuid_stamp_reg[60]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(60), - Q => uuid_stamp(60), - R => '0' - ); -\uuid_stamp_reg[61]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(61), - Q => uuid_stamp(61), - R => '0' - ); -\uuid_stamp_reg[62]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(62), - Q => uuid_stamp(62), - R => '0' - ); -\uuid_stamp_reg[63]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(63), - Q => uuid_stamp(63), - R => '0' - ); -\uuid_stamp_reg[64]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(64), - Q => uuid_stamp(64), - R => '0' - ); -\uuid_stamp_reg[65]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(65), - Q => uuid_stamp(65), - R => '0' - ); -\uuid_stamp_reg[66]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(66), - Q => uuid_stamp(66), - R => '0' - ); -\uuid_stamp_reg[67]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(67), - Q => uuid_stamp(67), - R => '0' - ); -\uuid_stamp_reg[68]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(68), - Q => uuid_stamp(68), - R => '0' - ); -\uuid_stamp_reg[69]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(69), - Q => uuid_stamp(69), - R => '0' - ); -\uuid_stamp_reg[6]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(6), - Q => uuid_stamp(6), - R => '0' - ); -\uuid_stamp_reg[70]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(70), - Q => uuid_stamp(70), - R => '0' - ); -\uuid_stamp_reg[71]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(71), - Q => uuid_stamp(71), - R => '0' - ); -\uuid_stamp_reg[72]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(72), - Q => uuid_stamp(72), - R => '0' - ); -\uuid_stamp_reg[73]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(73), - Q => uuid_stamp(73), - R => '0' - ); -\uuid_stamp_reg[74]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(74), - Q => uuid_stamp(74), - R => '0' - ); -\uuid_stamp_reg[75]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(75), - Q => uuid_stamp(75), - R => '0' - ); -\uuid_stamp_reg[76]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(76), - Q => uuid_stamp(76), - R => '0' - ); -\uuid_stamp_reg[77]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(77), - Q => uuid_stamp(77), - R => '0' - ); -\uuid_stamp_reg[78]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(78), - Q => uuid_stamp(78), - R => '0' - ); -\uuid_stamp_reg[79]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(79), - Q => uuid_stamp(79), - R => '0' - ); -\uuid_stamp_reg[7]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(7), - Q => uuid_stamp(7), - R => '0' - ); -\uuid_stamp_reg[80]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(80), - Q => uuid_stamp(80), - R => '0' - ); -\uuid_stamp_reg[81]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(81), - Q => uuid_stamp(81), - R => '0' - ); -\uuid_stamp_reg[82]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(82), - Q => uuid_stamp(82), - R => '0' - ); -\uuid_stamp_reg[83]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(83), - Q => uuid_stamp(83), - R => '0' - ); -\uuid_stamp_reg[84]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(84), - Q => uuid_stamp(84), - R => '0' - ); -\uuid_stamp_reg[85]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(85), - Q => uuid_stamp(85), - R => '0' - ); -\uuid_stamp_reg[86]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(86), - Q => uuid_stamp(86), - R => '0' - ); -\uuid_stamp_reg[87]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(87), - Q => uuid_stamp(87), - R => '0' - ); -\uuid_stamp_reg[88]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(88), - Q => uuid_stamp(88), - R => '0' - ); -\uuid_stamp_reg[89]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(89), - Q => uuid_stamp(89), - R => '0' - ); -\uuid_stamp_reg[8]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(8), - Q => uuid_stamp(8), - R => '0' - ); -\uuid_stamp_reg[90]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(90), - Q => uuid_stamp(90), - R => '0' - ); -\uuid_stamp_reg[91]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(91), - Q => uuid_stamp(91), - R => '0' - ); -\uuid_stamp_reg[92]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(92), - Q => uuid_stamp(92), - R => '0' - ); -\uuid_stamp_reg[93]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(93), - Q => uuid_stamp(93), - R => '0' - ); -\uuid_stamp_reg[94]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(94), - Q => uuid_stamp(94), - R => '0' - ); -\uuid_stamp_reg[95]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(95), - Q => uuid_stamp(95), - R => '0' - ); -\uuid_stamp_reg[96]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(96), - Q => uuid_stamp(96), - R => '0' - ); -\uuid_stamp_reg[97]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(97), - Q => uuid_stamp(97), - R => '0' - ); -\uuid_stamp_reg[98]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(98), - Q => uuid_stamp(98), - R => '0' - ); -\uuid_stamp_reg[99]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(99), - Q => uuid_stamp(99), - R => '0' - ); -\uuid_stamp_reg[9]\: unisim.vcomponents.FDRE - port map ( - C => \^sl_iport_i\(1), - CE => '1', - D => uuid_stamp(9), - Q => uuid_stamp(9), - R => '0' - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity vio_0_vio_v3_0_19_probe_out_all is - port ( - probe_out0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); - \Probe_out_reg_int_reg[15]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); - SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - in0 : in STD_LOGIC; - \^clk\ : in STD_LOGIC; - CLK : in STD_LOGIC; - s_daddr_o : in STD_LOGIC_VECTOR ( 10 downto 0 ); - \G_PROBE_OUT[0].wr_probe_out_reg[0]_0\ : in STD_LOGIC; - s_den_o : in STD_LOGIC; - s_dwe_o : in STD_LOGIC; - \G_PROBE_OUT[0].wr_probe_out_reg[0]_1\ : in STD_LOGIC; - \xsdb_wr__0\ : in STD_LOGIC; - \G_PROBE_OUT[0].wr_probe_out_reg[0]_2\ : in STD_LOGIC; - internal_cnt_rst : in STD_LOGIC; - Q : in STD_LOGIC_VECTOR ( 15 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of vio_0_vio_v3_0_19_probe_out_all : entity is "vio_v3_0_19_probe_out_all"; -end vio_0_vio_v3_0_19_probe_out_all; - -architecture STRUCTURE of vio_0_vio_v3_0_19_probe_out_all is - signal Bus_Data_out_int : STD_LOGIC_VECTOR ( 15 downto 0 ); - signal Committ_1 : STD_LOGIC; - attribute async_reg : string; - attribute async_reg of Committ_1 : signal is "true"; - signal Committ_2 : STD_LOGIC; - attribute async_reg of Committ_2 : signal is "true"; - signal \G_PROBE_OUT[0].wr_probe_out[0]_i_1_n_0\ : STD_LOGIC; - signal wr_probe_out : STD_LOGIC; - attribute ASYNC_REG_boolean : boolean; - attribute ASYNC_REG_boolean of Committ_1_reg : label is std.standard.true; - attribute KEEP : string; - attribute KEEP of Committ_1_reg : label is "yes"; - attribute ASYNC_REG_boolean of Committ_2_reg : label is std.standard.true; - attribute KEEP of Committ_2_reg : label is "yes"; -begin -Committ_1_reg: unisim.vcomponents.FDRE - port map ( - C => \^clk\, - CE => '1', - D => in0, - Q => Committ_1, - R => '0' - ); -Committ_2_reg: unisim.vcomponents.FDRE - port map ( - C => \^clk\, - CE => '1', - D => Committ_1, - Q => Committ_2, - R => '0' - ); -\G_PROBE_OUT[0].PROBE_OUT0_INST\: entity work.vio_0_vio_v3_0_19_probe_out_one - port map ( - \Bus_Data_out_int_reg[15]_0\(15 downto 0) => Bus_Data_out_int(15 downto 0), - CLK => CLK, - E(0) => wr_probe_out, - \Probe_out_reg[31]_0\(0) => Committ_2, - Q(15 downto 0) => Q(15 downto 0), - SR(0) => SR(0), - \addr_count_reg[0]_0\ => \G_PROBE_OUT[0].wr_probe_out_reg[0]_0\, - \^clk\ => \^clk\, - internal_cnt_rst => internal_cnt_rst, - probe_out0(31 downto 0) => probe_out0(31 downto 0), - s_daddr_o(10 downto 0) => s_daddr_o(10 downto 0), - s_den_o => s_den_o, - s_dwe_o => s_dwe_o - ); -\G_PROBE_OUT[0].wr_probe_out[0]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0000004000000000" - ) - port map ( - I0 => \G_PROBE_OUT[0].wr_probe_out_reg[0]_1\, - I1 => \xsdb_wr__0\, - I2 => s_daddr_o(3), - I3 => s_daddr_o(0), - I4 => \G_PROBE_OUT[0].wr_probe_out_reg[0]_2\, - I5 => \G_PROBE_OUT[0].wr_probe_out_reg[0]_0\, - O => \G_PROBE_OUT[0].wr_probe_out[0]_i_1_n_0\ - ); -\G_PROBE_OUT[0].wr_probe_out_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => \G_PROBE_OUT[0].wr_probe_out[0]_i_1_n_0\, - Q => wr_probe_out, - R => '0' - ); -\Probe_out_reg_int_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => Bus_Data_out_int(0), - Q => \Probe_out_reg_int_reg[15]_0\(0), - R => '0' - ); -\Probe_out_reg_int_reg[10]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => Bus_Data_out_int(10), - Q => \Probe_out_reg_int_reg[15]_0\(10), - R => '0' - ); -\Probe_out_reg_int_reg[11]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => Bus_Data_out_int(11), - Q => \Probe_out_reg_int_reg[15]_0\(11), - R => '0' - ); -\Probe_out_reg_int_reg[12]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => Bus_Data_out_int(12), - Q => \Probe_out_reg_int_reg[15]_0\(12), - R => '0' - ); -\Probe_out_reg_int_reg[13]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => Bus_Data_out_int(13), - Q => \Probe_out_reg_int_reg[15]_0\(13), - R => '0' - ); -\Probe_out_reg_int_reg[14]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => Bus_Data_out_int(14), - Q => \Probe_out_reg_int_reg[15]_0\(14), - R => '0' - ); -\Probe_out_reg_int_reg[15]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => Bus_Data_out_int(15), - Q => \Probe_out_reg_int_reg[15]_0\(15), - R => '0' - ); -\Probe_out_reg_int_reg[1]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => Bus_Data_out_int(1), - Q => \Probe_out_reg_int_reg[15]_0\(1), - R => '0' - ); -\Probe_out_reg_int_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => Bus_Data_out_int(2), - Q => \Probe_out_reg_int_reg[15]_0\(2), - R => '0' - ); -\Probe_out_reg_int_reg[3]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => Bus_Data_out_int(3), - Q => \Probe_out_reg_int_reg[15]_0\(3), - R => '0' - ); -\Probe_out_reg_int_reg[4]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => Bus_Data_out_int(4), - Q => \Probe_out_reg_int_reg[15]_0\(4), - R => '0' - ); -\Probe_out_reg_int_reg[5]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => Bus_Data_out_int(5), - Q => \Probe_out_reg_int_reg[15]_0\(5), - R => '0' - ); -\Probe_out_reg_int_reg[6]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => Bus_Data_out_int(6), - Q => \Probe_out_reg_int_reg[15]_0\(6), - R => '0' - ); -\Probe_out_reg_int_reg[7]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => Bus_Data_out_int(7), - Q => \Probe_out_reg_int_reg[15]_0\(7), - R => '0' - ); -\Probe_out_reg_int_reg[8]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => Bus_Data_out_int(8), - Q => \Probe_out_reg_int_reg[15]_0\(8), - R => '0' - ); -\Probe_out_reg_int_reg[9]\: unisim.vcomponents.FDRE - port map ( - C => CLK, - CE => '1', - D => Bus_Data_out_int(9), - Q => \Probe_out_reg_int_reg[15]_0\(9), - R => '0' - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity vio_0_vio_v3_0_19_vio is - port ( - clk : in STD_LOGIC; - probe_in0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); - probe_in1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); - probe_in2 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in3 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in4 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in5 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in6 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in7 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in8 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in9 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in10 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in11 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in12 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in13 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in14 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in15 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in16 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in17 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in18 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in19 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in20 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in21 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in22 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in23 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in24 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in25 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in26 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in27 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in28 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in29 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in30 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in31 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in32 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in33 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in34 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in35 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in36 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in37 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in38 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in39 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in40 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in41 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in42 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in43 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in44 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in45 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in46 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in47 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in48 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in49 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in50 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in51 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in52 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in53 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in54 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in55 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in56 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in57 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in58 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in59 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in60 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in61 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in62 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in63 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in64 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in65 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in66 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in67 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in68 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in69 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in70 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in71 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in72 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in73 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in74 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in75 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in76 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in77 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in78 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in79 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in80 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in81 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in82 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in83 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in84 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in85 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in86 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in87 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in88 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in89 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in90 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in91 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in92 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in93 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in94 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in95 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in96 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in97 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in98 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in99 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in100 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in101 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in102 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in103 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in104 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in105 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in106 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in107 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in108 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in109 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in110 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in111 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in112 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in113 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in114 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in115 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in116 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in117 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in118 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in119 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in120 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in121 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in122 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in123 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in124 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in125 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in126 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in127 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in128 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in129 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in130 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in131 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in132 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in133 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in134 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in135 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in136 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in137 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in138 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in139 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in140 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in141 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in142 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in143 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in144 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in145 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in146 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in147 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in148 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in149 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in150 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in151 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in152 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in153 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in154 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in155 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in156 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in157 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in158 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in159 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in160 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in161 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in162 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in163 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in164 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in165 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in166 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in167 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in168 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in169 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in170 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in171 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in172 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in173 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in174 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in175 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in176 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in177 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in178 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in179 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in180 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in181 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in182 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in183 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in184 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in185 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in186 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in187 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in188 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in189 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in190 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in191 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in192 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in193 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in194 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in195 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in196 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in197 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in198 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in199 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in200 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in201 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in202 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in203 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in204 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in205 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in206 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in207 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in208 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in209 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in210 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in211 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in212 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in213 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in214 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in215 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in216 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in217 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in218 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in219 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in220 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in221 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in222 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in223 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in224 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in225 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in226 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in227 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in228 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in229 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in230 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in231 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in232 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in233 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in234 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in235 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in236 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in237 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in238 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in239 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in240 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in241 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in242 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in243 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in244 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in245 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in246 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in247 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in248 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in249 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in250 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in251 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in252 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in253 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in254 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in255 : in STD_LOGIC_VECTOR ( 0 to 0 ); - sl_iport0 : in STD_LOGIC_VECTOR ( 36 downto 0 ); - sl_oport0 : out STD_LOGIC_VECTOR ( 16 downto 0 ); - probe_out0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); - probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out3 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out4 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out5 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out6 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out7 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out9 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out10 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out11 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out12 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out13 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out15 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out16 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out17 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out18 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out19 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out20 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out21 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out22 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out23 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out24 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out25 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out26 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out27 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out28 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out29 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out30 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out31 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out32 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out33 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out34 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out35 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out36 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out37 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out38 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out39 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out40 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out41 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out42 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out43 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out44 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out45 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out46 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out47 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out48 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out49 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out50 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out51 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out52 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out53 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out54 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out55 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out56 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out57 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out58 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out59 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out60 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out61 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out62 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out63 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out64 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out65 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out66 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out67 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out68 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out69 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out70 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out71 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out72 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out73 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out74 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out75 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out76 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out77 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out78 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out79 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out80 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out81 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out82 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out83 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out84 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out85 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out86 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out87 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out88 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out89 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out90 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out91 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out92 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out93 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out94 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out95 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out96 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out97 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out98 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out99 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out100 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out101 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out102 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out103 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out104 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out105 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out106 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out107 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out108 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out109 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out110 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out111 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out112 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out113 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out114 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out115 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out116 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out117 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out118 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out119 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out120 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out121 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out122 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out123 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out124 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out125 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out126 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out127 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out128 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out129 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out130 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out131 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out132 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out133 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out134 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out135 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out136 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out137 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out138 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out139 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out140 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out141 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out142 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out143 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out144 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out145 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out146 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out147 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out148 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out149 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out150 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out151 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out152 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out153 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out154 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out155 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out156 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out157 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out158 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out159 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out160 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out161 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out162 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out163 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out164 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out165 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out166 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out167 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out168 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out169 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out170 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out171 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out172 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out173 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out174 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out175 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out176 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out177 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out178 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out179 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out180 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out181 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out182 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out183 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out184 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out185 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out186 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out187 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out188 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out189 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out190 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out191 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out192 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out193 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out194 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out195 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out196 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out197 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out198 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out199 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out200 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out201 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out202 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out203 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out204 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out205 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out206 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out207 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out208 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out209 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out210 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out211 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out212 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out213 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out214 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out215 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out216 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out217 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out218 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out219 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out220 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out221 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out222 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out223 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out224 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out225 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out226 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out227 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out228 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out229 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out230 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out231 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out232 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out233 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out234 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out235 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out236 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out237 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out238 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out239 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out240 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out241 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out242 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out243 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out244 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out245 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out246 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out247 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out248 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out249 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out250 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out251 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out252 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out253 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out254 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out255 : out STD_LOGIC_VECTOR ( 0 to 0 ) - ); - attribute C_BUILD_REVISION : integer; - attribute C_BUILD_REVISION of vio_0_vio_v3_0_19_vio : entity is 0; - attribute C_BUS_ADDR_WIDTH : integer; - attribute C_BUS_ADDR_WIDTH of vio_0_vio_v3_0_19_vio : entity is 17; - attribute C_BUS_DATA_WIDTH : integer; - attribute C_BUS_DATA_WIDTH of vio_0_vio_v3_0_19_vio : entity is 16; - attribute C_CORE_INFO1 : string; - attribute C_CORE_INFO1 of vio_0_vio_v3_0_19_vio : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute C_CORE_INFO2 : string; - attribute C_CORE_INFO2 of vio_0_vio_v3_0_19_vio : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute C_CORE_MAJOR_VER : integer; - attribute C_CORE_MAJOR_VER of vio_0_vio_v3_0_19_vio : entity is 2; - attribute C_CORE_MINOR_ALPHA_VER : integer; - attribute C_CORE_MINOR_ALPHA_VER of vio_0_vio_v3_0_19_vio : entity is 97; - attribute C_CORE_MINOR_VER : integer; - attribute C_CORE_MINOR_VER of vio_0_vio_v3_0_19_vio : entity is 0; - attribute C_CORE_TYPE : integer; - attribute C_CORE_TYPE of vio_0_vio_v3_0_19_vio : entity is 2; - attribute C_CSE_DRV_VER : integer; - attribute C_CSE_DRV_VER of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_EN_PROBE_IN_ACTIVITY : integer; - attribute C_EN_PROBE_IN_ACTIVITY of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_EN_SYNCHRONIZATION : integer; - attribute C_EN_SYNCHRONIZATION of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_MAJOR_VERSION : integer; - attribute C_MAJOR_VERSION of vio_0_vio_v3_0_19_vio : entity is 2013; - attribute C_MAX_NUM_PROBE : integer; - attribute C_MAX_NUM_PROBE of vio_0_vio_v3_0_19_vio : entity is 256; - attribute C_MAX_WIDTH_PER_PROBE : integer; - attribute C_MAX_WIDTH_PER_PROBE of vio_0_vio_v3_0_19_vio : entity is 256; - attribute C_MINOR_VERSION : integer; - attribute C_MINOR_VERSION of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_NEXT_SLAVE : integer; - attribute C_NEXT_SLAVE of vio_0_vio_v3_0_19_vio : entity is 0; - attribute C_NUM_PROBE_IN : integer; - attribute C_NUM_PROBE_IN of vio_0_vio_v3_0_19_vio : entity is 2; - attribute C_NUM_PROBE_OUT : integer; - attribute C_NUM_PROBE_OUT of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PIPE_IFACE : integer; - attribute C_PIPE_IFACE of vio_0_vio_v3_0_19_vio : entity is 0; - attribute C_PROBE_IN0_WIDTH : integer; - attribute C_PROBE_IN0_WIDTH of vio_0_vio_v3_0_19_vio : entity is 32; - attribute C_PROBE_IN100_WIDTH : integer; - attribute C_PROBE_IN100_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN101_WIDTH : integer; - attribute C_PROBE_IN101_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN102_WIDTH : integer; - attribute C_PROBE_IN102_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN103_WIDTH : integer; - attribute C_PROBE_IN103_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN104_WIDTH : integer; - attribute C_PROBE_IN104_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN105_WIDTH : integer; - attribute C_PROBE_IN105_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN106_WIDTH : integer; - attribute C_PROBE_IN106_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN107_WIDTH : integer; - attribute C_PROBE_IN107_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN108_WIDTH : integer; - attribute C_PROBE_IN108_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN109_WIDTH : integer; - attribute C_PROBE_IN109_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN10_WIDTH : integer; - attribute C_PROBE_IN10_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN110_WIDTH : integer; - attribute C_PROBE_IN110_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN111_WIDTH : integer; - attribute C_PROBE_IN111_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN112_WIDTH : integer; - attribute C_PROBE_IN112_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN113_WIDTH : integer; - attribute C_PROBE_IN113_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN114_WIDTH : integer; - attribute C_PROBE_IN114_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN115_WIDTH : integer; - attribute C_PROBE_IN115_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN116_WIDTH : integer; - attribute C_PROBE_IN116_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN117_WIDTH : integer; - attribute C_PROBE_IN117_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN118_WIDTH : integer; - attribute C_PROBE_IN118_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN119_WIDTH : integer; - attribute C_PROBE_IN119_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN11_WIDTH : integer; - attribute C_PROBE_IN11_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN120_WIDTH : integer; - attribute C_PROBE_IN120_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN121_WIDTH : integer; - attribute C_PROBE_IN121_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN122_WIDTH : integer; - attribute C_PROBE_IN122_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN123_WIDTH : integer; - attribute C_PROBE_IN123_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN124_WIDTH : integer; - attribute C_PROBE_IN124_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN125_WIDTH : integer; - attribute C_PROBE_IN125_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN126_WIDTH : integer; - attribute C_PROBE_IN126_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN127_WIDTH : integer; - attribute C_PROBE_IN127_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN128_WIDTH : integer; - attribute C_PROBE_IN128_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN129_WIDTH : integer; - attribute C_PROBE_IN129_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN12_WIDTH : integer; - attribute C_PROBE_IN12_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN130_WIDTH : integer; - attribute C_PROBE_IN130_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN131_WIDTH : integer; - attribute C_PROBE_IN131_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN132_WIDTH : integer; - attribute C_PROBE_IN132_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN133_WIDTH : integer; - attribute C_PROBE_IN133_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN134_WIDTH : integer; - attribute C_PROBE_IN134_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN135_WIDTH : integer; - attribute C_PROBE_IN135_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN136_WIDTH : integer; - attribute C_PROBE_IN136_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN137_WIDTH : integer; - attribute C_PROBE_IN137_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN138_WIDTH : integer; - attribute C_PROBE_IN138_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN139_WIDTH : integer; - attribute C_PROBE_IN139_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN13_WIDTH : integer; - attribute C_PROBE_IN13_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN140_WIDTH : integer; - attribute C_PROBE_IN140_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN141_WIDTH : integer; - attribute C_PROBE_IN141_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN142_WIDTH : integer; - attribute C_PROBE_IN142_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN143_WIDTH : integer; - attribute C_PROBE_IN143_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN144_WIDTH : integer; - attribute C_PROBE_IN144_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN145_WIDTH : integer; - attribute C_PROBE_IN145_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN146_WIDTH : integer; - attribute C_PROBE_IN146_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN147_WIDTH : integer; - attribute C_PROBE_IN147_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN148_WIDTH : integer; - attribute C_PROBE_IN148_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN149_WIDTH : integer; - attribute C_PROBE_IN149_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN14_WIDTH : integer; - attribute C_PROBE_IN14_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN150_WIDTH : integer; - attribute C_PROBE_IN150_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN151_WIDTH : integer; - attribute C_PROBE_IN151_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN152_WIDTH : integer; - attribute C_PROBE_IN152_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN153_WIDTH : integer; - attribute C_PROBE_IN153_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN154_WIDTH : integer; - attribute C_PROBE_IN154_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN155_WIDTH : integer; - attribute C_PROBE_IN155_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN156_WIDTH : integer; - attribute C_PROBE_IN156_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN157_WIDTH : integer; - attribute C_PROBE_IN157_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN158_WIDTH : integer; - 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attribute C_PROBE_IN32_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN33_WIDTH : integer; - attribute C_PROBE_IN33_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN34_WIDTH : integer; - attribute C_PROBE_IN34_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN35_WIDTH : integer; - attribute C_PROBE_IN35_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN36_WIDTH : integer; - attribute C_PROBE_IN36_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN37_WIDTH : integer; - attribute C_PROBE_IN37_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN38_WIDTH : integer; - attribute C_PROBE_IN38_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN39_WIDTH : integer; - attribute C_PROBE_IN39_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN3_WIDTH : integer; - attribute C_PROBE_IN3_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN40_WIDTH : integer; - attribute C_PROBE_IN40_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN41_WIDTH : integer; - attribute C_PROBE_IN41_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN42_WIDTH : integer; - attribute C_PROBE_IN42_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN43_WIDTH : integer; - attribute C_PROBE_IN43_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN44_WIDTH : integer; - attribute C_PROBE_IN44_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN45_WIDTH : integer; - attribute C_PROBE_IN45_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN46_WIDTH : integer; - attribute C_PROBE_IN46_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN47_WIDTH : integer; - attribute C_PROBE_IN47_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN48_WIDTH : integer; - attribute C_PROBE_IN48_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN49_WIDTH : integer; - attribute C_PROBE_IN49_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN4_WIDTH : integer; - attribute C_PROBE_IN4_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN50_WIDTH : integer; - attribute C_PROBE_IN50_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN51_WIDTH : integer; - attribute C_PROBE_IN51_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN52_WIDTH : integer; - attribute C_PROBE_IN52_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN53_WIDTH : integer; - attribute C_PROBE_IN53_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN54_WIDTH : integer; - attribute C_PROBE_IN54_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN55_WIDTH : integer; - attribute C_PROBE_IN55_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN56_WIDTH : integer; - attribute C_PROBE_IN56_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN57_WIDTH : integer; - attribute C_PROBE_IN57_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN58_WIDTH : integer; - attribute C_PROBE_IN58_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN59_WIDTH : integer; - attribute C_PROBE_IN59_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN5_WIDTH : integer; - attribute C_PROBE_IN5_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN60_WIDTH : integer; - attribute C_PROBE_IN60_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN61_WIDTH : integer; - attribute C_PROBE_IN61_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN62_WIDTH : integer; - attribute C_PROBE_IN62_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN63_WIDTH : integer; - attribute C_PROBE_IN63_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN64_WIDTH : integer; - attribute C_PROBE_IN64_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN65_WIDTH : integer; - attribute C_PROBE_IN65_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN66_WIDTH : integer; - attribute C_PROBE_IN66_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN67_WIDTH : integer; - attribute C_PROBE_IN67_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN68_WIDTH : integer; - attribute C_PROBE_IN68_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN69_WIDTH : integer; - attribute C_PROBE_IN69_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN6_WIDTH : integer; - attribute C_PROBE_IN6_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN70_WIDTH : integer; - attribute C_PROBE_IN70_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN71_WIDTH : integer; - attribute C_PROBE_IN71_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN72_WIDTH : integer; - attribute C_PROBE_IN72_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN73_WIDTH : integer; - attribute C_PROBE_IN73_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN74_WIDTH : integer; - attribute C_PROBE_IN74_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN75_WIDTH : integer; - attribute C_PROBE_IN75_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN76_WIDTH : integer; - attribute C_PROBE_IN76_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN77_WIDTH : integer; - attribute C_PROBE_IN77_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN78_WIDTH : integer; - attribute C_PROBE_IN78_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN79_WIDTH : integer; - attribute C_PROBE_IN79_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN7_WIDTH : integer; - attribute C_PROBE_IN7_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN80_WIDTH : integer; - attribute C_PROBE_IN80_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN81_WIDTH : integer; - attribute C_PROBE_IN81_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN82_WIDTH : integer; - attribute C_PROBE_IN82_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN83_WIDTH : integer; - attribute C_PROBE_IN83_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN84_WIDTH : integer; - attribute C_PROBE_IN84_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN85_WIDTH : integer; - attribute C_PROBE_IN85_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN86_WIDTH : integer; - attribute C_PROBE_IN86_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN87_WIDTH : integer; - attribute C_PROBE_IN87_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN88_WIDTH : integer; - attribute C_PROBE_IN88_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN89_WIDTH : integer; - attribute C_PROBE_IN89_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN8_WIDTH : integer; - attribute C_PROBE_IN8_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN90_WIDTH : integer; - attribute C_PROBE_IN90_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN91_WIDTH : integer; - attribute C_PROBE_IN91_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN92_WIDTH : integer; - attribute C_PROBE_IN92_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN93_WIDTH : integer; - attribute C_PROBE_IN93_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN94_WIDTH : integer; - attribute C_PROBE_IN94_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN95_WIDTH : integer; - attribute C_PROBE_IN95_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN96_WIDTH : integer; - attribute C_PROBE_IN96_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN97_WIDTH : integer; - attribute C_PROBE_IN97_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN98_WIDTH : integer; - attribute C_PROBE_IN98_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN99_WIDTH : integer; - attribute C_PROBE_IN99_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_IN9_WIDTH : integer; - attribute C_PROBE_IN9_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT0_INIT_VAL : string; - attribute C_PROBE_OUT0_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "32'b00000000000000000000000000000000"; - attribute C_PROBE_OUT0_WIDTH : integer; - attribute C_PROBE_OUT0_WIDTH of vio_0_vio_v3_0_19_vio : entity is 32; - attribute C_PROBE_OUT100_INIT_VAL : string; - attribute C_PROBE_OUT100_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT100_WIDTH : integer; - attribute C_PROBE_OUT100_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT101_INIT_VAL : string; - attribute C_PROBE_OUT101_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT101_WIDTH : integer; - attribute C_PROBE_OUT101_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT102_INIT_VAL : string; - attribute C_PROBE_OUT102_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT102_WIDTH : integer; - attribute C_PROBE_OUT102_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT103_INIT_VAL : string; - attribute C_PROBE_OUT103_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT103_WIDTH : integer; - attribute C_PROBE_OUT103_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT104_INIT_VAL : string; - attribute C_PROBE_OUT104_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT104_WIDTH : integer; - attribute C_PROBE_OUT104_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT105_INIT_VAL : string; - attribute C_PROBE_OUT105_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT105_WIDTH : integer; - attribute C_PROBE_OUT105_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT106_INIT_VAL : string; - attribute C_PROBE_OUT106_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT106_WIDTH : integer; - attribute C_PROBE_OUT106_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT107_INIT_VAL : string; - attribute C_PROBE_OUT107_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT107_WIDTH : integer; - attribute C_PROBE_OUT107_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT108_INIT_VAL : string; - attribute C_PROBE_OUT108_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT108_WIDTH : integer; - attribute C_PROBE_OUT108_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT109_INIT_VAL : string; - attribute C_PROBE_OUT109_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT109_WIDTH : integer; - attribute C_PROBE_OUT109_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT10_INIT_VAL : string; - attribute C_PROBE_OUT10_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT10_WIDTH : integer; - attribute C_PROBE_OUT10_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT110_INIT_VAL : string; - attribute C_PROBE_OUT110_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT110_WIDTH : integer; - attribute C_PROBE_OUT110_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT111_INIT_VAL : string; - attribute C_PROBE_OUT111_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT111_WIDTH : integer; - attribute C_PROBE_OUT111_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT112_INIT_VAL : string; - attribute C_PROBE_OUT112_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT112_WIDTH : integer; - attribute C_PROBE_OUT112_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT113_INIT_VAL : string; - attribute C_PROBE_OUT113_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT113_WIDTH : integer; - attribute C_PROBE_OUT113_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT114_INIT_VAL : string; - attribute C_PROBE_OUT114_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT114_WIDTH : integer; - attribute C_PROBE_OUT114_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT115_INIT_VAL : string; - attribute C_PROBE_OUT115_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT115_WIDTH : integer; - attribute C_PROBE_OUT115_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT116_INIT_VAL : string; - attribute C_PROBE_OUT116_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT116_WIDTH : integer; - attribute C_PROBE_OUT116_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT117_INIT_VAL : string; - attribute C_PROBE_OUT117_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT117_WIDTH : integer; - attribute C_PROBE_OUT117_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT118_INIT_VAL : string; - attribute C_PROBE_OUT118_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT118_WIDTH : integer; - attribute C_PROBE_OUT118_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT119_INIT_VAL : string; - attribute C_PROBE_OUT119_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT119_WIDTH : integer; - attribute C_PROBE_OUT119_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT11_INIT_VAL : string; - attribute C_PROBE_OUT11_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT11_WIDTH : integer; - attribute C_PROBE_OUT11_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT120_INIT_VAL : string; - attribute C_PROBE_OUT120_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT120_WIDTH : integer; - attribute C_PROBE_OUT120_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT121_INIT_VAL : string; - attribute C_PROBE_OUT121_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT121_WIDTH : integer; - attribute C_PROBE_OUT121_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT122_INIT_VAL : string; - attribute C_PROBE_OUT122_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT122_WIDTH : integer; - attribute C_PROBE_OUT122_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT123_INIT_VAL : string; - attribute C_PROBE_OUT123_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT123_WIDTH : integer; - attribute C_PROBE_OUT123_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT124_INIT_VAL : string; - attribute C_PROBE_OUT124_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT124_WIDTH : integer; - attribute C_PROBE_OUT124_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT125_INIT_VAL : string; - attribute C_PROBE_OUT125_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT125_WIDTH : integer; - attribute C_PROBE_OUT125_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT126_INIT_VAL : string; - attribute C_PROBE_OUT126_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT126_WIDTH : integer; - attribute C_PROBE_OUT126_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT127_INIT_VAL : string; - attribute C_PROBE_OUT127_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT127_WIDTH : integer; - attribute C_PROBE_OUT127_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT128_INIT_VAL : string; - attribute C_PROBE_OUT128_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT128_WIDTH : integer; - attribute C_PROBE_OUT128_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT129_INIT_VAL : string; - attribute C_PROBE_OUT129_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT129_WIDTH : integer; - attribute C_PROBE_OUT129_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT12_INIT_VAL : string; - attribute C_PROBE_OUT12_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT12_WIDTH : integer; - attribute C_PROBE_OUT12_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT130_INIT_VAL : string; - attribute C_PROBE_OUT130_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT130_WIDTH : integer; - attribute C_PROBE_OUT130_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT131_INIT_VAL : string; - attribute C_PROBE_OUT131_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT131_WIDTH : integer; - attribute C_PROBE_OUT131_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT132_INIT_VAL : string; - attribute C_PROBE_OUT132_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT132_WIDTH : integer; - attribute C_PROBE_OUT132_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT133_INIT_VAL : string; - attribute C_PROBE_OUT133_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT133_WIDTH : integer; - attribute C_PROBE_OUT133_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT134_INIT_VAL : string; - attribute C_PROBE_OUT134_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT134_WIDTH : integer; - attribute C_PROBE_OUT134_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT135_INIT_VAL : string; - attribute C_PROBE_OUT135_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT135_WIDTH : integer; - attribute C_PROBE_OUT135_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT136_INIT_VAL : string; - attribute C_PROBE_OUT136_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT136_WIDTH : integer; - attribute C_PROBE_OUT136_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT137_INIT_VAL : string; - attribute C_PROBE_OUT137_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT137_WIDTH : integer; - attribute C_PROBE_OUT137_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT138_INIT_VAL : string; - attribute C_PROBE_OUT138_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT138_WIDTH : integer; - attribute C_PROBE_OUT138_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT139_INIT_VAL : string; - attribute C_PROBE_OUT139_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT139_WIDTH : integer; - attribute C_PROBE_OUT139_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT13_INIT_VAL : string; - attribute C_PROBE_OUT13_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT13_WIDTH : integer; - attribute C_PROBE_OUT13_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT140_INIT_VAL : string; - attribute C_PROBE_OUT140_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT140_WIDTH : integer; - attribute C_PROBE_OUT140_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT141_INIT_VAL : string; - attribute C_PROBE_OUT141_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT141_WIDTH : integer; - attribute C_PROBE_OUT141_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT142_INIT_VAL : string; - attribute C_PROBE_OUT142_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT142_WIDTH : integer; - attribute C_PROBE_OUT142_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT143_INIT_VAL : string; - attribute C_PROBE_OUT143_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT143_WIDTH : integer; - attribute C_PROBE_OUT143_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT144_INIT_VAL : string; - attribute C_PROBE_OUT144_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT144_WIDTH : integer; - attribute C_PROBE_OUT144_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT145_INIT_VAL : string; - attribute C_PROBE_OUT145_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT145_WIDTH : integer; - attribute C_PROBE_OUT145_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT146_INIT_VAL : string; - attribute C_PROBE_OUT146_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT146_WIDTH : integer; - attribute C_PROBE_OUT146_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT147_INIT_VAL : string; - attribute C_PROBE_OUT147_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT147_WIDTH : integer; - attribute C_PROBE_OUT147_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT148_INIT_VAL : string; - attribute C_PROBE_OUT148_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT148_WIDTH : integer; - attribute C_PROBE_OUT148_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT149_INIT_VAL : string; - attribute C_PROBE_OUT149_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT149_WIDTH : integer; - attribute C_PROBE_OUT149_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT14_INIT_VAL : string; - attribute C_PROBE_OUT14_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT14_WIDTH : integer; - attribute C_PROBE_OUT14_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT150_INIT_VAL : string; - attribute C_PROBE_OUT150_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT150_WIDTH : integer; - attribute C_PROBE_OUT150_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT151_INIT_VAL : string; - attribute C_PROBE_OUT151_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT151_WIDTH : integer; - attribute C_PROBE_OUT151_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT152_INIT_VAL : string; - attribute C_PROBE_OUT152_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT152_WIDTH : integer; - attribute C_PROBE_OUT152_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT153_INIT_VAL : string; - attribute C_PROBE_OUT153_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT153_WIDTH : integer; - attribute C_PROBE_OUT153_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT154_INIT_VAL : string; - attribute C_PROBE_OUT154_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT154_WIDTH : integer; - attribute C_PROBE_OUT154_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT155_INIT_VAL : string; - attribute C_PROBE_OUT155_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT155_WIDTH : integer; - attribute C_PROBE_OUT155_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT156_INIT_VAL : string; - attribute C_PROBE_OUT156_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT156_WIDTH : integer; - attribute C_PROBE_OUT156_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT157_INIT_VAL : string; - attribute C_PROBE_OUT157_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT157_WIDTH : integer; - attribute C_PROBE_OUT157_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT158_INIT_VAL : string; - attribute C_PROBE_OUT158_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT158_WIDTH : integer; - attribute C_PROBE_OUT158_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT159_INIT_VAL : string; - attribute C_PROBE_OUT159_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT159_WIDTH : integer; - attribute C_PROBE_OUT159_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT15_INIT_VAL : string; - attribute C_PROBE_OUT15_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT15_WIDTH : integer; - attribute C_PROBE_OUT15_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT160_INIT_VAL : string; - attribute C_PROBE_OUT160_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT160_WIDTH : integer; - attribute C_PROBE_OUT160_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT161_INIT_VAL : string; - attribute C_PROBE_OUT161_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT161_WIDTH : integer; - attribute C_PROBE_OUT161_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT162_INIT_VAL : string; - attribute C_PROBE_OUT162_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT162_WIDTH : integer; - attribute C_PROBE_OUT162_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT163_INIT_VAL : string; - attribute C_PROBE_OUT163_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT163_WIDTH : integer; - attribute C_PROBE_OUT163_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT164_INIT_VAL : string; - attribute C_PROBE_OUT164_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT164_WIDTH : integer; - attribute C_PROBE_OUT164_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT165_INIT_VAL : string; - attribute C_PROBE_OUT165_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT165_WIDTH : integer; - attribute C_PROBE_OUT165_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT166_INIT_VAL : string; - attribute C_PROBE_OUT166_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT166_WIDTH : integer; - attribute C_PROBE_OUT166_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT167_INIT_VAL : string; - attribute C_PROBE_OUT167_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT167_WIDTH : integer; - attribute C_PROBE_OUT167_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT168_INIT_VAL : string; - attribute C_PROBE_OUT168_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT168_WIDTH : integer; - attribute C_PROBE_OUT168_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT169_INIT_VAL : string; - attribute C_PROBE_OUT169_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT169_WIDTH : integer; - attribute C_PROBE_OUT169_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT16_INIT_VAL : string; - attribute C_PROBE_OUT16_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT16_WIDTH : integer; - attribute C_PROBE_OUT16_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT170_INIT_VAL : string; - attribute C_PROBE_OUT170_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT170_WIDTH : integer; - attribute C_PROBE_OUT170_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT171_INIT_VAL : string; - attribute C_PROBE_OUT171_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT171_WIDTH : integer; - attribute C_PROBE_OUT171_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT172_INIT_VAL : string; - attribute C_PROBE_OUT172_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT172_WIDTH : integer; - attribute C_PROBE_OUT172_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT173_INIT_VAL : string; - attribute C_PROBE_OUT173_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT173_WIDTH : integer; - attribute C_PROBE_OUT173_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT174_INIT_VAL : string; - attribute C_PROBE_OUT174_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT174_WIDTH : integer; - attribute C_PROBE_OUT174_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT175_INIT_VAL : string; - attribute C_PROBE_OUT175_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT175_WIDTH : integer; - attribute C_PROBE_OUT175_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT176_INIT_VAL : string; - attribute C_PROBE_OUT176_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT176_WIDTH : integer; - attribute C_PROBE_OUT176_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT177_INIT_VAL : string; - attribute C_PROBE_OUT177_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT177_WIDTH : integer; - attribute C_PROBE_OUT177_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT178_INIT_VAL : string; - attribute C_PROBE_OUT178_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT178_WIDTH : integer; - attribute C_PROBE_OUT178_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT179_INIT_VAL : string; - attribute C_PROBE_OUT179_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT179_WIDTH : integer; - attribute C_PROBE_OUT179_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT17_INIT_VAL : string; - attribute C_PROBE_OUT17_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT17_WIDTH : integer; - attribute C_PROBE_OUT17_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT180_INIT_VAL : string; - attribute C_PROBE_OUT180_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT180_WIDTH : integer; - attribute C_PROBE_OUT180_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT181_INIT_VAL : string; - attribute C_PROBE_OUT181_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT181_WIDTH : integer; - attribute C_PROBE_OUT181_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT182_INIT_VAL : string; - attribute C_PROBE_OUT182_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT182_WIDTH : integer; - attribute C_PROBE_OUT182_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT183_INIT_VAL : string; - attribute C_PROBE_OUT183_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT183_WIDTH : integer; - attribute C_PROBE_OUT183_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT184_INIT_VAL : string; - attribute C_PROBE_OUT184_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT184_WIDTH : integer; - attribute C_PROBE_OUT184_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT185_INIT_VAL : string; - attribute C_PROBE_OUT185_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT185_WIDTH : integer; - attribute C_PROBE_OUT185_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT186_INIT_VAL : string; - attribute C_PROBE_OUT186_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT186_WIDTH : integer; - attribute C_PROBE_OUT186_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT187_INIT_VAL : string; - attribute C_PROBE_OUT187_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT187_WIDTH : integer; - attribute C_PROBE_OUT187_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT188_INIT_VAL : string; - attribute C_PROBE_OUT188_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT188_WIDTH : integer; - attribute C_PROBE_OUT188_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT189_INIT_VAL : string; - attribute C_PROBE_OUT189_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT189_WIDTH : integer; - attribute C_PROBE_OUT189_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT18_INIT_VAL : string; - attribute C_PROBE_OUT18_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT18_WIDTH : integer; - attribute C_PROBE_OUT18_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT190_INIT_VAL : string; - attribute C_PROBE_OUT190_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT190_WIDTH : integer; - attribute C_PROBE_OUT190_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT191_INIT_VAL : string; - attribute C_PROBE_OUT191_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT191_WIDTH : integer; - attribute C_PROBE_OUT191_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT192_INIT_VAL : string; - attribute C_PROBE_OUT192_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT192_WIDTH : integer; - attribute C_PROBE_OUT192_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT193_INIT_VAL : string; - attribute C_PROBE_OUT193_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT193_WIDTH : integer; - attribute C_PROBE_OUT193_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT194_INIT_VAL : string; - attribute C_PROBE_OUT194_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT194_WIDTH : integer; - attribute C_PROBE_OUT194_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT195_INIT_VAL : string; - attribute C_PROBE_OUT195_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT195_WIDTH : integer; - attribute C_PROBE_OUT195_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT196_INIT_VAL : string; - attribute C_PROBE_OUT196_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT196_WIDTH : integer; - attribute C_PROBE_OUT196_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT197_INIT_VAL : string; - attribute C_PROBE_OUT197_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT197_WIDTH : integer; - attribute C_PROBE_OUT197_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT198_INIT_VAL : string; - attribute C_PROBE_OUT198_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT198_WIDTH : integer; - attribute C_PROBE_OUT198_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT199_INIT_VAL : string; - attribute C_PROBE_OUT199_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT199_WIDTH : integer; - attribute C_PROBE_OUT199_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT19_INIT_VAL : string; - attribute C_PROBE_OUT19_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT19_WIDTH : integer; - attribute C_PROBE_OUT19_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT1_INIT_VAL : string; - attribute C_PROBE_OUT1_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT1_WIDTH : integer; - attribute C_PROBE_OUT1_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT200_INIT_VAL : string; - attribute C_PROBE_OUT200_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT200_WIDTH : integer; - attribute C_PROBE_OUT200_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT201_INIT_VAL : string; - attribute C_PROBE_OUT201_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT201_WIDTH : integer; - attribute C_PROBE_OUT201_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT202_INIT_VAL : string; - attribute C_PROBE_OUT202_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT202_WIDTH : integer; - attribute C_PROBE_OUT202_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT203_INIT_VAL : string; - attribute C_PROBE_OUT203_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT203_WIDTH : integer; - attribute C_PROBE_OUT203_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT204_INIT_VAL : string; - attribute C_PROBE_OUT204_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT204_WIDTH : integer; - attribute C_PROBE_OUT204_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT205_INIT_VAL : string; - attribute C_PROBE_OUT205_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT205_WIDTH : integer; - attribute C_PROBE_OUT205_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT206_INIT_VAL : string; - attribute C_PROBE_OUT206_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT206_WIDTH : integer; - attribute C_PROBE_OUT206_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT207_INIT_VAL : string; - attribute C_PROBE_OUT207_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT207_WIDTH : integer; - attribute C_PROBE_OUT207_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT208_INIT_VAL : string; - attribute C_PROBE_OUT208_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT208_WIDTH : integer; - attribute C_PROBE_OUT208_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT209_INIT_VAL : string; - attribute C_PROBE_OUT209_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT209_WIDTH : integer; - attribute C_PROBE_OUT209_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT20_INIT_VAL : string; - attribute C_PROBE_OUT20_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT20_WIDTH : integer; - attribute C_PROBE_OUT20_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT210_INIT_VAL : string; - attribute C_PROBE_OUT210_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT210_WIDTH : integer; - attribute C_PROBE_OUT210_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT211_INIT_VAL : string; - attribute C_PROBE_OUT211_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT211_WIDTH : integer; - attribute C_PROBE_OUT211_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT212_INIT_VAL : string; - attribute C_PROBE_OUT212_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT212_WIDTH : integer; - attribute C_PROBE_OUT212_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT213_INIT_VAL : string; - attribute C_PROBE_OUT213_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT213_WIDTH : integer; - attribute C_PROBE_OUT213_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT214_INIT_VAL : string; - attribute C_PROBE_OUT214_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT214_WIDTH : integer; - attribute C_PROBE_OUT214_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT215_INIT_VAL : string; - attribute C_PROBE_OUT215_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT215_WIDTH : integer; - attribute C_PROBE_OUT215_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT216_INIT_VAL : string; - attribute C_PROBE_OUT216_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT216_WIDTH : integer; - attribute C_PROBE_OUT216_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT217_INIT_VAL : string; - attribute C_PROBE_OUT217_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT217_WIDTH : integer; - attribute C_PROBE_OUT217_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT218_INIT_VAL : string; - attribute C_PROBE_OUT218_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT218_WIDTH : integer; - attribute C_PROBE_OUT218_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT219_INIT_VAL : string; - attribute C_PROBE_OUT219_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT219_WIDTH : integer; - attribute C_PROBE_OUT219_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT21_INIT_VAL : string; - attribute C_PROBE_OUT21_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT21_WIDTH : integer; - attribute C_PROBE_OUT21_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT220_INIT_VAL : string; - attribute C_PROBE_OUT220_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT220_WIDTH : integer; - attribute C_PROBE_OUT220_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT221_INIT_VAL : string; - attribute C_PROBE_OUT221_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT221_WIDTH : integer; - attribute C_PROBE_OUT221_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT222_INIT_VAL : string; - attribute C_PROBE_OUT222_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT222_WIDTH : integer; - attribute C_PROBE_OUT222_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT223_INIT_VAL : string; - attribute C_PROBE_OUT223_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT223_WIDTH : integer; - attribute C_PROBE_OUT223_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT224_INIT_VAL : string; - attribute C_PROBE_OUT224_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT224_WIDTH : integer; - attribute C_PROBE_OUT224_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT225_INIT_VAL : string; - attribute C_PROBE_OUT225_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT225_WIDTH : integer; - attribute C_PROBE_OUT225_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT226_INIT_VAL : string; - attribute C_PROBE_OUT226_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT226_WIDTH : integer; - attribute C_PROBE_OUT226_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT227_INIT_VAL : string; - attribute C_PROBE_OUT227_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT227_WIDTH : integer; - attribute C_PROBE_OUT227_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT228_INIT_VAL : string; - attribute C_PROBE_OUT228_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT228_WIDTH : integer; - attribute C_PROBE_OUT228_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT229_INIT_VAL : string; - attribute C_PROBE_OUT229_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT229_WIDTH : integer; - attribute C_PROBE_OUT229_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT22_INIT_VAL : string; - attribute C_PROBE_OUT22_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT22_WIDTH : integer; - attribute C_PROBE_OUT22_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT230_INIT_VAL : string; - attribute C_PROBE_OUT230_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT230_WIDTH : integer; - attribute C_PROBE_OUT230_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT231_INIT_VAL : string; - attribute C_PROBE_OUT231_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT231_WIDTH : integer; - attribute C_PROBE_OUT231_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT232_INIT_VAL : string; - attribute C_PROBE_OUT232_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT232_WIDTH : integer; - attribute C_PROBE_OUT232_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT233_INIT_VAL : string; - attribute C_PROBE_OUT233_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT233_WIDTH : integer; - attribute C_PROBE_OUT233_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT234_INIT_VAL : string; - attribute C_PROBE_OUT234_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT234_WIDTH : integer; - attribute C_PROBE_OUT234_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT235_INIT_VAL : string; - attribute C_PROBE_OUT235_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT235_WIDTH : integer; - attribute C_PROBE_OUT235_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT236_INIT_VAL : string; - attribute C_PROBE_OUT236_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT236_WIDTH : integer; - attribute C_PROBE_OUT236_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT237_INIT_VAL : string; - attribute C_PROBE_OUT237_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT237_WIDTH : integer; - attribute C_PROBE_OUT237_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT238_INIT_VAL : string; - attribute C_PROBE_OUT238_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT238_WIDTH : integer; - attribute C_PROBE_OUT238_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT239_INIT_VAL : string; - attribute C_PROBE_OUT239_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT239_WIDTH : integer; - attribute C_PROBE_OUT239_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT23_INIT_VAL : string; - attribute C_PROBE_OUT23_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT23_WIDTH : integer; - attribute C_PROBE_OUT23_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT240_INIT_VAL : string; - attribute C_PROBE_OUT240_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT240_WIDTH : integer; - attribute C_PROBE_OUT240_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT241_INIT_VAL : string; - attribute C_PROBE_OUT241_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT241_WIDTH : integer; - attribute C_PROBE_OUT241_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT242_INIT_VAL : string; - attribute C_PROBE_OUT242_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT242_WIDTH : integer; - attribute C_PROBE_OUT242_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT243_INIT_VAL : string; - attribute C_PROBE_OUT243_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT243_WIDTH : integer; - attribute C_PROBE_OUT243_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT244_INIT_VAL : string; - attribute C_PROBE_OUT244_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT244_WIDTH : integer; - attribute C_PROBE_OUT244_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT245_INIT_VAL : string; - attribute C_PROBE_OUT245_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT245_WIDTH : integer; - attribute C_PROBE_OUT245_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT246_INIT_VAL : string; - attribute C_PROBE_OUT246_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT246_WIDTH : integer; - attribute C_PROBE_OUT246_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT247_INIT_VAL : string; - attribute C_PROBE_OUT247_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT247_WIDTH : integer; - attribute C_PROBE_OUT247_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT248_INIT_VAL : string; - attribute C_PROBE_OUT248_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT248_WIDTH : integer; - attribute C_PROBE_OUT248_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT249_INIT_VAL : string; - attribute C_PROBE_OUT249_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT249_WIDTH : integer; - attribute C_PROBE_OUT249_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT24_INIT_VAL : string; - attribute C_PROBE_OUT24_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT24_WIDTH : integer; - attribute C_PROBE_OUT24_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT250_INIT_VAL : string; - attribute C_PROBE_OUT250_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT250_WIDTH : integer; - attribute C_PROBE_OUT250_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT251_INIT_VAL : string; - attribute C_PROBE_OUT251_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT251_WIDTH : integer; - attribute C_PROBE_OUT251_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT252_INIT_VAL : string; - attribute C_PROBE_OUT252_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT252_WIDTH : integer; - attribute C_PROBE_OUT252_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT253_INIT_VAL : string; - attribute C_PROBE_OUT253_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT253_WIDTH : integer; - attribute C_PROBE_OUT253_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT254_INIT_VAL : string; - attribute C_PROBE_OUT254_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT254_WIDTH : integer; - attribute C_PROBE_OUT254_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT255_INIT_VAL : string; - attribute C_PROBE_OUT255_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT255_WIDTH : integer; - attribute C_PROBE_OUT255_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT25_INIT_VAL : string; - attribute C_PROBE_OUT25_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT25_WIDTH : integer; - attribute C_PROBE_OUT25_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT26_INIT_VAL : string; - attribute C_PROBE_OUT26_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT26_WIDTH : integer; - attribute C_PROBE_OUT26_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT27_INIT_VAL : string; - attribute C_PROBE_OUT27_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT27_WIDTH : integer; - attribute C_PROBE_OUT27_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT28_INIT_VAL : string; - attribute C_PROBE_OUT28_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT28_WIDTH : integer; - attribute C_PROBE_OUT28_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT29_INIT_VAL : string; - attribute C_PROBE_OUT29_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT29_WIDTH : integer; - attribute C_PROBE_OUT29_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT2_INIT_VAL : string; - attribute C_PROBE_OUT2_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT2_WIDTH : integer; - attribute C_PROBE_OUT2_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT30_INIT_VAL : string; - attribute C_PROBE_OUT30_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT30_WIDTH : integer; - attribute C_PROBE_OUT30_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT31_INIT_VAL : string; - attribute C_PROBE_OUT31_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT31_WIDTH : integer; - attribute C_PROBE_OUT31_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT32_INIT_VAL : string; - attribute C_PROBE_OUT32_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT32_WIDTH : integer; - attribute C_PROBE_OUT32_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT33_INIT_VAL : string; - attribute C_PROBE_OUT33_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT33_WIDTH : integer; - attribute C_PROBE_OUT33_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT34_INIT_VAL : string; - attribute C_PROBE_OUT34_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT34_WIDTH : integer; - attribute C_PROBE_OUT34_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT35_INIT_VAL : string; - attribute C_PROBE_OUT35_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT35_WIDTH : integer; - attribute C_PROBE_OUT35_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT36_INIT_VAL : string; - attribute C_PROBE_OUT36_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT36_WIDTH : integer; - attribute C_PROBE_OUT36_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT37_INIT_VAL : string; - attribute C_PROBE_OUT37_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT37_WIDTH : integer; - attribute C_PROBE_OUT37_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT38_INIT_VAL : string; - attribute C_PROBE_OUT38_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT38_WIDTH : integer; - attribute C_PROBE_OUT38_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT39_INIT_VAL : string; - attribute C_PROBE_OUT39_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT39_WIDTH : integer; - attribute C_PROBE_OUT39_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT3_INIT_VAL : string; - attribute C_PROBE_OUT3_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT3_WIDTH : integer; - attribute C_PROBE_OUT3_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT40_INIT_VAL : string; - attribute C_PROBE_OUT40_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT40_WIDTH : integer; - attribute C_PROBE_OUT40_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT41_INIT_VAL : string; - attribute C_PROBE_OUT41_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT41_WIDTH : integer; - attribute C_PROBE_OUT41_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT42_INIT_VAL : string; - attribute C_PROBE_OUT42_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT42_WIDTH : integer; - attribute C_PROBE_OUT42_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT43_INIT_VAL : string; - attribute C_PROBE_OUT43_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT43_WIDTH : integer; - attribute C_PROBE_OUT43_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT44_INIT_VAL : string; - attribute C_PROBE_OUT44_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT44_WIDTH : integer; - attribute C_PROBE_OUT44_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT45_INIT_VAL : string; - attribute C_PROBE_OUT45_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT45_WIDTH : integer; - attribute C_PROBE_OUT45_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT46_INIT_VAL : string; - attribute C_PROBE_OUT46_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT46_WIDTH : integer; - attribute C_PROBE_OUT46_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT47_INIT_VAL : string; - attribute C_PROBE_OUT47_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT47_WIDTH : integer; - attribute C_PROBE_OUT47_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT48_INIT_VAL : string; - attribute C_PROBE_OUT48_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT48_WIDTH : integer; - attribute C_PROBE_OUT48_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT49_INIT_VAL : string; - attribute C_PROBE_OUT49_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT49_WIDTH : integer; - attribute C_PROBE_OUT49_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT4_INIT_VAL : string; - attribute C_PROBE_OUT4_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT4_WIDTH : integer; - attribute C_PROBE_OUT4_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT50_INIT_VAL : string; - attribute C_PROBE_OUT50_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT50_WIDTH : integer; - attribute C_PROBE_OUT50_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT51_INIT_VAL : string; - attribute C_PROBE_OUT51_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT51_WIDTH : integer; - attribute C_PROBE_OUT51_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT52_INIT_VAL : string; - attribute C_PROBE_OUT52_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT52_WIDTH : integer; - attribute C_PROBE_OUT52_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT53_INIT_VAL : string; - attribute C_PROBE_OUT53_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT53_WIDTH : integer; - attribute C_PROBE_OUT53_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT54_INIT_VAL : string; - attribute C_PROBE_OUT54_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT54_WIDTH : integer; - attribute C_PROBE_OUT54_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT55_INIT_VAL : string; - attribute C_PROBE_OUT55_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT55_WIDTH : integer; - attribute C_PROBE_OUT55_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT56_INIT_VAL : string; - attribute C_PROBE_OUT56_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT56_WIDTH : integer; - attribute C_PROBE_OUT56_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT57_INIT_VAL : string; - attribute C_PROBE_OUT57_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT57_WIDTH : integer; - attribute C_PROBE_OUT57_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT58_INIT_VAL : string; - attribute C_PROBE_OUT58_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT58_WIDTH : integer; - attribute C_PROBE_OUT58_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT59_INIT_VAL : string; - attribute C_PROBE_OUT59_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT59_WIDTH : integer; - attribute C_PROBE_OUT59_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT5_INIT_VAL : string; - attribute C_PROBE_OUT5_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT5_WIDTH : integer; - attribute C_PROBE_OUT5_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT60_INIT_VAL : string; - attribute C_PROBE_OUT60_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT60_WIDTH : integer; - attribute C_PROBE_OUT60_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT61_INIT_VAL : string; - attribute C_PROBE_OUT61_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT61_WIDTH : integer; - attribute C_PROBE_OUT61_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT62_INIT_VAL : string; - attribute C_PROBE_OUT62_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT62_WIDTH : integer; - attribute C_PROBE_OUT62_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT63_INIT_VAL : string; - attribute C_PROBE_OUT63_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT63_WIDTH : integer; - attribute C_PROBE_OUT63_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT64_INIT_VAL : string; - attribute C_PROBE_OUT64_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT64_WIDTH : integer; - attribute C_PROBE_OUT64_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT65_INIT_VAL : string; - attribute C_PROBE_OUT65_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT65_WIDTH : integer; - attribute C_PROBE_OUT65_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT66_INIT_VAL : string; - attribute C_PROBE_OUT66_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT66_WIDTH : integer; - attribute C_PROBE_OUT66_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT67_INIT_VAL : string; - attribute C_PROBE_OUT67_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT67_WIDTH : integer; - attribute C_PROBE_OUT67_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT68_INIT_VAL : string; - attribute C_PROBE_OUT68_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT68_WIDTH : integer; - attribute C_PROBE_OUT68_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT69_INIT_VAL : string; - attribute C_PROBE_OUT69_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT69_WIDTH : integer; - attribute C_PROBE_OUT69_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT6_INIT_VAL : string; - attribute C_PROBE_OUT6_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT6_WIDTH : integer; - attribute C_PROBE_OUT6_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT70_INIT_VAL : string; - attribute C_PROBE_OUT70_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT70_WIDTH : integer; - attribute C_PROBE_OUT70_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT71_INIT_VAL : string; - attribute C_PROBE_OUT71_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT71_WIDTH : integer; - attribute C_PROBE_OUT71_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT72_INIT_VAL : string; - attribute C_PROBE_OUT72_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT72_WIDTH : integer; - attribute C_PROBE_OUT72_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT73_INIT_VAL : string; - attribute C_PROBE_OUT73_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT73_WIDTH : integer; - attribute C_PROBE_OUT73_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT74_INIT_VAL : string; - attribute C_PROBE_OUT74_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT74_WIDTH : integer; - attribute C_PROBE_OUT74_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT75_INIT_VAL : string; - attribute C_PROBE_OUT75_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT75_WIDTH : integer; - attribute C_PROBE_OUT75_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT76_INIT_VAL : string; - attribute C_PROBE_OUT76_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT76_WIDTH : integer; - attribute C_PROBE_OUT76_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT77_INIT_VAL : string; - attribute C_PROBE_OUT77_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT77_WIDTH : integer; - attribute C_PROBE_OUT77_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT78_INIT_VAL : string; - attribute C_PROBE_OUT78_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT78_WIDTH : integer; - attribute C_PROBE_OUT78_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT79_INIT_VAL : string; - attribute C_PROBE_OUT79_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT79_WIDTH : integer; - attribute C_PROBE_OUT79_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT7_INIT_VAL : string; - attribute C_PROBE_OUT7_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT7_WIDTH : integer; - attribute C_PROBE_OUT7_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT80_INIT_VAL : string; - attribute C_PROBE_OUT80_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT80_WIDTH : integer; - attribute C_PROBE_OUT80_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT81_INIT_VAL : string; - attribute C_PROBE_OUT81_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT81_WIDTH : integer; - attribute C_PROBE_OUT81_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT82_INIT_VAL : string; - attribute C_PROBE_OUT82_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT82_WIDTH : integer; - attribute C_PROBE_OUT82_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT83_INIT_VAL : string; - attribute C_PROBE_OUT83_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT83_WIDTH : integer; - attribute C_PROBE_OUT83_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT84_INIT_VAL : string; - attribute C_PROBE_OUT84_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT84_WIDTH : integer; - attribute C_PROBE_OUT84_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT85_INIT_VAL : string; - attribute C_PROBE_OUT85_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT85_WIDTH : integer; - attribute C_PROBE_OUT85_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT86_INIT_VAL : string; - attribute C_PROBE_OUT86_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT86_WIDTH : integer; - attribute C_PROBE_OUT86_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT87_INIT_VAL : string; - attribute C_PROBE_OUT87_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT87_WIDTH : integer; - attribute C_PROBE_OUT87_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT88_INIT_VAL : string; - attribute C_PROBE_OUT88_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT88_WIDTH : integer; - attribute C_PROBE_OUT88_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT89_INIT_VAL : string; - attribute C_PROBE_OUT89_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT89_WIDTH : integer; - attribute C_PROBE_OUT89_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT8_INIT_VAL : string; - attribute C_PROBE_OUT8_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT8_WIDTH : integer; - attribute C_PROBE_OUT8_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT90_INIT_VAL : string; - attribute C_PROBE_OUT90_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT90_WIDTH : integer; - attribute C_PROBE_OUT90_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT91_INIT_VAL : string; - attribute C_PROBE_OUT91_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT91_WIDTH : integer; - attribute C_PROBE_OUT91_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT92_INIT_VAL : string; - attribute C_PROBE_OUT92_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT92_WIDTH : integer; - attribute C_PROBE_OUT92_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT93_INIT_VAL : string; - attribute C_PROBE_OUT93_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT93_WIDTH : integer; - attribute C_PROBE_OUT93_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT94_INIT_VAL : string; - attribute C_PROBE_OUT94_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT94_WIDTH : integer; - attribute C_PROBE_OUT94_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT95_INIT_VAL : string; - attribute C_PROBE_OUT95_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT95_WIDTH : integer; - attribute C_PROBE_OUT95_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT96_INIT_VAL : string; - attribute C_PROBE_OUT96_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT96_WIDTH : integer; - attribute C_PROBE_OUT96_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT97_INIT_VAL : string; - attribute C_PROBE_OUT97_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT97_WIDTH : integer; - attribute C_PROBE_OUT97_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT98_INIT_VAL : string; - attribute C_PROBE_OUT98_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT98_WIDTH : integer; - attribute C_PROBE_OUT98_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT99_INIT_VAL : string; - attribute C_PROBE_OUT99_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT99_WIDTH : integer; - attribute C_PROBE_OUT99_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_PROBE_OUT9_INIT_VAL : string; - attribute C_PROBE_OUT9_INIT_VAL of vio_0_vio_v3_0_19_vio : entity is "1'b0"; - attribute C_PROBE_OUT9_WIDTH : integer; - attribute C_PROBE_OUT9_WIDTH of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_USE_TEST_REG : integer; - attribute C_USE_TEST_REG of vio_0_vio_v3_0_19_vio : entity is 1; - attribute C_XDEVICEFAMILY : string; - attribute C_XDEVICEFAMILY of vio_0_vio_v3_0_19_vio : entity is "zynq"; - attribute C_XLNX_HW_PROBE_INFO : string; - attribute C_XLNX_HW_PROBE_INFO of vio_0_vio_v3_0_19_vio : entity is "DEFAULT"; - attribute C_XSDB_SLAVE_TYPE : integer; - attribute C_XSDB_SLAVE_TYPE of vio_0_vio_v3_0_19_vio : entity is 33; - attribute DowngradeIPIdentifiedWarnings : string; - attribute DowngradeIPIdentifiedWarnings of vio_0_vio_v3_0_19_vio : entity is "yes"; - attribute LC_HIGH_BIT_POS_PROBE_OUT0 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT0 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000011111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT1 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT1 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000100000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT10 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT10 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000101001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT100 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT100 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010000011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT101 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT101 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010000100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT102 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT102 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010000101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT103 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT103 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010000110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT104 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT104 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010000111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT105 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT105 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010001000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT106 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT106 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010001001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT107 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT107 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010001010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT108 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT108 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010001011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT109 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT109 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010001100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT11 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT11 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000101010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT110 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT110 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010001101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT111 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT111 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010001110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT112 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT112 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010001111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT113 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT113 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010010000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT114 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT114 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010010001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT115 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT115 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010010010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT116 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT116 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010010011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT117 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT117 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010010100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT118 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT118 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010010101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT119 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT119 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010010110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT12 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT12 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000101011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT120 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT120 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010010111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT121 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT121 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010011000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT122 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT122 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010011001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT123 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT123 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010011010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT124 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT124 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010011011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT125 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT125 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010011100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT126 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT126 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010011101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT127 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT127 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010011110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT128 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT128 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010011111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT129 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT129 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010100000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT13 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT13 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000101100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT130 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT130 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010100001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT131 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT131 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010100010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT132 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT132 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010100011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT133 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT133 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010100100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT134 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT134 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010100101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT135 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT135 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010100110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT136 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT136 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010100111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT137 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT137 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010101000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT138 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT138 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010101001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT139 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT139 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010101010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT14 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT14 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000101101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT140 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT140 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010101011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT141 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT141 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010101100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT142 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT142 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010101101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT143 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT143 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010101110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT144 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT144 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010101111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT145 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT145 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010110000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT146 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT146 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010110001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT147 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT147 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010110010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT148 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT148 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010110011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT149 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT149 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010110100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT15 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT15 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000101110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT150 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT150 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010110101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT151 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT151 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010110110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT152 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT152 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010110111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT153 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT153 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010111000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT154 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT154 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010111001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT155 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT155 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010111010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT156 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT156 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010111011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT157 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT157 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010111100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT158 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT158 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010111101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT159 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT159 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010111110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT16 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT16 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000101111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT160 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT160 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010111111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT161 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT161 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011000000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT162 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT162 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011000001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT163 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT163 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011000010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT164 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT164 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011000011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT165 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT165 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011000100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT166 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT166 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011000101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT167 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT167 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011000110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT168 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT168 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011000111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT169 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT169 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011001000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT17 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT17 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000110000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT170 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT170 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011001001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT171 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT171 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011001010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT172 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT172 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011001011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT173 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT173 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011001100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT174 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT174 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011001101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT175 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT175 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011001110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT176 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT176 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011001111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT177 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT177 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011010000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT178 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT178 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011010001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT179 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT179 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011010010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT18 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT18 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000110001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT180 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT180 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011010011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT181 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT181 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011010100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT182 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT182 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011010101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT183 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT183 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011010110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT184 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT184 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011010111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT185 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT185 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011011000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT186 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT186 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011011001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT187 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT187 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011011010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT188 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT188 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011011011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT189 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT189 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011011100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT19 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT19 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000110010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT190 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT190 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011011101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT191 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT191 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011011110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT192 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT192 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011011111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT193 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT193 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011100000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT194 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT194 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011100001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT195 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT195 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011100010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT196 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT196 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011100011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT197 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT197 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011100100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT198 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT198 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011100101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT199 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT199 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011100110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT2 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT2 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000100001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT20 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT20 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000110011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT200 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT200 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011100111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT201 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT201 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011101000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT202 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT202 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011101001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT203 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT203 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011101010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT204 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT204 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011101011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT205 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT205 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011101100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT206 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT206 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011101101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT207 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT207 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011101110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT208 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT208 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011101111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT209 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT209 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011110000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT21 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT21 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000110100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT210 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT210 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011110001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT211 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT211 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011110010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT212 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT212 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011110011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT213 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT213 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011110100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT214 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT214 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011110101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT215 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT215 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011110110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT216 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT216 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011110111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT217 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT217 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011111000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT218 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT218 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011111001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT219 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT219 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011111010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT22 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT22 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000110101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT220 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT220 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011111011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT221 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT221 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011111100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT222 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT222 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011111101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT223 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT223 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011111110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT224 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT224 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011111111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT225 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT225 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100000000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT226 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT226 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100000001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT227 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT227 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100000010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT228 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT228 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100000011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT229 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT229 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100000100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT23 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT23 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000110110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT230 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT230 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100000101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT231 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT231 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100000110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT232 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT232 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100000111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT233 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT233 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100001000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT234 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT234 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100001001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT235 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT235 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100001010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT236 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT236 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100001011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT237 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT237 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100001100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT238 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT238 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100001101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT239 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT239 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100001110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT24 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT24 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000110111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT240 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT240 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100001111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT241 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT241 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100010000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT242 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT242 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100010001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT243 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT243 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100010010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT244 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT244 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100010011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT245 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT245 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100010100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT246 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT246 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100010101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT247 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT247 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100010110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT248 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT248 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100010111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT249 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT249 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100011000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT25 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT25 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000111000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT250 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT250 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100011001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT251 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT251 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100011010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT252 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT252 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100011011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT253 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT253 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100011100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT254 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT254 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100011101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT255 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT255 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100011110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT26 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT26 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000111001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT27 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT27 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000111010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT28 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT28 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000111011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT29 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT29 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000111100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT3 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT3 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000100010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT30 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT30 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000111101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT31 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT31 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000111110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT32 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT32 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000111111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT33 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT33 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001000000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT34 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT34 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001000001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT35 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT35 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001000010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT36 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT36 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001000011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT37 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT37 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001000100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT38 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT38 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001000101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT39 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT39 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001000110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT4 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT4 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000100011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT40 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT40 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001000111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT41 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT41 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001001000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT42 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT42 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001001001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT43 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT43 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001001010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT44 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT44 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001001011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT45 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT45 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001001100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT46 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT46 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001001101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT47 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT47 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001001110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT48 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT48 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001001111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT49 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT49 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001010000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT5 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT5 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000100100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT50 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT50 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001010001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT51 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT51 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001010010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT52 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT52 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001010011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT53 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT53 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001010100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT54 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT54 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001010101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT55 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT55 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001010110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT56 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT56 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001010111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT57 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT57 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001011000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT58 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT58 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001011001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT59 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT59 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001011010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT6 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT6 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000100101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT60 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT60 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001011011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT61 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT61 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001011100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT62 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT62 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001011101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT63 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT63 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001011110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT64 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT64 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001011111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT65 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT65 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001100000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT66 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT66 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001100001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT67 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT67 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001100010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT68 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT68 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001100011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT69 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT69 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001100100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT7 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT7 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000100110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT70 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT70 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001100101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT71 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT71 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001100110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT72 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT72 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001100111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT73 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT73 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001101000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT74 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT74 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001101001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT75 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT75 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001101010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT76 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT76 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001101011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT77 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT77 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001101100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT78 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT78 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001101101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT79 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT79 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001101110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT8 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT8 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000100111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT80 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT80 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001101111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT81 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT81 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001110000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT82 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT82 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001110001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT83 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT83 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001110010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT84 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT84 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001110011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT85 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT85 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001110100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT86 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT86 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001110101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT87 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT87 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001110110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT88 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT88 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001110111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT89 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT89 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001111000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT9 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT9 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000101000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT90 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT90 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001111001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT91 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT91 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001111010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT92 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT92 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001111011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT93 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT93 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001111100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT94 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT94 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001111101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT95 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT95 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001111110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT96 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT96 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001111111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT97 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT97 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010000000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT98 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT98 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010000001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT99 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT99 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010000010"; - attribute LC_LOW_BIT_POS_PROBE_OUT0 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT0 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000000000"; - attribute LC_LOW_BIT_POS_PROBE_OUT1 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT1 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000100000"; - attribute LC_LOW_BIT_POS_PROBE_OUT10 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT10 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000101001"; - attribute LC_LOW_BIT_POS_PROBE_OUT100 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT100 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010000011"; - attribute LC_LOW_BIT_POS_PROBE_OUT101 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT101 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010000100"; - attribute LC_LOW_BIT_POS_PROBE_OUT102 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT102 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010000101"; - attribute LC_LOW_BIT_POS_PROBE_OUT103 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT103 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010000110"; - attribute LC_LOW_BIT_POS_PROBE_OUT104 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT104 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010000111"; - attribute LC_LOW_BIT_POS_PROBE_OUT105 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT105 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010001000"; - attribute LC_LOW_BIT_POS_PROBE_OUT106 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT106 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010001001"; - attribute LC_LOW_BIT_POS_PROBE_OUT107 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT107 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010001010"; - attribute LC_LOW_BIT_POS_PROBE_OUT108 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT108 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010001011"; - attribute LC_LOW_BIT_POS_PROBE_OUT109 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT109 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010001100"; - attribute LC_LOW_BIT_POS_PROBE_OUT11 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT11 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000101010"; - attribute LC_LOW_BIT_POS_PROBE_OUT110 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT110 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010001101"; - attribute LC_LOW_BIT_POS_PROBE_OUT111 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT111 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010001110"; - attribute LC_LOW_BIT_POS_PROBE_OUT112 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT112 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010001111"; - attribute LC_LOW_BIT_POS_PROBE_OUT113 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT113 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010010000"; - attribute LC_LOW_BIT_POS_PROBE_OUT114 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT114 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010010001"; - attribute LC_LOW_BIT_POS_PROBE_OUT115 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT115 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010010010"; - attribute LC_LOW_BIT_POS_PROBE_OUT116 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT116 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010010011"; - attribute LC_LOW_BIT_POS_PROBE_OUT117 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT117 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010010100"; - attribute LC_LOW_BIT_POS_PROBE_OUT118 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT118 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010010101"; - attribute LC_LOW_BIT_POS_PROBE_OUT119 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT119 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010010110"; - attribute LC_LOW_BIT_POS_PROBE_OUT12 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT12 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000101011"; - attribute LC_LOW_BIT_POS_PROBE_OUT120 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT120 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010010111"; - attribute LC_LOW_BIT_POS_PROBE_OUT121 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT121 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010011000"; - attribute LC_LOW_BIT_POS_PROBE_OUT122 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT122 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010011001"; - attribute LC_LOW_BIT_POS_PROBE_OUT123 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT123 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010011010"; - attribute LC_LOW_BIT_POS_PROBE_OUT124 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT124 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010011011"; - attribute LC_LOW_BIT_POS_PROBE_OUT125 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT125 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010011100"; - attribute LC_LOW_BIT_POS_PROBE_OUT126 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT126 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010011101"; - attribute LC_LOW_BIT_POS_PROBE_OUT127 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT127 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010011110"; - attribute LC_LOW_BIT_POS_PROBE_OUT128 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT128 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010011111"; - attribute LC_LOW_BIT_POS_PROBE_OUT129 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT129 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010100000"; - attribute LC_LOW_BIT_POS_PROBE_OUT13 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT13 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000101100"; - attribute LC_LOW_BIT_POS_PROBE_OUT130 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT130 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010100001"; - attribute LC_LOW_BIT_POS_PROBE_OUT131 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT131 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010100010"; - attribute LC_LOW_BIT_POS_PROBE_OUT132 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT132 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010100011"; - attribute LC_LOW_BIT_POS_PROBE_OUT133 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT133 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010100100"; - attribute LC_LOW_BIT_POS_PROBE_OUT134 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT134 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010100101"; - attribute LC_LOW_BIT_POS_PROBE_OUT135 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT135 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010100110"; - attribute LC_LOW_BIT_POS_PROBE_OUT136 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT136 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010100111"; - attribute LC_LOW_BIT_POS_PROBE_OUT137 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT137 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010101000"; - attribute LC_LOW_BIT_POS_PROBE_OUT138 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT138 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010101001"; - attribute LC_LOW_BIT_POS_PROBE_OUT139 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT139 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010101010"; - attribute LC_LOW_BIT_POS_PROBE_OUT14 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT14 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000101101"; - attribute LC_LOW_BIT_POS_PROBE_OUT140 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT140 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010101011"; - attribute LC_LOW_BIT_POS_PROBE_OUT141 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT141 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010101100"; - attribute LC_LOW_BIT_POS_PROBE_OUT142 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT142 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010101101"; - attribute LC_LOW_BIT_POS_PROBE_OUT143 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT143 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010101110"; - attribute LC_LOW_BIT_POS_PROBE_OUT144 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT144 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010101111"; - attribute LC_LOW_BIT_POS_PROBE_OUT145 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT145 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010110000"; - attribute LC_LOW_BIT_POS_PROBE_OUT146 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT146 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010110001"; - attribute LC_LOW_BIT_POS_PROBE_OUT147 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT147 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010110010"; - attribute LC_LOW_BIT_POS_PROBE_OUT148 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT148 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010110011"; - attribute LC_LOW_BIT_POS_PROBE_OUT149 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT149 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010110100"; - attribute LC_LOW_BIT_POS_PROBE_OUT15 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT15 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000101110"; - attribute LC_LOW_BIT_POS_PROBE_OUT150 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT150 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010110101"; - attribute LC_LOW_BIT_POS_PROBE_OUT151 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT151 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010110110"; - attribute LC_LOW_BIT_POS_PROBE_OUT152 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT152 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010110111"; - attribute LC_LOW_BIT_POS_PROBE_OUT153 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT153 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010111000"; - attribute LC_LOW_BIT_POS_PROBE_OUT154 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT154 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010111001"; - attribute LC_LOW_BIT_POS_PROBE_OUT155 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT155 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010111010"; - attribute LC_LOW_BIT_POS_PROBE_OUT156 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT156 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010111011"; - attribute LC_LOW_BIT_POS_PROBE_OUT157 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT157 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010111100"; - attribute LC_LOW_BIT_POS_PROBE_OUT158 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT158 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010111101"; - attribute LC_LOW_BIT_POS_PROBE_OUT159 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT159 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010111110"; - attribute LC_LOW_BIT_POS_PROBE_OUT16 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT16 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000101111"; - attribute LC_LOW_BIT_POS_PROBE_OUT160 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT160 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010111111"; - attribute LC_LOW_BIT_POS_PROBE_OUT161 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT161 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011000000"; - attribute LC_LOW_BIT_POS_PROBE_OUT162 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT162 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011000001"; - attribute LC_LOW_BIT_POS_PROBE_OUT163 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT163 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011000010"; - attribute LC_LOW_BIT_POS_PROBE_OUT164 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT164 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011000011"; - attribute LC_LOW_BIT_POS_PROBE_OUT165 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT165 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011000100"; - attribute LC_LOW_BIT_POS_PROBE_OUT166 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT166 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011000101"; - attribute LC_LOW_BIT_POS_PROBE_OUT167 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT167 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011000110"; - attribute LC_LOW_BIT_POS_PROBE_OUT168 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT168 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011000111"; - attribute LC_LOW_BIT_POS_PROBE_OUT169 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT169 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011001000"; - attribute LC_LOW_BIT_POS_PROBE_OUT17 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT17 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000110000"; - attribute LC_LOW_BIT_POS_PROBE_OUT170 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT170 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011001001"; - attribute LC_LOW_BIT_POS_PROBE_OUT171 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT171 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011001010"; - attribute LC_LOW_BIT_POS_PROBE_OUT172 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT172 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011001011"; - attribute LC_LOW_BIT_POS_PROBE_OUT173 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT173 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011001100"; - attribute LC_LOW_BIT_POS_PROBE_OUT174 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT174 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011001101"; - attribute LC_LOW_BIT_POS_PROBE_OUT175 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT175 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011001110"; - attribute LC_LOW_BIT_POS_PROBE_OUT176 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT176 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011001111"; - attribute LC_LOW_BIT_POS_PROBE_OUT177 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT177 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011010000"; - attribute LC_LOW_BIT_POS_PROBE_OUT178 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT178 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011010001"; - attribute LC_LOW_BIT_POS_PROBE_OUT179 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT179 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011010010"; - attribute LC_LOW_BIT_POS_PROBE_OUT18 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT18 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000110001"; - attribute LC_LOW_BIT_POS_PROBE_OUT180 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT180 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011010011"; - attribute LC_LOW_BIT_POS_PROBE_OUT181 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT181 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011010100"; - attribute LC_LOW_BIT_POS_PROBE_OUT182 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT182 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011010101"; - attribute LC_LOW_BIT_POS_PROBE_OUT183 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT183 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011010110"; - attribute LC_LOW_BIT_POS_PROBE_OUT184 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT184 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011010111"; - attribute LC_LOW_BIT_POS_PROBE_OUT185 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT185 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011011000"; - attribute LC_LOW_BIT_POS_PROBE_OUT186 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT186 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011011001"; - attribute LC_LOW_BIT_POS_PROBE_OUT187 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT187 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011011010"; - attribute LC_LOW_BIT_POS_PROBE_OUT188 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT188 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011011011"; - attribute LC_LOW_BIT_POS_PROBE_OUT189 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT189 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011011100"; - attribute LC_LOW_BIT_POS_PROBE_OUT19 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT19 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000110010"; - attribute LC_LOW_BIT_POS_PROBE_OUT190 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT190 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011011101"; - attribute LC_LOW_BIT_POS_PROBE_OUT191 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT191 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011011110"; - attribute LC_LOW_BIT_POS_PROBE_OUT192 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT192 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011011111"; - attribute LC_LOW_BIT_POS_PROBE_OUT193 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT193 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011100000"; - attribute LC_LOW_BIT_POS_PROBE_OUT194 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT194 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011100001"; - attribute LC_LOW_BIT_POS_PROBE_OUT195 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT195 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011100010"; - attribute LC_LOW_BIT_POS_PROBE_OUT196 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT196 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011100011"; - attribute LC_LOW_BIT_POS_PROBE_OUT197 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT197 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011100100"; - attribute LC_LOW_BIT_POS_PROBE_OUT198 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT198 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011100101"; - attribute LC_LOW_BIT_POS_PROBE_OUT199 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT199 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011100110"; - attribute LC_LOW_BIT_POS_PROBE_OUT2 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT2 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000100001"; - attribute LC_LOW_BIT_POS_PROBE_OUT20 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT20 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000110011"; - attribute LC_LOW_BIT_POS_PROBE_OUT200 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT200 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011100111"; - attribute LC_LOW_BIT_POS_PROBE_OUT201 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT201 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011101000"; - attribute LC_LOW_BIT_POS_PROBE_OUT202 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT202 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011101001"; - attribute LC_LOW_BIT_POS_PROBE_OUT203 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT203 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011101010"; - attribute LC_LOW_BIT_POS_PROBE_OUT204 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT204 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011101011"; - attribute LC_LOW_BIT_POS_PROBE_OUT205 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT205 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011101100"; - attribute LC_LOW_BIT_POS_PROBE_OUT206 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT206 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011101101"; - attribute LC_LOW_BIT_POS_PROBE_OUT207 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT207 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011101110"; - attribute LC_LOW_BIT_POS_PROBE_OUT208 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT208 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011101111"; - attribute LC_LOW_BIT_POS_PROBE_OUT209 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT209 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011110000"; - attribute LC_LOW_BIT_POS_PROBE_OUT21 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT21 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000110100"; - attribute LC_LOW_BIT_POS_PROBE_OUT210 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT210 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011110001"; - attribute LC_LOW_BIT_POS_PROBE_OUT211 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT211 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011110010"; - attribute LC_LOW_BIT_POS_PROBE_OUT212 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT212 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011110011"; - attribute LC_LOW_BIT_POS_PROBE_OUT213 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT213 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011110100"; - attribute LC_LOW_BIT_POS_PROBE_OUT214 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT214 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011110101"; - attribute LC_LOW_BIT_POS_PROBE_OUT215 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT215 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011110110"; - attribute LC_LOW_BIT_POS_PROBE_OUT216 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT216 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011110111"; - attribute LC_LOW_BIT_POS_PROBE_OUT217 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT217 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011111000"; - attribute LC_LOW_BIT_POS_PROBE_OUT218 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT218 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011111001"; - attribute LC_LOW_BIT_POS_PROBE_OUT219 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT219 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011111010"; - attribute LC_LOW_BIT_POS_PROBE_OUT22 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT22 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000110101"; - attribute LC_LOW_BIT_POS_PROBE_OUT220 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT220 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011111011"; - attribute LC_LOW_BIT_POS_PROBE_OUT221 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT221 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011111100"; - attribute LC_LOW_BIT_POS_PROBE_OUT222 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT222 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011111101"; - attribute LC_LOW_BIT_POS_PROBE_OUT223 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT223 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011111110"; - attribute LC_LOW_BIT_POS_PROBE_OUT224 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT224 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000011111111"; - attribute LC_LOW_BIT_POS_PROBE_OUT225 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT225 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100000000"; - attribute LC_LOW_BIT_POS_PROBE_OUT226 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT226 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100000001"; - attribute LC_LOW_BIT_POS_PROBE_OUT227 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT227 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100000010"; - attribute LC_LOW_BIT_POS_PROBE_OUT228 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT228 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100000011"; - attribute LC_LOW_BIT_POS_PROBE_OUT229 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT229 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100000100"; - attribute LC_LOW_BIT_POS_PROBE_OUT23 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT23 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000110110"; - attribute LC_LOW_BIT_POS_PROBE_OUT230 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT230 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100000101"; - attribute LC_LOW_BIT_POS_PROBE_OUT231 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT231 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100000110"; - attribute LC_LOW_BIT_POS_PROBE_OUT232 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT232 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100000111"; - attribute LC_LOW_BIT_POS_PROBE_OUT233 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT233 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100001000"; - attribute LC_LOW_BIT_POS_PROBE_OUT234 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT234 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100001001"; - attribute LC_LOW_BIT_POS_PROBE_OUT235 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT235 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100001010"; - attribute LC_LOW_BIT_POS_PROBE_OUT236 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT236 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100001011"; - attribute LC_LOW_BIT_POS_PROBE_OUT237 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT237 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100001100"; - attribute LC_LOW_BIT_POS_PROBE_OUT238 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT238 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100001101"; - attribute LC_LOW_BIT_POS_PROBE_OUT239 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT239 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100001110"; - attribute LC_LOW_BIT_POS_PROBE_OUT24 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT24 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000110111"; - attribute LC_LOW_BIT_POS_PROBE_OUT240 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT240 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100001111"; - attribute LC_LOW_BIT_POS_PROBE_OUT241 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT241 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100010000"; - attribute LC_LOW_BIT_POS_PROBE_OUT242 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT242 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100010001"; - attribute LC_LOW_BIT_POS_PROBE_OUT243 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT243 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100010010"; - attribute LC_LOW_BIT_POS_PROBE_OUT244 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT244 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100010011"; - attribute LC_LOW_BIT_POS_PROBE_OUT245 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT245 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100010100"; - attribute LC_LOW_BIT_POS_PROBE_OUT246 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT246 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100010101"; - attribute LC_LOW_BIT_POS_PROBE_OUT247 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT247 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100010110"; - attribute LC_LOW_BIT_POS_PROBE_OUT248 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT248 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100010111"; - attribute LC_LOW_BIT_POS_PROBE_OUT249 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT249 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100011000"; - attribute LC_LOW_BIT_POS_PROBE_OUT25 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT25 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000111000"; - attribute LC_LOW_BIT_POS_PROBE_OUT250 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT250 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100011001"; - attribute LC_LOW_BIT_POS_PROBE_OUT251 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT251 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100011010"; - attribute LC_LOW_BIT_POS_PROBE_OUT252 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT252 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100011011"; - attribute LC_LOW_BIT_POS_PROBE_OUT253 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT253 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100011100"; - attribute LC_LOW_BIT_POS_PROBE_OUT254 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT254 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100011101"; - attribute LC_LOW_BIT_POS_PROBE_OUT255 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT255 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000100011110"; - attribute LC_LOW_BIT_POS_PROBE_OUT26 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT26 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000111001"; - attribute LC_LOW_BIT_POS_PROBE_OUT27 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT27 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000111010"; - attribute LC_LOW_BIT_POS_PROBE_OUT28 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT28 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000111011"; - attribute LC_LOW_BIT_POS_PROBE_OUT29 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT29 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000111100"; - attribute LC_LOW_BIT_POS_PROBE_OUT3 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT3 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000100010"; - attribute LC_LOW_BIT_POS_PROBE_OUT30 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT30 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000111101"; - attribute LC_LOW_BIT_POS_PROBE_OUT31 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT31 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000111110"; - attribute LC_LOW_BIT_POS_PROBE_OUT32 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT32 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000111111"; - attribute LC_LOW_BIT_POS_PROBE_OUT33 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT33 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001000000"; - attribute LC_LOW_BIT_POS_PROBE_OUT34 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT34 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001000001"; - attribute LC_LOW_BIT_POS_PROBE_OUT35 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT35 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001000010"; - attribute LC_LOW_BIT_POS_PROBE_OUT36 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT36 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001000011"; - attribute LC_LOW_BIT_POS_PROBE_OUT37 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT37 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001000100"; - attribute LC_LOW_BIT_POS_PROBE_OUT38 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT38 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001000101"; - attribute LC_LOW_BIT_POS_PROBE_OUT39 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT39 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001000110"; - attribute LC_LOW_BIT_POS_PROBE_OUT4 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT4 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000100011"; - attribute LC_LOW_BIT_POS_PROBE_OUT40 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT40 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001000111"; - attribute LC_LOW_BIT_POS_PROBE_OUT41 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT41 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001001000"; - attribute LC_LOW_BIT_POS_PROBE_OUT42 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT42 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001001001"; - attribute LC_LOW_BIT_POS_PROBE_OUT43 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT43 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001001010"; - attribute LC_LOW_BIT_POS_PROBE_OUT44 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT44 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001001011"; - attribute LC_LOW_BIT_POS_PROBE_OUT45 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT45 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001001100"; - attribute LC_LOW_BIT_POS_PROBE_OUT46 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT46 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001001101"; - attribute LC_LOW_BIT_POS_PROBE_OUT47 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT47 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001001110"; - attribute LC_LOW_BIT_POS_PROBE_OUT48 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT48 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001001111"; - attribute LC_LOW_BIT_POS_PROBE_OUT49 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT49 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001010000"; - attribute LC_LOW_BIT_POS_PROBE_OUT5 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT5 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000100100"; - attribute LC_LOW_BIT_POS_PROBE_OUT50 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT50 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001010001"; - attribute LC_LOW_BIT_POS_PROBE_OUT51 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT51 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001010010"; - attribute LC_LOW_BIT_POS_PROBE_OUT52 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT52 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001010011"; - attribute LC_LOW_BIT_POS_PROBE_OUT53 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT53 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001010100"; - attribute LC_LOW_BIT_POS_PROBE_OUT54 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT54 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001010101"; - attribute LC_LOW_BIT_POS_PROBE_OUT55 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT55 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001010110"; - attribute LC_LOW_BIT_POS_PROBE_OUT56 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT56 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001010111"; - attribute LC_LOW_BIT_POS_PROBE_OUT57 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT57 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001011000"; - attribute LC_LOW_BIT_POS_PROBE_OUT58 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT58 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001011001"; - attribute LC_LOW_BIT_POS_PROBE_OUT59 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT59 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001011010"; - attribute LC_LOW_BIT_POS_PROBE_OUT6 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT6 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000100101"; - attribute LC_LOW_BIT_POS_PROBE_OUT60 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT60 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001011011"; - attribute LC_LOW_BIT_POS_PROBE_OUT61 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT61 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001011100"; - attribute LC_LOW_BIT_POS_PROBE_OUT62 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT62 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001011101"; - attribute LC_LOW_BIT_POS_PROBE_OUT63 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT63 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001011110"; - attribute LC_LOW_BIT_POS_PROBE_OUT64 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT64 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001011111"; - attribute LC_LOW_BIT_POS_PROBE_OUT65 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT65 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001100000"; - attribute LC_LOW_BIT_POS_PROBE_OUT66 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT66 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001100001"; - attribute LC_LOW_BIT_POS_PROBE_OUT67 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT67 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001100010"; - attribute LC_LOW_BIT_POS_PROBE_OUT68 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT68 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001100011"; - attribute LC_LOW_BIT_POS_PROBE_OUT69 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT69 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001100100"; - attribute LC_LOW_BIT_POS_PROBE_OUT7 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT7 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000100110"; - attribute LC_LOW_BIT_POS_PROBE_OUT70 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT70 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001100101"; - attribute LC_LOW_BIT_POS_PROBE_OUT71 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT71 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001100110"; - attribute LC_LOW_BIT_POS_PROBE_OUT72 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT72 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001100111"; - attribute LC_LOW_BIT_POS_PROBE_OUT73 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT73 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001101000"; - attribute LC_LOW_BIT_POS_PROBE_OUT74 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT74 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001101001"; - attribute LC_LOW_BIT_POS_PROBE_OUT75 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT75 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001101010"; - attribute LC_LOW_BIT_POS_PROBE_OUT76 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT76 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001101011"; - attribute LC_LOW_BIT_POS_PROBE_OUT77 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT77 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001101100"; - attribute LC_LOW_BIT_POS_PROBE_OUT78 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT78 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001101101"; - attribute LC_LOW_BIT_POS_PROBE_OUT79 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT79 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001101110"; - attribute LC_LOW_BIT_POS_PROBE_OUT8 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT8 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000100111"; - attribute LC_LOW_BIT_POS_PROBE_OUT80 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT80 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001101111"; - attribute LC_LOW_BIT_POS_PROBE_OUT81 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT81 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001110000"; - attribute LC_LOW_BIT_POS_PROBE_OUT82 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT82 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001110001"; - attribute LC_LOW_BIT_POS_PROBE_OUT83 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT83 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001110010"; - attribute LC_LOW_BIT_POS_PROBE_OUT84 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT84 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001110011"; - attribute LC_LOW_BIT_POS_PROBE_OUT85 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT85 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001110100"; - attribute LC_LOW_BIT_POS_PROBE_OUT86 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT86 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001110101"; - attribute LC_LOW_BIT_POS_PROBE_OUT87 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT87 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001110110"; - attribute LC_LOW_BIT_POS_PROBE_OUT88 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT88 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001110111"; - attribute LC_LOW_BIT_POS_PROBE_OUT89 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT89 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001111000"; - attribute LC_LOW_BIT_POS_PROBE_OUT9 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT9 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000000101000"; - attribute LC_LOW_BIT_POS_PROBE_OUT90 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT90 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001111001"; - attribute LC_LOW_BIT_POS_PROBE_OUT91 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT91 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001111010"; - attribute LC_LOW_BIT_POS_PROBE_OUT92 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT92 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001111011"; - attribute LC_LOW_BIT_POS_PROBE_OUT93 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT93 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001111100"; - attribute LC_LOW_BIT_POS_PROBE_OUT94 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT94 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001111101"; - attribute LC_LOW_BIT_POS_PROBE_OUT95 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT95 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001111110"; - attribute LC_LOW_BIT_POS_PROBE_OUT96 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT96 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000001111111"; - attribute LC_LOW_BIT_POS_PROBE_OUT97 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT97 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010000000"; - attribute LC_LOW_BIT_POS_PROBE_OUT98 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT98 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010000001"; - attribute LC_LOW_BIT_POS_PROBE_OUT99 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT99 of vio_0_vio_v3_0_19_vio : entity is "16'b0000000010000010"; - attribute LC_PROBE_IN_WIDTH_STRING : string; - attribute LC_PROBE_IN_WIDTH_STRING of vio_0_vio_v3_0_19_vio : entity is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111100011111"; - attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING : string; - attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING of vio_0_vio_v3_0_19_vio : entity is "4096'b0000000100011110000000010001110100000001000111000000000100011011000000010001101000000001000110010000000100011000000000010001011100000001000101100000000100010101000000010001010000000001000100110000000100010010000000010001000100000001000100000000000100001111000000010000111000000001000011010000000100001100000000010000101100000001000010100000000100001001000000010000100000000001000001110000000100000110000000010000010100000001000001000000000100000011000000010000001000000001000000010000000100000000000000001111111100000000111111100000000011111101000000001111110000000000111110110000000011111010000000001111100100000000111110000000000011110111000000001111011000000000111101010000000011110100000000001111001100000000111100100000000011110001000000001111000000000000111011110000000011101110000000001110110100000000111011000000000011101011000000001110101000000000111010010000000011101000000000001110011100000000111001100000000011100101000000001110010000000000111000110000000011100010000000001110000100000000111000000000000011011111000000001101111000000000110111010000000011011100000000001101101100000000110110100000000011011001000000001101100000000000110101110000000011010110000000001101010100000000110101000000000011010011000000001101001000000000110100010000000011010000000000001100111100000000110011100000000011001101000000001100110000000000110010110000000011001010000000001100100100000000110010000000000011000111000000001100011000000000110001010000000011000100000000001100001100000000110000100000000011000001000000001100000000000000101111110000000010111110000000001011110100000000101111000000000010111011000000001011101000000000101110010000000010111000000000001011011100000000101101100000000010110101000000001011010000000000101100110000000010110010000000001011000100000000101100000000000010101111000000001010111000000000101011010000000010101100000000001010101100000000101010100000000010101001000000001010100000000000101001110000000010100110000000001010010100000000101001000000000010100011000000001010001000000000101000010000000010100000000000001001111100000000100111100000000010011101000000001001110000000000100110110000000010011010000000001001100100000000100110000000000010010111000000001001011000000000100101010000000010010100000000001001001100000000100100100000000010010001000000001001000000000000100011110000000010001110000000001000110100000000100011000000000010001011000000001000101000000000100010010000000010001000000000001000011100000000100001100000000010000101000000001000010000000000100000110000000010000010000000001000000100000000100000000000000001111111000000000111111000000000011111010000000001111100000000000111101100000000011110100000000001111001000000000111100000000000011101110000000001110110000000000111010100000000011101000000000001110011000000000111001000000000011100010000000001110000000000000110111100000000011011100000000001101101000000000110110000000000011010110000000001101010000000000110100100000000011010000000000001100111000000000110011000000000011001010000000001100100000000000110001100000000011000100000000001100001000000000110000000000000010111110000000001011110000000000101110100000000010111000000000001011011000000000101101000000000010110010000000001011000000000000101011100000000010101100000000001010101000000000101010000000000010100110000000001010010000000000101000100000000010100000000000001001111000000000100111000000000010011010000000001001100000000000100101100000000010010100000000001001001000000000100100000000000010001110000000001000110000000000100010100000000010001000000000001000011000000000100001000000000010000010000000001000000000000000011111100000000001111100000000000111101000000000011110000000000001110110000000000111010000000000011100100000000001110000000000000110111000000000011011000000000001101010000000000110100000000000011001100000000001100100000000000110001000000000011000000000000001011110000000000101110000000000010110100000000001011000000000000101011000000000010101000000000001010010000000000101000000000000010011100000000001001100000000000100101000000000010010000000000001000110000000000100010000000000010000100000000001000000000000000011111"; - attribute LC_PROBE_OUT_INIT_VAL_STRING : string; - attribute LC_PROBE_OUT_INIT_VAL_STRING of vio_0_vio_v3_0_19_vio : entity is "287'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute LC_PROBE_OUT_LOW_BIT_POS_STRING : string; - attribute LC_PROBE_OUT_LOW_BIT_POS_STRING of vio_0_vio_v3_0_19_vio : entity is "4096'b0000000100011110000000010001110100000001000111000000000100011011000000010001101000000001000110010000000100011000000000010001011100000001000101100000000100010101000000010001010000000001000100110000000100010010000000010001000100000001000100000000000100001111000000010000111000000001000011010000000100001100000000010000101100000001000010100000000100001001000000010000100000000001000001110000000100000110000000010000010100000001000001000000000100000011000000010000001000000001000000010000000100000000000000001111111100000000111111100000000011111101000000001111110000000000111110110000000011111010000000001111100100000000111110000000000011110111000000001111011000000000111101010000000011110100000000001111001100000000111100100000000011110001000000001111000000000000111011110000000011101110000000001110110100000000111011000000000011101011000000001110101000000000111010010000000011101000000000001110011100000000111001100000000011100101000000001110010000000000111000110000000011100010000000001110000100000000111000000000000011011111000000001101111000000000110111010000000011011100000000001101101100000000110110100000000011011001000000001101100000000000110101110000000011010110000000001101010100000000110101000000000011010011000000001101001000000000110100010000000011010000000000001100111100000000110011100000000011001101000000001100110000000000110010110000000011001010000000001100100100000000110010000000000011000111000000001100011000000000110001010000000011000100000000001100001100000000110000100000000011000001000000001100000000000000101111110000000010111110000000001011110100000000101111000000000010111011000000001011101000000000101110010000000010111000000000001011011100000000101101100000000010110101000000001011010000000000101100110000000010110010000000001011000100000000101100000000000010101111000000001010111000000000101011010000000010101100000000001010101100000000101010100000000010101001000000001010100000000000101001110000000010100110000000001010010100000000101001000000000010100011000000001010001000000000101000010000000010100000000000001001111100000000100111100000000010011101000000001001110000000000100110110000000010011010000000001001100100000000100110000000000010010111000000001001011000000000100101010000000010010100000000001001001100000000100100100000000010010001000000001001000000000000100011110000000010001110000000001000110100000000100011000000000010001011000000001000101000000000100010010000000010001000000000001000011100000000100001100000000010000101000000001000010000000000100000110000000010000010000000001000000100000000100000000000000001111111000000000111111000000000011111010000000001111100000000000111101100000000011110100000000001111001000000000111100000000000011101110000000001110110000000000111010100000000011101000000000001110011000000000111001000000000011100010000000001110000000000000110111100000000011011100000000001101101000000000110110000000000011010110000000001101010000000000110100100000000011010000000000001100111000000000110011000000000011001010000000001100100000000000110001100000000011000100000000001100001000000000110000000000000010111110000000001011110000000000101110100000000010111000000000001011011000000000101101000000000010110010000000001011000000000000101011100000000010101100000000001010101000000000101010000000000010100110000000001010010000000000101000100000000010100000000000001001111000000000100111000000000010011010000000001001100000000000100101100000000010010100000000001001001000000000100100000000000010001110000000001000110000000000100010100000000010001000000000001000011000000000100001000000000010000010000000001000000000000000011111100000000001111100000000000111101000000000011110000000000001110110000000000111010000000000011100100000000001110000000000000110111000000000011011000000000001101010000000000110100000000000011001100000000001100100000000000110001000000000011000000000000001011110000000000101110000000000010110100000000001011000000000000101011000000000010101000000000001010010000000000101000000000000010011100000000001001100000000000100101000000000010010000000000001000110000000000100010000000000010000100000000001000000000000000000000"; - attribute LC_PROBE_OUT_WIDTH_STRING : string; - attribute LC_PROBE_OUT_WIDTH_STRING of vio_0_vio_v3_0_19_vio : entity is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111"; - attribute LC_TOTAL_PROBE_IN_WIDTH : integer; - attribute LC_TOTAL_PROBE_IN_WIDTH of vio_0_vio_v3_0_19_vio : entity is 64; - attribute LC_TOTAL_PROBE_OUT_WIDTH : integer; - attribute LC_TOTAL_PROBE_OUT_WIDTH of vio_0_vio_v3_0_19_vio : entity is 32; - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of vio_0_vio_v3_0_19_vio : entity is "vio_v3_0_19_vio"; - attribute dont_touch : string; - attribute dont_touch of vio_0_vio_v3_0_19_vio : entity is "true"; -end vio_0_vio_v3_0_19_vio; - -architecture STRUCTURE of vio_0_vio_v3_0_19_vio is - signal \\ : STD_LOGIC; - signal Bus_Data_out : STD_LOGIC_VECTOR ( 15 downto 0 ); - signal DECODER_INST_n_10 : STD_LOGIC; - signal DECODER_INST_n_4 : STD_LOGIC; - signal DECODER_INST_n_6 : STD_LOGIC; - signal DECODER_INST_n_7 : STD_LOGIC; - signal DECODER_INST_n_8 : STD_LOGIC; - signal PROBE_OUT_ALL_INST_n_32 : STD_LOGIC; - signal PROBE_OUT_ALL_INST_n_33 : STD_LOGIC; - signal PROBE_OUT_ALL_INST_n_34 : STD_LOGIC; - signal PROBE_OUT_ALL_INST_n_35 : STD_LOGIC; - signal PROBE_OUT_ALL_INST_n_36 : STD_LOGIC; - signal PROBE_OUT_ALL_INST_n_37 : STD_LOGIC; - signal PROBE_OUT_ALL_INST_n_38 : STD_LOGIC; - signal PROBE_OUT_ALL_INST_n_39 : STD_LOGIC; - signal PROBE_OUT_ALL_INST_n_40 : STD_LOGIC; - signal PROBE_OUT_ALL_INST_n_41 : STD_LOGIC; - signal PROBE_OUT_ALL_INST_n_42 : STD_LOGIC; - signal PROBE_OUT_ALL_INST_n_43 : STD_LOGIC; - signal PROBE_OUT_ALL_INST_n_44 : STD_LOGIC; - signal PROBE_OUT_ALL_INST_n_45 : STD_LOGIC; - signal PROBE_OUT_ALL_INST_n_46 : STD_LOGIC; - signal PROBE_OUT_ALL_INST_n_47 : STD_LOGIC; - signal addr_count_reg0 : STD_LOGIC; - signal addr_count_reg1 : STD_LOGIC; - signal bus_addr : STD_LOGIC_VECTOR ( 16 downto 0 ); - signal bus_clk : STD_LOGIC; - attribute DONT_TOUCH_boolean : boolean; - attribute DONT_TOUCH_boolean of bus_clk : signal is std.standard.true; - signal \bus_data_int_reg_n_0_[0]\ : STD_LOGIC; - signal \bus_data_int_reg_n_0_[10]\ : STD_LOGIC; - signal \bus_data_int_reg_n_0_[11]\ : STD_LOGIC; - signal \bus_data_int_reg_n_0_[12]\ : STD_LOGIC; - signal \bus_data_int_reg_n_0_[13]\ : STD_LOGIC; - signal \bus_data_int_reg_n_0_[14]\ : STD_LOGIC; - signal \bus_data_int_reg_n_0_[15]\ : STD_LOGIC; - signal \bus_data_int_reg_n_0_[2]\ : STD_LOGIC; - signal \bus_data_int_reg_n_0_[3]\ : STD_LOGIC; - signal \bus_data_int_reg_n_0_[4]\ : STD_LOGIC; - signal \bus_data_int_reg_n_0_[5]\ : STD_LOGIC; - signal \bus_data_int_reg_n_0_[6]\ : STD_LOGIC; - signal \bus_data_int_reg_n_0_[7]\ : STD_LOGIC; - signal \bus_data_int_reg_n_0_[8]\ : STD_LOGIC; - signal \bus_data_int_reg_n_0_[9]\ : STD_LOGIC; - signal bus_den : STD_LOGIC; - signal bus_di : STD_LOGIC_VECTOR ( 15 downto 0 ); - signal bus_do : STD_LOGIC_VECTOR ( 15 downto 0 ); - signal bus_drdy : STD_LOGIC; - signal bus_dwe : STD_LOGIC; - signal bus_rst : STD_LOGIC; - signal clear : STD_LOGIC; - signal committ : STD_LOGIC; - signal internal_cnt_rst : STD_LOGIC; - signal p_0_in : STD_LOGIC; - signal xsdb_rd : STD_LOGIC; - signal \xsdb_wr__0\ : STD_LOGIC; - attribute C_BUILD_REVISION of U_XSDB_SLAVE : label is 0; - attribute C_CORE_INFO1 of U_XSDB_SLAVE : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute C_CORE_INFO2 of U_XSDB_SLAVE : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute C_CORE_MAJOR_VER of U_XSDB_SLAVE : label is 2; - attribute C_CORE_MINOR_VER of U_XSDB_SLAVE : label is 0; - attribute C_CORE_TYPE of U_XSDB_SLAVE : label is 2; - attribute C_CSE_DRV_VER of U_XSDB_SLAVE : label is 1; - attribute C_MAJOR_VERSION of U_XSDB_SLAVE : label is 2013; - attribute C_MINOR_VERSION of U_XSDB_SLAVE : label is 1; - attribute C_NEXT_SLAVE of U_XSDB_SLAVE : label is 0; - attribute C_PIPE_IFACE of U_XSDB_SLAVE : label is 0; - attribute C_USE_TEST_REG of U_XSDB_SLAVE : label is 1; - attribute C_XDEVICEFAMILY of U_XSDB_SLAVE : label is "zynq"; - attribute C_XSDB_SLAVE_TYPE of U_XSDB_SLAVE : label is 33; - attribute DONT_TOUCH_boolean of U_XSDB_SLAVE : label is std.standard.true; - attribute dont_touch of sl_iport0 : signal is "true"; - attribute dont_touch of sl_oport0 : signal is "true"; -begin - probe_out1(0) <= \\; - probe_out10(0) <= \\; - probe_out100(0) <= \\; - probe_out101(0) <= \\; - probe_out102(0) <= \\; - probe_out103(0) <= \\; - probe_out104(0) <= \\; - probe_out105(0) <= \\; - probe_out106(0) <= \\; - probe_out107(0) <= \\; - probe_out108(0) <= \\; - probe_out109(0) <= \\; - probe_out11(0) <= \\; - probe_out110(0) <= \\; - probe_out111(0) <= \\; - probe_out112(0) <= \\; - probe_out113(0) <= \\; - probe_out114(0) <= \\; - probe_out115(0) <= \\; - probe_out116(0) <= \\; - probe_out117(0) <= \\; - probe_out118(0) <= \\; - probe_out119(0) <= \\; - probe_out12(0) <= \\; - probe_out120(0) <= \\; - probe_out121(0) <= \\; - probe_out122(0) <= \\; - probe_out123(0) <= \\; - probe_out124(0) <= \\; - probe_out125(0) <= \\; - probe_out126(0) <= \\; - probe_out127(0) <= \\; - probe_out128(0) <= \\; - probe_out129(0) <= \\; - probe_out13(0) <= \\; - probe_out130(0) <= \\; - probe_out131(0) <= \\; - probe_out132(0) <= \\; - probe_out133(0) <= \\; - probe_out134(0) <= \\; - probe_out135(0) <= \\; - probe_out136(0) <= \\; - probe_out137(0) <= \\; - probe_out138(0) <= \\; - probe_out139(0) <= \\; - probe_out14(0) <= \\; - probe_out140(0) <= \\; - probe_out141(0) <= \\; - probe_out142(0) <= \\; - probe_out143(0) <= \\; - probe_out144(0) <= \\; - probe_out145(0) <= \\; - probe_out146(0) <= \\; - probe_out147(0) <= \\; - probe_out148(0) <= \\; - probe_out149(0) <= \\; - probe_out15(0) <= \\; - probe_out150(0) <= \\; - probe_out151(0) <= \\; - probe_out152(0) <= \\; - probe_out153(0) <= \\; - probe_out154(0) <= \\; - probe_out155(0) <= \\; - probe_out156(0) <= \\; - probe_out157(0) <= \\; - probe_out158(0) <= \\; - probe_out159(0) <= \\; - probe_out16(0) <= \\; - probe_out160(0) <= \\; - probe_out161(0) <= \\; - probe_out162(0) <= \\; - probe_out163(0) <= \\; - probe_out164(0) <= \\; - probe_out165(0) <= \\; - probe_out166(0) <= \\; - probe_out167(0) <= \\; - probe_out168(0) <= \\; - probe_out169(0) <= \\; - probe_out17(0) <= \\; - probe_out170(0) <= \\; - probe_out171(0) <= \\; - probe_out172(0) <= \\; - probe_out173(0) <= \\; - probe_out174(0) <= \\; - probe_out175(0) <= \\; - probe_out176(0) <= \\; - probe_out177(0) <= \\; - probe_out178(0) <= \\; - probe_out179(0) <= \\; - probe_out18(0) <= \\; - probe_out180(0) <= \\; - probe_out181(0) <= \\; - probe_out182(0) <= \\; - probe_out183(0) <= \\; - probe_out184(0) <= \\; - probe_out185(0) <= \\; - probe_out186(0) <= \\; - probe_out187(0) <= \\; - probe_out188(0) <= \\; - probe_out189(0) <= \\; - probe_out19(0) <= \\; - probe_out190(0) <= \\; - probe_out191(0) <= \\; - probe_out192(0) <= \\; - probe_out193(0) <= \\; - probe_out194(0) <= \\; - probe_out195(0) <= \\; - probe_out196(0) <= \\; - probe_out197(0) <= \\; - probe_out198(0) <= \\; - probe_out199(0) <= \\; - probe_out2(0) <= \\; - probe_out20(0) <= \\; - probe_out200(0) <= \\; - probe_out201(0) <= \\; - probe_out202(0) <= \\; - probe_out203(0) <= \\; - probe_out204(0) <= \\; - probe_out205(0) <= \\; - probe_out206(0) <= \\; - probe_out207(0) <= \\; - probe_out208(0) <= \\; - probe_out209(0) <= \\; - probe_out21(0) <= \\; - probe_out210(0) <= \\; - probe_out211(0) <= \\; - probe_out212(0) <= \\; - probe_out213(0) <= \\; - probe_out214(0) <= \\; - probe_out215(0) <= \\; - probe_out216(0) <= \\; - probe_out217(0) <= \\; - probe_out218(0) <= \\; - probe_out219(0) <= \\; - probe_out22(0) <= \\; - probe_out220(0) <= \\; - probe_out221(0) <= \\; - probe_out222(0) <= \\; - probe_out223(0) <= \\; - probe_out224(0) <= \\; - probe_out225(0) <= \\; - probe_out226(0) <= \\; - probe_out227(0) <= \\; - probe_out228(0) <= \\; - probe_out229(0) <= \\; - probe_out23(0) <= \\; - probe_out230(0) <= \\; - probe_out231(0) <= \\; - probe_out232(0) <= \\; - probe_out233(0) <= \\; - probe_out234(0) <= \\; - probe_out235(0) <= \\; - probe_out236(0) <= \\; - probe_out237(0) <= \\; - probe_out238(0) <= \\; - probe_out239(0) <= \\; - probe_out24(0) <= \\; - probe_out240(0) <= \\; - probe_out241(0) <= \\; - probe_out242(0) <= \\; - probe_out243(0) <= \\; - probe_out244(0) <= \\; - probe_out245(0) <= \\; - probe_out246(0) <= \\; - probe_out247(0) <= \\; - probe_out248(0) <= \\; - probe_out249(0) <= \\; - probe_out25(0) <= \\; - probe_out250(0) <= \\; - probe_out251(0) <= \\; - probe_out252(0) <= \\; - probe_out253(0) <= \\; - probe_out254(0) <= \\; - probe_out255(0) <= \\; - probe_out26(0) <= \\; - probe_out27(0) <= \\; - probe_out28(0) <= \\; - probe_out29(0) <= \\; - probe_out3(0) <= \\; - probe_out30(0) <= \\; - probe_out31(0) <= \\; - probe_out32(0) <= \\; - probe_out33(0) <= \\; - probe_out34(0) <= \\; - probe_out35(0) <= \\; - probe_out36(0) <= \\; - probe_out37(0) <= \\; - probe_out38(0) <= \\; - probe_out39(0) <= \\; - probe_out4(0) <= \\; - probe_out40(0) <= \\; - probe_out41(0) <= \\; - probe_out42(0) <= \\; - probe_out43(0) <= \\; - probe_out44(0) <= \\; - probe_out45(0) <= \\; - probe_out46(0) <= \\; - probe_out47(0) <= \\; - probe_out48(0) <= \\; - probe_out49(0) <= \\; - probe_out5(0) <= \\; - probe_out50(0) <= \\; - probe_out51(0) <= \\; - probe_out52(0) <= \\; - probe_out53(0) <= \\; - probe_out54(0) <= \\; - probe_out55(0) <= \\; - probe_out56(0) <= \\; - probe_out57(0) <= \\; - probe_out58(0) <= \\; - probe_out59(0) <= \\; - probe_out6(0) <= \\; - probe_out60(0) <= \\; - probe_out61(0) <= \\; - probe_out62(0) <= \\; - probe_out63(0) <= \\; - probe_out64(0) <= \\; - probe_out65(0) <= \\; - probe_out66(0) <= \\; - probe_out67(0) <= \\; - probe_out68(0) <= \\; - probe_out69(0) <= \\; - probe_out7(0) <= \\; - probe_out70(0) <= \\; - probe_out71(0) <= \\; - probe_out72(0) <= \\; - probe_out73(0) <= \\; - probe_out74(0) <= \\; - probe_out75(0) <= \\; - probe_out76(0) <= \\; - probe_out77(0) <= \\; - probe_out78(0) <= \\; - probe_out79(0) <= \\; - probe_out8(0) <= \\; - probe_out80(0) <= \\; - probe_out81(0) <= \\; - probe_out82(0) <= \\; - probe_out83(0) <= \\; - probe_out84(0) <= \\; - probe_out85(0) <= \\; - probe_out86(0) <= \\; - probe_out87(0) <= \\; - probe_out88(0) <= \\; - probe_out89(0) <= \\; - probe_out9(0) <= \\; - probe_out90(0) <= \\; - probe_out91(0) <= \\; - probe_out92(0) <= \\; - probe_out93(0) <= \\; - probe_out94(0) <= \\; - probe_out95(0) <= \\; - probe_out96(0) <= \\; - probe_out97(0) <= \\; - probe_out98(0) <= \\; - probe_out99(0) <= \\; -DECODER_INST: entity work.vio_0_vio_v3_0_19_decoder - port map ( - \Bus_data_out_reg[15]_0\(15 downto 0) => bus_do(15 downto 0), - \Bus_data_out_reg[15]_1\(15 downto 0) => Bus_Data_out(15 downto 0), - \Bus_data_out_reg[15]_2\(15) => PROBE_OUT_ALL_INST_n_32, - \Bus_data_out_reg[15]_2\(14) => PROBE_OUT_ALL_INST_n_33, - \Bus_data_out_reg[15]_2\(13) => PROBE_OUT_ALL_INST_n_34, - \Bus_data_out_reg[15]_2\(12) => PROBE_OUT_ALL_INST_n_35, - \Bus_data_out_reg[15]_2\(11) => PROBE_OUT_ALL_INST_n_36, - \Bus_data_out_reg[15]_2\(10) => PROBE_OUT_ALL_INST_n_37, - \Bus_data_out_reg[15]_2\(9) => PROBE_OUT_ALL_INST_n_38, - \Bus_data_out_reg[15]_2\(8) => PROBE_OUT_ALL_INST_n_39, - \Bus_data_out_reg[15]_2\(7) => PROBE_OUT_ALL_INST_n_40, - \Bus_data_out_reg[15]_2\(6) => PROBE_OUT_ALL_INST_n_41, - \Bus_data_out_reg[15]_2\(5) => PROBE_OUT_ALL_INST_n_42, - \Bus_data_out_reg[15]_2\(4) => PROBE_OUT_ALL_INST_n_43, - \Bus_data_out_reg[15]_2\(3) => PROBE_OUT_ALL_INST_n_44, - \Bus_data_out_reg[15]_2\(2) => PROBE_OUT_ALL_INST_n_45, - \Bus_data_out_reg[15]_2\(1) => PROBE_OUT_ALL_INST_n_46, - \Bus_data_out_reg[15]_2\(0) => PROBE_OUT_ALL_INST_n_47, - CLK => bus_clk, - E(0) => DECODER_INST_n_10, - Q(15) => \bus_data_int_reg_n_0_[15]\, - Q(14) => \bus_data_int_reg_n_0_[14]\, - Q(13) => \bus_data_int_reg_n_0_[13]\, - Q(12) => \bus_data_int_reg_n_0_[12]\, - Q(11) => \bus_data_int_reg_n_0_[11]\, - Q(10) => \bus_data_int_reg_n_0_[10]\, - Q(9) => \bus_data_int_reg_n_0_[9]\, - Q(8) => \bus_data_int_reg_n_0_[8]\, - Q(7) => \bus_data_int_reg_n_0_[7]\, - Q(6) => \bus_data_int_reg_n_0_[6]\, - Q(5) => \bus_data_int_reg_n_0_[5]\, - Q(4) => \bus_data_int_reg_n_0_[4]\, - Q(3) => \bus_data_int_reg_n_0_[3]\, - Q(2) => \bus_data_int_reg_n_0_[2]\, - Q(1) => p_0_in, - Q(0) => \bus_data_int_reg_n_0_[0]\, - Read_int_i_7_0 => DECODER_INST_n_7, - Read_int_i_7_1 => DECODER_INST_n_8, - SR(0) => clear, - addr_count_reg1 => addr_count_reg1, - in0 => committ, - int_cnt_rst_reg_0(0) => addr_count_reg0, - internal_cnt_rst => internal_cnt_rst, - s_daddr_o(16 downto 0) => bus_addr(16 downto 0), - s_den_o => bus_den, - s_drdy_i => bus_drdy, - s_dwe_o => bus_dwe, - s_rst_o => bus_rst, - \wr_en[2]_i_2_0\ => DECODER_INST_n_4, - \wr_en[2]_i_4_0\ => DECODER_INST_n_6, - xsdb_rd => xsdb_rd, - \xsdb_wr__0\ => \xsdb_wr__0\ - ); -GND: unisim.vcomponents.GND - port map ( - G => \\ - ); -PROBE_IN_INST: entity work.vio_0_vio_v3_0_19_probe_in_one - port map ( - CLK => bus_clk, - D(63 downto 32) => probe_in1(31 downto 0), - D(31 downto 0) => probe_in0(31 downto 0), - E(0) => DECODER_INST_n_10, - Q(15 downto 0) => Bus_Data_out(15 downto 0), - Read_int_reg_0 => DECODER_INST_n_8, - SR(0) => addr_count_reg0, - addr_count_reg1 => addr_count_reg1, - \^clk\ => clk, - s_daddr_o(16 downto 0) => bus_addr(16 downto 0), - s_den_o => bus_den, - s_dwe_o => bus_dwe, - xsdb_rd => xsdb_rd - ); -PROBE_OUT_ALL_INST: entity work.vio_0_vio_v3_0_19_probe_out_all - port map ( - CLK => bus_clk, - \G_PROBE_OUT[0].wr_probe_out_reg[0]_0\ => DECODER_INST_n_4, - \G_PROBE_OUT[0].wr_probe_out_reg[0]_1\ => DECODER_INST_n_7, - \G_PROBE_OUT[0].wr_probe_out_reg[0]_2\ => DECODER_INST_n_6, - \Probe_out_reg_int_reg[15]_0\(15) => PROBE_OUT_ALL_INST_n_32, - \Probe_out_reg_int_reg[15]_0\(14) => PROBE_OUT_ALL_INST_n_33, - \Probe_out_reg_int_reg[15]_0\(13) => PROBE_OUT_ALL_INST_n_34, - \Probe_out_reg_int_reg[15]_0\(12) => PROBE_OUT_ALL_INST_n_35, - \Probe_out_reg_int_reg[15]_0\(11) => PROBE_OUT_ALL_INST_n_36, - \Probe_out_reg_int_reg[15]_0\(10) => PROBE_OUT_ALL_INST_n_37, - \Probe_out_reg_int_reg[15]_0\(9) => PROBE_OUT_ALL_INST_n_38, - \Probe_out_reg_int_reg[15]_0\(8) => PROBE_OUT_ALL_INST_n_39, - \Probe_out_reg_int_reg[15]_0\(7) => PROBE_OUT_ALL_INST_n_40, - \Probe_out_reg_int_reg[15]_0\(6) => PROBE_OUT_ALL_INST_n_41, - \Probe_out_reg_int_reg[15]_0\(5) => PROBE_OUT_ALL_INST_n_42, - \Probe_out_reg_int_reg[15]_0\(4) => PROBE_OUT_ALL_INST_n_43, - \Probe_out_reg_int_reg[15]_0\(3) => PROBE_OUT_ALL_INST_n_44, - \Probe_out_reg_int_reg[15]_0\(2) => PROBE_OUT_ALL_INST_n_45, - \Probe_out_reg_int_reg[15]_0\(1) => PROBE_OUT_ALL_INST_n_46, - \Probe_out_reg_int_reg[15]_0\(0) => PROBE_OUT_ALL_INST_n_47, - Q(15) => \bus_data_int_reg_n_0_[15]\, - Q(14) => \bus_data_int_reg_n_0_[14]\, - Q(13) => \bus_data_int_reg_n_0_[13]\, - Q(12) => \bus_data_int_reg_n_0_[12]\, - Q(11) => \bus_data_int_reg_n_0_[11]\, - Q(10) => \bus_data_int_reg_n_0_[10]\, - Q(9) => \bus_data_int_reg_n_0_[9]\, - Q(8) => \bus_data_int_reg_n_0_[8]\, - Q(7) => \bus_data_int_reg_n_0_[7]\, - Q(6) => \bus_data_int_reg_n_0_[6]\, - Q(5) => \bus_data_int_reg_n_0_[5]\, - Q(4) => \bus_data_int_reg_n_0_[4]\, - Q(3) => \bus_data_int_reg_n_0_[3]\, - Q(2) => \bus_data_int_reg_n_0_[2]\, - Q(1) => p_0_in, - Q(0) => \bus_data_int_reg_n_0_[0]\, - SR(0) => clear, - \^clk\ => clk, - in0 => committ, - internal_cnt_rst => internal_cnt_rst, - probe_out0(31 downto 0) => probe_out0(31 downto 0), - s_daddr_o(10 downto 3) => bus_addr(15 downto 8), - s_daddr_o(2 downto 0) => bus_addr(3 downto 1), - s_den_o => bus_den, - s_dwe_o => bus_dwe, - \xsdb_wr__0\ => \xsdb_wr__0\ - ); -U_XSDB_SLAVE: entity work.vio_0_xsdbs_v1_0_2_xsdbs - port map ( - s_daddr_o(16 downto 0) => bus_addr(16 downto 0), - s_dclk_o => bus_clk, - s_den_o => bus_den, - s_di_o(15 downto 0) => bus_di(15 downto 0), - s_do_i(15 downto 0) => bus_do(15 downto 0), - s_drdy_i => bus_drdy, - s_dwe_o => bus_dwe, - s_rst_o => bus_rst, - sl_iport_i(36 downto 0) => sl_iport0(36 downto 0), - sl_oport_o(16 downto 0) => sl_oport0(16 downto 0) - ); -\bus_data_int_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => bus_clk, - CE => '1', - D => bus_di(0), - Q => \bus_data_int_reg_n_0_[0]\, - R => '0' - ); -\bus_data_int_reg[10]\: unisim.vcomponents.FDRE - port map ( - C => bus_clk, - CE => '1', - D => bus_di(10), - Q => \bus_data_int_reg_n_0_[10]\, - R => '0' - ); -\bus_data_int_reg[11]\: unisim.vcomponents.FDRE - port map ( - C => bus_clk, - CE => '1', - D => bus_di(11), - Q => \bus_data_int_reg_n_0_[11]\, - R => '0' - ); -\bus_data_int_reg[12]\: unisim.vcomponents.FDRE - port map ( - C => bus_clk, - CE => '1', - D => bus_di(12), - Q => \bus_data_int_reg_n_0_[12]\, - R => '0' - ); -\bus_data_int_reg[13]\: unisim.vcomponents.FDRE - port map ( - C => bus_clk, - CE => '1', - D => bus_di(13), - Q => \bus_data_int_reg_n_0_[13]\, - R => '0' - ); -\bus_data_int_reg[14]\: unisim.vcomponents.FDRE - port map ( - C => bus_clk, - CE => '1', - D => bus_di(14), - Q => \bus_data_int_reg_n_0_[14]\, - R => '0' - ); -\bus_data_int_reg[15]\: unisim.vcomponents.FDRE - port map ( - C => bus_clk, - CE => '1', - D => bus_di(15), - Q => \bus_data_int_reg_n_0_[15]\, - R => '0' - ); -\bus_data_int_reg[1]\: unisim.vcomponents.FDRE - port map ( - C => bus_clk, - CE => '1', - D => bus_di(1), - Q => p_0_in, - R => '0' - ); -\bus_data_int_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => bus_clk, - CE => '1', - D => bus_di(2), - Q => \bus_data_int_reg_n_0_[2]\, - R => '0' - ); -\bus_data_int_reg[3]\: unisim.vcomponents.FDRE - port map ( - C => bus_clk, - CE => '1', - D => bus_di(3), - Q => \bus_data_int_reg_n_0_[3]\, - R => '0' - ); -\bus_data_int_reg[4]\: unisim.vcomponents.FDRE - port map ( - C => bus_clk, - CE => '1', - D => bus_di(4), - Q => \bus_data_int_reg_n_0_[4]\, - R => '0' - ); -\bus_data_int_reg[5]\: unisim.vcomponents.FDRE - port map ( - C => bus_clk, - CE => '1', - D => bus_di(5), - Q => \bus_data_int_reg_n_0_[5]\, - R => '0' - ); -\bus_data_int_reg[6]\: unisim.vcomponents.FDRE - port map ( - C => bus_clk, - CE => '1', - D => bus_di(6), - Q => \bus_data_int_reg_n_0_[6]\, - R => '0' - ); -\bus_data_int_reg[7]\: unisim.vcomponents.FDRE - port map ( - C => bus_clk, - CE => '1', - D => bus_di(7), - Q => \bus_data_int_reg_n_0_[7]\, - R => '0' - ); -\bus_data_int_reg[8]\: unisim.vcomponents.FDRE - port map ( - C => bus_clk, - CE => '1', - D => bus_di(8), - Q => \bus_data_int_reg_n_0_[8]\, - R => '0' - ); -\bus_data_int_reg[9]\: unisim.vcomponents.FDRE - port map ( - C => bus_clk, - CE => '1', - D => bus_di(9), - Q => \bus_data_int_reg_n_0_[9]\, - R => '0' - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity vio_0 is - port ( - clk : in STD_LOGIC; - probe_in0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); - probe_in1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); - probe_out0 : out STD_LOGIC_VECTOR ( 31 downto 0 ) - ); - attribute NotValidForBitStream : boolean; - attribute NotValidForBitStream of vio_0 : entity is true; - attribute CHECK_LICENSE_TYPE : string; - attribute CHECK_LICENSE_TYPE of vio_0 : entity is "vio_0,vio,{}"; - attribute X_CORE_INFO : string; - attribute X_CORE_INFO of vio_0 : entity is "vio,Vivado 2019.2"; -end vio_0; - -architecture STRUCTURE of vio_0 is - signal NLW_inst_probe_out1_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out10_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out100_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out101_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out102_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out103_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out104_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out105_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out106_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out107_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out108_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out109_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out11_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out110_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out111_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out112_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out113_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out114_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out115_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out116_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out117_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out118_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out119_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out12_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out120_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out121_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out122_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out123_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out124_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out125_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out126_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out127_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out128_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out129_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out13_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out130_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out131_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out132_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out133_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out134_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out135_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out136_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out137_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out138_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out139_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out14_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out140_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out141_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out142_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out143_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out144_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out145_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out146_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out147_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out148_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out149_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out15_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out150_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out151_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out152_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out153_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out154_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out155_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out156_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out157_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out158_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out159_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out16_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out160_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out161_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out162_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out163_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out164_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out165_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out166_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out167_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out168_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out169_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out17_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out170_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out171_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out172_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out173_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out174_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out175_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out176_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out177_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out178_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out179_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out18_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out180_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out181_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out182_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out183_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out184_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out185_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out186_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out187_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out188_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out189_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out19_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out190_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out191_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out192_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out193_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out194_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out195_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out196_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out197_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out198_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out199_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out2_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out20_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out200_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out201_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out202_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out203_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out204_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out205_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out206_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out207_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out208_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out209_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out21_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out210_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out211_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out212_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out213_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out214_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out215_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out216_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out217_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out218_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out219_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out22_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out220_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out221_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out222_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out223_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out224_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out225_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out226_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out227_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out228_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out229_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out23_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out230_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out231_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out232_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out233_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out234_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out235_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out236_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out237_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out238_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out239_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out24_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out240_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out241_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out242_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out243_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out244_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out245_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out246_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out247_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out248_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out249_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out25_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out250_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out251_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out252_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out253_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out254_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out255_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out26_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out27_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out28_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out29_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out3_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out30_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out31_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out32_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out33_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out34_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out35_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out36_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out37_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out38_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out39_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out4_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out40_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out41_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out42_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out43_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out44_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out45_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out46_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out47_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out48_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out49_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out5_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out50_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out51_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out52_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out53_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out54_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out55_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out56_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out57_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out58_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out59_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out6_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out60_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out61_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out62_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out63_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out64_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out65_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out66_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out67_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out68_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out69_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out7_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out70_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out71_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out72_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out73_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out74_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out75_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out76_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out77_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out78_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out79_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out8_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out80_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out81_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out82_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out83_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out84_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out85_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out86_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out87_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out88_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out89_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out9_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out90_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out91_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out92_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out93_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out94_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out95_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out96_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out97_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out98_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_probe_out99_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_sl_oport0_UNCONNECTED : STD_LOGIC_VECTOR ( 16 downto 0 ); - attribute C_BUILD_REVISION : integer; - attribute C_BUILD_REVISION of inst : label is 0; - attribute C_BUS_ADDR_WIDTH : integer; - attribute C_BUS_ADDR_WIDTH of inst : label is 17; - attribute C_BUS_DATA_WIDTH : integer; - attribute C_BUS_DATA_WIDTH of inst : label is 16; - attribute C_CORE_INFO1 : string; - attribute C_CORE_INFO1 of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute C_CORE_INFO2 : string; - attribute C_CORE_INFO2 of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute C_CORE_MAJOR_VER : integer; - attribute C_CORE_MAJOR_VER of inst : label is 2; - attribute C_CORE_MINOR_ALPHA_VER : integer; - attribute C_CORE_MINOR_ALPHA_VER of inst : label is 97; - attribute C_CORE_MINOR_VER : integer; - attribute C_CORE_MINOR_VER of inst : label is 0; - attribute C_CORE_TYPE : integer; - attribute C_CORE_TYPE of inst : label is 2; - attribute C_CSE_DRV_VER : integer; - attribute C_CSE_DRV_VER of inst : label is 1; - attribute C_EN_PROBE_IN_ACTIVITY : integer; - attribute C_EN_PROBE_IN_ACTIVITY of inst : label is 1; - attribute C_EN_SYNCHRONIZATION : integer; - attribute C_EN_SYNCHRONIZATION of inst : label is 1; - attribute C_MAJOR_VERSION : integer; - attribute C_MAJOR_VERSION of inst : label is 2013; - attribute C_MAX_NUM_PROBE : integer; - attribute C_MAX_NUM_PROBE of inst : label is 256; - attribute C_MAX_WIDTH_PER_PROBE : integer; - attribute C_MAX_WIDTH_PER_PROBE of inst : label is 256; - attribute C_MINOR_VERSION : integer; - attribute C_MINOR_VERSION of inst : label is 1; - attribute C_NEXT_SLAVE : integer; - attribute C_NEXT_SLAVE of inst : label is 0; - attribute C_NUM_PROBE_IN : integer; - attribute C_NUM_PROBE_IN of inst : label is 2; - attribute C_NUM_PROBE_OUT : integer; - attribute C_NUM_PROBE_OUT of inst : label is 1; - attribute C_PIPE_IFACE : integer; - attribute C_PIPE_IFACE of inst : label is 0; - attribute C_PROBE_IN0_WIDTH : integer; - attribute C_PROBE_IN0_WIDTH of inst : label is 32; - attribute C_PROBE_IN100_WIDTH : integer; - attribute C_PROBE_IN100_WIDTH of inst : label is 1; - attribute C_PROBE_IN101_WIDTH : integer; - attribute C_PROBE_IN101_WIDTH of inst : label is 1; - attribute C_PROBE_IN102_WIDTH : integer; - attribute C_PROBE_IN102_WIDTH of inst : label is 1; - attribute C_PROBE_IN103_WIDTH : integer; - attribute C_PROBE_IN103_WIDTH of inst : label is 1; - attribute C_PROBE_IN104_WIDTH : integer; - attribute C_PROBE_IN104_WIDTH of inst : label is 1; - attribute C_PROBE_IN105_WIDTH : integer; - attribute C_PROBE_IN105_WIDTH of inst : label is 1; - attribute C_PROBE_IN106_WIDTH : integer; - attribute C_PROBE_IN106_WIDTH of inst : label is 1; - attribute C_PROBE_IN107_WIDTH : integer; - attribute C_PROBE_IN107_WIDTH of inst : label is 1; - attribute C_PROBE_IN108_WIDTH : integer; - attribute C_PROBE_IN108_WIDTH of inst : label is 1; - attribute C_PROBE_IN109_WIDTH : integer; - attribute C_PROBE_IN109_WIDTH of inst : label is 1; - attribute C_PROBE_IN10_WIDTH : integer; - attribute C_PROBE_IN10_WIDTH of inst : label is 1; - attribute C_PROBE_IN110_WIDTH : integer; - attribute C_PROBE_IN110_WIDTH of inst : label is 1; - attribute C_PROBE_IN111_WIDTH : integer; - attribute C_PROBE_IN111_WIDTH of inst : label is 1; - attribute C_PROBE_IN112_WIDTH : integer; - attribute C_PROBE_IN112_WIDTH of inst : label is 1; - attribute C_PROBE_IN113_WIDTH : integer; - attribute C_PROBE_IN113_WIDTH of inst : label is 1; - attribute C_PROBE_IN114_WIDTH : integer; - attribute C_PROBE_IN114_WIDTH of inst : label is 1; - attribute C_PROBE_IN115_WIDTH : integer; - attribute C_PROBE_IN115_WIDTH of inst : label is 1; - attribute C_PROBE_IN116_WIDTH : integer; - attribute C_PROBE_IN116_WIDTH of inst : label is 1; - attribute C_PROBE_IN117_WIDTH : integer; - attribute C_PROBE_IN117_WIDTH of inst : label is 1; - attribute C_PROBE_IN118_WIDTH : integer; - attribute C_PROBE_IN118_WIDTH of inst : label is 1; - attribute C_PROBE_IN119_WIDTH : integer; - attribute C_PROBE_IN119_WIDTH of inst : label is 1; - attribute C_PROBE_IN11_WIDTH : integer; - attribute C_PROBE_IN11_WIDTH of inst : label is 1; - attribute C_PROBE_IN120_WIDTH : integer; - attribute C_PROBE_IN120_WIDTH of inst : label is 1; - attribute C_PROBE_IN121_WIDTH : integer; - attribute C_PROBE_IN121_WIDTH of inst : label is 1; - attribute C_PROBE_IN122_WIDTH : integer; - attribute C_PROBE_IN122_WIDTH of inst : label is 1; - attribute C_PROBE_IN123_WIDTH : integer; - attribute C_PROBE_IN123_WIDTH of inst : label is 1; - attribute C_PROBE_IN124_WIDTH : integer; - attribute C_PROBE_IN124_WIDTH of inst : label is 1; - attribute C_PROBE_IN125_WIDTH : integer; - attribute C_PROBE_IN125_WIDTH of inst : label is 1; - attribute C_PROBE_IN126_WIDTH : integer; - attribute C_PROBE_IN126_WIDTH of inst : label is 1; - attribute C_PROBE_IN127_WIDTH : integer; - attribute C_PROBE_IN127_WIDTH of inst : label is 1; - attribute C_PROBE_IN128_WIDTH : integer; - attribute C_PROBE_IN128_WIDTH of inst : label is 1; - attribute C_PROBE_IN129_WIDTH : integer; - attribute C_PROBE_IN129_WIDTH of inst : label is 1; - attribute C_PROBE_IN12_WIDTH : integer; - attribute C_PROBE_IN12_WIDTH of inst : label is 1; - attribute C_PROBE_IN130_WIDTH : integer; - attribute C_PROBE_IN130_WIDTH of inst : label is 1; - attribute C_PROBE_IN131_WIDTH : integer; - attribute C_PROBE_IN131_WIDTH of inst : label is 1; - attribute C_PROBE_IN132_WIDTH : integer; - attribute C_PROBE_IN132_WIDTH of inst : label is 1; - attribute C_PROBE_IN133_WIDTH : integer; - attribute C_PROBE_IN133_WIDTH of inst : label is 1; - attribute C_PROBE_IN134_WIDTH : integer; - attribute C_PROBE_IN134_WIDTH of inst : label is 1; - attribute C_PROBE_IN135_WIDTH : integer; - attribute C_PROBE_IN135_WIDTH of inst : label is 1; - attribute C_PROBE_IN136_WIDTH : integer; - attribute C_PROBE_IN136_WIDTH of inst : label is 1; - attribute C_PROBE_IN137_WIDTH : integer; - attribute C_PROBE_IN137_WIDTH of inst : label is 1; - attribute C_PROBE_IN138_WIDTH : integer; - attribute C_PROBE_IN138_WIDTH of inst : label is 1; - attribute C_PROBE_IN139_WIDTH : integer; - attribute C_PROBE_IN139_WIDTH of inst : label is 1; - attribute C_PROBE_IN13_WIDTH : integer; - attribute C_PROBE_IN13_WIDTH of inst : label is 1; - attribute C_PROBE_IN140_WIDTH : integer; - attribute C_PROBE_IN140_WIDTH of inst : label is 1; - attribute C_PROBE_IN141_WIDTH : integer; - attribute C_PROBE_IN141_WIDTH of inst : label is 1; - attribute C_PROBE_IN142_WIDTH : integer; - attribute C_PROBE_IN142_WIDTH of inst : label is 1; - attribute C_PROBE_IN143_WIDTH : integer; - attribute C_PROBE_IN143_WIDTH of inst : label is 1; - attribute C_PROBE_IN144_WIDTH : integer; - attribute C_PROBE_IN144_WIDTH of inst : label is 1; - attribute C_PROBE_IN145_WIDTH : integer; - attribute C_PROBE_IN145_WIDTH of inst : label is 1; - attribute C_PROBE_IN146_WIDTH : integer; - attribute C_PROBE_IN146_WIDTH of inst : label is 1; - attribute C_PROBE_IN147_WIDTH : integer; - attribute C_PROBE_IN147_WIDTH of inst : label is 1; - attribute C_PROBE_IN148_WIDTH : integer; - attribute C_PROBE_IN148_WIDTH of inst : label is 1; - attribute C_PROBE_IN149_WIDTH : integer; - attribute C_PROBE_IN149_WIDTH of inst : label is 1; - attribute C_PROBE_IN14_WIDTH : integer; - attribute C_PROBE_IN14_WIDTH of inst : label is 1; - attribute C_PROBE_IN150_WIDTH : integer; - attribute C_PROBE_IN150_WIDTH of inst : label is 1; - attribute C_PROBE_IN151_WIDTH : integer; - attribute C_PROBE_IN151_WIDTH of inst : label is 1; - attribute C_PROBE_IN152_WIDTH : integer; - attribute C_PROBE_IN152_WIDTH of inst : label is 1; - attribute C_PROBE_IN153_WIDTH : integer; - attribute C_PROBE_IN153_WIDTH of inst : label is 1; - attribute C_PROBE_IN154_WIDTH : integer; - attribute C_PROBE_IN154_WIDTH of inst : label is 1; - attribute C_PROBE_IN155_WIDTH : integer; - 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attribute C_PROBE_OUT103_INIT_VAL : string; - attribute C_PROBE_OUT103_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT103_WIDTH : integer; - attribute C_PROBE_OUT103_WIDTH of inst : label is 1; - attribute C_PROBE_OUT104_INIT_VAL : string; - attribute C_PROBE_OUT104_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT104_WIDTH : integer; - attribute C_PROBE_OUT104_WIDTH of inst : label is 1; - attribute C_PROBE_OUT105_INIT_VAL : string; - attribute C_PROBE_OUT105_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT105_WIDTH : integer; - attribute C_PROBE_OUT105_WIDTH of inst : label is 1; - attribute C_PROBE_OUT106_INIT_VAL : string; - attribute C_PROBE_OUT106_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT106_WIDTH : integer; - attribute C_PROBE_OUT106_WIDTH of inst : label is 1; - attribute C_PROBE_OUT107_INIT_VAL : string; - attribute C_PROBE_OUT107_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT107_WIDTH : integer; - attribute C_PROBE_OUT107_WIDTH of inst : label is 1; - attribute C_PROBE_OUT108_INIT_VAL : string; - attribute C_PROBE_OUT108_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT108_WIDTH : integer; - attribute C_PROBE_OUT108_WIDTH of inst : label is 1; - attribute C_PROBE_OUT109_INIT_VAL : string; - attribute C_PROBE_OUT109_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT109_WIDTH : integer; - attribute C_PROBE_OUT109_WIDTH of inst : label is 1; - attribute C_PROBE_OUT10_INIT_VAL : string; - attribute C_PROBE_OUT10_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT10_WIDTH : integer; - attribute C_PROBE_OUT10_WIDTH of inst : label is 1; - attribute C_PROBE_OUT110_INIT_VAL : string; - attribute C_PROBE_OUT110_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT110_WIDTH : integer; - attribute C_PROBE_OUT110_WIDTH of inst : label is 1; - attribute C_PROBE_OUT111_INIT_VAL : string; - attribute C_PROBE_OUT111_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT111_WIDTH : integer; - attribute C_PROBE_OUT111_WIDTH of inst : label is 1; - attribute C_PROBE_OUT112_INIT_VAL : string; - attribute C_PROBE_OUT112_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT112_WIDTH : integer; - attribute C_PROBE_OUT112_WIDTH of inst : label is 1; - attribute C_PROBE_OUT113_INIT_VAL : string; - attribute C_PROBE_OUT113_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT113_WIDTH : integer; - attribute C_PROBE_OUT113_WIDTH of inst : label is 1; - attribute C_PROBE_OUT114_INIT_VAL : string; - attribute C_PROBE_OUT114_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT114_WIDTH : integer; - attribute C_PROBE_OUT114_WIDTH of inst : label is 1; - attribute C_PROBE_OUT115_INIT_VAL : string; - attribute C_PROBE_OUT115_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT115_WIDTH : integer; - attribute C_PROBE_OUT115_WIDTH of inst : label is 1; - attribute C_PROBE_OUT116_INIT_VAL : string; - attribute C_PROBE_OUT116_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT116_WIDTH : integer; - attribute C_PROBE_OUT116_WIDTH of inst : label is 1; - attribute C_PROBE_OUT117_INIT_VAL : string; - attribute C_PROBE_OUT117_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT117_WIDTH : integer; - attribute C_PROBE_OUT117_WIDTH of inst : label is 1; - attribute C_PROBE_OUT118_INIT_VAL : string; - attribute C_PROBE_OUT118_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT118_WIDTH : integer; - attribute C_PROBE_OUT118_WIDTH of inst : label is 1; - attribute C_PROBE_OUT119_INIT_VAL : string; - attribute C_PROBE_OUT119_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT119_WIDTH : integer; - attribute C_PROBE_OUT119_WIDTH of inst : label is 1; - attribute C_PROBE_OUT11_INIT_VAL : string; - attribute C_PROBE_OUT11_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT11_WIDTH : integer; - attribute C_PROBE_OUT11_WIDTH of inst : label is 1; - attribute C_PROBE_OUT120_INIT_VAL : string; - attribute C_PROBE_OUT120_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT120_WIDTH : integer; - attribute C_PROBE_OUT120_WIDTH of inst : label is 1; - attribute C_PROBE_OUT121_INIT_VAL : string; - attribute C_PROBE_OUT121_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT121_WIDTH : integer; - attribute C_PROBE_OUT121_WIDTH of inst : label is 1; - attribute C_PROBE_OUT122_INIT_VAL : string; - attribute C_PROBE_OUT122_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT122_WIDTH : integer; - attribute C_PROBE_OUT122_WIDTH of inst : label is 1; - attribute C_PROBE_OUT123_INIT_VAL : string; - attribute C_PROBE_OUT123_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT123_WIDTH : integer; - attribute C_PROBE_OUT123_WIDTH of inst : label is 1; - attribute C_PROBE_OUT124_INIT_VAL : string; - attribute C_PROBE_OUT124_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT124_WIDTH : integer; - attribute C_PROBE_OUT124_WIDTH of inst : label is 1; - attribute C_PROBE_OUT125_INIT_VAL : string; - attribute C_PROBE_OUT125_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT125_WIDTH : integer; - attribute C_PROBE_OUT125_WIDTH of inst : label is 1; - attribute C_PROBE_OUT126_INIT_VAL : string; - attribute C_PROBE_OUT126_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT126_WIDTH : integer; - attribute C_PROBE_OUT126_WIDTH of inst : label is 1; - attribute C_PROBE_OUT127_INIT_VAL : string; - attribute C_PROBE_OUT127_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT127_WIDTH : integer; - attribute C_PROBE_OUT127_WIDTH of inst : label is 1; - attribute C_PROBE_OUT128_INIT_VAL : string; - attribute C_PROBE_OUT128_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT128_WIDTH : integer; - attribute C_PROBE_OUT128_WIDTH of inst : label is 1; - attribute C_PROBE_OUT129_INIT_VAL : string; - attribute C_PROBE_OUT129_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT129_WIDTH : integer; - attribute C_PROBE_OUT129_WIDTH of inst : label is 1; - attribute C_PROBE_OUT12_INIT_VAL : string; - attribute C_PROBE_OUT12_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT12_WIDTH : integer; - attribute C_PROBE_OUT12_WIDTH of inst : label is 1; - attribute C_PROBE_OUT130_INIT_VAL : string; - attribute C_PROBE_OUT130_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT130_WIDTH : integer; - attribute C_PROBE_OUT130_WIDTH of inst : label is 1; - attribute C_PROBE_OUT131_INIT_VAL : string; - attribute C_PROBE_OUT131_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT131_WIDTH : integer; - attribute C_PROBE_OUT131_WIDTH of inst : label is 1; - attribute C_PROBE_OUT132_INIT_VAL : string; - attribute C_PROBE_OUT132_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT132_WIDTH : integer; - attribute C_PROBE_OUT132_WIDTH of inst : label is 1; - attribute C_PROBE_OUT133_INIT_VAL : string; - attribute C_PROBE_OUT133_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT133_WIDTH : integer; - attribute C_PROBE_OUT133_WIDTH of inst : label is 1; - attribute C_PROBE_OUT134_INIT_VAL : string; - attribute C_PROBE_OUT134_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT134_WIDTH : integer; - attribute C_PROBE_OUT134_WIDTH of inst : label is 1; - attribute C_PROBE_OUT135_INIT_VAL : string; - attribute C_PROBE_OUT135_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT135_WIDTH : integer; - attribute C_PROBE_OUT135_WIDTH of inst : label is 1; - attribute C_PROBE_OUT136_INIT_VAL : string; - attribute C_PROBE_OUT136_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT136_WIDTH : integer; - attribute C_PROBE_OUT136_WIDTH of inst : label is 1; - attribute C_PROBE_OUT137_INIT_VAL : string; - attribute C_PROBE_OUT137_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT137_WIDTH : integer; - attribute C_PROBE_OUT137_WIDTH of inst : label is 1; - attribute C_PROBE_OUT138_INIT_VAL : string; - attribute C_PROBE_OUT138_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT138_WIDTH : integer; - attribute C_PROBE_OUT138_WIDTH of inst : label is 1; - attribute C_PROBE_OUT139_INIT_VAL : string; - attribute C_PROBE_OUT139_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT139_WIDTH : integer; - attribute C_PROBE_OUT139_WIDTH of inst : label is 1; - attribute C_PROBE_OUT13_INIT_VAL : string; - attribute C_PROBE_OUT13_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT13_WIDTH : integer; - attribute C_PROBE_OUT13_WIDTH of inst : label is 1; - attribute C_PROBE_OUT140_INIT_VAL : string; - attribute C_PROBE_OUT140_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT140_WIDTH : integer; - attribute C_PROBE_OUT140_WIDTH of inst : label is 1; - attribute C_PROBE_OUT141_INIT_VAL : string; - attribute C_PROBE_OUT141_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT141_WIDTH : integer; - attribute C_PROBE_OUT141_WIDTH of inst : label is 1; - attribute C_PROBE_OUT142_INIT_VAL : string; - attribute C_PROBE_OUT142_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT142_WIDTH : integer; - attribute C_PROBE_OUT142_WIDTH of inst : label is 1; - attribute C_PROBE_OUT143_INIT_VAL : string; - attribute C_PROBE_OUT143_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT143_WIDTH : integer; - attribute C_PROBE_OUT143_WIDTH of inst : label is 1; - attribute C_PROBE_OUT144_INIT_VAL : string; - attribute C_PROBE_OUT144_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT144_WIDTH : integer; - attribute C_PROBE_OUT144_WIDTH of inst : label is 1; - attribute C_PROBE_OUT145_INIT_VAL : string; - attribute C_PROBE_OUT145_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT145_WIDTH : integer; - attribute C_PROBE_OUT145_WIDTH of inst : label is 1; - attribute C_PROBE_OUT146_INIT_VAL : string; - attribute C_PROBE_OUT146_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT146_WIDTH : integer; - attribute C_PROBE_OUT146_WIDTH of inst : label is 1; - attribute C_PROBE_OUT147_INIT_VAL : string; - attribute C_PROBE_OUT147_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT147_WIDTH : integer; - attribute C_PROBE_OUT147_WIDTH of inst : label is 1; - attribute C_PROBE_OUT148_INIT_VAL : string; - attribute C_PROBE_OUT148_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT148_WIDTH : integer; - attribute C_PROBE_OUT148_WIDTH of inst : label is 1; - attribute C_PROBE_OUT149_INIT_VAL : string; - attribute C_PROBE_OUT149_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT149_WIDTH : integer; - attribute C_PROBE_OUT149_WIDTH of inst : label is 1; - attribute C_PROBE_OUT14_INIT_VAL : string; - attribute C_PROBE_OUT14_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT14_WIDTH : integer; - attribute C_PROBE_OUT14_WIDTH of inst : label is 1; - attribute C_PROBE_OUT150_INIT_VAL : string; - attribute C_PROBE_OUT150_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT150_WIDTH : integer; - attribute C_PROBE_OUT150_WIDTH of inst : label is 1; - attribute C_PROBE_OUT151_INIT_VAL : string; - attribute C_PROBE_OUT151_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT151_WIDTH : integer; - attribute C_PROBE_OUT151_WIDTH of inst : label is 1; - attribute C_PROBE_OUT152_INIT_VAL : string; - attribute C_PROBE_OUT152_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT152_WIDTH : integer; - attribute C_PROBE_OUT152_WIDTH of inst : label is 1; - attribute C_PROBE_OUT153_INIT_VAL : string; - attribute C_PROBE_OUT153_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT153_WIDTH : integer; - attribute C_PROBE_OUT153_WIDTH of inst : label is 1; - attribute C_PROBE_OUT154_INIT_VAL : string; - attribute C_PROBE_OUT154_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT154_WIDTH : integer; - attribute C_PROBE_OUT154_WIDTH of inst : label is 1; - attribute C_PROBE_OUT155_INIT_VAL : string; - attribute C_PROBE_OUT155_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT155_WIDTH : integer; - attribute C_PROBE_OUT155_WIDTH of inst : label is 1; - attribute C_PROBE_OUT156_INIT_VAL : string; - attribute C_PROBE_OUT156_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT156_WIDTH : integer; - attribute C_PROBE_OUT156_WIDTH of inst : label is 1; - attribute C_PROBE_OUT157_INIT_VAL : string; - attribute C_PROBE_OUT157_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT157_WIDTH : integer; - attribute C_PROBE_OUT157_WIDTH of inst : label is 1; - attribute C_PROBE_OUT158_INIT_VAL : string; - attribute C_PROBE_OUT158_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT158_WIDTH : integer; - attribute C_PROBE_OUT158_WIDTH of inst : label is 1; - attribute C_PROBE_OUT159_INIT_VAL : string; - attribute C_PROBE_OUT159_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT159_WIDTH : integer; - attribute C_PROBE_OUT159_WIDTH of inst : label is 1; - attribute C_PROBE_OUT15_INIT_VAL : string; - attribute C_PROBE_OUT15_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT15_WIDTH : integer; - attribute C_PROBE_OUT15_WIDTH of inst : label is 1; - attribute C_PROBE_OUT160_INIT_VAL : string; - attribute C_PROBE_OUT160_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT160_WIDTH : integer; - attribute C_PROBE_OUT160_WIDTH of inst : label is 1; - attribute C_PROBE_OUT161_INIT_VAL : string; - attribute C_PROBE_OUT161_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT161_WIDTH : integer; - attribute C_PROBE_OUT161_WIDTH of inst : label is 1; - attribute C_PROBE_OUT162_INIT_VAL : string; - attribute C_PROBE_OUT162_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT162_WIDTH : integer; - attribute C_PROBE_OUT162_WIDTH of inst : label is 1; - attribute C_PROBE_OUT163_INIT_VAL : string; - attribute C_PROBE_OUT163_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT163_WIDTH : integer; - attribute C_PROBE_OUT163_WIDTH of inst : label is 1; - attribute C_PROBE_OUT164_INIT_VAL : string; - attribute C_PROBE_OUT164_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT164_WIDTH : integer; - attribute C_PROBE_OUT164_WIDTH of inst : label is 1; - attribute C_PROBE_OUT165_INIT_VAL : string; - attribute C_PROBE_OUT165_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT165_WIDTH : integer; - attribute C_PROBE_OUT165_WIDTH of inst : label is 1; - attribute C_PROBE_OUT166_INIT_VAL : string; - attribute C_PROBE_OUT166_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT166_WIDTH : integer; - attribute C_PROBE_OUT166_WIDTH of inst : label is 1; - attribute C_PROBE_OUT167_INIT_VAL : string; - attribute C_PROBE_OUT167_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT167_WIDTH : integer; - attribute C_PROBE_OUT167_WIDTH of inst : label is 1; - attribute C_PROBE_OUT168_INIT_VAL : string; - attribute C_PROBE_OUT168_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT168_WIDTH : integer; - attribute C_PROBE_OUT168_WIDTH of inst : label is 1; - attribute C_PROBE_OUT169_INIT_VAL : string; - attribute C_PROBE_OUT169_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT169_WIDTH : integer; - attribute C_PROBE_OUT169_WIDTH of inst : label is 1; - attribute C_PROBE_OUT16_INIT_VAL : string; - attribute C_PROBE_OUT16_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT16_WIDTH : integer; - attribute C_PROBE_OUT16_WIDTH of inst : label is 1; - attribute C_PROBE_OUT170_INIT_VAL : string; - attribute C_PROBE_OUT170_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT170_WIDTH : integer; - attribute C_PROBE_OUT170_WIDTH of inst : label is 1; - attribute C_PROBE_OUT171_INIT_VAL : string; - attribute C_PROBE_OUT171_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT171_WIDTH : integer; - attribute C_PROBE_OUT171_WIDTH of inst : label is 1; - attribute C_PROBE_OUT172_INIT_VAL : string; - attribute C_PROBE_OUT172_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT172_WIDTH : integer; - attribute C_PROBE_OUT172_WIDTH of inst : label is 1; - attribute C_PROBE_OUT173_INIT_VAL : string; - attribute C_PROBE_OUT173_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT173_WIDTH : integer; - attribute C_PROBE_OUT173_WIDTH of inst : label is 1; - attribute C_PROBE_OUT174_INIT_VAL : string; - attribute C_PROBE_OUT174_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT174_WIDTH : integer; - attribute C_PROBE_OUT174_WIDTH of inst : label is 1; - attribute C_PROBE_OUT175_INIT_VAL : string; - attribute C_PROBE_OUT175_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT175_WIDTH : integer; - attribute C_PROBE_OUT175_WIDTH of inst : label is 1; - attribute C_PROBE_OUT176_INIT_VAL : string; - attribute C_PROBE_OUT176_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT176_WIDTH : integer; - attribute C_PROBE_OUT176_WIDTH of inst : label is 1; - attribute C_PROBE_OUT177_INIT_VAL : string; - attribute C_PROBE_OUT177_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT177_WIDTH : integer; - attribute C_PROBE_OUT177_WIDTH of inst : label is 1; - attribute C_PROBE_OUT178_INIT_VAL : string; - attribute C_PROBE_OUT178_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT178_WIDTH : integer; - attribute C_PROBE_OUT178_WIDTH of inst : label is 1; - attribute C_PROBE_OUT179_INIT_VAL : string; - attribute C_PROBE_OUT179_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT179_WIDTH : integer; - attribute C_PROBE_OUT179_WIDTH of inst : label is 1; - attribute C_PROBE_OUT17_INIT_VAL : string; - attribute C_PROBE_OUT17_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT17_WIDTH : integer; - attribute C_PROBE_OUT17_WIDTH of inst : label is 1; - attribute C_PROBE_OUT180_INIT_VAL : string; - attribute C_PROBE_OUT180_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT180_WIDTH : integer; - attribute C_PROBE_OUT180_WIDTH of inst : label is 1; - attribute C_PROBE_OUT181_INIT_VAL : string; - attribute C_PROBE_OUT181_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT181_WIDTH : integer; - attribute C_PROBE_OUT181_WIDTH of inst : label is 1; - attribute C_PROBE_OUT182_INIT_VAL : string; - attribute C_PROBE_OUT182_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT182_WIDTH : integer; - attribute C_PROBE_OUT182_WIDTH of inst : label is 1; - attribute C_PROBE_OUT183_INIT_VAL : string; - attribute C_PROBE_OUT183_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT183_WIDTH : integer; - attribute C_PROBE_OUT183_WIDTH of inst : label is 1; - attribute C_PROBE_OUT184_INIT_VAL : string; - attribute C_PROBE_OUT184_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT184_WIDTH : integer; - attribute C_PROBE_OUT184_WIDTH of inst : label is 1; - attribute C_PROBE_OUT185_INIT_VAL : string; - attribute C_PROBE_OUT185_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT185_WIDTH : integer; - attribute C_PROBE_OUT185_WIDTH of inst : label is 1; - attribute C_PROBE_OUT186_INIT_VAL : string; - attribute C_PROBE_OUT186_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT186_WIDTH : integer; - attribute C_PROBE_OUT186_WIDTH of inst : label is 1; - attribute C_PROBE_OUT187_INIT_VAL : string; - attribute C_PROBE_OUT187_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT187_WIDTH : integer; - attribute C_PROBE_OUT187_WIDTH of inst : label is 1; - attribute C_PROBE_OUT188_INIT_VAL : string; - attribute C_PROBE_OUT188_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT188_WIDTH : integer; - attribute C_PROBE_OUT188_WIDTH of inst : label is 1; - attribute C_PROBE_OUT189_INIT_VAL : string; - attribute C_PROBE_OUT189_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT189_WIDTH : integer; - attribute C_PROBE_OUT189_WIDTH of inst : label is 1; - attribute C_PROBE_OUT18_INIT_VAL : string; - attribute C_PROBE_OUT18_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT18_WIDTH : integer; - attribute C_PROBE_OUT18_WIDTH of inst : label is 1; - attribute C_PROBE_OUT190_INIT_VAL : string; - attribute C_PROBE_OUT190_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT190_WIDTH : integer; - attribute C_PROBE_OUT190_WIDTH of inst : label is 1; - attribute C_PROBE_OUT191_INIT_VAL : string; - attribute C_PROBE_OUT191_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT191_WIDTH : integer; - attribute C_PROBE_OUT191_WIDTH of inst : label is 1; - attribute C_PROBE_OUT192_INIT_VAL : string; - attribute C_PROBE_OUT192_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT192_WIDTH : integer; - attribute C_PROBE_OUT192_WIDTH of inst : label is 1; - attribute C_PROBE_OUT193_INIT_VAL : string; - attribute C_PROBE_OUT193_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT193_WIDTH : integer; - attribute C_PROBE_OUT193_WIDTH of inst : label is 1; - attribute C_PROBE_OUT194_INIT_VAL : string; - attribute C_PROBE_OUT194_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT194_WIDTH : integer; - attribute C_PROBE_OUT194_WIDTH of inst : label is 1; - attribute C_PROBE_OUT195_INIT_VAL : string; - attribute C_PROBE_OUT195_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT195_WIDTH : integer; - attribute C_PROBE_OUT195_WIDTH of inst : label is 1; - attribute C_PROBE_OUT196_INIT_VAL : string; - attribute C_PROBE_OUT196_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT196_WIDTH : integer; - attribute C_PROBE_OUT196_WIDTH of inst : label is 1; - attribute C_PROBE_OUT197_INIT_VAL : string; - attribute C_PROBE_OUT197_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT197_WIDTH : integer; - attribute C_PROBE_OUT197_WIDTH of inst : label is 1; - attribute C_PROBE_OUT198_INIT_VAL : string; - attribute C_PROBE_OUT198_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT198_WIDTH : integer; - attribute C_PROBE_OUT198_WIDTH of inst : label is 1; - attribute C_PROBE_OUT199_INIT_VAL : string; - attribute C_PROBE_OUT199_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT199_WIDTH : integer; - attribute C_PROBE_OUT199_WIDTH of inst : label is 1; - attribute C_PROBE_OUT19_INIT_VAL : string; - attribute C_PROBE_OUT19_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT19_WIDTH : integer; - attribute C_PROBE_OUT19_WIDTH of inst : label is 1; - attribute C_PROBE_OUT1_INIT_VAL : string; - attribute C_PROBE_OUT1_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT1_WIDTH : integer; - attribute C_PROBE_OUT1_WIDTH of inst : label is 1; - attribute C_PROBE_OUT200_INIT_VAL : string; - attribute C_PROBE_OUT200_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT200_WIDTH : integer; - attribute C_PROBE_OUT200_WIDTH of inst : label is 1; - attribute C_PROBE_OUT201_INIT_VAL : string; - attribute C_PROBE_OUT201_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT201_WIDTH : integer; - attribute C_PROBE_OUT201_WIDTH of inst : label is 1; - attribute C_PROBE_OUT202_INIT_VAL : string; - attribute C_PROBE_OUT202_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT202_WIDTH : integer; - attribute C_PROBE_OUT202_WIDTH of inst : label is 1; - attribute C_PROBE_OUT203_INIT_VAL : string; - attribute C_PROBE_OUT203_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT203_WIDTH : integer; - attribute C_PROBE_OUT203_WIDTH of inst : label is 1; - attribute C_PROBE_OUT204_INIT_VAL : string; - attribute C_PROBE_OUT204_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT204_WIDTH : integer; - attribute C_PROBE_OUT204_WIDTH of inst : label is 1; - attribute C_PROBE_OUT205_INIT_VAL : string; - attribute C_PROBE_OUT205_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT205_WIDTH : integer; - attribute C_PROBE_OUT205_WIDTH of inst : label is 1; - attribute C_PROBE_OUT206_INIT_VAL : string; - attribute C_PROBE_OUT206_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT206_WIDTH : integer; - attribute C_PROBE_OUT206_WIDTH of inst : label is 1; - attribute C_PROBE_OUT207_INIT_VAL : string; - attribute C_PROBE_OUT207_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT207_WIDTH : integer; - attribute C_PROBE_OUT207_WIDTH of inst : label is 1; - attribute C_PROBE_OUT208_INIT_VAL : string; - attribute C_PROBE_OUT208_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT208_WIDTH : integer; - attribute C_PROBE_OUT208_WIDTH of inst : label is 1; - attribute C_PROBE_OUT209_INIT_VAL : string; - attribute C_PROBE_OUT209_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT209_WIDTH : integer; - attribute C_PROBE_OUT209_WIDTH of inst : label is 1; - attribute C_PROBE_OUT20_INIT_VAL : string; - attribute C_PROBE_OUT20_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT20_WIDTH : integer; - attribute C_PROBE_OUT20_WIDTH of inst : label is 1; - attribute C_PROBE_OUT210_INIT_VAL : string; - attribute C_PROBE_OUT210_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT210_WIDTH : integer; - attribute C_PROBE_OUT210_WIDTH of inst : label is 1; - attribute C_PROBE_OUT211_INIT_VAL : string; - attribute C_PROBE_OUT211_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT211_WIDTH : integer; - attribute C_PROBE_OUT211_WIDTH of inst : label is 1; - attribute C_PROBE_OUT212_INIT_VAL : string; - attribute C_PROBE_OUT212_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT212_WIDTH : integer; - attribute C_PROBE_OUT212_WIDTH of inst : label is 1; - attribute C_PROBE_OUT213_INIT_VAL : string; - attribute C_PROBE_OUT213_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT213_WIDTH : integer; - attribute C_PROBE_OUT213_WIDTH of inst : label is 1; - attribute C_PROBE_OUT214_INIT_VAL : string; - attribute C_PROBE_OUT214_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT214_WIDTH : integer; - attribute C_PROBE_OUT214_WIDTH of inst : label is 1; - attribute C_PROBE_OUT215_INIT_VAL : string; - attribute C_PROBE_OUT215_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT215_WIDTH : integer; - attribute C_PROBE_OUT215_WIDTH of inst : label is 1; - attribute C_PROBE_OUT216_INIT_VAL : string; - attribute C_PROBE_OUT216_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT216_WIDTH : integer; - attribute C_PROBE_OUT216_WIDTH of inst : label is 1; - attribute C_PROBE_OUT217_INIT_VAL : string; - attribute C_PROBE_OUT217_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT217_WIDTH : integer; - attribute C_PROBE_OUT217_WIDTH of inst : label is 1; - attribute C_PROBE_OUT218_INIT_VAL : string; - attribute C_PROBE_OUT218_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT218_WIDTH : integer; - attribute C_PROBE_OUT218_WIDTH of inst : label is 1; - attribute C_PROBE_OUT219_INIT_VAL : string; - attribute C_PROBE_OUT219_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT219_WIDTH : integer; - attribute C_PROBE_OUT219_WIDTH of inst : label is 1; - attribute C_PROBE_OUT21_INIT_VAL : string; - attribute C_PROBE_OUT21_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT21_WIDTH : integer; - attribute C_PROBE_OUT21_WIDTH of inst : label is 1; - attribute C_PROBE_OUT220_INIT_VAL : string; - attribute C_PROBE_OUT220_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT220_WIDTH : integer; - attribute C_PROBE_OUT220_WIDTH of inst : label is 1; - attribute C_PROBE_OUT221_INIT_VAL : string; - attribute C_PROBE_OUT221_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT221_WIDTH : integer; - attribute C_PROBE_OUT221_WIDTH of inst : label is 1; - attribute C_PROBE_OUT222_INIT_VAL : string; - attribute C_PROBE_OUT222_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT222_WIDTH : integer; - attribute C_PROBE_OUT222_WIDTH of inst : label is 1; - attribute C_PROBE_OUT223_INIT_VAL : string; - attribute C_PROBE_OUT223_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT223_WIDTH : integer; - attribute C_PROBE_OUT223_WIDTH of inst : label is 1; - attribute C_PROBE_OUT224_INIT_VAL : string; - attribute C_PROBE_OUT224_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT224_WIDTH : integer; - attribute C_PROBE_OUT224_WIDTH of inst : label is 1; - attribute C_PROBE_OUT225_INIT_VAL : string; - attribute C_PROBE_OUT225_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT225_WIDTH : integer; - attribute C_PROBE_OUT225_WIDTH of inst : label is 1; - attribute C_PROBE_OUT226_INIT_VAL : string; - attribute C_PROBE_OUT226_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT226_WIDTH : integer; - attribute C_PROBE_OUT226_WIDTH of inst : label is 1; - attribute C_PROBE_OUT227_INIT_VAL : string; - attribute C_PROBE_OUT227_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT227_WIDTH : integer; - attribute C_PROBE_OUT227_WIDTH of inst : label is 1; - attribute C_PROBE_OUT228_INIT_VAL : string; - attribute C_PROBE_OUT228_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT228_WIDTH : integer; - attribute C_PROBE_OUT228_WIDTH of inst : label is 1; - attribute C_PROBE_OUT229_INIT_VAL : string; - attribute C_PROBE_OUT229_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT229_WIDTH : integer; - attribute C_PROBE_OUT229_WIDTH of inst : label is 1; - attribute C_PROBE_OUT22_INIT_VAL : string; - attribute C_PROBE_OUT22_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT22_WIDTH : integer; - attribute C_PROBE_OUT22_WIDTH of inst : label is 1; - attribute C_PROBE_OUT230_INIT_VAL : string; - attribute C_PROBE_OUT230_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT230_WIDTH : integer; - attribute C_PROBE_OUT230_WIDTH of inst : label is 1; - attribute C_PROBE_OUT231_INIT_VAL : string; - attribute C_PROBE_OUT231_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT231_WIDTH : integer; - attribute C_PROBE_OUT231_WIDTH of inst : label is 1; - attribute C_PROBE_OUT232_INIT_VAL : string; - attribute C_PROBE_OUT232_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT232_WIDTH : integer; - attribute C_PROBE_OUT232_WIDTH of inst : label is 1; - attribute C_PROBE_OUT233_INIT_VAL : string; - attribute C_PROBE_OUT233_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT233_WIDTH : integer; - attribute C_PROBE_OUT233_WIDTH of inst : label is 1; - attribute C_PROBE_OUT234_INIT_VAL : string; - attribute C_PROBE_OUT234_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT234_WIDTH : integer; - attribute C_PROBE_OUT234_WIDTH of inst : label is 1; - attribute C_PROBE_OUT235_INIT_VAL : string; - attribute C_PROBE_OUT235_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT235_WIDTH : integer; - attribute C_PROBE_OUT235_WIDTH of inst : label is 1; - attribute C_PROBE_OUT236_INIT_VAL : string; - attribute C_PROBE_OUT236_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT236_WIDTH : integer; - attribute C_PROBE_OUT236_WIDTH of inst : label is 1; - attribute C_PROBE_OUT237_INIT_VAL : string; - attribute C_PROBE_OUT237_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT237_WIDTH : integer; - attribute C_PROBE_OUT237_WIDTH of inst : label is 1; - attribute C_PROBE_OUT238_INIT_VAL : string; - attribute C_PROBE_OUT238_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT238_WIDTH : integer; - attribute C_PROBE_OUT238_WIDTH of inst : label is 1; - attribute C_PROBE_OUT239_INIT_VAL : string; - attribute C_PROBE_OUT239_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT239_WIDTH : integer; - attribute C_PROBE_OUT239_WIDTH of inst : label is 1; - attribute C_PROBE_OUT23_INIT_VAL : string; - attribute C_PROBE_OUT23_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT23_WIDTH : integer; - attribute C_PROBE_OUT23_WIDTH of inst : label is 1; - attribute C_PROBE_OUT240_INIT_VAL : string; - attribute C_PROBE_OUT240_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT240_WIDTH : integer; - attribute C_PROBE_OUT240_WIDTH of inst : label is 1; - attribute C_PROBE_OUT241_INIT_VAL : string; - attribute C_PROBE_OUT241_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT241_WIDTH : integer; - attribute C_PROBE_OUT241_WIDTH of inst : label is 1; - attribute C_PROBE_OUT242_INIT_VAL : string; - attribute C_PROBE_OUT242_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT242_WIDTH : integer; - attribute C_PROBE_OUT242_WIDTH of inst : label is 1; - attribute C_PROBE_OUT243_INIT_VAL : string; - attribute C_PROBE_OUT243_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT243_WIDTH : integer; - attribute C_PROBE_OUT243_WIDTH of inst : label is 1; - attribute C_PROBE_OUT244_INIT_VAL : string; - attribute C_PROBE_OUT244_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT244_WIDTH : integer; - attribute C_PROBE_OUT244_WIDTH of inst : label is 1; - attribute C_PROBE_OUT245_INIT_VAL : string; - attribute C_PROBE_OUT245_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT245_WIDTH : integer; - attribute C_PROBE_OUT245_WIDTH of inst : label is 1; - attribute C_PROBE_OUT246_INIT_VAL : string; - attribute C_PROBE_OUT246_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT246_WIDTH : integer; - attribute C_PROBE_OUT246_WIDTH of inst : label is 1; - attribute C_PROBE_OUT247_INIT_VAL : string; - attribute C_PROBE_OUT247_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT247_WIDTH : integer; - attribute C_PROBE_OUT247_WIDTH of inst : label is 1; - attribute C_PROBE_OUT248_INIT_VAL : string; - attribute C_PROBE_OUT248_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT248_WIDTH : integer; - attribute C_PROBE_OUT248_WIDTH of inst : label is 1; - attribute C_PROBE_OUT249_INIT_VAL : string; - attribute C_PROBE_OUT249_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT249_WIDTH : integer; - attribute C_PROBE_OUT249_WIDTH of inst : label is 1; - attribute C_PROBE_OUT24_INIT_VAL : string; - attribute C_PROBE_OUT24_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT24_WIDTH : integer; - attribute C_PROBE_OUT24_WIDTH of inst : label is 1; - attribute C_PROBE_OUT250_INIT_VAL : string; - attribute C_PROBE_OUT250_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT250_WIDTH : integer; - attribute C_PROBE_OUT250_WIDTH of inst : label is 1; - attribute C_PROBE_OUT251_INIT_VAL : string; - attribute C_PROBE_OUT251_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT251_WIDTH : integer; - attribute C_PROBE_OUT251_WIDTH of inst : label is 1; - attribute C_PROBE_OUT252_INIT_VAL : string; - attribute C_PROBE_OUT252_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT252_WIDTH : integer; - attribute C_PROBE_OUT252_WIDTH of inst : label is 1; - attribute C_PROBE_OUT253_INIT_VAL : string; - attribute C_PROBE_OUT253_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT253_WIDTH : integer; - attribute C_PROBE_OUT253_WIDTH of inst : label is 1; - attribute C_PROBE_OUT254_INIT_VAL : string; - attribute C_PROBE_OUT254_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT254_WIDTH : integer; - attribute C_PROBE_OUT254_WIDTH of inst : label is 1; - attribute C_PROBE_OUT255_INIT_VAL : string; - attribute C_PROBE_OUT255_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT255_WIDTH : integer; - attribute C_PROBE_OUT255_WIDTH of inst : label is 1; - attribute C_PROBE_OUT25_INIT_VAL : string; - attribute C_PROBE_OUT25_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT25_WIDTH : integer; - attribute C_PROBE_OUT25_WIDTH of inst : label is 1; - attribute C_PROBE_OUT26_INIT_VAL : string; - attribute C_PROBE_OUT26_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT26_WIDTH : integer; - attribute C_PROBE_OUT26_WIDTH of inst : label is 1; - attribute C_PROBE_OUT27_INIT_VAL : string; - attribute C_PROBE_OUT27_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT27_WIDTH : integer; - attribute C_PROBE_OUT27_WIDTH of inst : label is 1; - attribute C_PROBE_OUT28_INIT_VAL : string; - attribute C_PROBE_OUT28_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT28_WIDTH : integer; - attribute C_PROBE_OUT28_WIDTH of inst : label is 1; - attribute C_PROBE_OUT29_INIT_VAL : string; - attribute C_PROBE_OUT29_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT29_WIDTH : integer; - attribute C_PROBE_OUT29_WIDTH of inst : label is 1; - attribute C_PROBE_OUT2_INIT_VAL : string; - attribute C_PROBE_OUT2_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT2_WIDTH : integer; - attribute C_PROBE_OUT2_WIDTH of inst : label is 1; - attribute C_PROBE_OUT30_INIT_VAL : string; - attribute C_PROBE_OUT30_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT30_WIDTH : integer; - attribute C_PROBE_OUT30_WIDTH of inst : label is 1; - attribute C_PROBE_OUT31_INIT_VAL : string; - attribute C_PROBE_OUT31_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT31_WIDTH : integer; - attribute C_PROBE_OUT31_WIDTH of inst : label is 1; - attribute C_PROBE_OUT32_INIT_VAL : string; - attribute C_PROBE_OUT32_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT32_WIDTH : integer; - attribute C_PROBE_OUT32_WIDTH of inst : label is 1; - attribute C_PROBE_OUT33_INIT_VAL : string; - attribute C_PROBE_OUT33_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT33_WIDTH : integer; - attribute C_PROBE_OUT33_WIDTH of inst : label is 1; - attribute C_PROBE_OUT34_INIT_VAL : string; - attribute C_PROBE_OUT34_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT34_WIDTH : integer; - attribute C_PROBE_OUT34_WIDTH of inst : label is 1; - attribute C_PROBE_OUT35_INIT_VAL : string; - attribute C_PROBE_OUT35_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT35_WIDTH : integer; - attribute C_PROBE_OUT35_WIDTH of inst : label is 1; - attribute C_PROBE_OUT36_INIT_VAL : string; - attribute C_PROBE_OUT36_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT36_WIDTH : integer; - attribute C_PROBE_OUT36_WIDTH of inst : label is 1; - attribute C_PROBE_OUT37_INIT_VAL : string; - attribute C_PROBE_OUT37_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT37_WIDTH : integer; - attribute C_PROBE_OUT37_WIDTH of inst : label is 1; - attribute C_PROBE_OUT38_INIT_VAL : string; - attribute C_PROBE_OUT38_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT38_WIDTH : integer; - attribute C_PROBE_OUT38_WIDTH of inst : label is 1; - attribute C_PROBE_OUT39_INIT_VAL : string; - attribute C_PROBE_OUT39_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT39_WIDTH : integer; - attribute C_PROBE_OUT39_WIDTH of inst : label is 1; - attribute C_PROBE_OUT3_INIT_VAL : string; - attribute C_PROBE_OUT3_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT3_WIDTH : integer; - attribute C_PROBE_OUT3_WIDTH of inst : label is 1; - attribute C_PROBE_OUT40_INIT_VAL : string; - attribute C_PROBE_OUT40_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT40_WIDTH : integer; - attribute C_PROBE_OUT40_WIDTH of inst : label is 1; - attribute C_PROBE_OUT41_INIT_VAL : string; - attribute C_PROBE_OUT41_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT41_WIDTH : integer; - attribute C_PROBE_OUT41_WIDTH of inst : label is 1; - attribute C_PROBE_OUT42_INIT_VAL : string; - attribute C_PROBE_OUT42_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT42_WIDTH : integer; - attribute C_PROBE_OUT42_WIDTH of inst : label is 1; - attribute C_PROBE_OUT43_INIT_VAL : string; - attribute C_PROBE_OUT43_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT43_WIDTH : integer; - attribute C_PROBE_OUT43_WIDTH of inst : label is 1; - attribute C_PROBE_OUT44_INIT_VAL : string; - attribute C_PROBE_OUT44_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT44_WIDTH : integer; - attribute C_PROBE_OUT44_WIDTH of inst : label is 1; - attribute C_PROBE_OUT45_INIT_VAL : string; - attribute C_PROBE_OUT45_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT45_WIDTH : integer; - attribute C_PROBE_OUT45_WIDTH of inst : label is 1; - attribute C_PROBE_OUT46_INIT_VAL : string; - attribute C_PROBE_OUT46_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT46_WIDTH : integer; - attribute C_PROBE_OUT46_WIDTH of inst : label is 1; - attribute C_PROBE_OUT47_INIT_VAL : string; - attribute C_PROBE_OUT47_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT47_WIDTH : integer; - attribute C_PROBE_OUT47_WIDTH of inst : label is 1; - attribute C_PROBE_OUT48_INIT_VAL : string; - attribute C_PROBE_OUT48_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT48_WIDTH : integer; - attribute C_PROBE_OUT48_WIDTH of inst : label is 1; - attribute C_PROBE_OUT49_INIT_VAL : string; - attribute C_PROBE_OUT49_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT49_WIDTH : integer; - attribute C_PROBE_OUT49_WIDTH of inst : label is 1; - attribute C_PROBE_OUT4_INIT_VAL : string; - attribute C_PROBE_OUT4_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT4_WIDTH : integer; - attribute C_PROBE_OUT4_WIDTH of inst : label is 1; - attribute C_PROBE_OUT50_INIT_VAL : string; - attribute C_PROBE_OUT50_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT50_WIDTH : integer; - attribute C_PROBE_OUT50_WIDTH of inst : label is 1; - attribute C_PROBE_OUT51_INIT_VAL : string; - attribute C_PROBE_OUT51_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT51_WIDTH : integer; - attribute C_PROBE_OUT51_WIDTH of inst : label is 1; - attribute C_PROBE_OUT52_INIT_VAL : string; - attribute C_PROBE_OUT52_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT52_WIDTH : integer; - attribute C_PROBE_OUT52_WIDTH of inst : label is 1; - attribute C_PROBE_OUT53_INIT_VAL : string; - attribute C_PROBE_OUT53_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT53_WIDTH : integer; - attribute C_PROBE_OUT53_WIDTH of inst : label is 1; - attribute C_PROBE_OUT54_INIT_VAL : string; - attribute C_PROBE_OUT54_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT54_WIDTH : integer; - attribute C_PROBE_OUT54_WIDTH of inst : label is 1; - attribute C_PROBE_OUT55_INIT_VAL : string; - attribute C_PROBE_OUT55_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT55_WIDTH : integer; - attribute C_PROBE_OUT55_WIDTH of inst : label is 1; - attribute C_PROBE_OUT56_INIT_VAL : string; - attribute C_PROBE_OUT56_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT56_WIDTH : integer; - attribute C_PROBE_OUT56_WIDTH of inst : label is 1; - attribute C_PROBE_OUT57_INIT_VAL : string; - attribute C_PROBE_OUT57_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT57_WIDTH : integer; - attribute C_PROBE_OUT57_WIDTH of inst : label is 1; - attribute C_PROBE_OUT58_INIT_VAL : string; - attribute C_PROBE_OUT58_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT58_WIDTH : integer; - attribute C_PROBE_OUT58_WIDTH of inst : label is 1; - attribute C_PROBE_OUT59_INIT_VAL : string; - attribute C_PROBE_OUT59_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT59_WIDTH : integer; - attribute C_PROBE_OUT59_WIDTH of inst : label is 1; - attribute C_PROBE_OUT5_INIT_VAL : string; - attribute C_PROBE_OUT5_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT5_WIDTH : integer; - attribute C_PROBE_OUT5_WIDTH of inst : label is 1; - attribute C_PROBE_OUT60_INIT_VAL : string; - attribute C_PROBE_OUT60_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT60_WIDTH : integer; - attribute C_PROBE_OUT60_WIDTH of inst : label is 1; - attribute C_PROBE_OUT61_INIT_VAL : string; - attribute C_PROBE_OUT61_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT61_WIDTH : integer; - attribute C_PROBE_OUT61_WIDTH of inst : label is 1; - attribute C_PROBE_OUT62_INIT_VAL : string; - attribute C_PROBE_OUT62_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT62_WIDTH : integer; - attribute C_PROBE_OUT62_WIDTH of inst : label is 1; - attribute C_PROBE_OUT63_INIT_VAL : string; - attribute C_PROBE_OUT63_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT63_WIDTH : integer; - attribute C_PROBE_OUT63_WIDTH of inst : label is 1; - attribute C_PROBE_OUT64_INIT_VAL : string; - attribute C_PROBE_OUT64_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT64_WIDTH : integer; - attribute C_PROBE_OUT64_WIDTH of inst : label is 1; - attribute C_PROBE_OUT65_INIT_VAL : string; - attribute C_PROBE_OUT65_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT65_WIDTH : integer; - attribute C_PROBE_OUT65_WIDTH of inst : label is 1; - attribute C_PROBE_OUT66_INIT_VAL : string; - attribute C_PROBE_OUT66_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT66_WIDTH : integer; - attribute C_PROBE_OUT66_WIDTH of inst : label is 1; - attribute C_PROBE_OUT67_INIT_VAL : string; - attribute C_PROBE_OUT67_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT67_WIDTH : integer; - attribute C_PROBE_OUT67_WIDTH of inst : label is 1; - attribute C_PROBE_OUT68_INIT_VAL : string; - attribute C_PROBE_OUT68_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT68_WIDTH : integer; - attribute C_PROBE_OUT68_WIDTH of inst : label is 1; - attribute C_PROBE_OUT69_INIT_VAL : string; - attribute C_PROBE_OUT69_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT69_WIDTH : integer; - attribute C_PROBE_OUT69_WIDTH of inst : label is 1; - attribute C_PROBE_OUT6_INIT_VAL : string; - attribute C_PROBE_OUT6_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT6_WIDTH : integer; - attribute C_PROBE_OUT6_WIDTH of inst : label is 1; - attribute C_PROBE_OUT70_INIT_VAL : string; - attribute C_PROBE_OUT70_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT70_WIDTH : integer; - attribute C_PROBE_OUT70_WIDTH of inst : label is 1; - attribute C_PROBE_OUT71_INIT_VAL : string; - attribute C_PROBE_OUT71_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT71_WIDTH : integer; - attribute C_PROBE_OUT71_WIDTH of inst : label is 1; - attribute C_PROBE_OUT72_INIT_VAL : string; - attribute C_PROBE_OUT72_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT72_WIDTH : integer; - attribute C_PROBE_OUT72_WIDTH of inst : label is 1; - attribute C_PROBE_OUT73_INIT_VAL : string; - attribute C_PROBE_OUT73_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT73_WIDTH : integer; - attribute C_PROBE_OUT73_WIDTH of inst : label is 1; - attribute C_PROBE_OUT74_INIT_VAL : string; - attribute C_PROBE_OUT74_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT74_WIDTH : integer; - attribute C_PROBE_OUT74_WIDTH of inst : label is 1; - attribute C_PROBE_OUT75_INIT_VAL : string; - attribute C_PROBE_OUT75_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT75_WIDTH : integer; - attribute C_PROBE_OUT75_WIDTH of inst : label is 1; - attribute C_PROBE_OUT76_INIT_VAL : string; - attribute C_PROBE_OUT76_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT76_WIDTH : integer; - attribute C_PROBE_OUT76_WIDTH of inst : label is 1; - attribute C_PROBE_OUT77_INIT_VAL : string; - attribute C_PROBE_OUT77_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT77_WIDTH : integer; - attribute C_PROBE_OUT77_WIDTH of inst : label is 1; - attribute C_PROBE_OUT78_INIT_VAL : string; - attribute C_PROBE_OUT78_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT78_WIDTH : integer; - attribute C_PROBE_OUT78_WIDTH of inst : label is 1; - attribute C_PROBE_OUT79_INIT_VAL : string; - attribute C_PROBE_OUT79_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT79_WIDTH : integer; - attribute C_PROBE_OUT79_WIDTH of inst : label is 1; - attribute C_PROBE_OUT7_INIT_VAL : string; - attribute C_PROBE_OUT7_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT7_WIDTH : integer; - attribute C_PROBE_OUT7_WIDTH of inst : label is 1; - attribute C_PROBE_OUT80_INIT_VAL : string; - attribute C_PROBE_OUT80_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT80_WIDTH : integer; - attribute C_PROBE_OUT80_WIDTH of inst : label is 1; - attribute C_PROBE_OUT81_INIT_VAL : string; - attribute C_PROBE_OUT81_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT81_WIDTH : integer; - attribute C_PROBE_OUT81_WIDTH of inst : label is 1; - attribute C_PROBE_OUT82_INIT_VAL : string; - attribute C_PROBE_OUT82_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT82_WIDTH : integer; - attribute C_PROBE_OUT82_WIDTH of inst : label is 1; - attribute C_PROBE_OUT83_INIT_VAL : string; - attribute C_PROBE_OUT83_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT83_WIDTH : integer; - attribute C_PROBE_OUT83_WIDTH of inst : label is 1; - attribute C_PROBE_OUT84_INIT_VAL : string; - attribute C_PROBE_OUT84_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT84_WIDTH : integer; - attribute C_PROBE_OUT84_WIDTH of inst : label is 1; - attribute C_PROBE_OUT85_INIT_VAL : string; - attribute C_PROBE_OUT85_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT85_WIDTH : integer; - attribute C_PROBE_OUT85_WIDTH of inst : label is 1; - attribute C_PROBE_OUT86_INIT_VAL : string; - attribute C_PROBE_OUT86_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT86_WIDTH : integer; - attribute C_PROBE_OUT86_WIDTH of inst : label is 1; - attribute C_PROBE_OUT87_INIT_VAL : string; - attribute C_PROBE_OUT87_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT87_WIDTH : integer; - attribute C_PROBE_OUT87_WIDTH of inst : label is 1; - attribute C_PROBE_OUT88_INIT_VAL : string; - attribute C_PROBE_OUT88_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT88_WIDTH : integer; - attribute C_PROBE_OUT88_WIDTH of inst : label is 1; - attribute C_PROBE_OUT89_INIT_VAL : string; - attribute C_PROBE_OUT89_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT89_WIDTH : integer; - attribute C_PROBE_OUT89_WIDTH of inst : label is 1; - attribute C_PROBE_OUT8_INIT_VAL : string; - attribute C_PROBE_OUT8_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT8_WIDTH : integer; - attribute C_PROBE_OUT8_WIDTH of inst : label is 1; - attribute C_PROBE_OUT90_INIT_VAL : string; - attribute C_PROBE_OUT90_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT90_WIDTH : integer; - attribute C_PROBE_OUT90_WIDTH of inst : label is 1; - attribute C_PROBE_OUT91_INIT_VAL : string; - attribute C_PROBE_OUT91_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT91_WIDTH : integer; - attribute C_PROBE_OUT91_WIDTH of inst : label is 1; - attribute C_PROBE_OUT92_INIT_VAL : string; - attribute C_PROBE_OUT92_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT92_WIDTH : integer; - attribute C_PROBE_OUT92_WIDTH of inst : label is 1; - attribute C_PROBE_OUT93_INIT_VAL : string; - attribute C_PROBE_OUT93_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT93_WIDTH : integer; - attribute C_PROBE_OUT93_WIDTH of inst : label is 1; - attribute C_PROBE_OUT94_INIT_VAL : string; - attribute C_PROBE_OUT94_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT94_WIDTH : integer; - attribute C_PROBE_OUT94_WIDTH of inst : label is 1; - attribute C_PROBE_OUT95_INIT_VAL : string; - attribute C_PROBE_OUT95_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT95_WIDTH : integer; - attribute C_PROBE_OUT95_WIDTH of inst : label is 1; - attribute C_PROBE_OUT96_INIT_VAL : string; - attribute C_PROBE_OUT96_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT96_WIDTH : integer; - attribute C_PROBE_OUT96_WIDTH of inst : label is 1; - attribute C_PROBE_OUT97_INIT_VAL : string; - attribute C_PROBE_OUT97_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT97_WIDTH : integer; - attribute C_PROBE_OUT97_WIDTH of inst : label is 1; - attribute C_PROBE_OUT98_INIT_VAL : string; - attribute C_PROBE_OUT98_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT98_WIDTH : integer; - attribute C_PROBE_OUT98_WIDTH of inst : label is 1; - attribute C_PROBE_OUT99_INIT_VAL : string; - attribute C_PROBE_OUT99_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT99_WIDTH : integer; - attribute C_PROBE_OUT99_WIDTH of inst : label is 1; - attribute C_PROBE_OUT9_INIT_VAL : string; - attribute C_PROBE_OUT9_INIT_VAL of inst : label is "1'b0"; - attribute C_PROBE_OUT9_WIDTH : integer; - attribute C_PROBE_OUT9_WIDTH of inst : label is 1; - attribute C_USE_TEST_REG : integer; - attribute C_USE_TEST_REG of inst : label is 1; - attribute C_XDEVICEFAMILY : string; - attribute C_XDEVICEFAMILY of inst : label is "zynq"; - attribute C_XLNX_HW_PROBE_INFO : string; - attribute C_XLNX_HW_PROBE_INFO of inst : label is "DEFAULT"; - attribute C_XSDB_SLAVE_TYPE : integer; - attribute C_XSDB_SLAVE_TYPE of inst : label is 33; - attribute DONT_TOUCH : boolean; - attribute DONT_TOUCH of inst : label is std.standard.true; - attribute DowngradeIPIdentifiedWarnings : string; - attribute DowngradeIPIdentifiedWarnings of inst : label is "yes"; - attribute LC_HIGH_BIT_POS_PROBE_OUT0 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT0 of inst : label is "16'b0000000000011111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT1 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT1 of inst : label is "16'b0000000000100000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT10 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT10 of inst : label is "16'b0000000000101001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT100 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT100 of inst : label is "16'b0000000010000011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT101 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT101 of inst : label is "16'b0000000010000100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT102 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT102 of inst : label is "16'b0000000010000101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT103 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT103 of inst : label is "16'b0000000010000110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT104 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT104 of inst : label is "16'b0000000010000111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT105 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT105 of inst : label is "16'b0000000010001000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT106 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT106 of inst : label is "16'b0000000010001001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT107 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT107 of inst : label is "16'b0000000010001010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT108 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT108 of inst : label is "16'b0000000010001011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT109 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT109 of inst : label is "16'b0000000010001100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT11 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT11 of inst : label is "16'b0000000000101010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT110 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT110 of inst : label is "16'b0000000010001101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT111 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT111 of inst : label is "16'b0000000010001110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT112 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT112 of inst : label is "16'b0000000010001111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT113 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT113 of inst : label is "16'b0000000010010000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT114 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT114 of inst : label is "16'b0000000010010001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT115 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT115 of inst : label is "16'b0000000010010010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT116 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT116 of inst : label is "16'b0000000010010011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT117 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT117 of inst : label is "16'b0000000010010100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT118 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT118 of inst : label is "16'b0000000010010101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT119 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT119 of inst : label is "16'b0000000010010110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT12 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT12 of inst : label is "16'b0000000000101011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT120 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT120 of inst : label is "16'b0000000010010111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT121 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT121 of inst : label is "16'b0000000010011000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT122 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT122 of inst : label is "16'b0000000010011001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT123 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT123 of inst : label is "16'b0000000010011010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT124 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT124 of inst : label is "16'b0000000010011011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT125 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT125 of inst : label is "16'b0000000010011100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT126 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT126 of inst : label is "16'b0000000010011101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT127 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT127 of inst : label is "16'b0000000010011110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT128 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT128 of inst : label is "16'b0000000010011111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT129 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT129 of inst : label is "16'b0000000010100000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT13 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT13 of inst : label is "16'b0000000000101100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT130 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT130 of inst : label is "16'b0000000010100001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT131 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT131 of inst : label is "16'b0000000010100010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT132 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT132 of inst : label is "16'b0000000010100011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT133 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT133 of inst : label is "16'b0000000010100100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT134 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT134 of inst : label is "16'b0000000010100101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT135 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT135 of inst : label is "16'b0000000010100110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT136 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT136 of inst : label is "16'b0000000010100111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT137 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT137 of inst : label is "16'b0000000010101000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT138 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT138 of inst : label is "16'b0000000010101001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT139 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT139 of inst : label is "16'b0000000010101010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT14 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT14 of inst : label is "16'b0000000000101101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT140 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT140 of inst : label is "16'b0000000010101011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT141 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT141 of inst : label is "16'b0000000010101100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT142 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT142 of inst : label is "16'b0000000010101101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT143 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT143 of inst : label is "16'b0000000010101110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT144 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT144 of inst : label is "16'b0000000010101111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT145 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT145 of inst : label is "16'b0000000010110000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT146 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT146 of inst : label is "16'b0000000010110001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT147 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT147 of inst : label is "16'b0000000010110010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT148 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT148 of inst : label is "16'b0000000010110011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT149 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT149 of inst : label is "16'b0000000010110100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT15 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT15 of inst : label is "16'b0000000000101110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT150 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT150 of inst : label is "16'b0000000010110101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT151 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT151 of inst : label is "16'b0000000010110110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT152 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT152 of inst : label is "16'b0000000010110111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT153 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT153 of inst : label is "16'b0000000010111000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT154 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT154 of inst : label is "16'b0000000010111001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT155 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT155 of inst : label is "16'b0000000010111010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT156 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT156 of inst : label is "16'b0000000010111011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT157 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT157 of inst : label is "16'b0000000010111100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT158 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT158 of inst : label is "16'b0000000010111101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT159 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT159 of inst : label is "16'b0000000010111110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT16 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT16 of inst : label is "16'b0000000000101111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT160 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT160 of inst : label is "16'b0000000010111111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT161 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT161 of inst : label is "16'b0000000011000000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT162 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT162 of inst : label is "16'b0000000011000001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT163 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT163 of inst : label is "16'b0000000011000010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT164 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT164 of inst : label is "16'b0000000011000011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT165 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT165 of inst : label is "16'b0000000011000100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT166 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT166 of inst : label is "16'b0000000011000101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT167 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT167 of inst : label is "16'b0000000011000110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT168 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT168 of inst : label is "16'b0000000011000111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT169 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT169 of inst : label is "16'b0000000011001000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT17 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT17 of inst : label is "16'b0000000000110000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT170 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT170 of inst : label is "16'b0000000011001001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT171 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT171 of inst : label is "16'b0000000011001010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT172 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT172 of inst : label is "16'b0000000011001011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT173 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT173 of inst : label is "16'b0000000011001100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT174 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT174 of inst : label is "16'b0000000011001101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT175 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT175 of inst : label is "16'b0000000011001110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT176 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT176 of inst : label is "16'b0000000011001111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT177 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT177 of inst : label is "16'b0000000011010000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT178 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT178 of inst : label is "16'b0000000011010001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT179 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT179 of inst : label is "16'b0000000011010010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT18 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT18 of inst : label is "16'b0000000000110001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT180 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT180 of inst : label is "16'b0000000011010011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT181 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT181 of inst : label is "16'b0000000011010100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT182 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT182 of inst : label is "16'b0000000011010101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT183 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT183 of inst : label is "16'b0000000011010110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT184 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT184 of inst : label is "16'b0000000011010111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT185 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT185 of inst : label is "16'b0000000011011000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT186 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT186 of inst : label is "16'b0000000011011001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT187 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT187 of inst : label is "16'b0000000011011010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT188 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT188 of inst : label is "16'b0000000011011011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT189 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT189 of inst : label is "16'b0000000011011100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT19 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT19 of inst : label is "16'b0000000000110010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT190 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT190 of inst : label is "16'b0000000011011101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT191 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT191 of inst : label is "16'b0000000011011110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT192 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT192 of inst : label is "16'b0000000011011111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT193 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT193 of inst : label is "16'b0000000011100000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT194 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT194 of inst : label is "16'b0000000011100001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT195 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT195 of inst : label is "16'b0000000011100010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT196 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT196 of inst : label is "16'b0000000011100011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT197 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT197 of inst : label is "16'b0000000011100100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT198 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT198 of inst : label is "16'b0000000011100101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT199 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT199 of inst : label is "16'b0000000011100110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT2 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT2 of inst : label is "16'b0000000000100001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT20 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT20 of inst : label is "16'b0000000000110011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT200 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT200 of inst : label is "16'b0000000011100111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT201 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT201 of inst : label is "16'b0000000011101000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT202 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT202 of inst : label is "16'b0000000011101001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT203 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT203 of inst : label is "16'b0000000011101010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT204 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT204 of inst : label is "16'b0000000011101011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT205 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT205 of inst : label is "16'b0000000011101100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT206 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT206 of inst : label is "16'b0000000011101101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT207 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT207 of inst : label is "16'b0000000011101110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT208 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT208 of inst : label is "16'b0000000011101111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT209 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT209 of inst : label is "16'b0000000011110000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT21 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT21 of inst : label is "16'b0000000000110100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT210 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT210 of inst : label is "16'b0000000011110001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT211 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT211 of inst : label is "16'b0000000011110010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT212 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT212 of inst : label is "16'b0000000011110011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT213 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT213 of inst : label is "16'b0000000011110100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT214 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT214 of inst : label is "16'b0000000011110101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT215 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT215 of inst : label is "16'b0000000011110110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT216 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT216 of inst : label is "16'b0000000011110111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT217 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT217 of inst : label is "16'b0000000011111000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT218 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT218 of inst : label is "16'b0000000011111001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT219 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT219 of inst : label is "16'b0000000011111010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT22 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT22 of inst : label is "16'b0000000000110101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT220 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT220 of inst : label is "16'b0000000011111011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT221 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT221 of inst : label is "16'b0000000011111100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT222 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT222 of inst : label is "16'b0000000011111101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT223 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT223 of inst : label is "16'b0000000011111110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT224 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT224 of inst : label is "16'b0000000011111111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT225 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT225 of inst : label is "16'b0000000100000000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT226 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT226 of inst : label is "16'b0000000100000001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT227 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT227 of inst : label is "16'b0000000100000010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT228 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT228 of inst : label is "16'b0000000100000011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT229 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT229 of inst : label is "16'b0000000100000100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT23 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT23 of inst : label is "16'b0000000000110110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT230 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT230 of inst : label is "16'b0000000100000101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT231 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT231 of inst : label is "16'b0000000100000110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT232 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT232 of inst : label is "16'b0000000100000111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT233 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT233 of inst : label is "16'b0000000100001000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT234 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT234 of inst : label is "16'b0000000100001001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT235 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT235 of inst : label is "16'b0000000100001010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT236 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT236 of inst : label is "16'b0000000100001011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT237 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT237 of inst : label is "16'b0000000100001100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT238 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT238 of inst : label is "16'b0000000100001101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT239 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT239 of inst : label is "16'b0000000100001110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT24 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT24 of inst : label is "16'b0000000000110111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT240 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT240 of inst : label is "16'b0000000100001111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT241 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT241 of inst : label is "16'b0000000100010000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT242 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT242 of inst : label is "16'b0000000100010001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT243 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT243 of inst : label is "16'b0000000100010010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT244 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT244 of inst : label is "16'b0000000100010011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT245 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT245 of inst : label is "16'b0000000100010100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT246 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT246 of inst : label is "16'b0000000100010101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT247 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT247 of inst : label is "16'b0000000100010110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT248 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT248 of inst : label is "16'b0000000100010111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT249 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT249 of inst : label is "16'b0000000100011000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT25 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT25 of inst : label is "16'b0000000000111000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT250 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT250 of inst : label is "16'b0000000100011001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT251 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT251 of inst : label is "16'b0000000100011010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT252 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT252 of inst : label is "16'b0000000100011011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT253 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT253 of inst : label is "16'b0000000100011100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT254 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT254 of inst : label is "16'b0000000100011101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT255 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT255 of inst : label is "16'b0000000100011110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT26 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT26 of inst : label is "16'b0000000000111001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT27 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT27 of inst : label is "16'b0000000000111010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT28 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT28 of inst : label is "16'b0000000000111011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT29 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT29 of inst : label is "16'b0000000000111100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT3 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT3 of inst : label is "16'b0000000000100010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT30 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT30 of inst : label is "16'b0000000000111101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT31 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT31 of inst : label is "16'b0000000000111110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT32 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT32 of inst : label is "16'b0000000000111111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT33 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT33 of inst : label is "16'b0000000001000000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT34 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT34 of inst : label is "16'b0000000001000001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT35 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT35 of inst : label is "16'b0000000001000010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT36 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT36 of inst : label is "16'b0000000001000011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT37 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT37 of inst : label is "16'b0000000001000100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT38 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT38 of inst : label is "16'b0000000001000101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT39 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT39 of inst : label is "16'b0000000001000110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT4 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT4 of inst : label is "16'b0000000000100011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT40 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT40 of inst : label is "16'b0000000001000111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT41 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT41 of inst : label is "16'b0000000001001000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT42 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT42 of inst : label is "16'b0000000001001001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT43 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT43 of inst : label is "16'b0000000001001010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT44 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT44 of inst : label is "16'b0000000001001011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT45 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT45 of inst : label is "16'b0000000001001100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT46 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT46 of inst : label is "16'b0000000001001101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT47 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT47 of inst : label is "16'b0000000001001110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT48 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT48 of inst : label is "16'b0000000001001111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT49 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT49 of inst : label is "16'b0000000001010000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT5 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT5 of inst : label is "16'b0000000000100100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT50 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT50 of inst : label is "16'b0000000001010001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT51 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT51 of inst : label is "16'b0000000001010010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT52 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT52 of inst : label is "16'b0000000001010011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT53 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT53 of inst : label is "16'b0000000001010100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT54 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT54 of inst : label is "16'b0000000001010101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT55 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT55 of inst : label is "16'b0000000001010110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT56 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT56 of inst : label is "16'b0000000001010111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT57 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT57 of inst : label is "16'b0000000001011000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT58 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT58 of inst : label is "16'b0000000001011001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT59 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT59 of inst : label is "16'b0000000001011010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT6 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT6 of inst : label is "16'b0000000000100101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT60 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT60 of inst : label is "16'b0000000001011011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT61 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT61 of inst : label is "16'b0000000001011100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT62 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT62 of inst : label is "16'b0000000001011101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT63 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT63 of inst : label is "16'b0000000001011110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT64 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT64 of inst : label is "16'b0000000001011111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT65 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT65 of inst : label is "16'b0000000001100000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT66 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT66 of inst : label is "16'b0000000001100001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT67 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT67 of inst : label is "16'b0000000001100010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT68 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT68 of inst : label is "16'b0000000001100011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT69 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT69 of inst : label is "16'b0000000001100100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT7 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT7 of inst : label is "16'b0000000000100110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT70 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT70 of inst : label is "16'b0000000001100101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT71 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT71 of inst : label is "16'b0000000001100110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT72 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT72 of inst : label is "16'b0000000001100111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT73 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT73 of inst : label is "16'b0000000001101000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT74 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT74 of inst : label is "16'b0000000001101001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT75 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT75 of inst : label is "16'b0000000001101010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT76 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT76 of inst : label is "16'b0000000001101011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT77 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT77 of inst : label is "16'b0000000001101100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT78 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT78 of inst : label is "16'b0000000001101101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT79 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT79 of inst : label is "16'b0000000001101110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT8 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT8 of inst : label is "16'b0000000000100111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT80 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT80 of inst : label is "16'b0000000001101111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT81 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT81 of inst : label is "16'b0000000001110000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT82 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT82 of inst : label is "16'b0000000001110001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT83 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT83 of inst : label is "16'b0000000001110010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT84 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT84 of inst : label is "16'b0000000001110011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT85 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT85 of inst : label is "16'b0000000001110100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT86 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT86 of inst : label is "16'b0000000001110101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT87 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT87 of inst : label is "16'b0000000001110110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT88 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT88 of inst : label is "16'b0000000001110111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT89 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT89 of inst : label is "16'b0000000001111000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT9 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT9 of inst : label is "16'b0000000000101000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT90 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT90 of inst : label is "16'b0000000001111001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT91 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT91 of inst : label is "16'b0000000001111010"; - attribute LC_HIGH_BIT_POS_PROBE_OUT92 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT92 of inst : label is "16'b0000000001111011"; - attribute LC_HIGH_BIT_POS_PROBE_OUT93 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT93 of inst : label is "16'b0000000001111100"; - attribute LC_HIGH_BIT_POS_PROBE_OUT94 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT94 of inst : label is "16'b0000000001111101"; - attribute LC_HIGH_BIT_POS_PROBE_OUT95 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT95 of inst : label is "16'b0000000001111110"; - attribute LC_HIGH_BIT_POS_PROBE_OUT96 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT96 of inst : label is "16'b0000000001111111"; - attribute LC_HIGH_BIT_POS_PROBE_OUT97 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT97 of inst : label is "16'b0000000010000000"; - attribute LC_HIGH_BIT_POS_PROBE_OUT98 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT98 of inst : label is "16'b0000000010000001"; - attribute LC_HIGH_BIT_POS_PROBE_OUT99 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT99 of inst : label is "16'b0000000010000010"; - attribute LC_LOW_BIT_POS_PROBE_OUT0 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT0 of inst : label is "16'b0000000000000000"; - attribute LC_LOW_BIT_POS_PROBE_OUT1 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT1 of inst : label is "16'b0000000000100000"; - attribute LC_LOW_BIT_POS_PROBE_OUT10 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT10 of inst : label is "16'b0000000000101001"; - attribute LC_LOW_BIT_POS_PROBE_OUT100 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT100 of inst : label is "16'b0000000010000011"; - attribute LC_LOW_BIT_POS_PROBE_OUT101 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT101 of inst : label is "16'b0000000010000100"; - attribute LC_LOW_BIT_POS_PROBE_OUT102 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT102 of inst : label is "16'b0000000010000101"; - attribute LC_LOW_BIT_POS_PROBE_OUT103 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT103 of inst : label is "16'b0000000010000110"; - attribute LC_LOW_BIT_POS_PROBE_OUT104 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT104 of inst : label is "16'b0000000010000111"; - attribute LC_LOW_BIT_POS_PROBE_OUT105 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT105 of inst : label is "16'b0000000010001000"; - attribute LC_LOW_BIT_POS_PROBE_OUT106 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT106 of inst : label is "16'b0000000010001001"; - attribute LC_LOW_BIT_POS_PROBE_OUT107 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT107 of inst : label is "16'b0000000010001010"; - attribute LC_LOW_BIT_POS_PROBE_OUT108 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT108 of inst : label is "16'b0000000010001011"; - attribute LC_LOW_BIT_POS_PROBE_OUT109 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT109 of inst : label is "16'b0000000010001100"; - attribute LC_LOW_BIT_POS_PROBE_OUT11 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT11 of inst : label is "16'b0000000000101010"; - attribute LC_LOW_BIT_POS_PROBE_OUT110 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT110 of inst : label is "16'b0000000010001101"; - attribute LC_LOW_BIT_POS_PROBE_OUT111 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT111 of inst : label is "16'b0000000010001110"; - attribute LC_LOW_BIT_POS_PROBE_OUT112 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT112 of inst : label is "16'b0000000010001111"; - attribute LC_LOW_BIT_POS_PROBE_OUT113 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT113 of inst : label is "16'b0000000010010000"; - attribute LC_LOW_BIT_POS_PROBE_OUT114 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT114 of inst : label is "16'b0000000010010001"; - attribute LC_LOW_BIT_POS_PROBE_OUT115 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT115 of inst : label is "16'b0000000010010010"; - attribute LC_LOW_BIT_POS_PROBE_OUT116 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT116 of inst : label is "16'b0000000010010011"; - attribute LC_LOW_BIT_POS_PROBE_OUT117 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT117 of inst : label is "16'b0000000010010100"; - attribute LC_LOW_BIT_POS_PROBE_OUT118 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT118 of inst : label is "16'b0000000010010101"; - attribute LC_LOW_BIT_POS_PROBE_OUT119 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT119 of inst : label is "16'b0000000010010110"; - attribute LC_LOW_BIT_POS_PROBE_OUT12 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT12 of inst : label is "16'b0000000000101011"; - attribute LC_LOW_BIT_POS_PROBE_OUT120 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT120 of inst : label is "16'b0000000010010111"; - attribute LC_LOW_BIT_POS_PROBE_OUT121 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT121 of inst : label is "16'b0000000010011000"; - attribute LC_LOW_BIT_POS_PROBE_OUT122 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT122 of inst : label is "16'b0000000010011001"; - attribute LC_LOW_BIT_POS_PROBE_OUT123 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT123 of inst : label is "16'b0000000010011010"; - attribute LC_LOW_BIT_POS_PROBE_OUT124 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT124 of inst : label is "16'b0000000010011011"; - attribute LC_LOW_BIT_POS_PROBE_OUT125 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT125 of inst : label is "16'b0000000010011100"; - attribute LC_LOW_BIT_POS_PROBE_OUT126 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT126 of inst : label is "16'b0000000010011101"; - attribute LC_LOW_BIT_POS_PROBE_OUT127 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT127 of inst : label is "16'b0000000010011110"; - attribute LC_LOW_BIT_POS_PROBE_OUT128 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT128 of inst : label is "16'b0000000010011111"; - attribute LC_LOW_BIT_POS_PROBE_OUT129 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT129 of inst : label is "16'b0000000010100000"; - attribute LC_LOW_BIT_POS_PROBE_OUT13 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT13 of inst : label is "16'b0000000000101100"; - attribute LC_LOW_BIT_POS_PROBE_OUT130 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT130 of inst : label is "16'b0000000010100001"; - attribute LC_LOW_BIT_POS_PROBE_OUT131 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT131 of inst : label is "16'b0000000010100010"; - attribute LC_LOW_BIT_POS_PROBE_OUT132 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT132 of inst : label is "16'b0000000010100011"; - attribute LC_LOW_BIT_POS_PROBE_OUT133 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT133 of inst : label is "16'b0000000010100100"; - attribute LC_LOW_BIT_POS_PROBE_OUT134 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT134 of inst : label is "16'b0000000010100101"; - attribute LC_LOW_BIT_POS_PROBE_OUT135 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT135 of inst : label is "16'b0000000010100110"; - attribute LC_LOW_BIT_POS_PROBE_OUT136 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT136 of inst : label is "16'b0000000010100111"; - attribute LC_LOW_BIT_POS_PROBE_OUT137 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT137 of inst : label is "16'b0000000010101000"; - attribute LC_LOW_BIT_POS_PROBE_OUT138 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT138 of inst : label is "16'b0000000010101001"; - attribute LC_LOW_BIT_POS_PROBE_OUT139 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT139 of inst : label is "16'b0000000010101010"; - attribute LC_LOW_BIT_POS_PROBE_OUT14 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT14 of inst : label is "16'b0000000000101101"; - attribute LC_LOW_BIT_POS_PROBE_OUT140 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT140 of inst : label is "16'b0000000010101011"; - attribute LC_LOW_BIT_POS_PROBE_OUT141 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT141 of inst : label is "16'b0000000010101100"; - attribute LC_LOW_BIT_POS_PROBE_OUT142 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT142 of inst : label is "16'b0000000010101101"; - attribute LC_LOW_BIT_POS_PROBE_OUT143 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT143 of inst : label is "16'b0000000010101110"; - attribute LC_LOW_BIT_POS_PROBE_OUT144 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT144 of inst : label is "16'b0000000010101111"; - attribute LC_LOW_BIT_POS_PROBE_OUT145 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT145 of inst : label is "16'b0000000010110000"; - attribute LC_LOW_BIT_POS_PROBE_OUT146 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT146 of inst : label is "16'b0000000010110001"; - attribute LC_LOW_BIT_POS_PROBE_OUT147 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT147 of inst : label is "16'b0000000010110010"; - attribute LC_LOW_BIT_POS_PROBE_OUT148 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT148 of inst : label is "16'b0000000010110011"; - attribute LC_LOW_BIT_POS_PROBE_OUT149 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT149 of inst : label is "16'b0000000010110100"; - attribute LC_LOW_BIT_POS_PROBE_OUT15 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT15 of inst : label is "16'b0000000000101110"; - attribute LC_LOW_BIT_POS_PROBE_OUT150 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT150 of inst : label is "16'b0000000010110101"; - attribute LC_LOW_BIT_POS_PROBE_OUT151 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT151 of inst : label is "16'b0000000010110110"; - attribute LC_LOW_BIT_POS_PROBE_OUT152 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT152 of inst : label is "16'b0000000010110111"; - attribute LC_LOW_BIT_POS_PROBE_OUT153 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT153 of inst : label is "16'b0000000010111000"; - attribute LC_LOW_BIT_POS_PROBE_OUT154 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT154 of inst : label is "16'b0000000010111001"; - attribute LC_LOW_BIT_POS_PROBE_OUT155 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT155 of inst : label is "16'b0000000010111010"; - attribute LC_LOW_BIT_POS_PROBE_OUT156 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT156 of inst : label is "16'b0000000010111011"; - attribute LC_LOW_BIT_POS_PROBE_OUT157 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT157 of inst : label is "16'b0000000010111100"; - attribute LC_LOW_BIT_POS_PROBE_OUT158 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT158 of inst : label is "16'b0000000010111101"; - attribute LC_LOW_BIT_POS_PROBE_OUT159 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT159 of inst : label is "16'b0000000010111110"; - attribute LC_LOW_BIT_POS_PROBE_OUT16 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT16 of inst : label is "16'b0000000000101111"; - attribute LC_LOW_BIT_POS_PROBE_OUT160 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT160 of inst : label is "16'b0000000010111111"; - attribute LC_LOW_BIT_POS_PROBE_OUT161 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT161 of inst : label is "16'b0000000011000000"; - attribute LC_LOW_BIT_POS_PROBE_OUT162 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT162 of inst : label is "16'b0000000011000001"; - attribute LC_LOW_BIT_POS_PROBE_OUT163 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT163 of inst : label is "16'b0000000011000010"; - attribute LC_LOW_BIT_POS_PROBE_OUT164 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT164 of inst : label is "16'b0000000011000011"; - attribute LC_LOW_BIT_POS_PROBE_OUT165 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT165 of inst : label is "16'b0000000011000100"; - attribute LC_LOW_BIT_POS_PROBE_OUT166 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT166 of inst : label is "16'b0000000011000101"; - attribute LC_LOW_BIT_POS_PROBE_OUT167 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT167 of inst : label is "16'b0000000011000110"; - attribute LC_LOW_BIT_POS_PROBE_OUT168 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT168 of inst : label is "16'b0000000011000111"; - attribute LC_LOW_BIT_POS_PROBE_OUT169 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT169 of inst : label is "16'b0000000011001000"; - attribute LC_LOW_BIT_POS_PROBE_OUT17 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT17 of inst : label is "16'b0000000000110000"; - attribute LC_LOW_BIT_POS_PROBE_OUT170 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT170 of inst : label is "16'b0000000011001001"; - attribute LC_LOW_BIT_POS_PROBE_OUT171 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT171 of inst : label is "16'b0000000011001010"; - attribute LC_LOW_BIT_POS_PROBE_OUT172 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT172 of inst : label is "16'b0000000011001011"; - attribute LC_LOW_BIT_POS_PROBE_OUT173 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT173 of inst : label is "16'b0000000011001100"; - attribute LC_LOW_BIT_POS_PROBE_OUT174 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT174 of inst : label is "16'b0000000011001101"; - attribute LC_LOW_BIT_POS_PROBE_OUT175 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT175 of inst : label is "16'b0000000011001110"; - attribute LC_LOW_BIT_POS_PROBE_OUT176 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT176 of inst : label is "16'b0000000011001111"; - attribute LC_LOW_BIT_POS_PROBE_OUT177 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT177 of inst : label is "16'b0000000011010000"; - attribute LC_LOW_BIT_POS_PROBE_OUT178 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT178 of inst : label is "16'b0000000011010001"; - attribute LC_LOW_BIT_POS_PROBE_OUT179 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT179 of inst : label is "16'b0000000011010010"; - attribute LC_LOW_BIT_POS_PROBE_OUT18 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT18 of inst : label is "16'b0000000000110001"; - attribute LC_LOW_BIT_POS_PROBE_OUT180 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT180 of inst : label is "16'b0000000011010011"; - attribute LC_LOW_BIT_POS_PROBE_OUT181 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT181 of inst : label is "16'b0000000011010100"; - attribute LC_LOW_BIT_POS_PROBE_OUT182 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT182 of inst : label is "16'b0000000011010101"; - attribute LC_LOW_BIT_POS_PROBE_OUT183 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT183 of inst : label is "16'b0000000011010110"; - attribute LC_LOW_BIT_POS_PROBE_OUT184 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT184 of inst : label is "16'b0000000011010111"; - attribute LC_LOW_BIT_POS_PROBE_OUT185 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT185 of inst : label is "16'b0000000011011000"; - attribute LC_LOW_BIT_POS_PROBE_OUT186 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT186 of inst : label is "16'b0000000011011001"; - attribute LC_LOW_BIT_POS_PROBE_OUT187 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT187 of inst : label is "16'b0000000011011010"; - attribute LC_LOW_BIT_POS_PROBE_OUT188 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT188 of inst : label is "16'b0000000011011011"; - attribute LC_LOW_BIT_POS_PROBE_OUT189 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT189 of inst : label is "16'b0000000011011100"; - attribute LC_LOW_BIT_POS_PROBE_OUT19 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT19 of inst : label is "16'b0000000000110010"; - attribute LC_LOW_BIT_POS_PROBE_OUT190 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT190 of inst : label is "16'b0000000011011101"; - attribute LC_LOW_BIT_POS_PROBE_OUT191 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT191 of inst : label is "16'b0000000011011110"; - attribute LC_LOW_BIT_POS_PROBE_OUT192 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT192 of inst : label is "16'b0000000011011111"; - attribute LC_LOW_BIT_POS_PROBE_OUT193 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT193 of inst : label is "16'b0000000011100000"; - attribute LC_LOW_BIT_POS_PROBE_OUT194 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT194 of inst : label is "16'b0000000011100001"; - attribute LC_LOW_BIT_POS_PROBE_OUT195 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT195 of inst : label is "16'b0000000011100010"; - attribute LC_LOW_BIT_POS_PROBE_OUT196 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT196 of inst : label is "16'b0000000011100011"; - attribute LC_LOW_BIT_POS_PROBE_OUT197 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT197 of inst : label is "16'b0000000011100100"; - attribute LC_LOW_BIT_POS_PROBE_OUT198 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT198 of inst : label is "16'b0000000011100101"; - attribute LC_LOW_BIT_POS_PROBE_OUT199 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT199 of inst : label is "16'b0000000011100110"; - attribute LC_LOW_BIT_POS_PROBE_OUT2 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT2 of inst : label is "16'b0000000000100001"; - attribute LC_LOW_BIT_POS_PROBE_OUT20 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT20 of inst : label is "16'b0000000000110011"; - attribute LC_LOW_BIT_POS_PROBE_OUT200 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT200 of inst : label is "16'b0000000011100111"; - attribute LC_LOW_BIT_POS_PROBE_OUT201 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT201 of inst : label is "16'b0000000011101000"; - attribute LC_LOW_BIT_POS_PROBE_OUT202 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT202 of inst : label is "16'b0000000011101001"; - attribute LC_LOW_BIT_POS_PROBE_OUT203 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT203 of inst : label is "16'b0000000011101010"; - attribute LC_LOW_BIT_POS_PROBE_OUT204 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT204 of inst : label is "16'b0000000011101011"; - attribute LC_LOW_BIT_POS_PROBE_OUT205 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT205 of inst : label is "16'b0000000011101100"; - attribute LC_LOW_BIT_POS_PROBE_OUT206 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT206 of inst : label is "16'b0000000011101101"; - attribute LC_LOW_BIT_POS_PROBE_OUT207 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT207 of inst : label is "16'b0000000011101110"; - attribute LC_LOW_BIT_POS_PROBE_OUT208 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT208 of inst : label is "16'b0000000011101111"; - attribute LC_LOW_BIT_POS_PROBE_OUT209 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT209 of inst : label is "16'b0000000011110000"; - attribute LC_LOW_BIT_POS_PROBE_OUT21 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT21 of inst : label is "16'b0000000000110100"; - attribute LC_LOW_BIT_POS_PROBE_OUT210 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT210 of inst : label is "16'b0000000011110001"; - attribute LC_LOW_BIT_POS_PROBE_OUT211 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT211 of inst : label is "16'b0000000011110010"; - attribute LC_LOW_BIT_POS_PROBE_OUT212 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT212 of inst : label is "16'b0000000011110011"; - attribute LC_LOW_BIT_POS_PROBE_OUT213 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT213 of inst : label is "16'b0000000011110100"; - attribute LC_LOW_BIT_POS_PROBE_OUT214 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT214 of inst : label is "16'b0000000011110101"; - attribute LC_LOW_BIT_POS_PROBE_OUT215 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT215 of inst : label is "16'b0000000011110110"; - attribute LC_LOW_BIT_POS_PROBE_OUT216 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT216 of inst : label is "16'b0000000011110111"; - attribute LC_LOW_BIT_POS_PROBE_OUT217 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT217 of inst : label is "16'b0000000011111000"; - attribute LC_LOW_BIT_POS_PROBE_OUT218 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT218 of inst : label is "16'b0000000011111001"; - attribute LC_LOW_BIT_POS_PROBE_OUT219 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT219 of inst : label is "16'b0000000011111010"; - attribute LC_LOW_BIT_POS_PROBE_OUT22 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT22 of inst : label is "16'b0000000000110101"; - attribute LC_LOW_BIT_POS_PROBE_OUT220 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT220 of inst : label is "16'b0000000011111011"; - attribute LC_LOW_BIT_POS_PROBE_OUT221 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT221 of inst : label is "16'b0000000011111100"; - attribute LC_LOW_BIT_POS_PROBE_OUT222 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT222 of inst : label is "16'b0000000011111101"; - attribute LC_LOW_BIT_POS_PROBE_OUT223 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT223 of inst : label is "16'b0000000011111110"; - attribute LC_LOW_BIT_POS_PROBE_OUT224 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT224 of inst : label is "16'b0000000011111111"; - attribute LC_LOW_BIT_POS_PROBE_OUT225 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT225 of inst : label is "16'b0000000100000000"; - attribute LC_LOW_BIT_POS_PROBE_OUT226 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT226 of inst : label is "16'b0000000100000001"; - attribute LC_LOW_BIT_POS_PROBE_OUT227 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT227 of inst : label is "16'b0000000100000010"; - attribute LC_LOW_BIT_POS_PROBE_OUT228 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT228 of inst : label is "16'b0000000100000011"; - attribute LC_LOW_BIT_POS_PROBE_OUT229 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT229 of inst : label is "16'b0000000100000100"; - attribute LC_LOW_BIT_POS_PROBE_OUT23 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT23 of inst : label is "16'b0000000000110110"; - attribute LC_LOW_BIT_POS_PROBE_OUT230 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT230 of inst : label is "16'b0000000100000101"; - attribute LC_LOW_BIT_POS_PROBE_OUT231 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT231 of inst : label is "16'b0000000100000110"; - attribute LC_LOW_BIT_POS_PROBE_OUT232 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT232 of inst : label is "16'b0000000100000111"; - attribute LC_LOW_BIT_POS_PROBE_OUT233 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT233 of inst : label is "16'b0000000100001000"; - attribute LC_LOW_BIT_POS_PROBE_OUT234 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT234 of inst : label is "16'b0000000100001001"; - attribute LC_LOW_BIT_POS_PROBE_OUT235 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT235 of inst : label is "16'b0000000100001010"; - attribute LC_LOW_BIT_POS_PROBE_OUT236 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT236 of inst : label is "16'b0000000100001011"; - attribute LC_LOW_BIT_POS_PROBE_OUT237 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT237 of inst : label is "16'b0000000100001100"; - attribute LC_LOW_BIT_POS_PROBE_OUT238 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT238 of inst : label is "16'b0000000100001101"; - attribute LC_LOW_BIT_POS_PROBE_OUT239 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT239 of inst : label is "16'b0000000100001110"; - attribute LC_LOW_BIT_POS_PROBE_OUT24 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT24 of inst : label is "16'b0000000000110111"; - attribute LC_LOW_BIT_POS_PROBE_OUT240 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT240 of inst : label is "16'b0000000100001111"; - attribute LC_LOW_BIT_POS_PROBE_OUT241 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT241 of inst : label is "16'b0000000100010000"; - attribute LC_LOW_BIT_POS_PROBE_OUT242 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT242 of inst : label is "16'b0000000100010001"; - attribute LC_LOW_BIT_POS_PROBE_OUT243 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT243 of inst : label is "16'b0000000100010010"; - attribute LC_LOW_BIT_POS_PROBE_OUT244 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT244 of inst : label is "16'b0000000100010011"; - attribute LC_LOW_BIT_POS_PROBE_OUT245 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT245 of inst : label is "16'b0000000100010100"; - attribute LC_LOW_BIT_POS_PROBE_OUT246 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT246 of inst : label is "16'b0000000100010101"; - attribute LC_LOW_BIT_POS_PROBE_OUT247 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT247 of inst : label is "16'b0000000100010110"; - attribute LC_LOW_BIT_POS_PROBE_OUT248 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT248 of inst : label is "16'b0000000100010111"; - attribute LC_LOW_BIT_POS_PROBE_OUT249 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT249 of inst : label is "16'b0000000100011000"; - attribute LC_LOW_BIT_POS_PROBE_OUT25 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT25 of inst : label is "16'b0000000000111000"; - attribute LC_LOW_BIT_POS_PROBE_OUT250 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT250 of inst : label is "16'b0000000100011001"; - attribute LC_LOW_BIT_POS_PROBE_OUT251 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT251 of inst : label is "16'b0000000100011010"; - attribute LC_LOW_BIT_POS_PROBE_OUT252 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT252 of inst : label is "16'b0000000100011011"; - attribute LC_LOW_BIT_POS_PROBE_OUT253 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT253 of inst : label is "16'b0000000100011100"; - attribute LC_LOW_BIT_POS_PROBE_OUT254 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT254 of inst : label is "16'b0000000100011101"; - attribute LC_LOW_BIT_POS_PROBE_OUT255 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT255 of inst : label is "16'b0000000100011110"; - attribute LC_LOW_BIT_POS_PROBE_OUT26 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT26 of inst : label is "16'b0000000000111001"; - attribute LC_LOW_BIT_POS_PROBE_OUT27 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT27 of inst : label is "16'b0000000000111010"; - attribute LC_LOW_BIT_POS_PROBE_OUT28 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT28 of inst : label is "16'b0000000000111011"; - attribute LC_LOW_BIT_POS_PROBE_OUT29 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT29 of inst : label is "16'b0000000000111100"; - attribute LC_LOW_BIT_POS_PROBE_OUT3 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT3 of inst : label is "16'b0000000000100010"; - attribute LC_LOW_BIT_POS_PROBE_OUT30 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT30 of inst : label is "16'b0000000000111101"; - attribute LC_LOW_BIT_POS_PROBE_OUT31 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT31 of inst : label is "16'b0000000000111110"; - attribute LC_LOW_BIT_POS_PROBE_OUT32 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT32 of inst : label is "16'b0000000000111111"; - attribute LC_LOW_BIT_POS_PROBE_OUT33 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT33 of inst : label is "16'b0000000001000000"; - attribute LC_LOW_BIT_POS_PROBE_OUT34 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT34 of inst : label is "16'b0000000001000001"; - attribute LC_LOW_BIT_POS_PROBE_OUT35 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT35 of inst : label is "16'b0000000001000010"; - attribute LC_LOW_BIT_POS_PROBE_OUT36 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT36 of inst : label is "16'b0000000001000011"; - attribute LC_LOW_BIT_POS_PROBE_OUT37 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT37 of inst : label is "16'b0000000001000100"; - attribute LC_LOW_BIT_POS_PROBE_OUT38 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT38 of inst : label is "16'b0000000001000101"; - attribute LC_LOW_BIT_POS_PROBE_OUT39 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT39 of inst : label is "16'b0000000001000110"; - attribute LC_LOW_BIT_POS_PROBE_OUT4 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT4 of inst : label is "16'b0000000000100011"; - attribute LC_LOW_BIT_POS_PROBE_OUT40 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT40 of inst : label is "16'b0000000001000111"; - attribute LC_LOW_BIT_POS_PROBE_OUT41 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT41 of inst : label is "16'b0000000001001000"; - attribute LC_LOW_BIT_POS_PROBE_OUT42 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT42 of inst : label is "16'b0000000001001001"; - attribute LC_LOW_BIT_POS_PROBE_OUT43 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT43 of inst : label is "16'b0000000001001010"; - attribute LC_LOW_BIT_POS_PROBE_OUT44 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT44 of inst : label is "16'b0000000001001011"; - attribute LC_LOW_BIT_POS_PROBE_OUT45 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT45 of inst : label is "16'b0000000001001100"; - attribute LC_LOW_BIT_POS_PROBE_OUT46 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT46 of inst : label is "16'b0000000001001101"; - attribute LC_LOW_BIT_POS_PROBE_OUT47 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT47 of inst : label is "16'b0000000001001110"; - attribute LC_LOW_BIT_POS_PROBE_OUT48 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT48 of inst : label is "16'b0000000001001111"; - attribute LC_LOW_BIT_POS_PROBE_OUT49 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT49 of inst : label is "16'b0000000001010000"; - attribute LC_LOW_BIT_POS_PROBE_OUT5 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT5 of inst : label is "16'b0000000000100100"; - attribute LC_LOW_BIT_POS_PROBE_OUT50 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT50 of inst : label is "16'b0000000001010001"; - attribute LC_LOW_BIT_POS_PROBE_OUT51 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT51 of inst : label is "16'b0000000001010010"; - attribute LC_LOW_BIT_POS_PROBE_OUT52 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT52 of inst : label is "16'b0000000001010011"; - attribute LC_LOW_BIT_POS_PROBE_OUT53 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT53 of inst : label is "16'b0000000001010100"; - attribute LC_LOW_BIT_POS_PROBE_OUT54 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT54 of inst : label is "16'b0000000001010101"; - attribute LC_LOW_BIT_POS_PROBE_OUT55 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT55 of inst : label is "16'b0000000001010110"; - attribute LC_LOW_BIT_POS_PROBE_OUT56 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT56 of inst : label is "16'b0000000001010111"; - attribute LC_LOW_BIT_POS_PROBE_OUT57 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT57 of inst : label is "16'b0000000001011000"; - attribute LC_LOW_BIT_POS_PROBE_OUT58 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT58 of inst : label is "16'b0000000001011001"; - attribute LC_LOW_BIT_POS_PROBE_OUT59 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT59 of inst : label is "16'b0000000001011010"; - attribute LC_LOW_BIT_POS_PROBE_OUT6 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT6 of inst : label is "16'b0000000000100101"; - attribute LC_LOW_BIT_POS_PROBE_OUT60 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT60 of inst : label is "16'b0000000001011011"; - attribute LC_LOW_BIT_POS_PROBE_OUT61 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT61 of inst : label is "16'b0000000001011100"; - attribute LC_LOW_BIT_POS_PROBE_OUT62 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT62 of inst : label is "16'b0000000001011101"; - attribute LC_LOW_BIT_POS_PROBE_OUT63 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT63 of inst : label is "16'b0000000001011110"; - attribute LC_LOW_BIT_POS_PROBE_OUT64 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT64 of inst : label is "16'b0000000001011111"; - attribute LC_LOW_BIT_POS_PROBE_OUT65 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT65 of inst : label is "16'b0000000001100000"; - attribute LC_LOW_BIT_POS_PROBE_OUT66 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT66 of inst : label is "16'b0000000001100001"; - attribute LC_LOW_BIT_POS_PROBE_OUT67 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT67 of inst : label is "16'b0000000001100010"; - attribute LC_LOW_BIT_POS_PROBE_OUT68 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT68 of inst : label is "16'b0000000001100011"; - attribute LC_LOW_BIT_POS_PROBE_OUT69 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT69 of inst : label is "16'b0000000001100100"; - attribute LC_LOW_BIT_POS_PROBE_OUT7 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT7 of inst : label is "16'b0000000000100110"; - attribute LC_LOW_BIT_POS_PROBE_OUT70 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT70 of inst : label is "16'b0000000001100101"; - attribute LC_LOW_BIT_POS_PROBE_OUT71 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT71 of inst : label is "16'b0000000001100110"; - attribute LC_LOW_BIT_POS_PROBE_OUT72 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT72 of inst : label is "16'b0000000001100111"; - attribute LC_LOW_BIT_POS_PROBE_OUT73 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT73 of inst : label is "16'b0000000001101000"; - attribute LC_LOW_BIT_POS_PROBE_OUT74 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT74 of inst : label is "16'b0000000001101001"; - attribute LC_LOW_BIT_POS_PROBE_OUT75 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT75 of inst : label is "16'b0000000001101010"; - attribute LC_LOW_BIT_POS_PROBE_OUT76 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT76 of inst : label is "16'b0000000001101011"; - attribute LC_LOW_BIT_POS_PROBE_OUT77 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT77 of inst : label is "16'b0000000001101100"; - attribute LC_LOW_BIT_POS_PROBE_OUT78 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT78 of inst : label is "16'b0000000001101101"; - attribute LC_LOW_BIT_POS_PROBE_OUT79 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT79 of inst : label is "16'b0000000001101110"; - attribute LC_LOW_BIT_POS_PROBE_OUT8 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT8 of inst : label is "16'b0000000000100111"; - attribute LC_LOW_BIT_POS_PROBE_OUT80 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT80 of inst : label is "16'b0000000001101111"; - attribute LC_LOW_BIT_POS_PROBE_OUT81 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT81 of inst : label is "16'b0000000001110000"; - attribute LC_LOW_BIT_POS_PROBE_OUT82 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT82 of inst : label is "16'b0000000001110001"; - attribute LC_LOW_BIT_POS_PROBE_OUT83 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT83 of inst : label is "16'b0000000001110010"; - attribute LC_LOW_BIT_POS_PROBE_OUT84 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT84 of inst : label is "16'b0000000001110011"; - attribute LC_LOW_BIT_POS_PROBE_OUT85 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT85 of inst : label is "16'b0000000001110100"; - attribute LC_LOW_BIT_POS_PROBE_OUT86 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT86 of inst : label is "16'b0000000001110101"; - attribute LC_LOW_BIT_POS_PROBE_OUT87 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT87 of inst : label is "16'b0000000001110110"; - attribute LC_LOW_BIT_POS_PROBE_OUT88 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT88 of inst : label is "16'b0000000001110111"; - attribute LC_LOW_BIT_POS_PROBE_OUT89 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT89 of inst : label is "16'b0000000001111000"; - attribute LC_LOW_BIT_POS_PROBE_OUT9 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT9 of inst : label is "16'b0000000000101000"; - attribute LC_LOW_BIT_POS_PROBE_OUT90 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT90 of inst : label is "16'b0000000001111001"; - attribute LC_LOW_BIT_POS_PROBE_OUT91 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT91 of inst : label is "16'b0000000001111010"; - attribute LC_LOW_BIT_POS_PROBE_OUT92 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT92 of inst : label is "16'b0000000001111011"; - attribute LC_LOW_BIT_POS_PROBE_OUT93 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT93 of inst : label is "16'b0000000001111100"; - attribute LC_LOW_BIT_POS_PROBE_OUT94 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT94 of inst : label is "16'b0000000001111101"; - attribute LC_LOW_BIT_POS_PROBE_OUT95 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT95 of inst : label is "16'b0000000001111110"; - attribute LC_LOW_BIT_POS_PROBE_OUT96 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT96 of inst : label is "16'b0000000001111111"; - attribute LC_LOW_BIT_POS_PROBE_OUT97 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT97 of inst : label is "16'b0000000010000000"; - attribute LC_LOW_BIT_POS_PROBE_OUT98 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT98 of inst : label is "16'b0000000010000001"; - attribute LC_LOW_BIT_POS_PROBE_OUT99 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT99 of inst : label is "16'b0000000010000010"; - attribute LC_PROBE_IN_WIDTH_STRING : string; - attribute LC_PROBE_IN_WIDTH_STRING of inst : label is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111100011111"; - attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING : string; - attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING of inst : label is "4096'b0000000100011110000000010001110100000001000111000000000100011011000000010001101000000001000110010000000100011000000000010001011100000001000101100000000100010101000000010001010000000001000100110000000100010010000000010001000100000001000100000000000100001111000000010000111000000001000011010000000100001100000000010000101100000001000010100000000100001001000000010000100000000001000001110000000100000110000000010000010100000001000001000000000100000011000000010000001000000001000000010000000100000000000000001111111100000000111111100000000011111101000000001111110000000000111110110000000011111010000000001111100100000000111110000000000011110111000000001111011000000000111101010000000011110100000000001111001100000000111100100000000011110001000000001111000000000000111011110000000011101110000000001110110100000000111011000000000011101011000000001110101000000000111010010000000011101000000000001110011100000000111001100000000011100101000000001110010000000000111000110000000011100010000000001110000100000000111000000000000011011111000000001101111000000000110111010000000011011100000000001101101100000000110110100000000011011001000000001101100000000000110101110000000011010110000000001101010100000000110101000000000011010011000000001101001000000000110100010000000011010000000000001100111100000000110011100000000011001101000000001100110000000000110010110000000011001010000000001100100100000000110010000000000011000111000000001100011000000000110001010000000011000100000000001100001100000000110000100000000011000001000000001100000000000000101111110000000010111110000000001011110100000000101111000000000010111011000000001011101000000000101110010000000010111000000000001011011100000000101101100000000010110101000000001011010000000000101100110000000010110010000000001011000100000000101100000000000010101111000000001010111000000000101011010000000010101100000000001010101100000000101010100000000010101001000000001010100000000000101001110000000010100110000000001010010100000000101001000000000010100011000000001010001000000000101000010000000010100000000000001001111100000000100111100000000010011101000000001001110000000000100110110000000010011010000000001001100100000000100110000000000010010111000000001001011000000000100101010000000010010100000000001001001100000000100100100000000010010001000000001001000000000000100011110000000010001110000000001000110100000000100011000000000010001011000000001000101000000000100010010000000010001000000000001000011100000000100001100000000010000101000000001000010000000000100000110000000010000010000000001000000100000000100000000000000001111111000000000111111000000000011111010000000001111100000000000111101100000000011110100000000001111001000000000111100000000000011101110000000001110110000000000111010100000000011101000000000001110011000000000111001000000000011100010000000001110000000000000110111100000000011011100000000001101101000000000110110000000000011010110000000001101010000000000110100100000000011010000000000001100111000000000110011000000000011001010000000001100100000000000110001100000000011000100000000001100001000000000110000000000000010111110000000001011110000000000101110100000000010111000000000001011011000000000101101000000000010110010000000001011000000000000101011100000000010101100000000001010101000000000101010000000000010100110000000001010010000000000101000100000000010100000000000001001111000000000100111000000000010011010000000001001100000000000100101100000000010010100000000001001001000000000100100000000000010001110000000001000110000000000100010100000000010001000000000001000011000000000100001000000000010000010000000001000000000000000011111100000000001111100000000000111101000000000011110000000000001110110000000000111010000000000011100100000000001110000000000000110111000000000011011000000000001101010000000000110100000000000011001100000000001100100000000000110001000000000011000000000000001011110000000000101110000000000010110100000000001011000000000000101011000000000010101000000000001010010000000000101000000000000010011100000000001001100000000000100101000000000010010000000000001000110000000000100010000000000010000100000000001000000000000000011111"; - attribute LC_PROBE_OUT_INIT_VAL_STRING : string; - attribute LC_PROBE_OUT_INIT_VAL_STRING of inst : label is "287'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute LC_PROBE_OUT_LOW_BIT_POS_STRING : string; - attribute LC_PROBE_OUT_LOW_BIT_POS_STRING of inst : label is "4096'b0000000100011110000000010001110100000001000111000000000100011011000000010001101000000001000110010000000100011000000000010001011100000001000101100000000100010101000000010001010000000001000100110000000100010010000000010001000100000001000100000000000100001111000000010000111000000001000011010000000100001100000000010000101100000001000010100000000100001001000000010000100000000001000001110000000100000110000000010000010100000001000001000000000100000011000000010000001000000001000000010000000100000000000000001111111100000000111111100000000011111101000000001111110000000000111110110000000011111010000000001111100100000000111110000000000011110111000000001111011000000000111101010000000011110100000000001111001100000000111100100000000011110001000000001111000000000000111011110000000011101110000000001110110100000000111011000000000011101011000000001110101000000000111010010000000011101000000000001110011100000000111001100000000011100101000000001110010000000000111000110000000011100010000000001110000100000000111000000000000011011111000000001101111000000000110111010000000011011100000000001101101100000000110110100000000011011001000000001101100000000000110101110000000011010110000000001101010100000000110101000000000011010011000000001101001000000000110100010000000011010000000000001100111100000000110011100000000011001101000000001100110000000000110010110000000011001010000000001100100100000000110010000000000011000111000000001100011000000000110001010000000011000100000000001100001100000000110000100000000011000001000000001100000000000000101111110000000010111110000000001011110100000000101111000000000010111011000000001011101000000000101110010000000010111000000000001011011100000000101101100000000010110101000000001011010000000000101100110000000010110010000000001011000100000000101100000000000010101111000000001010111000000000101011010000000010101100000000001010101100000000101010100000000010101001000000001010100000000000101001110000000010100110000000001010010100000000101001000000000010100011000000001010001000000000101000010000000010100000000000001001111100000000100111100000000010011101000000001001110000000000100110110000000010011010000000001001100100000000100110000000000010010111000000001001011000000000100101010000000010010100000000001001001100000000100100100000000010010001000000001001000000000000100011110000000010001110000000001000110100000000100011000000000010001011000000001000101000000000100010010000000010001000000000001000011100000000100001100000000010000101000000001000010000000000100000110000000010000010000000001000000100000000100000000000000001111111000000000111111000000000011111010000000001111100000000000111101100000000011110100000000001111001000000000111100000000000011101110000000001110110000000000111010100000000011101000000000001110011000000000111001000000000011100010000000001110000000000000110111100000000011011100000000001101101000000000110110000000000011010110000000001101010000000000110100100000000011010000000000001100111000000000110011000000000011001010000000001100100000000000110001100000000011000100000000001100001000000000110000000000000010111110000000001011110000000000101110100000000010111000000000001011011000000000101101000000000010110010000000001011000000000000101011100000000010101100000000001010101000000000101010000000000010100110000000001010010000000000101000100000000010100000000000001001111000000000100111000000000010011010000000001001100000000000100101100000000010010100000000001001001000000000100100000000000010001110000000001000110000000000100010100000000010001000000000001000011000000000100001000000000010000010000000001000000000000000011111100000000001111100000000000111101000000000011110000000000001110110000000000111010000000000011100100000000001110000000000000110111000000000011011000000000001101010000000000110100000000000011001100000000001100100000000000110001000000000011000000000000001011110000000000101110000000000010110100000000001011000000000000101011000000000010101000000000001010010000000000101000000000000010011100000000001001100000000000100101000000000010010000000000001000110000000000100010000000000010000100000000001000000000000000000000"; - attribute LC_PROBE_OUT_WIDTH_STRING : string; - attribute LC_PROBE_OUT_WIDTH_STRING of inst : label is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111"; - attribute LC_TOTAL_PROBE_IN_WIDTH : integer; - attribute LC_TOTAL_PROBE_IN_WIDTH of inst : label is 64; - attribute LC_TOTAL_PROBE_OUT_WIDTH : integer; - attribute LC_TOTAL_PROBE_OUT_WIDTH of inst : label is 32; - attribute syn_noprune : string; - attribute syn_noprune of inst : label is "1"; -begin -inst: entity work.vio_0_vio_v3_0_19_vio - port map ( - clk => clk, - probe_in0(31 downto 0) => probe_in0(31 downto 0), - probe_in1(31 downto 0) => probe_in1(31 downto 0), - probe_in10(0) => '0', - probe_in100(0) => '0', - probe_in101(0) => '0', - probe_in102(0) => '0', - probe_in103(0) => '0', - probe_in104(0) => '0', - probe_in105(0) => '0', - probe_in106(0) => '0', - probe_in107(0) => '0', - probe_in108(0) => '0', - probe_in109(0) => '0', - probe_in11(0) => '0', - probe_in110(0) => '0', - probe_in111(0) => '0', - probe_in112(0) => '0', - probe_in113(0) => '0', - probe_in114(0) => '0', - probe_in115(0) => '0', - probe_in116(0) => '0', - probe_in117(0) => '0', - probe_in118(0) => '0', - probe_in119(0) => '0', - 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probe_out104(0) => NLW_inst_probe_out104_UNCONNECTED(0), - probe_out105(0) => NLW_inst_probe_out105_UNCONNECTED(0), - probe_out106(0) => NLW_inst_probe_out106_UNCONNECTED(0), - probe_out107(0) => NLW_inst_probe_out107_UNCONNECTED(0), - probe_out108(0) => NLW_inst_probe_out108_UNCONNECTED(0), - probe_out109(0) => NLW_inst_probe_out109_UNCONNECTED(0), - probe_out11(0) => NLW_inst_probe_out11_UNCONNECTED(0), - probe_out110(0) => NLW_inst_probe_out110_UNCONNECTED(0), - probe_out111(0) => NLW_inst_probe_out111_UNCONNECTED(0), - probe_out112(0) => NLW_inst_probe_out112_UNCONNECTED(0), - probe_out113(0) => NLW_inst_probe_out113_UNCONNECTED(0), - probe_out114(0) => NLW_inst_probe_out114_UNCONNECTED(0), - probe_out115(0) => NLW_inst_probe_out115_UNCONNECTED(0), - probe_out116(0) => NLW_inst_probe_out116_UNCONNECTED(0), - probe_out117(0) => NLW_inst_probe_out117_UNCONNECTED(0), - probe_out118(0) => NLW_inst_probe_out118_UNCONNECTED(0), - probe_out119(0) => NLW_inst_probe_out119_UNCONNECTED(0), - probe_out12(0) => NLW_inst_probe_out12_UNCONNECTED(0), - probe_out120(0) => NLW_inst_probe_out120_UNCONNECTED(0), - probe_out121(0) => NLW_inst_probe_out121_UNCONNECTED(0), - probe_out122(0) => NLW_inst_probe_out122_UNCONNECTED(0), - probe_out123(0) => NLW_inst_probe_out123_UNCONNECTED(0), - probe_out124(0) => NLW_inst_probe_out124_UNCONNECTED(0), - probe_out125(0) => NLW_inst_probe_out125_UNCONNECTED(0), - probe_out126(0) => NLW_inst_probe_out126_UNCONNECTED(0), - probe_out127(0) => NLW_inst_probe_out127_UNCONNECTED(0), - probe_out128(0) => NLW_inst_probe_out128_UNCONNECTED(0), - probe_out129(0) => NLW_inst_probe_out129_UNCONNECTED(0), - probe_out13(0) => NLW_inst_probe_out13_UNCONNECTED(0), - probe_out130(0) => NLW_inst_probe_out130_UNCONNECTED(0), - probe_out131(0) => NLW_inst_probe_out131_UNCONNECTED(0), - probe_out132(0) => NLW_inst_probe_out132_UNCONNECTED(0), - probe_out133(0) => NLW_inst_probe_out133_UNCONNECTED(0), - probe_out134(0) => NLW_inst_probe_out134_UNCONNECTED(0), - probe_out135(0) => NLW_inst_probe_out135_UNCONNECTED(0), - probe_out136(0) => NLW_inst_probe_out136_UNCONNECTED(0), - probe_out137(0) => NLW_inst_probe_out137_UNCONNECTED(0), - probe_out138(0) => NLW_inst_probe_out138_UNCONNECTED(0), - probe_out139(0) => NLW_inst_probe_out139_UNCONNECTED(0), - probe_out14(0) => NLW_inst_probe_out14_UNCONNECTED(0), - probe_out140(0) => NLW_inst_probe_out140_UNCONNECTED(0), - probe_out141(0) => NLW_inst_probe_out141_UNCONNECTED(0), - probe_out142(0) => NLW_inst_probe_out142_UNCONNECTED(0), - probe_out143(0) => NLW_inst_probe_out143_UNCONNECTED(0), - probe_out144(0) => NLW_inst_probe_out144_UNCONNECTED(0), - probe_out145(0) => NLW_inst_probe_out145_UNCONNECTED(0), - probe_out146(0) => NLW_inst_probe_out146_UNCONNECTED(0), - probe_out147(0) => NLW_inst_probe_out147_UNCONNECTED(0), - probe_out148(0) => NLW_inst_probe_out148_UNCONNECTED(0), - probe_out149(0) => NLW_inst_probe_out149_UNCONNECTED(0), - probe_out15(0) => NLW_inst_probe_out15_UNCONNECTED(0), - probe_out150(0) => NLW_inst_probe_out150_UNCONNECTED(0), - probe_out151(0) => NLW_inst_probe_out151_UNCONNECTED(0), - probe_out152(0) => NLW_inst_probe_out152_UNCONNECTED(0), - probe_out153(0) => NLW_inst_probe_out153_UNCONNECTED(0), - probe_out154(0) => NLW_inst_probe_out154_UNCONNECTED(0), - probe_out155(0) => NLW_inst_probe_out155_UNCONNECTED(0), - probe_out156(0) => NLW_inst_probe_out156_UNCONNECTED(0), - probe_out157(0) => NLW_inst_probe_out157_UNCONNECTED(0), - probe_out158(0) => NLW_inst_probe_out158_UNCONNECTED(0), - probe_out159(0) => NLW_inst_probe_out159_UNCONNECTED(0), - probe_out16(0) => NLW_inst_probe_out16_UNCONNECTED(0), - probe_out160(0) => NLW_inst_probe_out160_UNCONNECTED(0), - probe_out161(0) => NLW_inst_probe_out161_UNCONNECTED(0), - probe_out162(0) => NLW_inst_probe_out162_UNCONNECTED(0), - probe_out163(0) => NLW_inst_probe_out163_UNCONNECTED(0), - probe_out164(0) => NLW_inst_probe_out164_UNCONNECTED(0), - probe_out165(0) => NLW_inst_probe_out165_UNCONNECTED(0), - probe_out166(0) => NLW_inst_probe_out166_UNCONNECTED(0), - probe_out167(0) => NLW_inst_probe_out167_UNCONNECTED(0), - probe_out168(0) => NLW_inst_probe_out168_UNCONNECTED(0), - probe_out169(0) => NLW_inst_probe_out169_UNCONNECTED(0), - probe_out17(0) => NLW_inst_probe_out17_UNCONNECTED(0), - probe_out170(0) => NLW_inst_probe_out170_UNCONNECTED(0), - probe_out171(0) => NLW_inst_probe_out171_UNCONNECTED(0), - probe_out172(0) => NLW_inst_probe_out172_UNCONNECTED(0), - probe_out173(0) => NLW_inst_probe_out173_UNCONNECTED(0), - probe_out174(0) => NLW_inst_probe_out174_UNCONNECTED(0), - probe_out175(0) => NLW_inst_probe_out175_UNCONNECTED(0), - probe_out176(0) => NLW_inst_probe_out176_UNCONNECTED(0), - probe_out177(0) => NLW_inst_probe_out177_UNCONNECTED(0), - probe_out178(0) => NLW_inst_probe_out178_UNCONNECTED(0), - probe_out179(0) => NLW_inst_probe_out179_UNCONNECTED(0), - probe_out18(0) => NLW_inst_probe_out18_UNCONNECTED(0), - probe_out180(0) => NLW_inst_probe_out180_UNCONNECTED(0), - probe_out181(0) => NLW_inst_probe_out181_UNCONNECTED(0), - probe_out182(0) => NLW_inst_probe_out182_UNCONNECTED(0), - probe_out183(0) => NLW_inst_probe_out183_UNCONNECTED(0), - probe_out184(0) => NLW_inst_probe_out184_UNCONNECTED(0), - probe_out185(0) => NLW_inst_probe_out185_UNCONNECTED(0), - probe_out186(0) => NLW_inst_probe_out186_UNCONNECTED(0), - probe_out187(0) => NLW_inst_probe_out187_UNCONNECTED(0), - probe_out188(0) => NLW_inst_probe_out188_UNCONNECTED(0), - probe_out189(0) => NLW_inst_probe_out189_UNCONNECTED(0), - probe_out19(0) => NLW_inst_probe_out19_UNCONNECTED(0), - probe_out190(0) => NLW_inst_probe_out190_UNCONNECTED(0), - probe_out191(0) => NLW_inst_probe_out191_UNCONNECTED(0), - probe_out192(0) => NLW_inst_probe_out192_UNCONNECTED(0), - probe_out193(0) => NLW_inst_probe_out193_UNCONNECTED(0), - probe_out194(0) => NLW_inst_probe_out194_UNCONNECTED(0), - probe_out195(0) => NLW_inst_probe_out195_UNCONNECTED(0), - probe_out196(0) => NLW_inst_probe_out196_UNCONNECTED(0), - probe_out197(0) => NLW_inst_probe_out197_UNCONNECTED(0), - probe_out198(0) => NLW_inst_probe_out198_UNCONNECTED(0), - probe_out199(0) => NLW_inst_probe_out199_UNCONNECTED(0), - probe_out2(0) => NLW_inst_probe_out2_UNCONNECTED(0), - probe_out20(0) => NLW_inst_probe_out20_UNCONNECTED(0), - probe_out200(0) => NLW_inst_probe_out200_UNCONNECTED(0), - probe_out201(0) => NLW_inst_probe_out201_UNCONNECTED(0), - probe_out202(0) => NLW_inst_probe_out202_UNCONNECTED(0), - probe_out203(0) => NLW_inst_probe_out203_UNCONNECTED(0), - probe_out204(0) => NLW_inst_probe_out204_UNCONNECTED(0), - probe_out205(0) => NLW_inst_probe_out205_UNCONNECTED(0), - probe_out206(0) => NLW_inst_probe_out206_UNCONNECTED(0), - probe_out207(0) => NLW_inst_probe_out207_UNCONNECTED(0), - probe_out208(0) => NLW_inst_probe_out208_UNCONNECTED(0), - probe_out209(0) => NLW_inst_probe_out209_UNCONNECTED(0), - probe_out21(0) => NLW_inst_probe_out21_UNCONNECTED(0), - probe_out210(0) => NLW_inst_probe_out210_UNCONNECTED(0), - probe_out211(0) => NLW_inst_probe_out211_UNCONNECTED(0), - probe_out212(0) => NLW_inst_probe_out212_UNCONNECTED(0), - probe_out213(0) => NLW_inst_probe_out213_UNCONNECTED(0), - probe_out214(0) => NLW_inst_probe_out214_UNCONNECTED(0), - probe_out215(0) => NLW_inst_probe_out215_UNCONNECTED(0), - probe_out216(0) => NLW_inst_probe_out216_UNCONNECTED(0), - probe_out217(0) => NLW_inst_probe_out217_UNCONNECTED(0), - probe_out218(0) => NLW_inst_probe_out218_UNCONNECTED(0), - probe_out219(0) => NLW_inst_probe_out219_UNCONNECTED(0), - probe_out22(0) => NLW_inst_probe_out22_UNCONNECTED(0), - probe_out220(0) => NLW_inst_probe_out220_UNCONNECTED(0), - probe_out221(0) => NLW_inst_probe_out221_UNCONNECTED(0), - probe_out222(0) => NLW_inst_probe_out222_UNCONNECTED(0), - probe_out223(0) => NLW_inst_probe_out223_UNCONNECTED(0), - probe_out224(0) => NLW_inst_probe_out224_UNCONNECTED(0), - probe_out225(0) => NLW_inst_probe_out225_UNCONNECTED(0), - probe_out226(0) => NLW_inst_probe_out226_UNCONNECTED(0), - probe_out227(0) => NLW_inst_probe_out227_UNCONNECTED(0), - probe_out228(0) => NLW_inst_probe_out228_UNCONNECTED(0), - probe_out229(0) => NLW_inst_probe_out229_UNCONNECTED(0), - probe_out23(0) => NLW_inst_probe_out23_UNCONNECTED(0), - probe_out230(0) => NLW_inst_probe_out230_UNCONNECTED(0), - probe_out231(0) => NLW_inst_probe_out231_UNCONNECTED(0), - probe_out232(0) => NLW_inst_probe_out232_UNCONNECTED(0), - probe_out233(0) => NLW_inst_probe_out233_UNCONNECTED(0), - probe_out234(0) => NLW_inst_probe_out234_UNCONNECTED(0), - probe_out235(0) => NLW_inst_probe_out235_UNCONNECTED(0), - probe_out236(0) => NLW_inst_probe_out236_UNCONNECTED(0), - probe_out237(0) => NLW_inst_probe_out237_UNCONNECTED(0), - probe_out238(0) => NLW_inst_probe_out238_UNCONNECTED(0), - probe_out239(0) => NLW_inst_probe_out239_UNCONNECTED(0), - probe_out24(0) => NLW_inst_probe_out24_UNCONNECTED(0), - probe_out240(0) => NLW_inst_probe_out240_UNCONNECTED(0), - probe_out241(0) => NLW_inst_probe_out241_UNCONNECTED(0), - probe_out242(0) => NLW_inst_probe_out242_UNCONNECTED(0), - probe_out243(0) => NLW_inst_probe_out243_UNCONNECTED(0), - probe_out244(0) => NLW_inst_probe_out244_UNCONNECTED(0), - probe_out245(0) => NLW_inst_probe_out245_UNCONNECTED(0), - probe_out246(0) => NLW_inst_probe_out246_UNCONNECTED(0), - probe_out247(0) => NLW_inst_probe_out247_UNCONNECTED(0), - probe_out248(0) => NLW_inst_probe_out248_UNCONNECTED(0), - probe_out249(0) => NLW_inst_probe_out249_UNCONNECTED(0), - probe_out25(0) => NLW_inst_probe_out25_UNCONNECTED(0), - probe_out250(0) => NLW_inst_probe_out250_UNCONNECTED(0), - probe_out251(0) => NLW_inst_probe_out251_UNCONNECTED(0), - probe_out252(0) => NLW_inst_probe_out252_UNCONNECTED(0), - probe_out253(0) => NLW_inst_probe_out253_UNCONNECTED(0), - probe_out254(0) => NLW_inst_probe_out254_UNCONNECTED(0), - probe_out255(0) => NLW_inst_probe_out255_UNCONNECTED(0), - probe_out26(0) => NLW_inst_probe_out26_UNCONNECTED(0), - probe_out27(0) => NLW_inst_probe_out27_UNCONNECTED(0), - probe_out28(0) => NLW_inst_probe_out28_UNCONNECTED(0), - probe_out29(0) => NLW_inst_probe_out29_UNCONNECTED(0), - probe_out3(0) => NLW_inst_probe_out3_UNCONNECTED(0), - probe_out30(0) => NLW_inst_probe_out30_UNCONNECTED(0), - probe_out31(0) => NLW_inst_probe_out31_UNCONNECTED(0), - probe_out32(0) => NLW_inst_probe_out32_UNCONNECTED(0), - probe_out33(0) => NLW_inst_probe_out33_UNCONNECTED(0), - probe_out34(0) => NLW_inst_probe_out34_UNCONNECTED(0), - probe_out35(0) => NLW_inst_probe_out35_UNCONNECTED(0), - probe_out36(0) => NLW_inst_probe_out36_UNCONNECTED(0), - probe_out37(0) => NLW_inst_probe_out37_UNCONNECTED(0), - probe_out38(0) => NLW_inst_probe_out38_UNCONNECTED(0), - probe_out39(0) => NLW_inst_probe_out39_UNCONNECTED(0), - probe_out4(0) => NLW_inst_probe_out4_UNCONNECTED(0), - probe_out40(0) => NLW_inst_probe_out40_UNCONNECTED(0), - probe_out41(0) => NLW_inst_probe_out41_UNCONNECTED(0), - probe_out42(0) => NLW_inst_probe_out42_UNCONNECTED(0), - probe_out43(0) => NLW_inst_probe_out43_UNCONNECTED(0), - probe_out44(0) => NLW_inst_probe_out44_UNCONNECTED(0), - probe_out45(0) => NLW_inst_probe_out45_UNCONNECTED(0), - probe_out46(0) => NLW_inst_probe_out46_UNCONNECTED(0), - probe_out47(0) => NLW_inst_probe_out47_UNCONNECTED(0), - probe_out48(0) => NLW_inst_probe_out48_UNCONNECTED(0), - probe_out49(0) => NLW_inst_probe_out49_UNCONNECTED(0), - probe_out5(0) => NLW_inst_probe_out5_UNCONNECTED(0), - probe_out50(0) => NLW_inst_probe_out50_UNCONNECTED(0), - probe_out51(0) => NLW_inst_probe_out51_UNCONNECTED(0), - probe_out52(0) => NLW_inst_probe_out52_UNCONNECTED(0), - probe_out53(0) => NLW_inst_probe_out53_UNCONNECTED(0), - probe_out54(0) => NLW_inst_probe_out54_UNCONNECTED(0), - probe_out55(0) => NLW_inst_probe_out55_UNCONNECTED(0), - probe_out56(0) => NLW_inst_probe_out56_UNCONNECTED(0), - probe_out57(0) => NLW_inst_probe_out57_UNCONNECTED(0), - probe_out58(0) => NLW_inst_probe_out58_UNCONNECTED(0), - probe_out59(0) => NLW_inst_probe_out59_UNCONNECTED(0), - probe_out6(0) => NLW_inst_probe_out6_UNCONNECTED(0), - probe_out60(0) => NLW_inst_probe_out60_UNCONNECTED(0), - probe_out61(0) => NLW_inst_probe_out61_UNCONNECTED(0), - probe_out62(0) => NLW_inst_probe_out62_UNCONNECTED(0), - probe_out63(0) => NLW_inst_probe_out63_UNCONNECTED(0), - probe_out64(0) => NLW_inst_probe_out64_UNCONNECTED(0), - probe_out65(0) => NLW_inst_probe_out65_UNCONNECTED(0), - probe_out66(0) => NLW_inst_probe_out66_UNCONNECTED(0), - probe_out67(0) => NLW_inst_probe_out67_UNCONNECTED(0), - probe_out68(0) => NLW_inst_probe_out68_UNCONNECTED(0), - probe_out69(0) => NLW_inst_probe_out69_UNCONNECTED(0), - probe_out7(0) => NLW_inst_probe_out7_UNCONNECTED(0), - probe_out70(0) => NLW_inst_probe_out70_UNCONNECTED(0), - probe_out71(0) => NLW_inst_probe_out71_UNCONNECTED(0), - probe_out72(0) => NLW_inst_probe_out72_UNCONNECTED(0), - probe_out73(0) => NLW_inst_probe_out73_UNCONNECTED(0), - probe_out74(0) => NLW_inst_probe_out74_UNCONNECTED(0), - probe_out75(0) => NLW_inst_probe_out75_UNCONNECTED(0), - probe_out76(0) => NLW_inst_probe_out76_UNCONNECTED(0), - probe_out77(0) => NLW_inst_probe_out77_UNCONNECTED(0), - probe_out78(0) => NLW_inst_probe_out78_UNCONNECTED(0), - probe_out79(0) => NLW_inst_probe_out79_UNCONNECTED(0), - probe_out8(0) => NLW_inst_probe_out8_UNCONNECTED(0), - probe_out80(0) => NLW_inst_probe_out80_UNCONNECTED(0), - probe_out81(0) => NLW_inst_probe_out81_UNCONNECTED(0), - probe_out82(0) => NLW_inst_probe_out82_UNCONNECTED(0), - probe_out83(0) => NLW_inst_probe_out83_UNCONNECTED(0), - probe_out84(0) => NLW_inst_probe_out84_UNCONNECTED(0), - probe_out85(0) => NLW_inst_probe_out85_UNCONNECTED(0), - probe_out86(0) => NLW_inst_probe_out86_UNCONNECTED(0), - probe_out87(0) => NLW_inst_probe_out87_UNCONNECTED(0), - probe_out88(0) => NLW_inst_probe_out88_UNCONNECTED(0), - probe_out89(0) => NLW_inst_probe_out89_UNCONNECTED(0), - probe_out9(0) => NLW_inst_probe_out9_UNCONNECTED(0), - probe_out90(0) => NLW_inst_probe_out90_UNCONNECTED(0), - probe_out91(0) => NLW_inst_probe_out91_UNCONNECTED(0), - probe_out92(0) => NLW_inst_probe_out92_UNCONNECTED(0), - probe_out93(0) => NLW_inst_probe_out93_UNCONNECTED(0), - probe_out94(0) => NLW_inst_probe_out94_UNCONNECTED(0), - probe_out95(0) => NLW_inst_probe_out95_UNCONNECTED(0), - probe_out96(0) => NLW_inst_probe_out96_UNCONNECTED(0), - probe_out97(0) => NLW_inst_probe_out97_UNCONNECTED(0), - probe_out98(0) => NLW_inst_probe_out98_UNCONNECTED(0), - probe_out99(0) => NLW_inst_probe_out99_UNCONNECTED(0), - sl_iport0(36 downto 0) => B"0000000000000000000000000000000000000", - sl_oport0(16 downto 0) => NLW_inst_sl_oport0_UNCONNECTED(16 downto 0) - ); -end STRUCTURE; diff --git a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/vio_0_stub.v b/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/vio_0_stub.v deleted file mode 100755 index edae579..0000000 --- a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/vio_0_stub.v +++ /dev/null @@ -1,23 +0,0 @@ -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.2 (win64) Build 2700185 Thu Oct 24 18:46:05 MDT 2019 -// Date : Fri Apr 1 15:55:35 2022 -// Host : PAVLOV running 64-bit Service Pack 1 (build 7601) -// Command : write_verilog -force -mode synth_stub -// J:/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/vio_0_stub.v -// Design : vio_0 -// Purpose : Stub declaration of top-level module interface -// Device : xc7z020clg400-1 -// -------------------------------------------------------------------------------- - -// This empty module with port declaration file causes synthesis tools to infer a black box for IP. -// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. -// Please paste the declaration into a Verilog source file or add the file as an additional source. -(* X_CORE_INFO = "vio,Vivado 2019.2" *) -module vio_0(clk, probe_in0, probe_in1, probe_out0) -/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[31:0],probe_in1[31:0],probe_out0[31:0]" */; - input clk; - input [31:0]probe_in0; - input [31:0]probe_in1; - output [31:0]probe_out0; -endmodule diff --git a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/vio_0_stub.vhdl b/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/vio_0_stub.vhdl deleted file mode 100755 index 93c3244..0000000 --- a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/vio_0_stub.vhdl +++ /dev/null @@ -1,33 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.2 (win64) Build 2700185 Thu Oct 24 18:46:05 MDT 2019 --- Date : Fri Apr 1 15:55:35 2022 --- Host : PAVLOV running 64-bit Service Pack 1 (build 7601) --- Command : write_vhdl -force -mode synth_stub --- J:/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/vio_0_stub.vhdl --- Design : vio_0 --- Purpose : Stub declaration of top-level module interface --- Device : xc7z020clg400-1 --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -entity vio_0 is - Port ( - clk : in STD_LOGIC; - probe_in0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); - probe_in1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); - probe_out0 : out STD_LOGIC_VECTOR ( 31 downto 0 ) - ); - -end vio_0; - -architecture stub of vio_0 is -attribute syn_black_box : boolean; -attribute black_box_pad_pin : string; -attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[31:0],probe_in1[31:0],probe_out0[31:0]"; -attribute X_CORE_INFO : string; -attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.2"; -begin -end; diff --git a/example_projects/vivado_test_prj_template_v3/.gitignore b/example_projects/vivado_test_prj_template_v3/.gitignore new file mode 100644 index 0000000..02ade49 --- /dev/null +++ b/example_projects/vivado_test_prj_template_v3/.gitignore @@ -0,0 +1,28 @@ +#------------------------------------------------------------------------------ +# .gitignore for Xilinx Vivado +# published as part of https://github.com/pConst/basic_verilog +# Konstantin Pavlov, pavlovconst@gmail.com +#------------------------------------------------------------------------------ + +# INFO ------------------------------------------------------------------------ +# rename the file to ".gitignore" and place into your Vivado project directory +# + + +*.cache +*.hw +*.gen +*.ip_user_files +*.runs +*.sim +.Xil + +.ioplanning +*.jou +*.log +*.str +*.tmp +usage_statistics_webtalk.* + +*.xsa + diff --git a/example_projects/vivado_test_prj_template_v3/clean_vivado.bat b/example_projects/vivado_test_prj_template_v3/clean_vivado.bat new file mode 100644 index 0000000..88fd00b --- /dev/null +++ b/example_projects/vivado_test_prj_template_v3/clean_vivado.bat @@ -0,0 +1,49 @@ +@echo off +rem ------------------------------------------------------------------------------ +rem clean_vivado.bat +rem published as part of https://github.com/pConst/basic_verilog +rem Konstantin Pavlov, pavlovconst@gmail.com +rem ------------------------------------------------------------------------------ + +rem Use this file as a boilerplate for your custom clean script +rem for Vivado/Vitis projects + + +for /R %%f in (*.xpr) do ( + echo "Project name is %%~nf" + + del /s /f /q .\.Xil\* + rmdir /s /q .\.Xil\ + + del /s /f /q .\%%~nf.cache\* + rmdir /s /q .\%%~nf.cache\ + + del /s /f /q .\%%~nf.gen\* + rmdir /s /q .\%%~nf.gen\ + + del /s /f /q .\%%~nf.hw\* + rmdir /s /q .\%%~nf.hw\ + + del /s /f /q .\%%~nf.ip_user_files\* + rmdir /s /q .\%%~nf.ip_user_files\ + + del /s /f /q .\%%~nf.runs\* + rmdir /s /q .\%%~nf.runs\ + + del /s /f /q .\%%~nf.sim\* + rmdir /s /q .\%%~nf.sim\ + + + del /s /f /q .\*.jou + del /s /f /q .\*.log + del /s /f /q .\*.str + del /s /f /q .\*.tmp + del /s /f /q .\usage_statistics_webtalk.* + + del /s /f /q *.xsa + +) + +pause +goto :eof + diff --git a/example_projects/vivado_test_prj_template_v2/src/clk_divider.sv b/example_projects/vivado_test_prj_template_v3/src/clk_divider.sv old mode 100755 new mode 100644 similarity index 100% rename from example_projects/vivado_test_prj_template_v2/src/clk_divider.sv rename to example_projects/vivado_test_prj_template_v3/src/clk_divider.sv diff --git a/example_projects/vivado_test_prj_template_v2/src/clogb2.svh b/example_projects/vivado_test_prj_template_v3/src/clogb2.svh old mode 100755 new mode 100644 similarity index 100% rename from example_projects/vivado_test_prj_template_v2/src/clogb2.svh rename to example_projects/vivado_test_prj_template_v3/src/clogb2.svh diff --git a/example_projects/vivado_test_prj_template_v2/src/define.svh b/example_projects/vivado_test_prj_template_v3/src/define.svh old mode 100755 new mode 100644 similarity index 100% rename from example_projects/vivado_test_prj_template_v2/src/define.svh rename to example_projects/vivado_test_prj_template_v3/src/define.svh diff --git a/example_projects/vivado_test_prj_template_v2/src/delay.sv b/example_projects/vivado_test_prj_template_v3/src/delay.sv old mode 100755 new mode 100644 similarity index 100% rename from example_projects/vivado_test_prj_template_v2/src/delay.sv rename to example_projects/vivado_test_prj_template_v3/src/delay.sv diff --git a/example_projects/vivado_test_prj_template_v2/src/edge_detect.sv b/example_projects/vivado_test_prj_template_v3/src/edge_detect.sv old mode 100755 new mode 100644 similarity index 100% rename from example_projects/vivado_test_prj_template_v2/src/edge_detect.sv rename to example_projects/vivado_test_prj_template_v3/src/edge_detect.sv diff --git a/example_projects/vivado_test_prj_template_v2/src/main.sv b/example_projects/vivado_test_prj_template_v3/src/main.sv old mode 100755 new mode 100644 similarity index 93% rename from example_projects/vivado_test_prj_template_v2/src/main.sv rename to example_projects/vivado_test_prj_template_v3/src/main.sv index af62b41..b26cab0 --- a/example_projects/vivado_test_prj_template_v2/src/main.sv +++ b/example_projects/vivado_test_prj_template_v3/src/main.sv @@ -5,7 +5,7 @@ //------------------------------------------------------------------------------ // INFO ------------------------------------------------------------------------ -// Vivado test project template, v2 +// Vivado test project template, v3 // Compatible with Digilent Arty-7020 board // // - use this as a boilerplate project for fast prototyping @@ -69,12 +69,12 @@ module main( input [5:0] ck_an_n, // Digital I/O On Outer Analog Header - output [5:0] ck_a, + inout [5:0] ck_a, // Digital I/O On Inner Analog Header // // Digital I/O Low - output [13:0] ck_io_low, + input [13:0] ck_io_low, // Digital I/O High output [41:26] ck_io_high, @@ -87,9 +87,16 @@ module main( output ck_ioa ); -`VIVADO_MODULE_HEADER +//`VIVADO_MODULE_HEADER +// convinience rename ========================================================== + logic [13:0] hdr_in; + assign hdr_in[13:0] = ck_io_low[13:0]; + + logic [15:0] hdr_out; + assign ck_io_high[41:26] = hdr_out[15:0]; + // clocks ====================================================================== logic sys_pll_locked; // asyn diff --git a/example_projects/vivado_test_prj_template_v2/src/physical.xdc b/example_projects/vivado_test_prj_template_v3/src/physical.xdc old mode 100755 new mode 100644 similarity index 100% rename from example_projects/vivado_test_prj_template_v2/src/physical.xdc rename to example_projects/vivado_test_prj_template_v3/src/physical.xdc diff --git a/example_projects/vivado_test_prj_template_v2/src/timing.xdc b/example_projects/vivado_test_prj_template_v3/src/timing.xdc old mode 100755 new mode 100644 similarity index 100% rename from example_projects/vivado_test_prj_template_v2/src/timing.xdc rename to example_projects/vivado_test_prj_template_v3/src/timing.xdc diff --git a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci b/example_projects/vivado_test_prj_template_v3/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci old mode 100755 new mode 100644 similarity index 86% rename from example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci rename to example_projects/vivado_test_prj_template_v3/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci index 359e054..d5f92e8 --- a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci +++ b/example_projects/vivado_test_prj_template_v3/test.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci @@ -18,37 +18,47 @@ false 100000000 + 100000000 + 0 0 - 0.000 + 0.0 + 100000000 + 0 0 - 0.000 + 0.0 + 100000000 + 0 0 - 0.000 + 0.0 1 LEVEL_HIGH + 100000000 + 0 0 - 0.000 + 0.0 0 0 + 100000000 + 0 0 - 0.000 + 0.0 1 0 0 @@ -72,7 +82,7 @@ 1 1 1 - 0.000 + 0.0 AXI4LITE READ_WRITE 0 @@ -204,11 +214,11 @@ 0000 1 0.25 - 1.25 - 1.25 - 1.25 - 1.25 - 1.25 + 0.125 + 0.125 + 0.125 + 0.125 + 0.125 dout drdy dwe @@ -290,6 +300,7 @@ 64.000 2.000 2 + 0 Output Output Phase Duty Cycle Pk-to-Pk Phase Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) clk_out1__125.00000______0.000______50.0______119.348_____96.948 @@ -567,6 +578,7 @@ 0.010 false 2 + false false false WAVEFORM @@ -665,12 +677,12 @@ TRUE TRUE IP_Flow - 4 + 9 TRUE - . + ../../../../test.gen/sources_1/ip/clk_wiz_0 . - 2019.2 + 2021.2 OUT_OF_CONTEXT @@ -712,6 +724,16 @@ + + + diff --git a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/vio_0.xci b/example_projects/vivado_test_prj_template_v3/test.srcs/sources_1/ip/vio_0/vio_0.xci old mode 100755 new mode 100644 similarity index 95% rename from example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/vio_0.xci rename to example_projects/vivado_test_prj_template_v3/test.srcs/sources_1/ip/vio_0/vio_0.xci index 9fb089f..5ee945c --- a/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/vio_0.xci +++ b/example_projects/vivado_test_prj_template_v3/test.srcs/sources_1/ip/vio_0/vio_0.xci @@ -10,11 +10,13 @@ + 100000000 + 0 0 - 0.000 + 0.0 1 2 1 @@ -279,7 +281,7 @@ 1 1 1 - 0x0 + 0x00000000 32 0x0 1 @@ -806,12 +808,12 @@ TRUE TRUE IP_Flow - 19 + 22 TRUE - . + ../../../../test.gen/sources_1/ip/vio_0 . - 2019.2 + 2021.2 OUT_OF_CONTEXT @@ -822,6 +824,11 @@ + + + diff --git a/example_projects/vivado_test_prj_template_v2/test.xpr b/example_projects/vivado_test_prj_template_v3/test.xpr old mode 100755 new mode 100644 similarity index 78% rename from example_projects/vivado_test_prj_template_v2/test.xpr rename to example_projects/vivado_test_prj_template_v3/test.xpr index ac930f2..437a4f5 --- a/example_projects/vivado_test_prj_template_v2/test.xpr +++ b/example_projects/vivado_test_prj_template_v3/test.xpr @@ -1,9 +1,9 @@ - + - + - + - + @@ -80,12 +107,14 @@ + + @@ -101,7 +130,7 @@ - + @@ -120,7 +149,7 @@ - + - + - - + + - - - - - + + - - - @@ -188,8 +217,8 @@