tests/extmod_hardware/machine_uart_irq_rxidle.py: Ignore inital IRQ.

dpgeorge · dpgeorge · commit a4a098ff8210 · 2025-07-08T13:18:09.000+10:00
On stm32, the hardware generates an RXIDLE IRQ after enabling the UART,
because the RX line is technically idle.

Signed-off-by: Damien George &lt;damien@micropython.org&gt;
diff --git a/tests/extmod_hardware/machine_uart_irq_rxidle.py b/tests/extmod_hardware/machine_uart_irq_rxidle.py
@@ -13,6 +13,9 @@
 
 import time, sys
 
+# Target tuning options.
+tune_wait_initial_rxidle = False
+
 # Configure pins based on the target.
 if "alif" in sys.platform:
     uart_id = 1
@@ -26,6 +29,7 @@
     uart_id = 1
     tx_pin = None
 elif "pyboard" in sys.platform:
+    tune_wait_initial_rxidle = True
     if "STM32WB" in sys.implementation._machine:
         # LPUART(1) is on PA2/PA3
         uart_id = "LP1"
@@ -69,8 +73,15 @@ def irq(u):
     else:
         uart = UART(uart_id, bits_per_s, tx=tx_pin, rx=rx_pin)
 
+    # Ignore a possible initial RXIDLE condition after creating UART.
+    if tune_wait_initial_rxidle:
+        uart.irq(lambda _: None, uart.IRQ_RXIDLE)
+        time.sleep_ms(10)
+
+    # Configure desired IRQ.
     uart.irq(irq, uart.IRQ_RXIDLE)
 
+    # Write data and wait for IRQ.
     print("write", bits_per_s)
     uart.write(text)
     uart.flush()
