diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml new file mode 100644 index 0000000..0aec6ca --- /dev/null +++ b/.github/workflows/main.yml @@ -0,0 +1,23 @@ +name: Testing the GitHub pages Publication + +on: + schedule: + - cron: '*/60 0 * * *' + push: + branch: + - master + +jobs: + jekyll: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v2 + - uses: actions/cache@v2 + with: + path: vendor/bundle + key: ${{ runner.os }}-gems-${{ hashFiles('**/Gemfile') }} + restore-keys: | + ${{ runner.os }}-gems- + - uses: helaili/jekyll-action@v2 + with: + token: ${{ secrets.JEKYLL_PAT }} diff --git a/NetFPGA-PLUS.html b/NetFPGA-PLUS.html index 0f4b88b..ec7f3dc 100644 --- a/NetFPGA-PLUS.html +++ b/NetFPGA-PLUS.html @@ -56,24 +56,91 @@

NetFPGA PLUS



- +
diff --git a/Publications.html b/Publications.html index b240284..b3e8ba2 100644 --- a/Publications.html +++ b/Publications.html @@ -3,12 +3,13 @@ ---

Publications featuring NetFPGA

-

A partial list of publications using the NetFPGA platform

-

the links for the addresses are, where possible, doi.org links

+

A partial list of publications using the NetFPGA platform.

+

The links for the addresses are, where possible, doi.org links.



{% include 2021-Publications.html %}
+
{% include 2020-Publications.html %}
diff --git a/_posts/ecosystem/example-ecosystem.md b/_posts/ecosystem/example-ecosystem.md index a480994..a5de604 100644 --- a/_posts/ecosystem/example-ecosystem.md +++ b/_posts/ecosystem/example-ecosystem.md @@ -23,29 +23,53 @@ target-platform1-5: PLUS --- title: The name for the product/Project/service + date: the date it was added to the site + posttype: used for the ecosystem cards to show up on the ecosystem page not the news and events page + type: whether it is a product/project/service + category: what kind of product/project/service it is + description: A description of the product/project/service + organisation: The name of the organisation + organisation-logo: the url to the organisation's logo + organisation-type: The type of organisation it is (Academic, Non-profit or Vendor) + product-repo: the link to the product/project/service's public repo + product-site: the link to the product/project/service's website + product-image: if provided an image of the product + primary-contact-name: The name provided from the submission form + primary-contact-email: The email provided from the submission form + secondary-contact-name: If provided from the submission form + secondary-contact-email: If provided from the submission form + seller: The name of the seller of the product + seller-url: The link to the seller's website, if provided + seller-email: The email of the seller, if provided + seller-phone: The phone number of the seller, if provided + target-platform1: the main NetFPGA platform the product is designed for/uses + target-platform2: The secondary NetFPGA platform the product is designed for/uses + target-platform3: The tertiary NetFPGA platform the product is designed for/uses + target-platform4: The quarternary NetFPGA platform the product is designed for/uses + target-platform5: The quinary NetFPGA platform the product is designed for/uses ***If adding new organisations, organisation types, product types, target platforms please make sure to check (adding-to-javascript.md)[/_posts/ecosystem/adding-to-javascript.md]*** diff --git a/_posts/news-and-events/2021-09-24-NetFPGA-PLUS-Release-1.0.md b/_posts/news-and-events/2021-09-24-NetFPGA-PLUS-Release-1.0.md new file mode 100644 index 0000000..41e998c --- /dev/null +++ b/_posts/news-and-events/2021-09-24-NetFPGA-PLUS-Release-1.0.md @@ -0,0 +1,41 @@ +--- +title: NetFPGA PLUS Release 1.0.0 +date: 2021-09-24 +eventdate: 2021-09-24 +eoldate: 2023-09-24 +category: news +posttype: news-and-events +--- + +It is with great excitement we announce the release of NetFPGA PLUS. + +NetFPGA PLUS 1.0.0 + +NetFPGA PLUS 1.0.0 has arrived, available in a public repository to all, links on the netfpga.org website. I’ve reprinted the outline, included as part of the original announcement, at the bottom of this newsletter. The overly optimistic timetable fell to the brutal realities of the last 9 months. + +NetFPGA PLUS has been is a momentous effort that largely has fallen to the broad shoulders of the increasingly slim NetFPGA team at Cambridge; one person in particular deserves much credit for this huge effort and for us achieving this first release. + +On behalf of us all, I thank Yuta Tokusashi who has lead the NetFPGA PLUS work throughout this effort and who has managed this despite the extraordinary challenges of the last 18 months. + +Many critical issues were managed and overcome with the expert guidance of Noa Zilberman, while release testing and preparation would not have been possible without the assistance of Salvator Galea. + +This entire effort was enabled by many members of the excellent Xilinx team from Gordon Brebner’s leadership and enthusiasm through to the phenomenal efforts of the Open-NIC team; notably Yan Zhang, and Chris Neely, as well as critical advice from Cathal McCabe, part of Xilinx in Dublin. + +My personal thanks and on behalf of the NetFPGA community to each of them. (I’m excruciatingly aware the moment I send this email I will realise I’ve not credited a critical member of the team - my apologies in advance.) + +I will leave some details to a future newsletter - in preparation - but promise it shortly, as soon as we have all caught up on our sleep. + +Do check out the new website, thanks to Adam Pettigrew for his efforts there; and of course do check out the public, openly available, Apache licensed, NetFPGA PLUS codebase too! + +Items planned for the next announcement will include + +1. License change for NetFPGA +2. NetFPGA PLUS plans +3. NetFPGA SUME status + + +Thank you all, +Andrew Moore +on behalf of the NetFPGA team. + + diff --git a/_posts/news-and-events/example-events-post.md b/_posts/news-and-events/example-events-post.md index 1d0819c..46f896a 100644 --- a/_posts/news-and-events/example-events-post.md +++ b/_posts/news-and-events/example-events-post.md @@ -14,14 +14,23 @@ titlelink: http://sites.ieee.org/netsoft/ For easy naming convention name the news files should be saved yyyy-mm-dd-title.md title: Title is the metadata tag that is used to give the name of the post on the website + date: Date is the metadata tag that is used by jekyll to know if it should post the post to the website or not + eventdate: Eventdate is the metadata tag that is used to give the date of the event on the website, this means that the date for the event and the date the event is posted to the website can be different + eoldate: the date for it be removed from the index page, default date is a year after posting + category: declares whether it shows up on the news and events when toggled as well as what content is shown. + posttype: declares the type of the post to where they will be seen on the website + location: Location is the metadata tag that is used to give the place that the event will take place at on the website + presenter: Presenter is the metadata tag that is used to give the person giving the event on the website + website: Website is the metadata tag that is used to give the link of the website to find out more information about the event + titlelink: TitleLink is the link to the organisation that is organising the event The only metadata tags that are required for an event are title, date and category all other ones present are found using if tags in the events page. diff --git a/_posts/news-and-events/example-news-post.md b/_posts/news-and-events/example-news-post.md index b403419..6fcd4be 100644 --- a/_posts/news-and-events/example-news-post.md +++ b/_posts/news-and-events/example-news-post.md @@ -10,8 +10,13 @@ posttype: news-and-events For easy naming convention name the news files should be saved yyyy-mm-dd-title.md title: Title is the metadata tag that is used to give the title of the post on the website + date: Date is the metadata tag used by jekyll to know when a post should be posted to the website + eventdate: eventdate is the metadata tag that is used to give a date of the post on the website + eoldate: eoldate is the "end of life" date, which is when the news post is removed from the frontpage + category: declares whether it shows up on the events page or on the news page + posttype: declares the type of the post to where they will be seen on the website diff --git a/_site/index.html b/_site/index.html new file mode 100644 index 0000000..d2ba198 --- /dev/null +++ b/_site/index.html @@ -0,0 +1,208 @@ + + + + + + + + + NetFPGA + + + + + + + + + + + + + +
+
+
+
+

NetFPGA

+
+
+
+
+ + +
+
+
+

The NetFPGA is:

+
+

A line-rate, flexible, and open platform for research, and classroom experimentation. More than 3,500 NetFPGA systems have been deployed at over 300 institutions in over 60 countries around the world.

+
+
+ + +
+ + + + + +
+ +
+
+
+ NetFPGA PLUS +
+

NetFPGA PLUS

+
+ +
+
+
+
+ NetFPGA SUME board +
+

NetFPGA SUME

+
+ +
+
+
+
+ +
+
+
+
+
+ NetFPGA CML Board +
+

NetFPGA CML

+
+ +
+
+
+
+
+ NetFPGA 10G Board +
+

NetFPGA 10G

+
+ +
+
+
+
+
+ NetFPGA 1G Board +
+

NetFPGA 1G

+
+ +
+
+
+
+
+
+ + +
+ + + + + + + + + + + diff --git a/_site/netfpga-10g.html b/_site/netfpga-10g.html new file mode 100644 index 0000000..0317f06 --- /dev/null +++ b/_site/netfpga-10g.html @@ -0,0 +1,331 @@ + + + + + + + + + NetFPGA + + + + + + + + + + + + + +
+
+
+
+

NetFPGA

+
+
+
+
+ + +
+
+
+

NetFPGA 10G

+
+
+
+ +
+
+

The NetFPGA-10G is an FPGA-based PCI Express board with 10-Gigabit SFP+ interface, a x8 gen1 PCIe adapter card incorporating Xilinx’s Virtex-5 TX240TFPGA. It is ideal for the high bandwidth applications.

+

Features list:

+
    +
  • Field Programmable Gate Array (FPGA) Logic
  • +
  • 10-Gigabit Ethernet networking ports
      +
    • 4 SFP+ connectors
    • +
    • Connected to the FPGA through four Broadcom’s AEL2005 PHY devices
    • +
    • Supports both 10-Gigabit and 1-Gigabit modes
    • +
  • +
  • Quad Data Rate Static Random Access Memory (QDRII SRAM)
      +
    • Suitable for storing and forwarding table data
    • +
    • 300MHz Quad data rate (1.2 Giga transactions every second), synchronous with the logic
    • +
    • Three parallel banks of 72 MBit QDRII+ memories
    • +
    • Total capacity: 27 MBytes
    • +
    • Cypress: CY7C1515KV18
    • +
  • +
  • Reduced Latency Random Access Memory (RLDRAM II)
      +
    • Suitable for packet buffering
    • +
    • Four x36 RLDRAMII on-board device
    • +
    • 400MHz clock (800MT/s)
    • +
    • 115.2 Gbps peak memory throughput
    • +
    • Total Capacity: 288MByte
    • +
    • Micron: MT49H16M36HT-25
    • +
  • +
  • PCI Express Gen. 1
      +
    • First generation PCI Express interface, 2.5Gbps/lane
    • +
    • 8 lanes (x8)
    • +
    • Hard IP
    • +
    • Provides CPU access to memory-mapped registers and memory on the NetFPGA hardware
    • +
    • x4 Gen.2 PCI Express can be used as a soft core
    • +
  • +
  • Storage
      +
    • Two FLASH devices
    • +
    • Total Capacity: 256Mb
    • +
  • +
  • Expansion Interfaces
      +
    • Two SAMTEC QTH connectors
    • +
    • Allowing to connect additional 20 RocketIO GTX transceivers
    • +
  • +
  • Additional Features
      +
    • DB9 (RS232) Connector
    • +
    • User LEDs & Push Buttons
    • +
  • +
  • Standard PCIe Form Factor
      +
    • Standard PCIe card
    • +
    • 3/4 length, full height
    • +
  • +
  • Flexible, Open-source code
  • +
+
+
+
+
+
+ +
+

To see the NetFPGA-10G repository and Wiki you will need to register.

+

Reference Projects

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TitleOrganisationDocumentation
Production TestStanford UniversityWiki
RLDRAM TestXilinxWiki
10G Ethernet Interface Loopback TestStanford University / University of CambridgeWiki
1G Ethernet Interface Loopback TestStanford University / University of CambridgeWiki
Reference NIC 10GStanford University / University of CambridgeWiki
Reference NIC 1GStanford University / University of CambridgeWiki
Flash ConfigurationUniversity of CambridgeWiki
Learning CAM SwitchUniversity of Pisa / University of CambridgeWiki
+

Contributed Projects

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TitleOrganisationDocumentation
NetFPGA-1G Ported Switch 10GUniversity of Pisa / University of CambridgeWiki
NetFPGA-1G Ported NIC 1GUniversity of Pisa / University of CambridgeWiki
NICStanford University / University of CambridgeWiki
OpenFlow SwitchStanford UniversityWiki
NIC (SRAM)Stanford University / University of CambridgeWiki
Simple 10G SwitchXilinxWiki
NetFlow simple 10G BramUniversidad Autónoma de MadridWiki
FlashUniversity of CambridgeWiki
+
+
+
+
+
+ +
+
+

Where can I buy a NetFPGA 10G Platform?

+ +

It seems that my board is broken, what should I do?

+ +

What if I have Hardware problems with my board?

+ +

What if I have Software problems with my board?

+ +

You can exchange your ideas and questions with the NetFPGA 10G community here.

+

How can I get involved with the NetFPGA project?

+ +

How can I obtain the gateware and software package?

+ +
+

Once you have used the NetFPGA, we hope that you will contribute to the project.

+
+

You can find our Wiki here.

+
+
+
+
+ +
+
+ +
+ + + + + + + + + + + diff --git a/_site/netfpga-1g.html b/_site/netfpga-1g.html new file mode 100644 index 0000000..9211c46 --- /dev/null +++ b/_site/netfpga-1g.html @@ -0,0 +1,501 @@ + + + + + + + + + NetFPGA + + + + + + + + + + + + + +
+
+
+
+

NetFPGA

+
+
+
+
+ + +
+
+
+

NetFPGA 1G

+
+
+
+ +
+
+

The NetFPGA is the low-cost reconfigurable hardware platform optimized for high-speed networking. The NetFPGA includes the all fo the logic resources, memory, and Gigabit Ethernet interfaces necessary to build a complete switch, router, and/or security device. Because the entire datapath is implemented in hardware, the system can support back-to-back packets at full Gigabit line rates and has a processing latency measured in only a few clock cycles.

+
    +
  • Field Programmable Gate Array (FPGA) Logic
      +
    • Xilinx Virtex-II Pro 50
    • +
    • 53,136 logic cells
    • +
    • 4,176 Kbit block RAM
    • +
    • up to 738 Kbit distributed RAM
    • +
    • 2 x PowerPC cores
    • +
    • Fully programmable by the user
    • +
  • +
  • Gigabit Ethernet networking ports
      +
    • Connector block on left of PCB interfaces to 4 external RJ45 plugs
    • +
    • Interfaces with standard Cat5E or Cat6 copper network cables using Broadcom PHY
    • +
    • Wire-speed processing on all ports at all time using FPGA logic
        +
      • 1 Gbits * 2 (bi-directional) * 4 (ports) = 8 Gbps throughput
      • +
    • +
  • +
  • Static Random Access Memory (SRAM)
      +
    • Suitable for storing forwarding table data
    • +
    • Zero-bus turnaround (ZBT), synchronous with the logic
    • +
    • Two parallel banks of 18 MBit (2.25 MByte) ZBT memories
    • +
    • Total capacity: 4.5 MBytes
    • +
    • Cypress: CY7C1370D-167AXC
    • +
  • +
  • Double-Date Rate Random Access Memory (DDR2 DRAM)
      +
    • 400 MHz Asynchronous clock
    • +
    • Suitable for packet buffering
    • +
    • 25.6 Gbps peak memory throughput
    • +
    • Total capacity: 64 MBytes
    • +
    • Micron: MT47H16M16BG-5E
    • +
  • +
  • Multi-gigabit I/O
      +
    • Two SATA-style connectors to Multi-Gigabit I/O (MGIO) on right-side of PCB
    • +
    • Allows multiple NetFPGAs within a PC to be chained together
    • +
  • +
  • Standard PCI Form Factor
      +
    • Standard PCI card
    • +
    • Can be used in a PCI-X slot
    • +
    • Enables fast reconfiguration of the FPGA over PCI bus without using JTAG cable
    • +
    • Provides CPU access to memory-mapped registers and memory on the NetFPGA hardware
    • +
  • +
  • Hardware Debugging ports
      +
    • JTAG cable connector can be used to run Xilinx ChipScope Pro
    • +
  • +
  • Flexible, Open-source code
      +
    • BSD-style open-source reference router available from the NetFPGA.org website. Download it, use it, keep it, give back to the community if you choose.
    • +
  • +
+
+
+
+
+
+ +
+

Projects

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TitleOrganisationDocumentation
IPv4 Reference RouterStanford UniversityWiki
Quad-Port Gigabit NICStanford UniversityWiki
Ethernet SwitchStanford UniversityWiki
Buffer Monitoring SystemStanford UniversityWiki
Hardware-Accelerated Linux RouterStanford UniversityWiki
DRAM-RouterStanford UniversityWiki
DRAM-Queue TestStanford UniversityWiki
Packet GeneratorStanford UniversityWiki
OpenFlow SwitchStanford UniversityWiki
NetFlow ProbeBrno UniversityWiki
AirFPGAStanford UniversityWiki
Fast Reroute & Multipath RouterStanford UniversityWiki
NetThreadsUniversity of TorontoWiki
NetThreads-REUniversity of TorontoWiki
NetTMUniversity of TorontoWiki
Precise Traffic GeneratorUniversity of TorontoWiki
URL ExtractionUniv. of New South WalesWiki
zFilter Sprouter (Pub/Sub)EricssonWiki
Windows DriverMicrosoft ResearchWiki
REDStanford UniversityWiki
Open Network LabWashington UniversityWiki
DFAUMass LowellWiki
G/PaXXilinxWiki
RCP RouterStanford UniversityWiki
Deficit Round Robin (DRR)Stanford UniversityWiki
OpenFlow-MPLS SwitchEricssonWiki
PTP-enabled RouterStanford UniversityWiki
Vlan Tag HandlerStanford UniversityWiki
Port AggregatorStanford UniversityWiki
IP Lookup w/Blooming TreeUniversity of PisaWiki
KOREN TestbedChungnam-KoreaWiki
Virtual Data PlaneGeorgia TechWiki
Deficit Round Robin (DRR) Input ArbiterUniversidade Federal do Rio Grande do Sul (Brazil)Wiki
Counter BraidsStanford (Lu, Jianying)Wiki
Ethernet Switch with Real-time supportUniversity of Waterloo and Universidad de ConcepcionWiki
End-to-End Ethernet AuthorizationEuskal Herriko UnibertsitatekoWiki
Ultra-high Speed Congestion-controlUniversity of North CarolinaWiki
Promiscuous Reference RouterUniversity of CataniaWiki
BORPH (Operating System)University of Hong Kong / University of Cape TownWiki
Traffic MonitorUniversity of CataniaWiki
Latency Measurement ModuleAlgo-Logic SystemsWiki
NetFPGA Logic AnalyzerUSC/ISIWiki
Bounded Jitter PolicyUniversity of TorontoWiki
Traffic ClassifierUniversity of TorontoWiki
Network IO FairnessGeorgia TechWiki
Tunneling OpenFlow Switch with ICMPStanford UniversityWiki
zFormation PSrouter (Pub/Sub)EricssonWiki
High Performance Packet ClassifierUniversity of PisaWiki
Flexible RouterUniversity of CataniaWiki
Monitoring SystemUniversity of Pisa / University of CambridgeWiki
Deficit Round Robin Router BackplaneCairo UniversityWiki
NetCoding Project Transmit Node?Download
Router Buffer AdaptationUniversity of New South WalesWiki
+
+
+
+
+
+ +
+
+

Where can I buy a NetFPGA 1G platform

+ +

It seems that my board is broken, what should I do?

+ +

What if I have Hardware problems with my boards?

+ +

What if I have Software problems with my board?

+
    +
  • Register to the NetFPGA Forums.
  • +
+

You can exchange your ideas and questions with the NetFPGA community here.

+

How can I get involved with the NetFPGA project?

+ +

How can I obtain the gateware and software package?

+ +
+

Once you have used the NetFPGA, we hope that you will contribute to the project.

+
+

You can find our Wiki here.

+
+
+
+
+ +
+
+ +
+ + + + + + + + + + + diff --git a/_site/netfpga-cml.html b/_site/netfpga-cml.html new file mode 100644 index 0000000..fe0db5b --- /dev/null +++ b/_site/netfpga-cml.html @@ -0,0 +1,271 @@ + + + + + + + + + NetFPGA + + + + + + + + + + + + + +
+
+
+
+

NetFPGA

+
+
+
+
+ + +
+
+
+

NetFPGA CML

+
+
+
+ +
+
+

The NetFPGA-1G-CML is an FPGA-based PCI Express board with Gigabit Ethernet I/O, an x4 gen2 PCIe adapter card incorporating Xilinx’s Kintex-7 325T FPGA. It is ideal for the development of highly complex, low bandwidth applications.

+

Features list:

+
    +
  • Field Programmable Gate Array (FPGA) Logic
      +
    • Xilinx Kintex-7 325T
    • +
    • 326,080 logic cells
    • +
    • 16,020 Kbit block RAM
    • +
    • up to 4,000 Kbit distributed RAM
    • +
    • Fully programmable by the user
    • +
  • +
  • Gigabit Ethernet networking ports
      +
    • Four 10/100/1000 Ethernet PHYs with RGMII
    • +
    • Wire-speed processing on all ports at all time using FPGA logic
    • +
  • +
  • Quad Data Rate Static Random Access Memory (QDRII+ SRAM)
      +
    • Suitable for storing and forwarding table data
    • +
    • 450MHz Quad data rate (1.8 Giga transactions every second), synchronous with the logic
    • +
    • 36 MBit (4.5 MBytes) QDRII+ memory
    • +
    • Cypress: CY7C2263KV18
    • +
  • +
  • Double-Date Rate Random Access Memory (DDR3 DRAM)
      +
    • Suitable for packet buffering
    • +
    • x8 DDR3 on-board device
    • +
    • 800MHz clock (1600MT/s)
    • +
    • 12.8 Gbps peak memory throughput
    • +
    • Capacity: 512MByte
    • +
    • Micron: MT41K512M8
    • +
  • +
  • PCI Express Gen. 2
      +
    • Second generation PCI Express interface, 5Gbps/lane
    • +
    • 4 lanes (x4)
    • +
    • Hard IP
    • +
    • Provides CPU access to memory-mapped registers and memory on the NetFPGA hardware
    • +
  • +
  • Storage
      +
    • SD-card slot
    • +
    • 1Gbit FLASH
    • +
  • +
  • Expansion Interfaces
      +
    • Fully compliant VITA-57 FMC HPC connector, including 4 high-speed serial links (GTX)
    • +
    • Two Digilent PMOD expansion connectors
    • +
  • +
  • Additional Features
      +
    • 32-bit PIC microcontroller
    • +
    • USB microcontroller
    • +
    • Real Time clock
    • +
    • Crypto-authentication chip
    • +
    • User LEDs & Push Buttons
    • +
  • +
  • Standard PCIe Form Factor
      +
    • Standard PCIe card
    • +
    • 3/4 length, full height
    • +
  • +
  • Flexible, Open-source code
  • +
+
+
+
+
+
+ +
+

To see the NetFPGA-1G-CML repository and Wiki you will need to register.

+

Reference Projects

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TitleOrganisationDocumentation
Ethernet Interface Loopback TestCML / University of CambridgeWiki
Reference NICCML / University of CambridgeWiki
Reference FlashCML / University of CambridgeWiki
Learning CAM SwitchCML / University of CambridgeWiki
Learning Switch (Lite)CML / University of CambridgeWiki
Reference RouterCML / University of CambridgeWiki
+
+
+
+
+
+ +
+
+

Where can I buy a NetFPGA 1G CML Platform?

+ +

It seems that my board is broken, what should I do?

+ +

What if I have Hardware problems with my board?

+ +

What if I have Software problems with my board?

+ +

You can exchange your ideas and questions with the NetFPGA CML community here.

+

How can I get involved with the NetFPGA project?

+ +

How can I obtain the gateware and software package?

+
  • Registration
  • +
  • NetFPGA-1G-CML license
  • +
    +

    Once you have used the NetFPGA, we hope that you will contribute to the project.

    +
    +

    You can find our Wiki here.

    +
    +
    +
    +
    + +
    +
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    + + + + + + + + + + + diff --git a/_site/netfpga-sume.html b/_site/netfpga-sume.html new file mode 100644 index 0000000..1aa0b20 --- /dev/null +++ b/_site/netfpga-sume.html @@ -0,0 +1,272 @@ + + + + + + + + + NetFPGA + + + + + + + + + + + + + +
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    NetFPGA

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    NetFPGA SUME

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    The NetFPGA SUME is an FPGA-based PCI Express board with I/O capabilities for 10 and 100 Gbps operation, an x8 gen3 PCIe adapter card incorporating Xilinx’s Virtex-7 690T FPGA. It can be used as NIC, multiport switch, firewall, test/measurement environment, and more.

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    Features list:

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    • Field Programmable Gate (FPGA) Logic
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      • Xilinx Virtex-7 690T
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      • 693,120 logic cells
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      • 52,920 Kbit block RAM
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      • up to 10,888 Kbit distributed RA
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      • 30 GTH (up to 13.1Gbps) Transceivers
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      • Fully programmable by the user
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    • 10-Gigabit Ethernet Connection
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      • Connector block on left of PCB interfaces to 4 external SFP+ ports
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      • Directly connected to the FPGA.
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      • Wire-speed processing on all ports at all time using FPGA logic.
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    • Quad Data Rate Static Random Access Memory (QDRII+ SRAM)
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      • Suitable for storing and forwarding table data
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      • 500MHz Quad data rate (2 Giga transactions every second), synchronous with the logic
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      • Three parallel banks of 72 MBit QDRII+ memories
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      • Total capacity: 27 MBytes
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      • Cypress: CY7C25652KV18-500BZC
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    • Double-Date Rate Random Access Memory (DDR3 DRAM)
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      • Suitable for packet buffering
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      • Two replaceable DDR3-SoDIMM modules
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      • 933MHz clock (1866MT/s)
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      • 238.8 Gbps peak memory throughput
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      • Total capacity: 8 GBytes (Supports up to 32 GBytes)
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      • Micron: MT8KTF51264HZ-1G9E5
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    • PCI Express Gen. 3
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      • Third generation PCI Express interface, 8Gbps/lane
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      • 8 lanes (x8)
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      • Hard IP
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      • Provides CPU access to memory-mapped registers and memory on the NetFPGA hardware
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    • Expansion Interfaces
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      • Fully compliant VITA-57 FMC HPC connector, including 10 high-speed serial links
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      • SAMTEC QTH-DP connector, connected to 8 high-speed serial links
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      • Allowing to connect additional 18 GTH transceivers
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      • Digilent PMOD expansion connector
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    • Storage
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      • 2 SATA connectors
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      • Micro-SD slot
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      • 2 FLASH devices, each 512Mbit (1Gbit total)
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    • Additional Features
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      • Clock recovery circuit
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      • Voltage sensors
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      • Current sensors
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      • User LEDs & Push Buttons
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    • Standard PCIe Form Factor
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      • Standard PCIe card
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      • Full length, full height
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    • Flexible, Open-source code
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    A full description of the board and its potential use cases is provided in the following paper:

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    Noa Zilberman, Yury Audzevich, G. Adam Covington, Andrew W. Moore, 'NetFPGA SUME: Toward 100 Gbps as Research Commodity,' IEEE Micro, vol.34, no.5, pp.32,41, September-October 2014 (official version) (pdf)

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    Please use this citation as the canonical reference for NetFPGA-SUME.

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    To see the NetFPGA-SUME repository and Wiki you will need to register.

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    Reference Projects

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    TitleOrganisationDocumentation
    Reference SwitchUniversity of CambridgeWiki
    Reference Switch LiteUniversity of CambridgeWiki
    Reference NICUniversity of CambridgeWiki
    Reference RouterUniversity of CambridgeWiki
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    Where can I buy a NetFPGA SUME Platform?

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    It seems that my board is broken, what should I do?

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    What if I have Hardware problems with my board?

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    What if I have Software problems with my board?

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    You can change your ideas and questions with the NetFPGA SUME community, please register here.

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    How can I get involved with the NetFPGA project?

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    How can I obtain the gateware and software package?

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    Digilent Hardware documentation wiki about NetFPGA SUME board here.

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    Once you have used the NetFPGA, we hope that you will contribute to the project.

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    You can find our Wiki here.

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    NetFPGA

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    Publications featuring NetFPGA

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    A partial list of publications using the NetFPGA platform.

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    The links for the addresses are, where possible, doi.org links.

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  • Antichi, G., Callegari, C., Giordano, S. (2012, December). An open hardware implementation of CUSUM based Network Anomaly Detection. Globecom. IEEE.
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  • Rojas, E., Naous, J., Ibáñez, G., Recio, C. (2012, October). Dynamic Load Routing-Path Diversity in a Network of ARP-Path NetFPGA Switches. Conference on Local Computer Networks (LCN). IEEE.
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  • Huang, T. Y., Handigol, N., Heller, B., McKeown, N., & Johari, R. (2012, November). Confused, timid, and unstable: picking a video streaming rate is hard. In Proceedings of the 2012 ACM conference on Internet measurement conference (pp. 225-238). ACM.
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  • Matias, J., Jacob, E., Higuero, M., & Toledo, N. (2012, June). Extending Neutrality to Experimental Facilities. In ACCESS 2012, The Third International Conference on Access Networks (pp. 14-20).
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  • Liu, X., Wada, A., Xing, T., Juluri, P., Sato, Y., Ata, S., ... & Medhi, D. (2012, April). SeRViTR: A framework for trust and policy management for a secure Internet and its proof-of-concept implementation. In Network Operations and Management Symposium (NOMS), 2012 IEEE (pp. 1159-1166). IEEE.
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  • Matias, J., Tornero, B., Mendiola, A., Jacob, E., & Toledo, N. (2012, October). Implementing Layer 2 Network Virtualization using OpenFlow: Challenges and Solutions. In Software Defined Networking (EWSDN), 2012 European Workshop on (pp. 30-35). IEEE.
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  • Handigol, N., Heller, B., Jeyakumar, V., Lantz, B., & McKeown, N. (2012, December). Reproducible network experiments using container-based emulation. In Proceedings of the 8th international conference on Emerging networking experiments and technologies (pp. 253-264). ACM.
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  • Xie, D., Ding, N., Hu, Y. C., & Kompella, R. (2012). The only constant is change: incorporating time-varying network reservations in data centers. ACM SIGCOMM Computer Communication Review, 42(4), 199-210.
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  • Hu, J. W., Huang, W. Y., Tseng, H. M., Lee, H. L., Ku, L. C., Lin, S. C., ... & Yang, C. S. (2012, July). Future Internet in Taiwan: Design and Research Activities over TWAREN Network. In Innovative Mobile and Internet Services in Ubiquitous Computing (IMIS), 2012 Sixth International Conference on (pp. 329-333). IEEE.
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  • Seddiki, M. S., & Frikha, M. (2012, July). Resource Allocation for Virtual Routers through Non-Cooperative Games. In Computer Communications and Networks (ICCCN), 2012 21st International Conference on (pp. 1-6). IEEE.
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  • Sonkoly, B., Gulyas, A., Nemeth, F., Czentye, J., Kurucz, K., Novak, B., & Vaszkun, G. (2012, October). On QoS Support to Ofelia and OpenFlow. In Software Defined Networking (EWSDN), 2012 European Workshop on (pp. 109-113). IEEE.
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  • Gibb, G., Zeng, H., & McKeown, N. (2012, August). Outsourcing network functionality. In Proceedings of the first workshop on Hot topics in software defined networks (pp. 73-78). ACM.
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  • Mendonca, M., Seetharaman, S., & Obraczka, K. (2012, June). A flexible in-network IP anonymization service. In Communications (ICC), 2012 IEEE International Conference on (pp. 6651-6656). IEEE.
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  • Mirkovic, J., Shi, H., & Hussain, A. (2012, November). Reducing allocation errors in network testbeds. In Proceedings of the 2012 ACM conference on Internet measurement conference (pp. 495-508). ACM.
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  • Corin, R. D., Gerola, M., Riggio, R., De Pellegrini, F., & Salvadori, E. (2012, October). VeRTIGO: Network Virtualization and Beyond. In Software Defined Networking (EWSDN), 2012 European Workshop on (pp. 24-29). IEEE.
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  • Fotiou, N., Nikander, P., Trossen, D., & Polyzos, G. C. (2012). Developing information networking further: From PSIRP to PURSUIT. In Broadband Communications, Networks, and Systems (pp. 1-13). Springer Berlin Heidelberg.
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  • Groleat, T., Arzel, M., & Vaton, S. (2012, August). Hardware acceleration of SVM-based traffic classification on FPGA. In Wireless Communications and Mobile Computing Conference (IWCMC), 2012 8th International (pp. 443-449). IEEE.
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  • Konorski, J., Pacyna, P., Kolaczek, G., Kotulski, Z., Cabaj, K., & Szalachowski, P. (2012). A Virtualization-Level Future Internet Defense-in-Depth Architecture. In Recent Trends in Computer Networks and Distributed Systems Security (pp. 283-292). Springer Berlin Heidelberg.
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  • Jiang, W., Ren, F., Shu, R., & Lin, C. (2012, March). Sliding Mode Congestion Control for data center Ethernet networks. In INFOCOM, 2012 Proceedings IEEE (pp. 1404-1412). IEEE.
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  • Revsbech, K., Madsen, T. K., & Schioler, H. (2012, November). High precision testbed to evaluate ethernet performance for in-car networks. In ITS Telecommunications (ITST), 2012 12th International Conference on (pp. 548-552). IEEE.
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  • Tarasiuk, H., Hanczewski, S., Kaliszan, A., Szuman, R., Ogrodowczyk, L., Olszewski, I., ... & Wisniewski, P. (2012, October). A proposal of the IPv6 QoS system implementation in virtual infrastructure. In Telecommunications Network Strategy and Planning Symposium (NETWORKS), 2012 XVth International (pp. 1-6). IEEE.
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  • Tran, N. T., Tomiyama, S., Kittitornkun, S., & Vu, T. H. (2012, May). TCP reassembly for signature-based Network Intrusion Detection systems. In Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON), 2012 9th International Conference on (pp. 1-4). IEEE.
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  • Anand, M., Fischmeister, S., Lee, I., & Phan, L. T. (2012). State-based scheduling with tree schedules: analysis and evaluation. Real-Time Systems, 48(4), 430-462.
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  • Jiang, W., Ren, F., Lin, C., & Stojmenovic, I. (2012, March). Analysis of backward congestion notification with delay for enhanced ethernet networks. In INFOCOM, 2012 Proceedings IEEE (pp. 2961-2965). IEEE.
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  • Lockwood, J. W., Gupte, A., Mehta, N., Blott, M., English, T., & Vissers, K. (2012, August). A Low-Latency Library in FPGA Hardware for High-Frequency Trading (HFT). In High-Performance Interconnects (HOTI), 2012 IEEE 20th Annual Symposium on (pp. 9-16). IEEE.
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  • Mehmood, M. A., Wundsam, A., Uhlig, S., Levin, D., Sarrar, N., & Feldmann, A. (2012). QoE-lab: Towards evaluating quality of experience for future internet conditions. In Testbeds and Research Infrastructure. Development of Networks and Communities (pp. 286-301). Springer Berlin Heidelberg.
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  • Tarasiuk, H., & Rogowski, J. (2012, July). On the signaling system in the IPv6 QoS Parallel Internet. In Communication Systems, Networks & Digital Signal Processing (CSNDSP), 2012 8th International Symposium on (pp. 1-6). IEEE.
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  • Liu, X., Fouli, K., Kang, R., & Maier, M. (2012). Network-Coding-Based Energy Management for Next-Generation Passive Optical Networks. Journal of Lightwave Technology, 30(6), 864-875.
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  • Yin, D., & Li, G. (2012). Scalable MapReduce Framework on FPGA Accelerated Commodity Hardware. In Internet of Things, Smart Spaces, and Next Generation Networking (pp. 280-294). Springer Berlin Heidelberg.
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  • Pries, R., Jarschel, M., & Goll, S. (2012, June). On the usability of OpenFlow in data center environments. In Communications (ICC), 2012 IEEE International Conference on (pp. 5533-5537). IEEE.
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  • Ghobadi, M., Salmon, G., Ganjali, Y., Labrecque, M., & Steffan, J. G. (2012, August). Caliper: Precise and responsive traffic generator. In High-Performance Interconnects (HOTI), 2012 IEEE 20th Annual Symposium on (pp. 25-32). IEEE.
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  • Meng, W., Wang, Y., Hu, C., He, K., Li, J., & Liu, B. (2012, March). Greening the Internet Using Multi-frequency Scaling Scheme. In Advanced Information Networking and Applications (AINA), 2012 IEEE 26th International Conference on (pp. 928-935). IEEE.
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  • Papadimitriou, K., Vatsolakis, C., & Pnevmatikatos, D. (2012, July). Invited paper: Acceleration of computationally-intensive kernels in the reconfigurable era. In Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2012 7th International Workshop on (pp. 1-5). IEEE.
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  • Zhang, F., Xie, Y., Liu, J., Luo, L., Ning, Q., & Wu, X. (2012, August). ITester: A FPGA based high performance traffic replay tool. In Field Programmable Logic and Applications (FPL), 2012 22nd International Conference on (pp. 699-702). IEEE.
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  • Maravic, I., & Smiljanic, A. (2012, June). MPLS implementation for the Linux kernel. In High Performance Switching and Routing (HPSR), 2012 IEEE 13th International Conference on (pp. 23-28). IEEE.
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  • Li, J., Li, Y., Li, H., Zhu, Z., Zhang, H., & Chen, F. (2012, July). A synchronous algorithm of network coding with hardware logic. In ICT and Energy Efficiency and Workshop on Information Theory and Security (CIICT 2012), Symposium on (pp. 82-87). IET.
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  • Wang, K., Yang, B., Chen, Z., & Sun, T. (2012). Design and Implementation of FPGA Network Simulation and Verification Platform. In Advances in Computer Science and Information Engineering (pp. 659-664). Springer Berlin Heidelberg.
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  • Reforgiato, D., Lombardo, A., Davoli, F., Fialho, L., Collier, M., Donadio, P., ... & Bruschi, R. (2012, June). Exporting data-plane energy-aware capabilities from network devices toward the control plane: The Green Abstraction Layer. In Networks and Optical Communications (NOC), 2012 17th European Conference on (pp. 1-6). IEEE.
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  • Dixit, A. A., Prakash, P., Kompella, R. R., & Hu, C. (2012, June). On the efficacy of fine-grained traffic splitting protocols in data center networks. In Proceedings of the 12th ACM SIGMETRICS/PERFORMANCE joint international conference on Measurement and Modeling of Computer Systems (pp. 411-412). ACM.
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  • Antichi, G., Giordano, S., Miller, D. J., & Moore, A. W. (2012, April). Enabling open-source high speed network monitoring on NetFPGA. In Network Operations and Management Symposium (NOMS), 2012 IEEE (pp. 1029-1035). IEEE.
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  • Unnikrishnan, D., Vadlamani, R., Liao, Y., Crenne, J., Gao, L., & Tessier, R. (2012). Reconfigurable Data Planes for Scalable Network Virtualization.
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  • Chasaki, D., & Wolf, T. (2012). Attacks and Defenses in the Data Plane of Networks.
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  • Carvajal, G., Wu, C., & Fischmeister, S. (2012). Evaluation of Communication Architectures for Switched Real-time Ethernet.
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  • Thinh, T. N., Hieu, T. T., & Kittitornkun, S. (2012, May). A FPGA-based deep packet inspection engine for Network Intrusion Detection System. In Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON), 2012 9th International Conference on (pp. 1-4). IEEE.
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  • Chydzinski, A., Rawski, M., Wisniewski, P., Adamczyk, B., Olszewski, I., Szotkowski, P., ... & Parniewicz, D. (2012, August). Virtualization Devices for Prototyping of Future Internet. In Software Engineering, Artificial Intelligence, Networking and Parallel & Distributed Computing (SNPD), 2012 13th ACIS International Conference on (pp. 672-678). IEEE.
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  • Michalski, M. (2012, July). The configurations for experimental study of the network performance. In Communication Systems, Networks & Digital Signal Processing (CSNDSP), 2012 8th International Symposium on (pp. 1-6). IEEE.
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  • Guo, F., Ormond, O., Fialho, L., Collier, M., & Wang, X. (2012). Power consumption analysis of a NetFPGA based router. The Journal of China Universities of Posts and Telecommunications, 19, 94-99.
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  • Gringoli, F., Nava, L., Este, A., & Salgarelli, L. (2012, August). MTCLASS: Enabling statistical traffic classification of multi-gigabit aggregates on inexpensive hardware. In Wireless Communications and Mobile Computing Conference (IWCMC), 2012 8th International (pp. 450-455). IEEE.
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  • Thanh, N. H., Nam, P. N., Truong, T. H., Hung, N. T., Doanh, L. K., & Pries, R. (2012, August). Enabling experiments for energy-efficient data center networks on OpenFlow-based platform. In Communications and Electronics (ICCE), 2012 Fourth International Conference on (pp. 239-244). IEEE.
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  • Muehlbach, S., & Koch, A. (2012, October). Malacoda: towards high-level compilation of network security applications on reconfigurable hardware. In Proceedings of the eighth ACM/IEEE symposium on Architectures for networking and communications systems (pp. 247-258). ACM.
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  • Belias, A., Koutsoumpos, V., Manolopoulos, K., & Kachris, C. (2012). Reconfigurable hardware applications on NetFPGA for network monitoring in large area sensor networks. Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment.
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  • Lombardo, A., Reforgiato, D., Riccobene, V., & Schembra, G. (2012, October). A Markov model to control heat dissipation in open multi-frequency green routers. In Sustainable Internet and ICT for Sustainability (SustainIT), 2012 (pp. 1-9). IEEE.
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  • Vu, T. H., Nam, P. N., Thanh, T., Linh, N. D., Thien, T. D., & Thanh, N. H. (2012, October). Power aware OpenFlow switch extension for energy saving in data centers. In Advanced Technologies for Communications (ATC), 2012 International Conference on (pp. 309-313). IEEE.
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  • Xu, Y., Gu, R., & Ji, Y. (2012, September). Network traffic on-line classification using decision tree fast parallel processing strategy. In Network Infrastructure and Digital Content (IC-NIDC), 2012 3rd IEEE International Conference on (pp. 339-343). IEEE.
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  • Orosz, P., Skopko, T., & Imrek, J. (2012, October). A NetFPGA-based network monitoring system with multi-layer timestamping: Rnetprobe. In Telecommunications Network Strategy and Planning Symposium (NETWORKS), 2012 XVth International (pp. 1-6). IEEE.
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  • Liu, G., & Neufeld, N. (2012, June). LHCb: The LHCb off-Site HLT Farm Demonstration. In Conference: 18th IEEE Real-Time Conference 2012 (No. Poster-2012-238).
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  • Hieu, T. T., Thinh, T. N., & Tomiyama, S. (2013). ENREM: An Efficient NFA-based Regular Expression Matching Engine on Reconfigurable Hardware for NIDS. Journal of Systems Architecture.
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  • Xin Liu; Fouli, K.; Rui Kang; Maier, M.; , 'Network-Coding-Based Energy Management for Next-Generation Passive Optical Networks,' Lightwave Technology, Journal of , vol.30, no.6, pp.864-875, March 15, 2012
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