From 23ce81646830e0bb1ef446967031daa56ead6fb4 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Mon, 26 May 2025 14:13:31 +0800 Subject: [PATCH 01/15] bsp: k230: fix kconfig warnings scons --menuconfig will report: ``` warning: the choice symbol PKG_USING_ZLIB_LATEST_VERSION (defined at /home/u/.env/packages/packages/misc/zlib/Kconfig:31) is selected by the following symbols, but select/imply has no effect on choice symbols - BSP_ROOTFS_TYPE_CROMFS (defined at Kconfig:36) warning: default on the choice symbol BSP_USING_SDIO0 (defined at board/Kconfig:20) will have no effect, as defaults do not affect choice symbols warning: default on the choice symbol BSP_USING_SDIO1 (defined at board/Kconfig:34) will have no effect, as defaults do not affect choice symbols ``` Fix and remove these warnings. Signed-off-by: Chen Wang --- bsp/k230/Kconfig | 1 - bsp/k230/board/Kconfig | 2 -- 2 files changed, 3 deletions(-) diff --git a/bsp/k230/Kconfig b/bsp/k230/Kconfig index 937ed23cef5..93af5a32488 100644 --- a/bsp/k230/Kconfig +++ b/bsp/k230/Kconfig @@ -37,5 +37,4 @@ choice BSP_ROOTFS_TYPE bool "Use Compressed ROM File-System (ReadOnly)" select RT_USING_DFS_CROMFS select PKG_USING_ZLIB - select PKG_USING_ZLIB_LATEST_VERSION endchoice diff --git a/bsp/k230/board/Kconfig b/bsp/k230/board/Kconfig index f25908a2fd1..93d3df2c380 100644 --- a/bsp/k230/board/Kconfig +++ b/bsp/k230/board/Kconfig @@ -19,7 +19,6 @@ menu "Drivers Configuration" config BSP_USING_SDIO0 bool "Enable SDIO0" - default y if BSP_USING_SDIO0 config BSP_SDIO0_EMMC @@ -33,7 +32,6 @@ menu "Drivers Configuration" config BSP_USING_SDIO1 bool "Enable SDIO1" - default n endchoice config BSP_SD_MNT_DEVNAME From 1526fe152d76846efe078fcb2abc2cc65fbd2423 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E4=B8=8B=E9=87=8C=E5=B7=B4=E4=BA=BA?= Date: Tue, 27 May 2025 11:02:45 +0800 Subject: [PATCH 02/15] [bsp][stm32] add descriptions of 2 board in README.md doc (#10327) --- bsp/stm32/README.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/bsp/stm32/README.md b/bsp/stm32/README.md index b5cd005a084..dd8d32bf613 100644 --- a/bsp/stm32/README.md +++ b/bsp/stm32/README.md @@ -55,11 +55,13 @@ STM32 系列 BSP 目前支持情况如下表所示： | [stm32f767-st-nucleo](stm32f767-st-nucleo) | ST 官方 STM32F767-nucleo 开发板 | | [stm32f769-st-disco](stm32f769-st-disco) | ST 官方 STM32f769-discovery 开发板 | | **G0 系列** | | +| [stm32g030-tiny-board](stm32g030-tiny-board) | STM32G030-tiny-board 开发板 | | [stm32g070-st-nucleo](stm32g070-st-nucleo) | ST 官方 STM32G070-nucleo 开发板 | | [stm32g071-st-nucleo](stm32g071-st-nucleo) | ST 官方 STM32G071-nucleo 开发板 | | **G4 系列** | | | [stm32g431-st-nucleo](stm32g431-st-nucleo) | ST 官方 STM32G431-nucleo 开发板 | | **H7 系列** | | +| [stm32h723-st-nucleo](stm32h723-st-nucleo) | ST 官方 STM32H723-nucleo 开发板 | | [stm32h743-armfly-v7](stm32h743-armfly-v7) | 安富莱 STM32H743 v7 开发板 | | [stm32h743-atk-apollo](stm32h743-atk-apollo) | 正点原子 h743 阿波罗开发板 | | [stm32h743-openmv-h7plus](stm32h743-openmv-h7plus) | OPENMV 官方 H7-PLUS 开发板 | From aaae1a880935892a00fac41d52afe97064f97339 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Tue, 27 May 2025 08:33:54 +0800 Subject: [PATCH 03/15] bsp: k230: add watchdog support K230 has two watchdog timers. Add unit tests based on utest framework. Watchdog and test are both configuable, disabled by default. Signed-off-by: Chen Wang --- bsp/k230/.config | 2 + bsp/k230/board/Kconfig | 21 ++ bsp/k230/drivers/interdrv/wdt/SConscript | 19 ++ bsp/k230/drivers/interdrv/wdt/drv_wdt.c | 274 +++++++++++++++++++++++ bsp/k230/drivers/interdrv/wdt/drv_wdt.h | 73 ++++++ bsp/k230/drivers/utest/SConscript | 12 + bsp/k230/drivers/utest/test_wdt.c | 170 ++++++++++++++ 7 files changed, 571 insertions(+) create mode 100644 bsp/k230/drivers/interdrv/wdt/SConscript create mode 100644 bsp/k230/drivers/interdrv/wdt/drv_wdt.c create mode 100644 bsp/k230/drivers/interdrv/wdt/drv_wdt.h create mode 100644 bsp/k230/drivers/utest/SConscript create mode 100644 bsp/k230/drivers/utest/test_wdt.c diff --git a/bsp/k230/.config b/bsp/k230/.config index 67267cd508a..b019e93de7e 100644 --- a/bsp/k230/.config +++ b/bsp/k230/.config @@ -1497,6 +1497,8 @@ CONFIG_BSP_USING_SDIO0=y # CONFIG_BSP_SDIO0_1V8 is not set # CONFIG_BSP_USING_SDIO1 is not set CONFIG_BSP_SD_MNT_DEVNAME="sd0p1" +# CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_UTEST_DRIVERS is not set # end of Drivers Configuration CONFIG_BOARD_fpgac908=y diff --git a/bsp/k230/board/Kconfig b/bsp/k230/board/Kconfig index 93d3df2c380..c91fed4f61b 100644 --- a/bsp/k230/board/Kconfig +++ b/bsp/k230/board/Kconfig @@ -39,4 +39,25 @@ menu "Drivers Configuration" default "sd0p1" endif + menuconfig BSP_USING_WDT + bool "Enable Watchdog Timer" + select RT_USING_WDT + default n + + if BSP_USING_WDT + config BSP_USING_WDT0 + bool "Enable WDT0" + default n + + config BSP_USING_WDT1 + bool "Enable WDT1" + default n + + endif + + config BSP_UTEST_DRIVERS + bool "Enable drivers utest" + select RT_USING_UTEST + default n + endmenu diff --git a/bsp/k230/drivers/interdrv/wdt/SConscript b/bsp/k230/drivers/interdrv/wdt/SConscript new file mode 100644 index 00000000000..d7c561ee12b --- /dev/null +++ b/bsp/k230/drivers/interdrv/wdt/SConscript @@ -0,0 +1,19 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('WDT', src, depend = ['BSP_USING_WDT'], CPPPATH = CPPPATH) + +objs = [group] + +list = os.listdir(cwd) + +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + objs = objs + SConscript(os.path.join(item, 'SConscript')) + +Return('objs') diff --git a/bsp/k230/drivers/interdrv/wdt/drv_wdt.c b/bsp/k230/drivers/interdrv/wdt/drv_wdt.c new file mode 100644 index 00000000000..296f1cf5615 --- /dev/null +++ b/bsp/k230/drivers/interdrv/wdt/drv_wdt.c @@ -0,0 +1,274 @@ +/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include "board.h" +#include "ioremap.h" +#include "sysctl_clk.h" +#include "drv_wdt.h" +#include +#include + +struct k230_wdt_dev +{ + struct rt_watchdog_device device; + const char *name; + rt_ubase_t base; + size_t size; + sysctl_clk_node_e clk; /* clock source */ +}; + +/* There are sixteen TOPs (timeout periods) that can be set in the watchdog. */ + +static const rt_uint32_t *tops; + +static const rt_uint32_t k230_wdt_fix_tops[KD_WDT_NUM_TOPS] = { + KD_WDT_FIX_TOP(0), KD_WDT_FIX_TOP(1), KD_WDT_FIX_TOP(2), + KD_WDT_FIX_TOP(3), KD_WDT_FIX_TOP(4), KD_WDT_FIX_TOP(5), + KD_WDT_FIX_TOP(6), KD_WDT_FIX_TOP(7), KD_WDT_FIX_TOP(8), + KD_WDT_FIX_TOP(9), KD_WDT_FIX_TOP(10), KD_WDT_FIX_TOP(11), + KD_WDT_FIX_TOP(12), KD_WDT_FIX_TOP(13), KD_WDT_FIX_TOP(14), + KD_WDT_FIX_TOP(15) +}; + +static struct k230_wdt_timeout timeouts[KD_WDT_NUM_TOPS]; +static char rmod; /* wdt reset mode, */ + +static void k230_wdt_timeouts_init(struct k230_wdt_dev *dev) +{ + rt_uint32_t wdt_clk; + rt_uint32_t time_value; + rt_uint32_t i, t; + rt_uint64_t msec; + struct k230_wdt_timeout tout, *dst; + /* caculate timeout value */ + wdt_clk = sysctl_clk_get_leaf_freq(dev->clk); + + for (i = 0; i < KD_WDT_NUM_TOPS; ++i) + { + tout.top_val = i; + tout.sec = tops[i] / wdt_clk; + msec = (rt_uint64_t)tops[i] * (rt_uint64_t)1000L; + msec = msec / wdt_clk; + tout.msec = msec - (rt_uint64_t)tout.sec * (rt_uint64_t)1000L; + + for (t = 0; t < i; ++t) + { + dst = &timeouts[t]; + if (tout.sec > dst->sec || (tout.sec == dst->sec && + tout.msec >= dst->msec)) + continue; + else + swap(*dst, tout); + } + + timeouts[i] = tout; + } + rt_kprintf("watchdog timeout table init OK!\n"); +} + +static rt_err_t k230_wdt_feed(struct k230_wdt_dev *dev) +{ + k230_wdt_t *reg = (k230_wdt_t *)dev->base; + reg->crr = 0x76; + + return RT_EOK; +} + +static rt_err_t k230_wdt_enable(struct k230_wdt_dev *dev) +{ + k230_wdt_t *reg = (k230_wdt_t *)dev->base; + reg->crr = 0x76; + reg->cr |= 0x1; + + return RT_EOK; +} + +static rt_err_t k230_wdt_disable(struct k230_wdt_dev *dev) +{ + k230_wdt_t *reg = (k230_wdt_t *)dev->base; + reg->crr = 0x76; + reg->cr &= ~0x1; + + return RT_EOK; +} + +static rt_err_t k230_wdt_set_timeout(struct k230_wdt_dev *dev, rt_uint64_t timeout) +{ + k230_wdt_t *reg = (k230_wdt_t *)dev->base; + rt_uint32_t top_val; + rt_uint32_t i; + rt_uint32_t time = (timeout + rmod -1) / rmod; + + for (i = 0; i < KD_WDT_NUM_TOPS; ++i) + { + if (timeouts[i].sec >= time) + break; + } + + if (i == KD_WDT_NUM_TOPS) + --i; + + top_val = timeouts[i].top_val; + + reg->torr = (top_val << 4) | (top_val << 0); + + return RT_EOK; +} + +static rt_err_t k230_wdt_get_timeout(struct k230_wdt_dev *dev, void *timeout) +{ + rt_uint64_t top_val; + rt_uint32_t i; + k230_wdt_t *reg = (k230_wdt_t *)dev->base; + top_val = ((reg->torr) & 0xf); + + for (i = 0; i < KD_WDT_NUM_TOPS; ++i) + { + if (timeouts[i].top_val == top_val) + break; + } + + *((rt_uint64_t *)timeout) = timeouts[i].sec * rmod; + + return RT_EOK; +} + +static rt_err_t k230_wdt_init(rt_watchdog_t *wdt) +{ + RT_ASSERT(wdt != NULL); + + struct k230_wdt_dev *dev = rt_container_of(wdt, struct k230_wdt_dev, device); + k230_wdt_t *reg = (k230_wdt_t *)dev->base; + + reg->cr &= ~(0x01 << 1); + reg->cr |= (0x0 << 1); /* default set wdt reset mode */ + rmod = KD_WDT_RMOD_RESET; + + if (reg->comp_param_1 & (1 << 6)) + { + tops = k230_wdt_fix_tops; + } + + k230_wdt_timeouts_init(dev); + + if (!timeouts[KD_WDT_NUM_TOPS - 1].sec) + { + rt_kprintf("No any valid Timeout period detected\n"); + return -RT_EINVAL; + } + + return RT_EOK; +} + +static rt_err_t k230_wdt_control(rt_watchdog_t *wdt, int cmd, void *args) +{ + RT_ASSERT(wdt != NULL); + + struct k230_wdt_dev *dev = rt_container_of(wdt, struct k230_wdt_dev, device); + + switch(cmd) + { + case KD_DEVICE_CTRL_WDT_GET_TIMEOUT: + k230_wdt_get_timeout(dev, args); + break; + case KD_DEVICE_CTRL_WDT_SET_TIMEOUT: + k230_wdt_set_timeout(dev, *((rt_uint32_t*)args)); + break; + case KD_DEVICE_CTRL_WDT_KEEPALIVE: + k230_wdt_feed(dev); + break; + case KD_DEVICE_CTRL_WDT_START: + k230_wdt_enable(dev); + break; + case RT_DEVICE_CTRL_WDT_STOP: + case KD_DEVICE_CTRL_WDT_STOP: + k230_wdt_disable(dev); + break; + default: + return -RT_EINVAL; + } + + return RT_EOK; +} + +static struct rt_watchdog_ops k230_wdt_ops = +{ + .init = k230_wdt_init, + .control = k230_wdt_control, +}; + +static struct k230_wdt_dev wdt_devices[] = +{ +#ifdef BSP_USING_WDT0 + { + .name = "wdt0", + .base = WDT0_BASE_ADDR, + .size = WDT0_IO_SIZE, + .clk = SYSCTL_CLK_WDT0, + }, +#endif /* BSP_USING_WDT0 */ + +#ifdef BSP_USING_WDT1 + { + .name = "wdt1", + .base = WDT1_BASE_ADDR, + .size = WDT1_IO_SIZE, + .clk = SYSCTL_CLK_WDT1, + }, +#endif /* BSP_USING_WDT1 */ + +#if !defined(BSP_USING_WDT0) && !defined(BSP_USING_WDT1) +#error "No watchdog device defined!" +#endif +}; + +int rt_hw_wdt_init(void) +{ + rt_uint8_t i; + for (i = 0; i < sizeof(wdt_devices) / sizeof(struct k230_wdt_dev); i++) + { + wdt_devices[i].device.ops = &k230_wdt_ops; + wdt_devices[i].base = (rt_ubase_t)rt_ioremap((void *)wdt_devices[i].base, wdt_devices[i].size); + + if (rt_hw_watchdog_register(&wdt_devices[i].device, wdt_devices[i].name, RT_DEVICE_FLAG_RDWR, RT_NULL) != RT_EOK) + { + LOG_E("%s register failed!", wdt_devices[i].name); + return -RT_ERROR; + } + LOG_D("%s register OK!", wdt_devices[i].name); + } + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_wdt_init); \ No newline at end of file diff --git a/bsp/k230/drivers/interdrv/wdt/drv_wdt.h b/bsp/k230/drivers/interdrv/wdt/drv_wdt.h new file mode 100644 index 00000000000..6afb2b0e48f --- /dev/null +++ b/bsp/k230/drivers/interdrv/wdt/drv_wdt.h @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef DRV_WDT_H_ +#define DRV_WDT_H_ + +#include +#include + +#define DEFUALT_TIMEOUT 30*1000 /* ms */ +#define KD_WDT_NUM_TOPS 16 +#define KD_WDT_FIX_TOP(_idx) (1U << (16 + _idx)) +#define KD_WDT_RMOD_RESET 1 +#define KD_WDT_RMOD_IRQ 2 + +#define KD_DEVICE_CTRL_WDT_GET_TIMEOUT _IOW('W', 1, int) /* get timeout(in seconds) */ +#define KD_DEVICE_CTRL_WDT_SET_TIMEOUT _IOW('W', 2, int) /* set timeout(in seconds) */ +#define KD_DEVICE_CTRL_WDT_GET_TIMELEFT _IOW('W', 3, int) /* get the left time before reboot(in seconds) */ +#define KD_DEVICE_CTRL_WDT_KEEPALIVE _IOW('W', 4, int) /* refresh watchdog */ +#define KD_DEVICE_CTRL_WDT_START _IOW('W', 5, int) /* start watchdog */ +#define KD_DEVICE_CTRL_WDT_STOP _IOW('W', 6, int) /* stop watchdog */ + +struct k230_wdt_timeout { + rt_uint32_t top_val; + rt_uint32_t sec; + rt_uint32_t msec; +}; + +#define swap(a, b) \ + do { struct k230_wdt_timeout __tmp = (a); (a) = (b); (b) = __tmp; } while (0) + +/* wdt register map */ +typedef struct _wdt +{ + /* WDT Control Register (0x00) */ + volatile uint32_t cr; + /* WDT Timeout Range Register (0x04) */ + volatile uint32_t torr; + /* WDT Current Counter Value Register (0x08) */ + volatile uint32_t ccvr; + /* WDT Counter Restart Register (0x0c) */ + volatile uint32_t crr; + /* WDT Interrupt Status Register (0x10) */ + volatile uint32_t stat; + /* WDT Interrupt Clear Register (0x14) */ + volatile uint32_t eoi; + /* reserverd (0x18) */ + volatile uint32_t resv1; + /* WDT Protection level Register (0x1c) */ + volatile uint32_t prot_level; + /* reserved (0x20-0xe0) */ + volatile uint32_t resv4[49]; + /* WDT Component Parameters Register 5 (0xe4) */ + volatile uint32_t comp_param_5; + /* WDT Component Parameters Register 4 (0xe8) */ + volatile uint32_t comp_param_4; + /* WDT Component Parameters Register 3 (0xec) */ + volatile uint32_t comp_param_3; + /* WDT Component Parameters Register 2 (0xf0) */ + volatile uint32_t comp_param_2; + /* WDT Component Parameters Register 1 (0xf4) */ + volatile uint32_t comp_param_1; + /* WDT Component Version Register (0xf8) */ + volatile uint32_t comp_version; + /* WDT Component Type Register (0xfc) */ + volatile uint32_t comp_type; +} __attribute__((packed, aligned(4))) k230_wdt_t; + + +#endif /* DRV_WDT_H_ */ \ No newline at end of file diff --git a/bsp/k230/drivers/utest/SConscript b/bsp/k230/drivers/utest/SConscript new file mode 100644 index 00000000000..d8032f39235 --- /dev/null +++ b/bsp/k230/drivers/utest/SConscript @@ -0,0 +1,12 @@ +from building import * + +src = [] + +if GetDepend('RT_UTEST_USING_ALL_CASES') or GetDepend('BSP_UTEST_DRIVERS'): + + if GetDepend('BSP_USING_WDT'): + src += ['test_wdt.c'] + +group = DefineGroup('utestcases', src, depend = ['']) + +Return('group') diff --git a/bsp/k230/drivers/utest/test_wdt.c b/bsp/k230/drivers/utest/test_wdt.c new file mode 100644 index 00000000000..6736ca7f342 --- /dev/null +++ b/bsp/k230/drivers/utest/test_wdt.c @@ -0,0 +1,170 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * Refer to https://www.rt-thread.org/document/api/iwdg_sample_8c-example.html + * This is a watchdog device test routine, the program searches for the watchdog + * device by device name, then initializes the device and sets the watchdog + * device overflow time. + * + * "test_wdt_feed" tests that the watchdog timer will not time out when the + * watchdog is fed and will not cause the system to restart. + * + * "test_wdt_nofeed" tests that the watchdog timer will time out when the + * watchdog is not fed and cause the system to restart. + */ + +#include +#include + +#include "../interdrv/wdt/drv_wdt.h" +#include "utest.h" + +/* Default watchdog device name */ +/* If WDT0 and WDT1 both enabled, we use WDT0 */ +#ifdef BSP_USING_WDT0 +#define IWDG_DEVICE_NAME "wdt0" +#elif defined(BSP_USING_WDT1) +#define IWDG_DEVICE_NAME "wdt1" +#else +#error "No watchdog device defined!" +#endif + +/* Watchdog device handle */ +static rt_device_t wdg_dev; + +/* + * Dog feeding flag, 1 means feeding the dog, 0 means not feeding the dog. + * This flag is used in the idle thread callback function. + * If the dog is not fed, the system will restart due to watchdog timeout. + */ +static int flag_feed; + +/* Overflow time, in seconds. */ +static rt_uint32_t timeout = 3; + +static void idle_hook(void) +{ + /* Feed the dog in the callback function of the idle thread */ + if (flag_feed) + rt_device_control(wdg_dev, KD_DEVICE_CTRL_WDT_KEEPALIVE, NULL); + + /* Do not print, otherwise the screen will display too much. */ +} + +static void waiting_for_timeout(int seconds) +{ + LOG_I("Waiting for watchdog timer time-out...\n"); + for (int i = 0; i < seconds; i++) + { + rt_thread_mdelay(1000); + LOG_I("."); + } +} + +static void test_wdt_feed(void) +{ + rt_err_t ret = RT_EOK; + + /* Find the watchdog device according to the name and obtain the handle */ + wdg_dev = rt_device_find(IWDG_DEVICE_NAME); + if (!wdg_dev) + { + LOG_E("find %s failed!\n", IWDG_DEVICE_NAME); + return; + } + + /* Initialize the device */ + ret = rt_device_init(wdg_dev); + if (ret != RT_EOK) + { + LOG_E("initialize %s failed!\n", IWDG_DEVICE_NAME); + return; + } + + /* Set the watchdog timeout time */ + ret = rt_device_control(wdg_dev, KD_DEVICE_CTRL_WDT_SET_TIMEOUT, &timeout); + if (ret != RT_EOK) + { + LOG_E("set %s timeout failed!\n", IWDG_DEVICE_NAME); + return; + } + + flag_feed = 1; /* Set feed the dog sign */ + + /* start watchdog timer */ + rt_device_control(wdg_dev, KD_DEVICE_CTRL_WDT_START, RT_NULL); + LOG_I("Watchdog Timer [%s] is launched!\n", IWDG_DEVICE_NAME); + + /* Delay enough time to see if the system will be restarted by the watchdog */ + waiting_for_timeout(10); + + LOG_I("Thanks for feeding me, I'm still alive!\n"); + /* If you feed the dog successfully, you will have a chance to come here and close the gate dog. */ + rt_device_close(wdg_dev); + LOG_I("Watchdog is closed!\n"); + + LOG_I("Test Done with Feed!\n"); + + return; +} + +static void test_wdt_nofeed(void) +{ + rt_err_t ret = RT_EOK; + + /* Find the watchdog device according to the name and obtain the handle */ + wdg_dev = rt_device_find(IWDG_DEVICE_NAME); + if (!wdg_dev) + { + LOG_E("find %s failed!\n", IWDG_DEVICE_NAME); + return; + } + + /* Initialize the device */ + ret = rt_device_init(wdg_dev); + if (ret != RT_EOK) + { + LOG_E("initialize %s failed!\n", IWDG_DEVICE_NAME); + return; + } + + /* Set the watchdog timeout time */ + ret = rt_device_control(wdg_dev, KD_DEVICE_CTRL_WDT_SET_TIMEOUT, &timeout); + if (ret != RT_EOK) + { + LOG_E("set %s timeout failed!\n", IWDG_DEVICE_NAME); + return; + } + + flag_feed = 0; /* Do not feed the dog */ + + rt_device_control(wdg_dev, KD_DEVICE_CTRL_WDT_START, RT_NULL); + LOG_I("Watchdog Timer [%s] is launched!\n", IWDG_DEVICE_NAME); + + /* Delay long enough and the system should reboot due to watchdog timeout. */ + LOG_I("Oops, I am so hungary and will be killed in seconds!\n"); + waiting_for_timeout(10); + + LOG_I("SHOULD NOT SEE THIS PRINT!\n"); + + return; +} + +static void test_wdt (void) +{ + UTEST_UNIT_RUN(test_wdt_feed); + UTEST_UNIT_RUN(test_wdt_nofeed); +} + +static rt_err_t utest_init(void) +{ + flag_feed = 0; + rt_thread_idle_sethook(idle_hook); + return RT_EOK; +} + +UTEST_TC_EXPORT(test_wdt, "wdt", utest_init, NULL, 10); \ No newline at end of file From 3c2897fe9242b9d6f557b213a87d89a41047b04c Mon Sep 17 00:00:00 2001 From: zhangjing Date: Thu, 3 Apr 2025 10:30:30 +0800 Subject: [PATCH 04/15] [libcpu][risc-v] fix:only map the 1GB space where the original code segment is located --- libcpu/risc-v/common64/mmu.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/libcpu/risc-v/common64/mmu.c b/libcpu/risc-v/common64/mmu.c index 6cab811eca7..a260a06e581 100644 --- a/libcpu/risc-v/common64/mmu.c +++ b/libcpu/risc-v/common64/mmu.c @@ -691,11 +691,10 @@ void rt_hw_mem_setup_early(void) * identical mapping, * PC are still at lower region before relocating to high memory */ - for (size_t i = 0; i < __SIZE(PPN0_BIT); i++) - { - early_pgtbl[i] = COMBINEPTE(ps, MMU_MAP_EARLY); - ps += L1_PAGE_SIZE; - } + rt_ubase_t pg_idx ; + ps = (rt_ubase_t)symb_pc & (~(L1_PAGE_SIZE - 1)); + pg_idx = GET_L1(ps); + early_pgtbl[pg_idx] = COMBINEPTE(ps, MMU_MAP_EARLY); /* relocate text region */ __asm__ volatile("la %0, _start\n" : "=r"(ps)); From 9777a9662b777727411fd7783f9586b4736579fe Mon Sep 17 00:00:00 2001 From: zhangjing Date: Wed, 28 May 2025 09:38:54 +0000 Subject: [PATCH 05/15] [libcpu][risc-v]:add comment for the round down of symb_pc --- libcpu/risc-v/common64/mmu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/libcpu/risc-v/common64/mmu.c b/libcpu/risc-v/common64/mmu.c index a260a06e581..19c7f7c0195 100644 --- a/libcpu/risc-v/common64/mmu.c +++ b/libcpu/risc-v/common64/mmu.c @@ -692,6 +692,9 @@ void rt_hw_mem_setup_early(void) * PC are still at lower region before relocating to high memory */ rt_ubase_t pg_idx ; + /* Round down symb_pc to L1_PAGE_SIZE boundary to ensure proper page alignment. + * This is necessary because MMU operations work with page-aligned addresses, and + * make sure all the text region is mapped.*/ ps = (rt_ubase_t)symb_pc & (~(L1_PAGE_SIZE - 1)); pg_idx = GET_L1(ps); early_pgtbl[pg_idx] = COMBINEPTE(ps, MMU_MAP_EARLY); From 425ac775d5987847d3931a476be8726b2269fa6b Mon Sep 17 00:00:00 2001 From: qianjiuyuan <149981328+heyQianJiu@users.noreply.github.com> Date: Thu, 29 May 2025 11:49:48 +0800 Subject: [PATCH 06/15] =?UTF-8?q?[bsp]stm32f103-keysking=20=E9=A9=B1?= =?UTF-8?q?=E5=8A=A8=EF=BC=9Auart=E3=80=81pwm=E3=80=81pulse=20encoder=20(#?= =?UTF-8?q?10330)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../.ci/attachconfig/ci.attachconfig.yml | 19 +- .../stm32f103-keysking-learning/README.md | 21 +- .../board/CubeMX_Config/.mxproject | 4 +- .../board/CubeMX_Config/CubeMX_Config.ioc | 69 +++++- .../CubeMX_Config/Inc/stm32f1xx_hal_conf.h | 2 +- .../CubeMX_Config/Src/stm32f1xx_hal_msp.c | 221 +++++++++++++++++- .../stm32f103-keysking-learning/board/Kconfig | 67 +++++- .../stm32f103-keysking-learning/project.ewp | 104 ++++----- .../project.uvprojx | 84 +++---- 9 files changed, 469 insertions(+), 122 deletions(-) diff --git a/bsp/stm32/stm32f103-keysking-learning/.ci/attachconfig/ci.attachconfig.yml b/bsp/stm32/stm32f103-keysking-learning/.ci/attachconfig/ci.attachconfig.yml index ad74d731f5e..44c1b881af1 100644 --- a/bsp/stm32/stm32f103-keysking-learning/.ci/attachconfig/ci.attachconfig.yml +++ b/bsp/stm32/stm32f103-keysking-learning/.ci/attachconfig/ci.attachconfig.yml @@ -1,16 +1,21 @@ scons.args: &scons scons_arg: - '--strict' -system.use_nano: + + + +devices.uart: <<: *scons kconfig: - CONFIG_RT_USING_NANO=y -devices.gpio: + - CONFIG_BSP_USING_GPIO=y + - CONFIG_BSP_USING_UART=y + - CONFIG_USING_SERIAL=y +devices.servo: <<: *scons kconfig: - - CONFIG_BSP_USING_GPIO=y -devices.uart: + - CONFIG_BSP_USING_SERVO=y +devices.pulse_encoder: <<: *scons kconfig: - - CONFIG_BSP_USING_UART=y - - CONFIG_USING_SERIAL=y \ No newline at end of file + - CONFIG_BSP_USING_PULSE_ENCODER=y + - CONFIG_BSP_USING_PULSE_ENCODER1=y diff --git a/bsp/stm32/stm32f103-keysking-learning/README.md b/bsp/stm32/stm32f103-keysking-learning/README.md index 3b1e26bedf0..1bb845c0393 100644 --- a/bsp/stm32/stm32f103-keysking-learning/README.md +++ b/bsp/stm32/stm32f103-keysking-learning/README.md @@ -41,12 +41,19 @@ Keysking学习板是B站UP主Keysking推出的一块基于ARM Cortex-M3内核的 本BSP目前对外设的支持情况如下： -| 板载外设 | 支持情况 | 备注 | -| -------- |:--------:| ------- | -| USB转串口 | 支持 | UART2 | -| **片上外设** | **支持情况** | **备注** | -| GPIO | 支持 | | -| UART | 支持 | UART1,2 | +| 板载外设 | 支持情况 | 备注 | +|------------|:--------:|--------------------------------------------| +| USB转串口 | 支持 | UART2(用作finsh) | +| 旋转编码器 | 支持 | A相(PA8),B相(PA9),按键(PB15) | +| OLED | | | +| LED | 支持 | GPIO or PWM: Blue(PA6)，Green(PA7)，Red(PB0) | +| 无源蜂鸣器 | 支持 | PWM4_CH4 | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | | +| UART | 支持 | UART2,3 | +| PWM | 支持 | PWM3,PWM4 | +| **预留外设接口** | **支持情况** | **备注** | +| SERVO | 支持 | PWM4_CH3 | ## 使用说明 @@ -120,4 +127,4 @@ STM32F103C8T6的Flash在官方文档中的大小是64KB，但是其实该芯片 维护人: -* qianjiuyuan, 邮箱:<3211471056@qq.com> +* qianjiuyuan, 邮箱: diff --git a/bsp/stm32/stm32f103-keysking-learning/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32f103-keysking-learning/board/CubeMX_Config/.mxproject index 6445cb89afa..f3c11fac742 100644 --- a/bsp/stm32/stm32f103-keysking-learning/board/CubeMX_Config/.mxproject +++ b/bsp/stm32/stm32f103-keysking-learning/board/CubeMX_Config/.mxproject @@ -1,8 +1,8 @@ [PreviousLibFiles] -LibFiles=Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_tim.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_tim_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_uart.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_usart.h;Drivers\STM32F1xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_def.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_rcc.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_rcc_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_bus.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_rcc.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_system.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_utils.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_gpio.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_gpio_ex.h;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_gpio.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_dma_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_dma.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_dma.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_cortex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_cortex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_pwr.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_pwr.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_flash.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_flash_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_exti.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_exti.h;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_uart.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_dma.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cortex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pwr.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_exti.c;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_tim.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_tim_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_uart.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_usart.h;Drivers\STM32F1xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_def.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_rcc.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_rcc_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_bus.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_rcc.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_system.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_utils.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_gpio.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_gpio_ex.h;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_gpio.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_dma_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_dma.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_dma.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_cortex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_cortex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_pwr.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_pwr.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_flash.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_flash_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_exti.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_exti.h;Drivers\CMSIS\Device\ST\STM32F1xx\Include\stm32f103xb.h;Drivers\CMSIS\Device\ST\STM32F1xx\Include\stm32f1xx.h;Drivers\CMSIS\Device\ST\STM32F1xx\Include\system_stm32f1xx.h;Drivers\CMSIS\Device\ST\STM32F1xx\Include\system_stm32f1xx.h;Drivers\CMSIS\Device\ST\STM32F1xx\Source\Templates\system_stm32f1xx.c;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\tz_context.h; +LibFiles=Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_tim.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_tim_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_tim.h;Drivers\STM32F1xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_def.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_rcc.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_rcc_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_bus.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_rcc.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_system.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_utils.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_gpio.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_gpio_ex.h;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_gpio.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_dma_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_dma.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_dma.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_cortex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_cortex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_pwr.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_pwr.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_flash.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_flash_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_exti.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_exti.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_uart.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_usart.h;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_dma.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cortex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pwr.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_exti.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_uart.c;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_tim.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_tim_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_tim.h;Drivers\STM32F1xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_def.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_rcc.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_rcc_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_bus.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_rcc.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_system.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_utils.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_gpio.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_gpio_ex.h;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_gpio.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_dma_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_dma.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_dma.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_cortex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_cortex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_pwr.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_pwr.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_flash.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_flash_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_exti.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_exti.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_uart.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_usart.h;Drivers\CMSIS\Device\ST\STM32F1xx\Include\stm32f103xb.h;Drivers\CMSIS\Device\ST\STM32F1xx\Include\stm32f1xx.h;Drivers\CMSIS\Device\ST\STM32F1xx\Include\system_stm32f1xx.h;Drivers\CMSIS\Device\ST\STM32F1xx\Include\system_stm32f1xx.h;Drivers\CMSIS\Device\ST\STM32F1xx\Source\Templates\system_stm32f1xx.c;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\tz_context.h; [PreviousUsedKeilFiles] -SourceFiles=..\Src\main.c;..\Src\stm32f1xx_it.c;..\Src\stm32f1xx_hal_msp.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim_ex.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_uart.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc_ex.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_dma.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cortex.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pwr.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash_ex.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_exti.c;..\Drivers\CMSIS\Device\ST\STM32F1xx\Source\Templates\system_stm32f1xx.c;..\\Src\system_stm32f1xx.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim_ex.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_uart.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc_ex.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_dma.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cortex.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pwr.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash_ex.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_exti.c;..\Drivers\CMSIS\Device\ST\STM32F1xx\Source\Templates\system_stm32f1xx.c;..\\Src\system_stm32f1xx.c;;; +SourceFiles=..\Src\main.c;..\Src\stm32f1xx_it.c;..\Src\stm32f1xx_hal_msp.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim_ex.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc_ex.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_dma.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cortex.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pwr.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash_ex.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_exti.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_uart.c;..\Drivers\CMSIS\Device\ST\STM32F1xx\Source\Templates\system_stm32f1xx.c;..\\Src\system_stm32f1xx.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim_ex.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc_ex.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_dma.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cortex.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pwr.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash_ex.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_exti.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_uart.c;..\Drivers\CMSIS\Device\ST\STM32F1xx\Source\Templates\system_stm32f1xx.c;..\\Src\system_stm32f1xx.c;;; HeaderPath=..\Drivers\STM32F1xx_HAL_Driver\Inc;..\Drivers\STM32F1xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F1xx\Include;..\Drivers\CMSIS\Include;..\Inc; CDefines=USE_HAL_DRIVER;STM32F103xB;USE_HAL_DRIVER;USE_HAL_DRIVER; diff --git a/bsp/stm32/stm32f103-keysking-learning/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f103-keysking-learning/board/CubeMX_Config/CubeMX_Config.ioc index 110cf73b9c0..31fdf3fc0b1 100644 --- a/bsp/stm32/stm32f103-keysking-learning/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32f103-keysking-learning/board/CubeMX_Config/CubeMX_Config.ioc @@ -10,20 +10,33 @@ Mcu.Family=STM32F1 Mcu.IP0=NVIC Mcu.IP1=RCC Mcu.IP2=SYS -Mcu.IP3=USART2 -Mcu.IPNb=4 +Mcu.IP3=TIM1 +Mcu.IP4=TIM3 +Mcu.IP5=TIM4 +Mcu.IP6=USART2 +Mcu.IP7=USART3 +Mcu.IPNb=8 Mcu.Name=STM32F103C(8-B)Tx Mcu.Package=LQFP48 Mcu.Pin0=PC14-OSC32_IN Mcu.Pin1=PC15-OSC32_OUT +Mcu.Pin10=PA9 +Mcu.Pin11=PA13 +Mcu.Pin12=PA14 +Mcu.Pin13=PB8 +Mcu.Pin14=PB9 +Mcu.Pin15=VP_SYS_VS_Systick +Mcu.Pin16=VP_TIM3_VS_ClockSourceINT +Mcu.Pin17=VP_TIM4_VS_ClockSourceINT Mcu.Pin2=PD0-OSC_IN Mcu.Pin3=PD1-OSC_OUT Mcu.Pin4=PA2 Mcu.Pin5=PA3 -Mcu.Pin6=PA13 -Mcu.Pin7=PA14 -Mcu.Pin8=VP_SYS_VS_Systick -Mcu.PinsNb=9 +Mcu.Pin6=PA6 +Mcu.Pin7=PB10 +Mcu.Pin8=PB11 +Mcu.Pin9=PA8 +Mcu.PinsNb=18 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32F103C8Tx @@ -52,6 +65,17 @@ PA3.GPIOParameters=GPIO_PuPd PA3.GPIO_PuPd=GPIO_PULLUP PA3.Mode=Asynchronous PA3.Signal=USART2_RX +PA6.Locked=true +PA6.Signal=S_TIM3_CH1 +PA8.Signal=S_TIM1_CH1 +PA9.Signal=S_TIM1_CH2 +PB10.Mode=Asynchronous +PB10.Signal=USART3_TX +PB11.Mode=Asynchronous +PB11.Signal=USART3_RX +PB8.Locked=true +PB8.Signal=S_TIM4_CH3 +PB9.Signal=S_TIM4_CH4 PC14-OSC32_IN.Mode=LSE-External-Oscillator PC14-OSC32_IN.Signal=RCC_OSC32_IN PC15-OSC32_OUT.Mode=LSE-External-Oscillator @@ -91,7 +115,7 @@ ProjectManager.ToolChainLocation= ProjectManager.UAScriptAfterPath= ProjectManager.UAScriptBeforePath= ProjectManager.UnderRoot=false -ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART2_UART_Init-USART2-false-HAL-true +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART2_UART_Init-USART2-false-HAL-true,4-MX_USART3_UART_Init-USART3-false-HAL-true,5-MX_TIM3_Init-TIM3-false-HAL-true,6-MX_TIM4_Init-TIM4-false-HAL-true,7-MX_TIM1_Init-TIM1-false-HAL-true RCC.ADCFreqValue=12000000 RCC.ADCPresc=RCC_ADCPCLK2_DIV6 RCC.AHBFreq_Value=72000000 @@ -103,20 +127,47 @@ RCC.APB2TimFreq_Value=72000000 RCC.FCLKCortexFreq_Value=72000000 RCC.FamilyName=M RCC.HCLKFreq_Value=72000000 -RCC.IPParameters=ADCFreqValue,ADCPresc,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLMUL,PLLSourceVirtual,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USBFreq_Value,USBPrescaler,VCOOutput2Freq_Value -RCC.MCOFreq_Value=72000000 +RCC.IPParameters=ADCFreqValue,ADCPresc,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLMUL,PLLSourceVirtual,RCC_MCOSource,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USBFreq_Value,USBPrescaler,VCOOutput2Freq_Value +RCC.MCOFreq_Value=36000000 RCC.PLLCLKFreq_Value=72000000 RCC.PLLMCOFreq_Value=36000000 RCC.PLLMUL=RCC_PLL_MUL9 RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE +RCC.RCC_MCOSource=RCC_MCO1SOURCE_PLLCLK RCC.SYSCLKFreq_VALUE=72000000 RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK RCC.TimSysFreq_Value=72000000 RCC.USBFreq_Value=48000000 RCC.USBPrescaler=RCC_USBCLKSOURCE_PLL_DIV1_5 RCC.VCOOutput2Freq_Value=8000000 +SH.S_TIM1_CH1.0=TIM1_CH1,Encoder_Interface +SH.S_TIM1_CH1.ConfNb=1 +SH.S_TIM1_CH2.0=TIM1_CH2,Encoder_Interface +SH.S_TIM1_CH2.ConfNb=1 +SH.S_TIM3_CH1.0=TIM3_CH1,PWM Generation1 CH1 +SH.S_TIM3_CH1.ConfNb=1 +SH.S_TIM4_CH3.0=TIM4_CH3,PWM Generation3 CH3 +SH.S_TIM4_CH3.ConfNb=1 +SH.S_TIM4_CH4.0=TIM4_CH4,PWM Generation4 CH4 +SH.S_TIM4_CH4.ConfNb=1 +TIM1.IPParameters=Prescaler +TIM1.Prescaler=2-1 +TIM3.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1 +TIM3.IPParameters=Channel-PWM Generation1 CH1,Prescaler,Period,Pulse-PWM Generation1 CH1 +TIM3.Period=10000-1 +TIM3.Prescaler=7200-1 +TIM3.Pulse-PWM\ Generation1\ CH1=50 +TIM4.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3 +TIM4.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4 +TIM4.IPParameters=Channel-PWM Generation3 CH3,Channel-PWM Generation4 CH4 USART2.IPParameters=VirtualMode USART2.VirtualMode=VM_ASYNC +USART3.IPParameters=VirtualMode +USART3.VirtualMode=VM_ASYNC VP_SYS_VS_Systick.Mode=SysTick VP_SYS_VS_Systick.Signal=SYS_VS_Systick +VP_TIM3_VS_ClockSourceINT.Mode=Internal +VP_TIM3_VS_ClockSourceINT.Signal=TIM3_VS_ClockSourceINT +VP_TIM4_VS_ClockSourceINT.Mode=Internal +VP_TIM4_VS_ClockSourceINT.Signal=TIM4_VS_ClockSourceINT board=custom diff --git a/bsp/stm32/stm32f103-keysking-learning/board/CubeMX_Config/Inc/stm32f1xx_hal_conf.h b/bsp/stm32/stm32f103-keysking-learning/board/CubeMX_Config/Inc/stm32f1xx_hal_conf.h index a0fcf27f579..705db016ae6 100644 --- a/bsp/stm32/stm32f103-keysking-learning/board/CubeMX_Config/Inc/stm32f1xx_hal_conf.h +++ b/bsp/stm32/stm32f103-keysking-learning/board/CubeMX_Config/Inc/stm32f1xx_hal_conf.h @@ -64,7 +64,7 @@ /*#define HAL_SMARTCARD_MODULE_ENABLED */ /*#define HAL_SPI_MODULE_ENABLED */ /*#define HAL_SRAM_MODULE_ENABLED */ -/*#define HAL_TIM_MODULE_ENABLED */ +#define HAL_TIM_MODULE_ENABLED #define HAL_UART_MODULE_ENABLED /*#define HAL_USART_MODULE_ENABLED */ /*#define HAL_WWDG_MODULE_ENABLED */ diff --git a/bsp/stm32/stm32f103-keysking-learning/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c b/bsp/stm32/stm32f103-keysking-learning/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c index 4b76386bac6..b9949f5e689 100644 --- a/bsp/stm32/stm32f103-keysking-learning/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c +++ b/bsp/stm32/stm32f103-keysking-learning/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c @@ -58,7 +58,9 @@ /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ -/** + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + /** * Initializes the Global MSP. */ void HAL_MspInit(void) @@ -81,6 +83,178 @@ void HAL_MspInit(void) /* USER CODE END MspInit 1 */ } +/** +* @brief TIM_Encoder MSP Initialization +* This function configures the hardware resources used in this example +* @param htim_encoder: TIM_Encoder handle pointer +* @retval None +*/ +void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* htim_encoder) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(htim_encoder->Instance==TIM1) + { + /* USER CODE BEGIN TIM1_MspInit 0 */ + + /* USER CODE END TIM1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**TIM1 GPIO Configuration + PA8 ------> TIM1_CH1 + PA9 ------> TIM1_CH2 + */ + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN TIM1_MspInit 1 */ + + /* USER CODE END TIM1_MspInit 1 */ + } + +} + +/** +* @brief TIM_Base MSP Initialization +* This function configures the hardware resources used in this example +* @param htim_base: TIM_Base handle pointer +* @retval None +*/ +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) +{ + if(htim_base->Instance==TIM3) + { + /* USER CODE BEGIN TIM3_MspInit 0 */ + + /* USER CODE END TIM3_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM3_CLK_ENABLE(); + /* USER CODE BEGIN TIM3_MspInit 1 */ + + /* USER CODE END TIM3_MspInit 1 */ + } + else if(htim_base->Instance==TIM4) + { + /* USER CODE BEGIN TIM4_MspInit 0 */ + + /* USER CODE END TIM4_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM4_CLK_ENABLE(); + /* USER CODE BEGIN TIM4_MspInit 1 */ + + /* USER CODE END TIM4_MspInit 1 */ + } + +} + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(htim->Instance==TIM3) + { + /* USER CODE BEGIN TIM3_MspPostInit 0 */ + + /* USER CODE END TIM3_MspPostInit 0 */ + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**TIM3 GPIO Configuration + PA6 ------> TIM3_CH1 + */ + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN TIM3_MspPostInit 1 */ + + /* USER CODE END TIM3_MspPostInit 1 */ + } + else if(htim->Instance==TIM4) + { + /* USER CODE BEGIN TIM4_MspPostInit 0 */ + + /* USER CODE END TIM4_MspPostInit 0 */ + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**TIM4 GPIO Configuration + PB8 ------> TIM4_CH3 + PB9 ------> TIM4_CH4 + */ + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN TIM4_MspPostInit 1 */ + + /* USER CODE END TIM4_MspPostInit 1 */ + } + +} +/** +* @brief TIM_Encoder MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param htim_encoder: TIM_Encoder handle pointer +* @retval None +*/ +void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef* htim_encoder) +{ + if(htim_encoder->Instance==TIM1) + { + /* USER CODE BEGIN TIM1_MspDeInit 0 */ + + /* USER CODE END TIM1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM1_CLK_DISABLE(); + + /**TIM1 GPIO Configuration + PA8 ------> TIM1_CH1 + PA9 ------> TIM1_CH2 + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_8|GPIO_PIN_9); + + /* USER CODE BEGIN TIM1_MspDeInit 1 */ + + /* USER CODE END TIM1_MspDeInit 1 */ + } + +} + +/** +* @brief TIM_Base MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param htim_base: TIM_Base handle pointer +* @retval None +*/ +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base) +{ + if(htim_base->Instance==TIM3) + { + /* USER CODE BEGIN TIM3_MspDeInit 0 */ + + /* USER CODE END TIM3_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM3_CLK_DISABLE(); + /* USER CODE BEGIN TIM3_MspDeInit 1 */ + + /* USER CODE END TIM3_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM4) + { + /* USER CODE BEGIN TIM4_MspDeInit 0 */ + + /* USER CODE END TIM4_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM4_CLK_DISABLE(); + /* USER CODE BEGIN TIM4_MspDeInit 1 */ + + /* USER CODE END TIM4_MspDeInit 1 */ + } + +} + /** * @brief UART MSP Initialization * This function configures the hardware resources used in this example @@ -117,6 +291,33 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspInit 1 */ } + else if(huart->Instance==USART3) + { + /* USER CODE BEGIN USART3_MspInit 0 */ + + /* USER CODE END USART3_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_USART3_CLK_ENABLE(); + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**USART3 GPIO Configuration + PB10 ------> USART3_TX + PB11 ------> USART3_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_11; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN USART3_MspInit 1 */ + + /* USER CODE END USART3_MspInit 1 */ + } } @@ -146,6 +347,24 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART2_MspDeInit 1 */ } + else if(huart->Instance==USART3) + { + /* USER CODE BEGIN USART3_MspDeInit 0 */ + + /* USER CODE END USART3_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART3_CLK_DISABLE(); + + /**USART3 GPIO Configuration + PB10 ------> USART3_TX + PB11 ------> USART3_RX + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_10|GPIO_PIN_11); + + /* USER CODE BEGIN USART3_MspDeInit 1 */ + + /* USER CODE END USART3_MspDeInit 1 */ + } } diff --git a/bsp/stm32/stm32f103-keysking-learning/board/Kconfig b/bsp/stm32/stm32f103-keysking-learning/board/Kconfig index ee4349ab832..2f1ed35e5cb 100644 --- a/bsp/stm32/stm32f103-keysking-learning/board/Kconfig +++ b/bsp/stm32/stm32f103-keysking-learning/board/Kconfig @@ -7,6 +7,13 @@ menu "Onboard Peripheral Drivers" select BSP_USING_UART select BSP_USING_UART2 default y + config BSP_USING_SERVO + bool "Enable Servo" + select BSP_USING_PWM + select BSP_USING_PWM4 + select BSP_USING_PWM4_CH3 + default n + endmenu @@ -23,7 +30,6 @@ menu "On-chip Peripheral Drivers" select RT_USING_SERIAL if BSP_USING_UART - config BSP_STM32_UART_V1_TX_TIMEOUT int "UART TX timeout" default 2000 @@ -31,15 +37,74 @@ menu "On-chip Peripheral Drivers" config BSP_USING_UART2 bool "Enable UART2" default y + config BSP_USING_UART3 + bool "Enable UART3" + default y #config BSP_UART2_RX_USING_DMA # bool "Enable UART2 RX DMA" # depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA # default n + endif + + menuconfig BSP_USING_PWM + bool "Enable PWM" + select RT_USING_PWM + default n + + if BSP_USING_PWM + menuconfig BSP_USING_PWM3 + bool "Enable PWM3" + default y + if BSP_USING_PWM3 + config BSP_USING_PWM3_CH1 + bool "Enable PWM3_CH1(PA6,Blue LED)" + default y + config BSP_USING_PWM3_CH2 + bool "Enable PWM3_CH2(PA7,Green LED)" + default n + config BSP_USING_PWM3_CH3 + bool "Enable PWM3_CH3(PB0,Red LED)" + default n + config BSP_USING_PWM3_CH4 + bool "Enable PWM3_CH4" + default n + endif + + menuconfig BSP_USING_PWM4 + bool "Enable PWM4" + default n + if BSP_USING_PWM4 + config BSP_USING_PWM4_CH1 + bool "Enable PWM4_CH1" + default n + config BSP_USING_PWM4_CH2 + bool "Enable PWM4_CH2" + default n + config BSP_USING_PWM4_CH3 + bool "Enable PWM4_CH3(PB8,Servo)" + default y + config BSP_USING_PWM4_CH4 + bool "Enable PWM4_CH4(PB9,Beeper)" + default y + endif + + endif + menuconfig BSP_USING_PULSE_ENCODER + bool "Enable Pulse Encoder" + select RT_USING_PULSE_ENCODER + default n + + if BSP_USING_PULSE_ENCODER + config BSP_USING_PULSE_ENCODER1 + bool "Enable Pulse Encoder1" + default y endif + + source "$(BSP_DIR)/../libraries/HAL_Drivers/drivers/Kconfig" endmenu diff --git a/bsp/stm32/stm32f103-keysking-learning/project.ewp b/bsp/stm32/stm32f103-keysking-learning/project.ewp index 1dfedecb58b..f33d843e9e6 100644 --- a/bsp/stm32/stm32f103-keysking-learning/project.ewp +++ b/bsp/stm32/stm32f103-keysking-learning/project.ewp @@ -348,30 +348,30 @@