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Add simple UDP Ethernet packet generator
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‎udp_packet.sv

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//------------------------------------------------------------------------------
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// udp_packet.sv
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// published as part of https://github.com/pConst/basic_verilog
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// A simple hardcoded UDP packet generator
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//
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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udp_packet #(
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.MODE( "BYTES" ) // "BYTES" or "NIBBLES"
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) UP1 (
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.clk( clk ),
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.nrst( nrst ),
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.tx_en( ),
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.od( )
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);
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--- INSTANTIATION TEMPLATE END ---*/
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module udp_packet #( parameter
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MODE = "BYTES" // "BYTES" or "NIBBLES"
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)(
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input clk,
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input nrst,
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output logic tx_en = 1'b0,
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output logic [7:0] od = '0
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);
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logic [15:0] seq_cntr = '0;
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logic nibble_high = 1'b0;
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logic [7:0] data_byte;
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// tx_en and od signals are late one cycle after their respective seq_cntr[]
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always_ff @(posedge clk) begin
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if( ~nrst ) begin
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tx_en = 1'b0;
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od[7:0] = '0;
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seq_cntr[15:0] <= '0;
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nibble_high <= 1'b0;
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end else begin
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if ( MODE == "BYTES" ) begin
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tx_en <= ( (seq_cntr[15:0] >=0) &&
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(seq_cntr[15:0] <72) );
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od[7:0] <= data_byte[7:0];
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if (seq_cntr[15:0] == 255 ) begin
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// sequence reset
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seq_cntr[15:0] <= '0;
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end else begin
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seq_cntr[15:0] <= seq_cntr[15:0] + 1'b1;
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end
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end else begin
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tx_en <= ( (seq_cntr[15:0] >=0) &&
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(seq_cntr[15:0] <72) );
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if( nibble_high ) begin
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od[7:0] <= {4'h0,data_byte[3:0]};
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if (seq_cntr[15:0] == 127 ) begin
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// sequence reset
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seq_cntr[15:0] <= '0;
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end else begin
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seq_cntr[15:0] <= seq_cntr[15:0] + 1'b1;
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end
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end else begin
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od[7:0] <= {4'h0,data_byte[7:4]};
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end // if
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nibble_high <= !nibble_high;
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end // if
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end
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end
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always_comb begin
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case ( seq_cntr[15:0] )
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// Sending the preambule and asserting tx_en
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0 : data_byte[7:0] <= 8'h55;
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1 : data_byte[7:0] <= 8'h55;
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2 : data_byte[7:0] <= 8'h55;
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3 : data_byte[7:0] <= 8'h55;
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4 : data_byte[7:0] <= 8'h55;
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5 : data_byte[7:0] <= 8'h55;
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6 : data_byte[7:0] <= 8'h55;
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7 : data_byte[7:0] <= 8'hd5;
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// Sending the UDP/IP-packet itself
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8 : data_byte[7:0] <= 8'hd8;
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9 : data_byte[7:0] <= 8'hd3;
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10: data_byte[7:0] <= 8'h85;
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11: data_byte[7:0] <= 8'h26;
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12: data_byte[7:0] <= 8'hc5;
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13: data_byte[7:0] <= 8'h78;
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14: data_byte[7:0] <= 8'h00;
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15: data_byte[7:0] <= 8'h23;
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16: data_byte[7:0] <= 8'h54;
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17: data_byte[7:0] <= 8'h3c;
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18: data_byte[7:0] <= 8'h47;
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19: data_byte[7:0] <= 8'h1b;
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20: data_byte[7:0] <= 8'h08;
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21: data_byte[7:0] <= 8'h00;
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22: data_byte[7:0] <= 8'h45;
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23: data_byte[7:0] <= 8'h00;
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24: data_byte[7:0] <= 8'h00;
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25: data_byte[7:0] <= 8'h2e;
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26: data_byte[7:0] <= 8'h00;
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27: data_byte[7:0] <= 8'h00;
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28: data_byte[7:0] <= 8'h00;
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29: data_byte[7:0] <= 8'h00;
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30: data_byte[7:0] <= 8'hc8;
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31: data_byte[7:0] <= 8'h11;
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32: data_byte[7:0] <= 8'hd6;
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33: data_byte[7:0] <= 8'h73;
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34: data_byte[7:0] <= 8'hc0;
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35: data_byte[7:0] <= 8'ha8;
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36: data_byte[7:0] <= 8'h4d;
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37: data_byte[7:0] <= 8'h21;
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38: data_byte[7:0] <= 8'hc0;
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39: data_byte[7:0] <= 8'ha8;
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40: data_byte[7:0] <= 8'h4d;
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41: data_byte[7:0] <= 8'hd9;
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42: data_byte[7:0] <= 8'hc3;
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43: data_byte[7:0] <= 8'h50;
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44: data_byte[7:0] <= 8'hc3;
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45: data_byte[7:0] <= 8'h60;
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46: data_byte[7:0] <= 8'h00;
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47: data_byte[7:0] <= 8'h1a;
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48: data_byte[7:0] <= 8'h00;
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49: data_byte[7:0] <= 8'h00;
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50: data_byte[7:0] <= 8'h01;
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51: data_byte[7:0] <= 8'h02;
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52: data_byte[7:0] <= 8'h03;
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53: data_byte[7:0] <= 8'h04;
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54: data_byte[7:0] <= 8'h01;
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55: data_byte[7:0] <= 8'h01;
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56: data_byte[7:0] <= 8'h01;
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57: data_byte[7:0] <= 8'h01;
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58: data_byte[7:0] <= 8'h01;
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59: data_byte[7:0] <= 8'h01;
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60: data_byte[7:0] <= 8'h01;
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61: data_byte[7:0] <= 8'h01;
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62: data_byte[7:0] <= 8'h01;
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63: data_byte[7:0] <= 8'h01;
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64: data_byte[7:0] <= 8'h01;
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65: data_byte[7:0] <= 8'h01;
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66: data_byte[7:0] <= 8'h01;
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67: data_byte[7:0] <= 8'h01;
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// CRC32 checksum
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68: data_byte[7:0] <= 8'he3;
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69: data_byte[7:0] <= 8'h8e;
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70: data_byte[7:0] <= 8'hdf;
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71: data_byte[7:0] <= 8'h1f;
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default: data_byte[7:0] <= '0; // pause
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endcase
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end
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endmodule
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‎udp_packet_tb.sv

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//------------------------------------------------------------------------------
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// udp_packet_tb.sv
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// published as part of https://github.com/pConst/basic_verilog
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// udp_packet testbench
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// use this define to make some things differently in simulation
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`define SIMULATION yes
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`timescale 1ns / 1ps
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module udp_packet_tb();
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initial begin
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// Print out time markers in nanoseconds
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// Example: $display("[T=%0t] start=%d", $realtime, start);
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$timeformat(-9, 3, " ns");
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// seed value setting is intentionally manual to achieve repeatability between sim runs
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$urandom( 1 ); // SEED value
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end
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logic clk200;
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sim_clk_gen #(
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.FREQ( 200_000_000 ), // in Hz
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.PHASE( 0 ), // in degrees
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.DUTY( 50 ), // in percentage
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.DISTORT( 10 ) // in picoseconds
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) clk200_gen (
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.ena( 1'b1 ),
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.clk( clk200 ),
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.clkd( )
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);
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logic nrst_once;
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logic [31:0] clk200_div;
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clk_divider #(
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.WIDTH( 32 )
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) cd1 (
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.clk( clk200 ),
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.nrst( nrst_once ),
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.ena( 1'b1 ),
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.out( clk200_div[31:0] )
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);
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logic [31:0] clk200_div_rise;
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edge_detect ed1[31:0] (
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.clk( {32{clk200}} ),
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.anrst( {32{nrst_once}} ),
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.in( clk200_div[31:0] ),
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.rising( clk200_div_rise[31:0] ),
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.falling( ),
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.both( )
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);
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// external device "asynchronous" clock
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logic clk33;
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logic clk33d;
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sim_clk_gen #(
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.FREQ( 200_000_000 ), // in Hz
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.PHASE( 0 ), // in degrees
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.DUTY( 50 ), // in percentage
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.DISTORT( 1000 ) // in picoseconds
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) clk33_gen (
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.ena( 1'b1 ),
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.clk( clk33 ),
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.clkd( clk33d )
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);
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logic rst;
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initial begin
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rst = 1'b0; // initialization
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repeat( 1 ) @(posedge clk200);
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forever begin
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repeat( 1 ) @(posedge clk200); // synchronous rise
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rst = 1'b1;
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//$urandom( 1 ); // uncomment to get the same random pattern EVERY nrst
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repeat( 2 ) @(posedge clk200); // synchronous fall, controls rst pulse width
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rst = 1'b0;
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repeat( 100 ) @(posedge clk200); // controls test body width
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end
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end
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logic nrst;
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assign nrst = ~rst;
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logic rst_once;
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initial begin
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rst_once = 1'b0; // initialization
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repeat( 1 ) @(posedge clk200);
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repeat( 1 ) @(posedge clk200); // synchronous rise
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rst_once = 1'b1;
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repeat( 2 ) @(posedge clk200); // synchronous fall, controls rst_once pulse width
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rst_once = 1'b0;
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end
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//logic nrst_once; // declared before
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assign nrst_once = ~rst_once;
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// random pattern generation
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logic [31:0] rnd_data;
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always_ff @(posedge clk200) begin
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rnd_data[31:0] <= $urandom;
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end
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initial forever begin
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@(posedge nrst);
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$display("[T=%0t] rnd_data[]=%h", $realtime, rnd_data[31:0]);
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end
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// helper start strobe appears unpredictable up to 20 clocks after nrst
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logic start;
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initial forever begin
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start = 1'b0; // initialization
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@(posedge nrst); // synchronous rise after EVERY nrst
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repeat( $urandom_range(0, 20) ) @(posedge clk200);
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start = 1'b1;
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@(posedge clk200); // synchronous fall exactly 1 clock after rise
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start = 1'b0;
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end
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initial begin
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// #10000 $stop;
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// #10000 $finish;
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end
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// sweeping pulses
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logic sp = 1'b1;
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logic [4:0] sp_duty_cycle = 8'd0;
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initial forever begin
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if( sp_duty_cycle[4:0] == 0 ) begin
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sp = 1'b1;
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repeat( 10 ) @(posedge clk200);
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end
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sp = 1'b0;
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repeat( 1 ) @(posedge clk200);
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sp = 1'b1;
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repeat( 1 ) @(posedge clk200);
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sp = 1'b0;
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repeat( sp_duty_cycle ) @(posedge clk200);
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sp_duty_cycle[4:0] = sp_duty_cycle[4:0] + 1'b1; // overflow is expected here
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end
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// Module under test ===========================================================
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logic [15:0] seq_cntr = '0;
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logic [31:0] id = '0;
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always_ff @(posedge clk200) begin
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if( ~nrst_once ) begin
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seq_cntr[15:0] <= '0;
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id[31:0] <= '0;
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end else begin
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// incrementing sequence counter
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if( seq_cntr[15:0]!= '1 ) begin
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seq_cntr[15:0] <= seq_cntr[15:0] + 1'b1;
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end
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if( seq_cntr[15:0]<300 ) begin
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id[31:0] <= '1;
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//id[31:0] <= {4{rnd_data[15:0]}};
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end else begin
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id[31:0] <= '0;
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end
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end
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end
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udp_packet #(
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.MODE( "BYTES" ) // "BYTES" or "NIBBLES"
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) M1 (
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.clk( clk200 ),
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.nrst( nrst_once ),
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.tx_en( ),
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.od( )
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);
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udp_packet #(
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.MODE( "NIBBLES" ) // "BYTES" or "NIBBLES"
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) M2 (
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.clk( clk200 ),
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.nrst( nrst_once ),
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.tx_en( ),
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.od( )
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);
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endmodule
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