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| 1 | +//------------------------------------------------------------------------------ |
| 2 | +// debounce_v1.v |
| 3 | +// published as part of https://github.com/pConst/basic_verilog |
| 4 | +// Konstantin Pavlov, pavlovconst@gmail.com |
| 5 | +//------------------------------------------------------------------------------ |
| 6 | + |
| 7 | +// INFO ------------------------------------------------------------------------ |
| 8 | +// Button debounce v1 |
| 9 | +// |
| 10 | +// - sampling inputs using configurable divided clock (ithis is the |
| 11 | +// simplest form of low-pass filter) |
| 12 | +// - switching output only when both samples have equal level |
| 13 | +// (this gives some form of hysteresis in case we sample unstable data) |
| 14 | +// |
| 15 | + |
| 16 | + |
| 17 | +/* --- INSTANTIATION TEMPLATE BEGIN --- |
| 18 | +
|
| 19 | +debounce_v1 #( |
| 20 | + .WIDTH( 4 ), |
| 21 | + .SAMPLING_FACTOR( 16 ) |
| 22 | +) DB1 ( |
| 23 | + .clk( clk ), |
| 24 | + .nrst( 1'b1 ), |
| 25 | + .ena( 1'b1 ), |
| 26 | + .in( btn[3:0] ), |
| 27 | + .out( btn_db[3:0] ) |
| 28 | +); |
| 29 | +
|
| 30 | +--- INSTANTIATION TEMPLATE END ---*/ |
| 31 | + |
| 32 | + |
| 33 | +module debounce_v1 #( parameter |
| 34 | + WIDTH = 1, |
| 35 | + SAMPLING_FACTOR = 16 // 0 - sampling every clk |
| 36 | + // 1 - sampling on clk/2 |
| 37 | + // 2 - sampling on clk/4 etc.... |
| 38 | + |
| 39 | + // only one or none should be enabled |
| 40 | + TREAT_UNSTABLE_AS_HIGH = 0, |
| 41 | + TREAT_UNSTABLE_AS_LOW = 0 |
| 42 | +)( |
| 43 | + input clk, |
| 44 | + input nrst, |
| 45 | + input ena, |
| 46 | + |
| 47 | + input [WIDTH-1:0] in, |
| 48 | + output reg [WIDTH-1:0] out |
| 49 | +); |
| 50 | + |
| 51 | + |
| 52 | + localparam SAMPLING_RANGE = 32; |
| 53 | + |
| 54 | + |
| 55 | + wire [SAMPLING_RANGE-1:0] s_clk; |
| 56 | + clk_divider #( |
| 57 | + .WIDTH( SAMPLING_RANGE ) |
| 58 | + ) clk_div ( |
| 59 | + .clk( clk ), |
| 60 | + .nrst( nrst ), |
| 61 | + .ena( 1'b1 ), |
| 62 | + .out( s_clk[SAMPLING_RANGE-1:0] ) |
| 63 | + ); |
| 64 | + |
| 65 | + wire [SAMPLING_RANGE-1:0] s_clk_rise; |
| 66 | + edge_detect #( |
| 67 | + .WIDTH( SAMPLING_RANGE ) |
| 68 | + ) clk_div_ed ( |
| 69 | + .clk( clk ), |
| 70 | + .anrst( nrst ), |
| 71 | + .in( s_clk[SAMPLING_RANGE-1:0] ), |
| 72 | + .rising( s_clk_rise[SAMPLING_RANGE-1:0] ) |
| 73 | + ); |
| 74 | + |
| 75 | + wire do_sample; |
| 76 | + assign do_sample = s_clk_rise[SAMPLING_FACTOR]; |
| 77 | + |
| 78 | + |
| 79 | + reg [WIDTH-1:0] in_d1 = 0; |
| 80 | + reg [WIDTH-1:0] in_d2 = 0; |
| 81 | + |
| 82 | + always @(posedge clk) begin |
| 83 | + if (~nrst) begin |
| 84 | + in_d1[WIDTH-1:0] <= 0; |
| 85 | + in_d2[WIDTH-1:0] <= 0; |
| 86 | + end else if (ena && do_sample) begin |
| 87 | + in_d1[WIDTH-1:0] <= in_d2[WIDTH-1:0]; |
| 88 | + in_d2[WIDTH-1:0] <= in[WIDTH-1:0]; |
| 89 | + end // if |
| 90 | + end |
| 91 | + |
| 92 | + integer i; |
| 93 | + always @(posedge clk) begin |
| 94 | + if( ~nrst ) begin |
| 95 | + out[WIDTH-1:0] <= 0; |
| 96 | + end else begin |
| 97 | + // every input has its own state |
| 98 | + |
| 99 | + for (i = 0; i < WIDTH; i=i+1) begin |
| 100 | + |
| 101 | + case ( {in_d2[i],in_d1[i]} ) |
| 102 | + 2'b00: out[i] <= 1'b0; |
| 103 | + 2'b11: out[i] <= 1'b1; |
| 104 | + default: begin |
| 105 | + if (TREAT_UNSTABLE_AS_HIGH) begin |
| 106 | + out[i] <= 1'b1; |
| 107 | + end else if (TREAT_UNSTABLE_AS_LOW) begin |
| 108 | + out[i] <= 1'b0; |
| 109 | + end |
| 110 | + end |
| 111 | + endcase |
| 112 | + |
| 113 | + end // for |
| 114 | + end |
| 115 | + end |
| 116 | + |
| 117 | +endmodule |
| 118 | + |
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