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Fixed out[] initialization
1 parent 71303a0 commit b81fda6

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3 files changed

+10
-10
lines changed

3 files changed

+10
-10
lines changed

debounce_v1.v

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -45,7 +45,7 @@ module debounce_v1 #( parameter
4545
input ena,
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4747
input [WIDTH-1:0] in,
48-
output reg [WIDTH-1:0] out
48+
output reg [WIDTH-1:0] out = 0
4949
);
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5151

debounce_v2.sv

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -47,7 +47,7 @@ module debounce_v2 #( parameter
4747
input ena,
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4949
input [WIDTH-1:0] in,
50-
output logic [WIDTH-1:0] out
50+
output logic [WIDTH-1:0] out = '0
5151
);
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5353

@@ -78,15 +78,15 @@ module debounce_v2 #( parameter
7878
assign do_sample = s_clk_rise[SAMPLING_FACTOR];
7979

8080

81-
logic [WIDTH-1:0] in_is_high = 0;
82-
logic [WIDTH-1:0] in_is_low = 0;
81+
logic [WIDTH-1:0] in_is_high = '0;
82+
logic [WIDTH-1:0] in_is_low = '0;
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8484
always_ff @(posedge clk) begin
8585
if (~nrst) begin
86-
out[WIDTH-1:0] <= 0;
86+
out[WIDTH-1:0] <= '0;
8787

88-
in_is_high[WIDTH-1:0] <= 0;
89-
in_is_low[WIDTH-1:0] <= 0;
88+
in_is_high[WIDTH-1:0] <= '0;
89+
in_is_low[WIDTH-1:0] <= '0;
9090
end else if (ena && do_sample) begin
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9292
// making decisions for outputs
@@ -105,8 +105,8 @@ module debounce_v2 #( parameter
105105
end // for
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// resetting flags to initialize new sample window
108-
in_is_high[WIDTH-1:0] <= 0;
109-
in_is_low[WIDTH-1:0] <= 0;
108+
in_is_high[WIDTH-1:0] <= '0;
109+
in_is_low[WIDTH-1:0] <= '0;
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111111
end else begin
112112

debounce_v2.v

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -47,7 +47,7 @@ module debounce_v2 #( parameter
4747
input ena,
4848

4949
input [WIDTH-1:0] in,
50-
output reg [WIDTH-1:0] out
50+
output reg [WIDTH-1:0] out = 0
5151
);
5252

5353

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